From nobody Sun Feb 8 10:49:36 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13C6CC77B75 for ; Mon, 15 May 2023 23:57:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245694AbjEOX5d (ORCPT ); Mon, 15 May 2023 19:57:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42040 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235082AbjEOX52 (ORCPT ); Mon, 15 May 2023 19:57:28 -0400 Received: from mail-il1-x132.google.com (mail-il1-x132.google.com [IPv6:2607:f8b0:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E54A57A99 for ; Mon, 15 May 2023 16:57:27 -0700 (PDT) Received: by mail-il1-x132.google.com with SMTP id e9e14a558f8ab-3319a6f989aso94368985ab.2 for ; Mon, 15 May 2023 16:57:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684195047; x=1686787047; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dygmSIeKyL1Qr6osm0gPJv6LRBfSTNTnVZ/IpsRKoBs=; b=ifiSs08y2MIXBn42MVs3fNmMJZNFceO8x5OBZxjHHuPseUh9GHHt2QVVxaJ1tjr0rH 4lgxmX4/5PLmd3TS0m4VoQvGK0siotAuZaVUL57vq0Fr+x3Zxddw3A3lTreQhjcQxqNH tnGG9MYqlx8tz0qt9vIMxWNuiqR0XCqgIE3nTul09t7jYA3Ah59gZ4cEDExLcAGXScxB ciVkw5p668JwtFCQ3SI+dfCZYKEUZ0v9xU1L5iTLhd1y1DlxGg579Gx/Q4QUEIZ6GeII CHOCMUvoC7stPSQY2HtFkjcojT26Kq2ty1+wlzns4ijmz2vXBiY/KU5/MZ3UftgwI1SD x+dQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684195047; x=1686787047; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dygmSIeKyL1Qr6osm0gPJv6LRBfSTNTnVZ/IpsRKoBs=; b=TsMz5siu/k9FgLfq2CMiTmewii1K3ipvh1X42qhBI3h0PUKGwk2pkuJLBYYSoY9Qn0 ONgTBSl1fxLTGSCqUuztPnXUa6XwMZV7Hf4fZ+KmvSptN0RTNgxgLVpo0zoh8kRPHqM/ DYGG9WCLiwWpYZskYY4KvVAvPtSknAjwCf71flfOUK9B8BhF9N/Mr9qoYFDPVLgr2bOs 6t+j/utm9/hSvkmh7Nc0gs6P1y6PS1Wx8/vwTWmSD7Nn5fB0vRi91zTymS/uLxDo6uvu VgSSUtKsm3brXWJ5RmzImHtkzYPLZIEEHvbJ28e7RkiRPFoFagVhkMmGpx4RGkOCppx6 7yEQ== X-Gm-Message-State: AC+VfDwE/4M1QY/p1DslZasKVyI3Rf8GysdfeYu/yXt4U7EMv4xItvf/ 6ePTHbD0hJcrLxOUEQhQ13U= X-Google-Smtp-Source: ACHHUZ6evfIxkAscIh79dMFR3cgzi0moXGEy9Fy4vlp+9hRCEen8qyXWbLURAPkFLQPKP8NXCqRz2w== X-Received: by 2002:a92:d403:0:b0:326:3a39:89d0 with SMTP id q3-20020a92d403000000b003263a3989d0mr23300881ilm.1.1684195047045; Mon, 15 May 2023 16:57:27 -0700 (PDT) Received: from aford-B741.lan ([2601:447:d001:897f:61e0:9fee:1bca:ea3c]) by smtp.gmail.com with ESMTPSA id f6-20020a056638112600b00411b5ea8576sm7427851jar.108.2023.05.15.16.57.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 May 2023 16:57:26 -0700 (PDT) From: Adam Ford To: dri-devel@lists.freedesktop.org Cc: aford@beaconembedded.com, Lucas Stach , Adam Ford , Chen-Yu Tsai , Frieder Schrempf , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , Inki Dae , Jagan Teki , Marek Szyprowski , linux-kernel@vger.kernel.org Subject: [PATCH V6 1/6] drm: bridge: samsung-dsim: fix blanking packet size calculation Date: Mon, 15 May 2023 18:57:08 -0500 Message-Id: <20230515235713.232939-2-aford173@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230515235713.232939-1-aford173@gmail.com> References: <20230515235713.232939-1-aford173@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Lucas Stach Scale the blanking packet sizes to match the ratio between HS clock and DPI interface clock. The controller seems to do internal scaling to the number of active lanes, so we don't take those into account. Signed-off-by: Lucas Stach Signed-off-by: Adam Ford Tested-by: Chen-Yu Tsai Tested-by: Frieder Schrempf Reviewed-by: Jagan Teki Tested-by: Jagan Teki # imx8mm-icore Tested-by: Marek Szyprowski --- drivers/gpu/drm/bridge/samsung-dsim.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge= /samsung-dsim.c index e0a402a85787..2be3b58624c3 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -874,17 +874,29 @@ static void samsung_dsim_set_display_mode(struct sams= ung_dsim *dsi) u32 reg; =20 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { + int byte_clk_khz =3D dsi->burst_clk_rate / 1000 / 8; + int hfp =3D (m->hsync_start - m->hdisplay) * byte_clk_khz / m->clock; + int hbp =3D (m->htotal - m->hsync_end) * byte_clk_khz / m->clock; + int hsa =3D (m->hsync_end - m->hsync_start) * byte_clk_khz / m->clock; + + /* remove packet overhead when possible */ + hfp =3D max(hfp - 6, 0); + hbp =3D max(hbp - 6, 0); + hsa =3D max(hsa - 6, 0); + + dev_dbg(dsi->dev, "calculated hfp: %u, hbp: %u, hsa: %u", + hfp, hbp, hsa); + reg =3D DSIM_CMD_ALLOW(0xf) | DSIM_STABLE_VFP(m->vsync_start - m->vdisplay) | DSIM_MAIN_VBP(m->vtotal - m->vsync_end); samsung_dsim_write(dsi, DSIM_MVPORCH_REG, reg); =20 - reg =3D DSIM_MAIN_HFP(m->hsync_start - m->hdisplay) - | DSIM_MAIN_HBP(m->htotal - m->hsync_end); + reg =3D DSIM_MAIN_HFP(hfp) | DSIM_MAIN_HBP(hbp); samsung_dsim_write(dsi, DSIM_MHPORCH_REG, reg); =20 reg =3D DSIM_MAIN_VSA(m->vsync_end - m->vsync_start) - | DSIM_MAIN_HSA(m->hsync_end - m->hsync_start); + | DSIM_MAIN_HSA(hsa); samsung_dsim_write(dsi, DSIM_MSYNC_REG, reg); } reg =3D DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) | --=20 2.39.2 From nobody Sun Feb 8 10:49:36 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C439C7EE26 for ; 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Mon, 15 May 2023 16:57:28 -0700 (PDT) Received: from aford-B741.lan ([2601:447:d001:897f:61e0:9fee:1bca:ea3c]) by smtp.gmail.com with ESMTPSA id f6-20020a056638112600b00411b5ea8576sm7427851jar.108.2023.05.15.16.57.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 May 2023 16:57:28 -0700 (PDT) From: Adam Ford To: dri-devel@lists.freedesktop.org Cc: aford@beaconembedded.com, Adam Ford , Lucas Stach , Chen-Yu Tsai , Frieder Schrempf , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , Inki Dae , Jagan Teki , Marek Szyprowski , Marek Vasut , linux-kernel@vger.kernel.org Subject: [PATCH V6 2/6] drm: bridge: samsung-dsim: Fix PMS Calculator on imx8m[mnp] Date: Mon, 15 May 2023 18:57:09 -0500 Message-Id: <20230515235713.232939-3-aford173@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230515235713.232939-1-aford173@gmail.com> References: <20230515235713.232939-1-aford173@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" According to Table 13-45 of the i.MX8M Mini Reference Manual, the min and max values for M and the frequency range for the VCO_out calculator were incorrect. This information was contradicted in other parts of the mini, nano and plus manuals. After reaching out to my NXP Rep, when confronting him about discrepencies in the Nano manual, he responded with: "Yes it is definitely wrong, the one that is part of the NOTE in MIPI_DPHY_M_PLLPMS register table against PMS_P, PMS_M and PMS_S is not correct. I will report this to Doc team, the one customer should be take into account is the Table 13-40 DPHY PLL Parameters and the Note above." These updated values also match what is used in the NXP downstream kernel. To fix this, make new variables to hold the min and max values of m and the minimum value of VCO_out, and update the PMS calculator to use these new variables instead of using hard-coded values to keep the backwards compatibility with other parts using this driver. Fixes: 4d562c70c4dc ("drm: bridge: samsung-dsim: Add i.MX8M Mini/Nano suppo= rt") Signed-off-by: Adam Ford Reviewed-by: Lucas Stach Tested-by: Chen-Yu Tsai Tested-by: Frieder Schrempf Reviewed-by: Frieder Schrempf Reviewed-by: Jagan Teki Tested-by: Jagan Teki # imx8mm-icore Tested-by: Marek Szyprowski --- drivers/gpu/drm/bridge/samsung-dsim.c | 22 ++++++++++++++++++++-- include/drm/bridge/samsung-dsim.h | 3 +++ 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge= /samsung-dsim.c index 2be3b58624c3..bf4b33d2de76 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -405,6 +405,9 @@ static const struct samsung_dsim_driver_data exynos3_ds= i_driver_data =3D { .num_bits_resol =3D 11, .pll_p_offset =3D 13, .reg_values =3D reg_values, + .m_min =3D 41, + .m_max =3D 125, + .min_freq =3D 500, }; =20 static const struct samsung_dsim_driver_data exynos4_dsi_driver_data =3D { @@ -418,6 +421,9 @@ static const struct samsung_dsim_driver_data exynos4_ds= i_driver_data =3D { .num_bits_resol =3D 11, .pll_p_offset =3D 13, .reg_values =3D reg_values, + .m_min =3D 41, + .m_max =3D 125, + .min_freq =3D 500, }; =20 static const struct samsung_dsim_driver_data exynos5_dsi_driver_data =3D { @@ -429,6 +435,9 @@ static const struct samsung_dsim_driver_data exynos5_ds= i_driver_data =3D { .num_bits_resol =3D 11, .pll_p_offset =3D 13, .reg_values =3D reg_values, + .m_min =3D 41, + .m_max =3D 125, + .min_freq =3D 500, }; =20 static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = =3D { @@ -441,6 +450,9 @@ static const struct samsung_dsim_driver_data exynos5433= _dsi_driver_data =3D { .num_bits_resol =3D 12, .pll_p_offset =3D 13, .reg_values =3D exynos5433_reg_values, + .m_min =3D 41, + .m_max =3D 125, + .min_freq =3D 500, }; =20 static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = =3D { @@ -453,6 +465,9 @@ static const struct samsung_dsim_driver_data exynos5422= _dsi_driver_data =3D { .num_bits_resol =3D 12, .pll_p_offset =3D 13, .reg_values =3D exynos5422_reg_values, + .m_min =3D 41, + .m_max =3D 125, + .min_freq =3D 500, }; =20 static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data =3D { @@ -469,6 +484,9 @@ static const struct samsung_dsim_driver_data imx8mm_dsi= _driver_data =3D { */ .pll_p_offset =3D 14, .reg_values =3D imx8mm_dsim_reg_values, + .m_min =3D 64, + .m_max =3D 1023, + .min_freq =3D 1050, }; =20 static const struct samsung_dsim_driver_data * @@ -547,12 +565,12 @@ static unsigned long samsung_dsim_pll_find_pms(struct= samsung_dsim *dsi, tmp =3D (u64)fout * (_p << _s); do_div(tmp, fin); _m =3D tmp; - if (_m < 41 || _m > 125) + if (_m < driver_data->m_min || _m > driver_data->m_max) continue; =20 tmp =3D (u64)_m * fin; do_div(tmp, _p); - if (tmp < 500 * MHZ || + if (tmp < driver_data->min_freq * MHZ || tmp > driver_data->max_freq * MHZ) continue; =20 diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung= -dsim.h index ba5484de2b30..a1a5b2b89a7a 100644 --- a/include/drm/bridge/samsung-dsim.h +++ b/include/drm/bridge/samsung-dsim.h @@ -54,11 +54,14 @@ struct samsung_dsim_driver_data { unsigned int has_freqband:1; unsigned int has_clklane_stop:1; unsigned int num_clks; + unsigned int min_freq; unsigned int max_freq; unsigned int wait_for_reset; unsigned int num_bits_resol; unsigned int pll_p_offset; const unsigned int *reg_values; + u16 m_min; + u16 m_max; }; =20 struct samsung_dsim_host_ops { --=20 2.39.2 From nobody Sun Feb 8 10:49:36 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A79DC77B7D for ; Mon, 15 May 2023 23:57:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343590AbjEOX5i (ORCPT ); Mon, 15 May 2023 19:57:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42056 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245660AbjEOX5c (ORCPT ); Mon, 15 May 2023 19:57:32 -0400 Received: from mail-il1-x12a.google.com (mail-il1-x12a.google.com [IPv6:2607:f8b0:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 31E9B7D8B for ; Mon, 15 May 2023 16:57:31 -0700 (PDT) Received: by mail-il1-x12a.google.com with SMTP id e9e14a558f8ab-335598ae8b4so23943335ab.2 for ; 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charset="utf-8" Make the pll-clock-frequency optional. If it's present, use it to maintain backwards compatibility with existing hardware. If it is absent, read clock rate of "sclk_mipi" to determine the rate. Since it can be optional, change the message from an error to dev_info. Signed-off-by: Adam Ford Tested-by: Chen-Yu Tsai Tested-by: Frieder Schrempf Reviewed-by: Frieder Schrempf Reviewed-by: Jagan Teki Tested-by: Jagan Teki # imx8mm-icore Tested-by: Marek Szyprowski --- drivers/gpu/drm/bridge/samsung-dsim.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge= /samsung-dsim.c index bf4b33d2de76..08266303c261 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -1712,11 +1712,11 @@ static const struct mipi_dsi_host_ops samsung_dsim_= ops =3D { }; =20 static int samsung_dsim_of_read_u32(const struct device_node *np, - const char *propname, u32 *out_value) + const char *propname, u32 *out_value, bool optional) { int ret =3D of_property_read_u32(np, propname, out_value); =20 - if (ret < 0) + if (ret < 0 && !optional) pr_err("%pOF: failed to get '%s' property\n", np, propname); =20 return ret; @@ -1726,20 +1726,29 @@ static int samsung_dsim_parse_dt(struct samsung_dsi= m *dsi) { struct device *dev =3D dsi->dev; struct device_node *node =3D dev->of_node; + struct clk *pll_clk; int ret; =20 ret =3D samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency", - &dsi->pll_clk_rate); - if (ret < 0) - return ret; + &dsi->pll_clk_rate, 1); + + /* If it doesn't exist, read it from the clock instead of failing */ + if (ret < 0) { + dev_info(dev, "Using sclk_mipi for pll clock frequency\n"); + pll_clk =3D devm_clk_get(dev, "sclk_mipi"); + if (!IS_ERR(pll_clk)) + dsi->pll_clk_rate =3D clk_get_rate(pll_clk); + else + return PTR_ERR(pll_clk); + } =20 ret =3D samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency", - &dsi->burst_clk_rate); + &dsi->burst_clk_rate, 0); if (ret < 0) return ret; =20 ret =3D samsung_dsim_of_read_u32(node, "samsung,esc-clock-frequency", - &dsi->esc_clk_rate); + &dsi->esc_clk_rate, 0); if (ret < 0) return ret; =20 --=20 2.39.2 From nobody Sun Feb 8 10:49:36 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26618C77B7D for ; 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Mon, 15 May 2023 16:57:32 -0700 (PDT) Received: from aford-B741.lan ([2601:447:d001:897f:61e0:9fee:1bca:ea3c]) by smtp.gmail.com with ESMTPSA id f6-20020a056638112600b00411b5ea8576sm7427851jar.108.2023.05.15.16.57.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 May 2023 16:57:31 -0700 (PDT) From: Adam Ford To: dri-devel@lists.freedesktop.org Cc: aford@beaconembedded.com, Adam Ford , Frieder Schrempf , Chen-Yu Tsai , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , Inki Dae , Jagan Teki , Marek Szyprowski , Marek Vasut , linux-kernel@vger.kernel.org Subject: [PATCH V6 4/6] drm: bridge: samsung-dsim: Select GENERIC_PHY_MIPI_DPHY Date: Mon, 15 May 2023 18:57:11 -0500 Message-Id: <20230515235713.232939-5-aford173@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230515235713.232939-1-aford173@gmail.com> References: <20230515235713.232939-1-aford173@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In order to support variable DPHY timings, it's necessary to enable GENERIC_PHY_MIPI_DPHY so phy_mipi_dphy_get_default_config can be used to determine the nominal values for a given resolution and refresh rate. Signed-off-by: Adam Ford Tested-by: Frieder Schrempf Reviewed-by: Frieder Schrempf Tested-by: Chen-Yu Tsai Tested-by: Marek Szyprowski --- drivers/gpu/drm/bridge/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index f076a09afac0..82c68b042444 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -227,6 +227,7 @@ config DRM_SAMSUNG_DSIM select DRM_KMS_HELPER select DRM_MIPI_DSI select DRM_PANEL_BRIDGE + select GENERIC_PHY_MIPI_DPHY help The Samsung MIPI DSIM bridge controller driver. This MIPI DSIM bridge can be found it on Exynos SoCs and --=20 2.39.2 From nobody Sun Feb 8 10:49:36 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0FFEC77B75 for ; Mon, 15 May 2023 23:57:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343602AbjEOX5o (ORCPT ); Mon, 15 May 2023 19:57:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42118 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343564AbjEOX5g (ORCPT ); Mon, 15 May 2023 19:57:36 -0400 Received: from mail-io1-xd32.google.com (mail-io1-xd32.google.com [IPv6:2607:f8b0:4864:20::d32]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9849E7EC8 for ; Mon, 15 May 2023 16:57:34 -0700 (PDT) Received: by mail-io1-xd32.google.com with SMTP id ca18e2360f4ac-76c5db6a5cfso576837839f.2 for ; Mon, 15 May 2023 16:57:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684195054; x=1686787054; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uTlvZRtjqJ4RiQO6GT2A0vqR1tGkbMy9z6E7MumB9ME=; b=gj6pzDw8b/0S9AQZXm4IyzrQtiSC0UbHtBq1afEExH4ElHAptQwmobhd6yPREI9fNy PkdmB067g+jx+Rn+knIPAiWh9fazkWzfuHYWSQeslSMRQZZeCyMp47ioCDXQnY682mN7 0hbfcLTZf1D/l6eLrAn5GEiW18AIPMbZDqtDhv2Upwnse3Qw1GJTpXXfi2Tcy82TZklZ Tr5oV0vTpLth1YZjyPyzgjTS9WC/lvcOV+FY3Sww7iBKLjPqTddnAIA45H74ARMAN3el gi7UAm/3wEoM6GLeGJW/c/Lik716MEhyJWUYLcRL03o7LxT5i/jJKjcRyqxbMEq4MQET FoZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684195054; x=1686787054; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uTlvZRtjqJ4RiQO6GT2A0vqR1tGkbMy9z6E7MumB9ME=; b=AmorDUjQ2eeQkmZSpHkYAv4C4SEYKf+kC5gtP3FR/wIjt70lSA5ktBcepLY5v/7wGs 0ODc8ertmAxC77F4S1mC6frPhDBpCtlVQeNYjVaHWSWFYxlv/VsiosqaTXXDkVHbSC7d 8xXRDE+gZEfbvHrS44/YfNJ1FaM6HguNxOXO00p4X8tRRm5KlVDnEzhyakmfgbUCwcUy HikA4+vDgpwlHAfJ8stdjJ2UNMEBkmUyhogisOqJ01orMLpUCdRrCygmTOBZe3a1rbV4 E6gcod7vJt4tat4UnvMOeVwCUK8e3BDhmP0m8WRFRLqo3ei3lOkVKgTBhIljAZH7c6qJ TO1w== X-Gm-Message-State: AC+VfDyRdJLvol5uzRRt/kQaJ3qmy/T8QLDXUT6sckgayi/3MN6iir/Q xZceXAaC3LFIrxYbQjGMM6w= X-Google-Smtp-Source: ACHHUZ6IzAlVq2AuTaceDKzB7cDava2bGBw25HhaUcC1vSxeQEeDdXdktUKadX5vNcWJCj5/QN4bkw== X-Received: by 2002:a6b:917:0:b0:76c:779c:7ebe with SMTP id t23-20020a6b0917000000b0076c779c7ebemr831545ioi.14.1684195053878; Mon, 15 May 2023 16:57:33 -0700 (PDT) Received: from aford-B741.lan ([2601:447:d001:897f:61e0:9fee:1bca:ea3c]) by smtp.gmail.com with ESMTPSA id f6-20020a056638112600b00411b5ea8576sm7427851jar.108.2023.05.15.16.57.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 May 2023 16:57:33 -0700 (PDT) From: Adam Ford To: dri-devel@lists.freedesktop.org Cc: aford@beaconembedded.com, Adam Ford , Lucas Stach , Chen-Yu Tsai , Frieder Schrempf , Michael Walle , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , Inki Dae , Jagan Teki , Marek Szyprowski , Marek Vasut , linux-kernel@vger.kernel.org Subject: [PATCH V6 5/6] drm: bridge: samsung-dsim: Dynamically configure DPHY timing Date: Mon, 15 May 2023 18:57:12 -0500 Message-Id: <20230515235713.232939-6-aford173@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230515235713.232939-1-aford173@gmail.com> References: <20230515235713.232939-1-aford173@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The DPHY timings are currently hard coded. Since the input clock can be variable, the phy timings need to be variable too. To facilitate this, we need to cache the hs_clock based on what is generated from the PLL. The phy_mipi_dphy_get_default_config_for_hsclk function configures the DPHY timings in pico-seconds, and a small macro converts those timings into clock cycles based on the hs_clk. Signed-off-by: Adam Ford Signed-off-by: Lucas Stach Tested-by: Chen-Yu Tsai Tested-by: Frieder Schrempf Reviewed-by: Frieder Schrempf Tested-by: Michael Walle Tested-by: Jagan Teki # imx8mm-icore Tested-by: Marek Szyprowski --- drivers/gpu/drm/bridge/samsung-dsim.c | 57 +++++++++++++++++++++++---- include/drm/bridge/samsung-dsim.h | 1 + 2 files changed, 51 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge= /samsung-dsim.c index 08266303c261..3944b7cfbbdf 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -218,6 +218,8 @@ =20 #define OLD_SCLK_MIPI_CLK_NAME "pll_clk" =20 +#define PS_TO_CYCLE(ps, hz) DIV64_U64_ROUND_CLOSEST(((ps) * (hz)), 1000000= 000000ULL) + static const char *const clk_names[5] =3D { "bus_clk", "sclk_mipi", @@ -651,6 +653,8 @@ static unsigned long samsung_dsim_set_pll(struct samsun= g_dsim *dsi, reg =3D samsung_dsim_read(dsi, DSIM_STATUS_REG); } while ((reg & DSIM_PLL_STABLE) =3D=3D 0); =20 + dsi->hs_clock =3D fout; + return fout; } =20 @@ -698,13 +702,46 @@ static void samsung_dsim_set_phy_ctrl(struct samsung_= dsim *dsi) const struct samsung_dsim_driver_data *driver_data =3D dsi->driver_data; const unsigned int *reg_values =3D driver_data->reg_values; u32 reg; + struct phy_configure_opts_mipi_dphy cfg; + int clk_prepare, lpx, clk_zero, clk_post, clk_trail; + int hs_exit, hs_prepare, hs_zero, hs_trail; + unsigned long long byte_clock =3D dsi->hs_clock / 8; =20 if (driver_data->has_freqband) return; =20 + phy_mipi_dphy_get_default_config_for_hsclk(dsi->hs_clock, + dsi->lanes, &cfg); + + /* + * TODO: + * The tech reference manual for i.MX8M Mini/Nano/Plus + * doesn't state what the definition of the PHYTIMING + * bits are beyond their address and bit position. + * After reviewing NXP's downstream code, it appears + * that the various PHYTIMING registers take the number + * of cycles and use various dividers on them. This + * calculation does not result in an exact match to the + * downstream code, but it is very close, and it appears + * to sync at a variety of resolutions. If someone + * can get a more accurate mathematical equation needed + * for these registers, this should be updated. + */ + + lpx =3D PS_TO_CYCLE(cfg.lpx, byte_clock); + hs_exit =3D PS_TO_CYCLE(cfg.hs_exit, byte_clock); + clk_prepare =3D PS_TO_CYCLE(cfg.clk_prepare, byte_clock); + clk_zero =3D PS_TO_CYCLE(cfg.clk_zero, byte_clock); + clk_post =3D PS_TO_CYCLE(cfg.clk_post, byte_clock); + clk_trail =3D PS_TO_CYCLE(cfg.clk_trail, byte_clock); + hs_prepare =3D PS_TO_CYCLE(cfg.hs_prepare, byte_clock); + hs_zero =3D PS_TO_CYCLE(cfg.hs_zero, byte_clock); + hs_trail =3D PS_TO_CYCLE(cfg.hs_trail, byte_clock); + /* B D-PHY: D-PHY Master & Slave Analog Block control */ reg =3D reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] | reg_values[PHYCTRL_SLEW_UP]; + samsung_dsim_write(dsi, DSIM_PHYCTRL_REG, reg); =20 /* @@ -712,7 +749,9 @@ static void samsung_dsim_set_phy_ctrl(struct samsung_ds= im *dsi) * T HS-EXIT: Time that the transmitter drives LP-11 following a HS * burst */ - reg =3D reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT]; + + reg =3D DSIM_PHYTIMING_LPX(lpx) | DSIM_PHYTIMING_HS_EXIT(hs_exit); + samsung_dsim_write(dsi, DSIM_PHYTIMING_REG, reg); =20 /* @@ -728,10 +767,11 @@ static void samsung_dsim_set_phy_ctrl(struct samsung_= dsim *dsi) * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after * the last payload clock bit of a HS transmission burst */ - reg =3D reg_values[PHYTIMING_CLK_PREPARE] | - reg_values[PHYTIMING_CLK_ZERO] | - reg_values[PHYTIMING_CLK_POST] | - reg_values[PHYTIMING_CLK_TRAIL]; + + reg =3D DSIM_PHYTIMING1_CLK_PREPARE(clk_prepare) | + DSIM_PHYTIMING1_CLK_ZERO(clk_zero) | + DSIM_PHYTIMING1_CLK_POST(clk_post) | + DSIM_PHYTIMING1_CLK_TRAIL(clk_trail); =20 samsung_dsim_write(dsi, DSIM_PHYTIMING1_REG, reg); =20 @@ -744,8 +784,11 @@ static void samsung_dsim_set_phy_ctrl(struct samsung_d= sim *dsi) * T HS-TRAIL: Time that the transmitter drives the flipped differential * state after last payload data bit of a HS transmission burst */ - reg =3D reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] | - reg_values[PHYTIMING_HS_TRAIL]; + + reg =3D DSIM_PHYTIMING2_HS_PREPARE(hs_prepare) | + DSIM_PHYTIMING2_HS_ZERO(hs_zero) | + DSIM_PHYTIMING2_HS_TRAIL(hs_trail); + samsung_dsim_write(dsi, DSIM_PHYTIMING2_REG, reg); } =20 diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung= -dsim.h index a1a5b2b89a7a..d9d431e3b65a 100644 --- a/include/drm/bridge/samsung-dsim.h +++ b/include/drm/bridge/samsung-dsim.h @@ -93,6 +93,7 @@ struct samsung_dsim { =20 u32 pll_clk_rate; u32 burst_clk_rate; + u32 hs_clock; u32 esc_clk_rate; u32 lanes; u32 mode_flags; --=20 2.39.2 From nobody Sun Feb 8 10:49:36 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57125C77B7D for ; Mon, 15 May 2023 23:58:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343491AbjEOX57 (ORCPT ); Mon, 15 May 2023 19:57:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42148 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343583AbjEOX5h (ORCPT ); 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Mon, 15 May 2023 16:57:35 -0700 (PDT) From: Adam Ford To: dri-devel@lists.freedesktop.org Cc: aford@beaconembedded.com, Adam Ford , Chen-Yu Tsai , Frieder Schrempf , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , Inki Dae , Jagan Teki , Marek Szyprowski , Marek Vasut , linux-kernel@vger.kernel.org Subject: [PATCH V6 6/6] drm: bridge: samsung-dsim: Support non-burst mode Date: Mon, 15 May 2023 18:57:13 -0500 Message-Id: <20230515235713.232939-7-aford173@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230515235713.232939-1-aford173@gmail.com> References: <20230515235713.232939-1-aford173@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The high-speed clock is hard-coded to the burst-clock frequency specified in the device tree. However, when using devices like certain bridge chips without burst mode and varying resolutions and refresh rates, it may be necessary to set the high-speed clock dynamically based on the desired pixel clock for the connected device. This also removes the need to set a clock speed from the device tree for non-burst mode operation, since the pixel clock rate is the rate requested from the attached device like a bridge chip. This should have no impact for people using burst-mode and setting the burst clock rate is still required for those users. If the burst clock is not present, change the error message to dev_info indicating the clock use the pixel clock. Signed-off-by: Adam Ford Tested-by: Chen-Yu Tsai Tested-by: Frieder Schrempf Reviewed-by: Frieder Schrempf Reviewed-by: Jagan Teki Tested-by: Jagan Teki # imx8mm-icore Tested-by: Marek Szyprowski --- drivers/gpu/drm/bridge/samsung-dsim.c | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge= /samsung-dsim.c index 3944b7cfbbdf..03b21d13f067 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -655,16 +655,28 @@ static unsigned long samsung_dsim_set_pll(struct sams= ung_dsim *dsi, =20 dsi->hs_clock =3D fout; =20 + dsi->hs_clock =3D fout; + return fout; } =20 static int samsung_dsim_enable_clock(struct samsung_dsim *dsi) { - unsigned long hs_clk, byte_clk, esc_clk; + unsigned long hs_clk, byte_clk, esc_clk, pix_clk; unsigned long esc_div; u32 reg; + struct drm_display_mode *m =3D &dsi->mode; + int bpp =3D mipi_dsi_pixel_format_to_bpp(dsi->format); + + /* m->clock is in KHz */ + pix_clk =3D m->clock * 1000; + + /* Use burst_clk_rate if available, otherwise use the pix_clk */ + if (dsi->burst_clk_rate) + hs_clk =3D samsung_dsim_set_pll(dsi, dsi->burst_clk_rate); + else + hs_clk =3D samsung_dsim_set_pll(dsi, DIV_ROUND_UP(pix_clk * bpp, dsi->la= nes)); =20 - hs_clk =3D samsung_dsim_set_pll(dsi, dsi->burst_clk_rate); if (!hs_clk) { dev_err(dsi->dev, "failed to configure DSI PLL\n"); return -EFAULT; @@ -935,7 +947,7 @@ static void samsung_dsim_set_display_mode(struct samsun= g_dsim *dsi) u32 reg; =20 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { - int byte_clk_khz =3D dsi->burst_clk_rate / 1000 / 8; + int byte_clk_khz =3D dsi->hs_clock / 1000 / 8; int hfp =3D (m->hsync_start - m->hdisplay) * byte_clk_khz / m->clock; int hbp =3D (m->htotal - m->hsync_end) * byte_clk_khz / m->clock; int hsa =3D (m->hsync_end - m->hsync_start) * byte_clk_khz / m->clock; @@ -1785,10 +1797,13 @@ static int samsung_dsim_parse_dt(struct samsung_dsi= m *dsi) return PTR_ERR(pll_clk); } =20 + /* If it doesn't exist, use pixel clock instead of failing */ ret =3D samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency", - &dsi->burst_clk_rate, 0); - if (ret < 0) - return ret; + &dsi->burst_clk_rate, 1); + if (ret < 0) { + dev_info(dev, "Using pixel clock for HS clock frequency\n"); + dsi->burst_clk_rate =3D 0; + } =20 ret =3D samsung_dsim_of_read_u32(node, "samsung,esc-clock-frequency", &dsi->esc_clk_rate, 0); --=20 2.39.2