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charset="utf-8" Add devicetree binding document and related header file for the T-HEAD TH1520 clock. Cc: Icenowy Zheng Cc: Wei Fu Cc: Jisheng Zhang Signed-off-by: Yangtao Li --- .../bindings/clock/thead,th1520-ccu.yaml | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/thead,th1520-cc= u.yaml diff --git a/Documentation/devicetree/bindings/clock/thead,th1520-ccu.yaml = b/Documentation/devicetree/bindings/clock/thead,th1520-ccu.yaml new file mode 100644 index 000000000000..c3e2d8c7efa6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/thead,th1520-ccu.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/thead,th1520-ccu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-HEAD Clock Control Unit + +maintainers: + - Jisheng Zhang + - Wei Fu + - Yangtao Li + + +properties: + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + compatible: + enum: + - thead,th1520-ccu + + reg: + maxItems: 1 + + clocks: + const: 2 + items: + - description: High Frequency Oscillator (usually at 24MHz) + - description: Low Frequency Oscillator (usually at 32kHz) + + clock-names: + const: 2 + items: + - const: hosc + - const: losc + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + clk: clock-controller@ffef010000 { + compatible =3D "thead,th1520-ccu"; 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charset="utf-8" Add support for th1520 in the clock framework. Cc: Icenowy Zheng Cc: Wei Fu Cc: Jisheng Zhang Signed-off-by: Yangtao Li --- drivers/clk/Kconfig | 6 + drivers/clk/Makefile | 1 + drivers/clk/clk-th1520.c | 999 +++++++++++++++++++++++ include/dt-bindings/clock/th1520-clock.h | 92 +++ 4 files changed, 1098 insertions(+) create mode 100644 drivers/clk/clk-th1520.c create mode 100644 include/dt-bindings/clock/th1520-clock.h diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 016814e15536..aa69a4d17916 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -464,6 +464,12 @@ config COMMON_CLK_SP7021 Not all features of the PLL are currently supported by the driver. =20 +config COMMON_CLK_THEAD + tristate "Clock driver for TH1520 SoC" + depends on ARCH_THEAD || COMPILE_TEST + help + Support for the T-HEAD TH1520 RISC-V SoC clocks. + source "drivers/clk/actions/Kconfig" source "drivers/clk/analogbits/Kconfig" source "drivers/clk/baikal-t1/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 0aebef17edc6..95c89bfb129f 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -76,6 +76,7 @@ obj-$(CONFIG_CLK_TWL6040) +=3D clk-twl6040.o obj-$(CONFIG_ARCH_VT8500) +=3D clk-vt8500.o obj-$(CONFIG_COMMON_CLK_RS9_PCIE) +=3D clk-renesas-pcie.o obj-$(CONFIG_COMMON_CLK_SI521XX) +=3D clk-si521xx.o +obj-$(CONFIG_COMMON_CLK_THEAD) +=3D clk-th1520.o obj-$(CONFIG_COMMON_CLK_VC5) +=3D clk-versaclock5.o obj-$(CONFIG_COMMON_CLK_VC7) +=3D clk-versaclock7.o obj-$(CONFIG_COMMON_CLK_WM831X) +=3D clk-wm831x.o diff --git a/drivers/clk/clk-th1520.c b/drivers/clk/clk-th1520.c new file mode 100644 index 000000000000..5dfa9e5207e2 --- /dev/null +++ b/drivers/clk/clk-th1520.c @@ -0,0 +1,999 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Vivo Communication Technology Co. Ltd. + * Authors: Yangtao Li + */ + +#include +#include +#include +#include +#include +#include + +struct ccu_internal { + u8 shift; + u8 width; +}; + +struct ccu_div_internal { + u8 shift; + u8 width; + u32 flags; +}; + +struct ccu_common { + struct regmap *map; + u16 reg; + struct clk_hw hw; +}; + +struct ccu_mux { + struct ccu_internal mux; + struct ccu_common common; +}; + +struct ccu_gate { + u32 enable; + struct ccu_common common; +}; + +struct ccu_div { + u32 enable; + struct ccu_div_internal div; + struct ccu_internal mux; + struct ccu_common common; +}; + +/* + * struct ccu_mdiv - Definition of an M-D-I-V clock + * + * Clocks based on the formula (parent * M) / (D * I * V) + */ +struct ccu_mdiv { + struct ccu_internal m; + struct ccu_internal d; + struct ccu_internal i; + struct ccu_internal v; + struct ccu_common common; +}; + +#define TH_CCU_ARG(_shift, _width) \ + { \ + .shift =3D _shift, \ + .width =3D _width, \ + } + +#define TH_CCU_DIV_FLAGS(_shift, _width, _flags) \ + { \ + .shift =3D _shift, \ + .width =3D _width, \ + .flags =3D _flags, \ + } + +#define CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ + struct ccu_gate _struct =3D { \ + .enable =3D _gate, \ + .common =3D { \ + .reg =3D _reg, \ + .hw.init =3D CLK_HW_INIT(_name, \ + _parent, \ + &ccu_gate_ops, \ + _flags), \ + } \ + } + +static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw) +{ + return container_of(hw, struct ccu_common, hw); +} + +static inline struct ccu_mux *hw_to_ccu_mux(struct clk_hw *hw) +{ + struct ccu_common *common =3D hw_to_ccu_common(hw); + + return container_of(common, struct ccu_mux, common); +} + +static inline struct ccu_mdiv *hw_to_ccu_mdiv(struct clk_hw *hw) +{ + struct ccu_common *common =3D hw_to_ccu_common(hw); + + return container_of(common, struct ccu_mdiv, common); +} + +static inline struct ccu_div *hw_to_ccu_div(struct clk_hw *hw) +{ + struct ccu_common *common =3D hw_to_ccu_common(hw); + + return container_of(common, struct ccu_div, common); +} + +static inline struct ccu_gate *hw_to_ccu_gate(struct clk_hw *hw) +{ + struct ccu_common *common =3D hw_to_ccu_common(hw); + + return container_of(common, struct ccu_gate, common); +} + +static u8 ccu_get_parent_helper(struct ccu_common *common, + struct ccu_internal *mux) +{ + unsigned int val; + u8 parent; + + regmap_read(common->map, common->reg, &val); + parent =3D val >> mux->shift; + parent &=3D GENMASK(mux->width - 1, 0); + + return parent; +} + +static int ccu_set_parent_helper(struct ccu_common *common, + struct ccu_internal *mux, + u8 index) +{ + return regmap_update_bits(common->map, common->reg, + GENMASK(mux->width - 1, 0) << mux->shift, + index << mux->shift); +} + +static u8 ccu_mux_get_parent(struct clk_hw *hw) +{ + struct ccu_mux *cm =3D hw_to_ccu_mux(hw); + + return ccu_get_parent_helper(&cm->common, &cm->mux); +} + +static int ccu_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct ccu_mux *cm =3D hw_to_ccu_mux(hw); + + return ccu_set_parent_helper(&cm->common, &cm->mux, index); +} + +static const struct clk_ops ccu_mux_ops =3D { + .get_parent =3D ccu_mux_get_parent, + .set_parent =3D ccu_mux_set_parent, + .determine_rate =3D __clk_mux_determine_rate, +}; + +void ccu_disable_helper(struct ccu_common *common, u32 gate) +{ + if (!gate) + return; + + regmap_update_bits(common->map, common->reg, + gate, ~gate); +} + +int ccu_enable_helper(struct ccu_common *common, u32 gate) +{ + if (!gate) + return 0; + + return regmap_update_bits(common->map, common->reg, + gate, gate); +} + +static int ccu_is_enabled_helper(struct ccu_common *common, u32 gate) +{ + unsigned int val; + + if (!gate) + return true; + + regmap_read(common->map, common->reg, &val); + return val & gate; +} + +static int ccu_gate_is_enabled(struct clk_hw *hw) +{ + struct ccu_gate *cg =3D hw_to_ccu_gate(hw); + + return ccu_is_enabled_helper(&cg->common, cg->enable); +} + +static void ccu_gate_disable(struct clk_hw *hw) +{ + struct ccu_gate *cg =3D hw_to_ccu_gate(hw); + + ccu_disable_helper(&cg->common, cg->enable); +} + +static int ccu_gate_enable(struct clk_hw *hw) +{ + struct ccu_gate *cg =3D hw_to_ccu_gate(hw); + + return ccu_enable_helper(&cg->common, cg->enable); +} + +static const struct clk_ops ccu_gate_ops =3D { + .disable =3D ccu_gate_disable, + .enable =3D ccu_gate_enable, + .is_enabled =3D ccu_gate_is_enabled, +}; + +static unsigned long ccu_div_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ccu_div *cd =3D hw_to_ccu_div(hw); + unsigned int val; + + regmap_read(cd->common.map, cd->common.reg, &val); + val =3D val >> cd->div.shift; + val &=3D GENMASK(cd->div.width - 1, 0); + + val =3D divider_recalc_rate(hw, parent_rate, val, NULL, + cd->div.flags, cd->div.width); + + return val; +} + +static u8 ccu_div_get_parent(struct clk_hw *hw) +{ + struct ccu_div *cd =3D hw_to_ccu_div(hw); + + return ccu_get_parent_helper(&cd->common, &cd->mux); +} + +static int ccu_div_set_parent(struct clk_hw *hw, u8 index) +{ + struct ccu_div *cd =3D hw_to_ccu_div(hw); + + return ccu_set_parent_helper(&cd->common, &cd->mux, index); +} + +static void ccu_div_disable(struct clk_hw *hw) +{ + struct ccu_div *cd =3D hw_to_ccu_div(hw); + + ccu_disable_helper(&cd->common, cd->enable); +} + +static int ccu_div_enable(struct clk_hw *hw) +{ + struct ccu_div *cd =3D hw_to_ccu_div(hw); + + return ccu_enable_helper(&cd->common, cd->enable); +} + +static int ccu_div_is_enabled(struct clk_hw *hw) +{ + struct ccu_div *cd =3D hw_to_ccu_div(hw); + + return ccu_is_enabled_helper(&cd->common, cd->enable); +} + +static const struct clk_ops ccu_div_ops =3D { + .disable =3D ccu_div_disable, + .enable =3D ccu_div_enable, + .is_enabled =3D ccu_div_is_enabled, + .get_parent =3D ccu_div_get_parent, + .set_parent =3D ccu_div_set_parent, + .recalc_rate =3D ccu_div_recalc_rate, +}; + + +static unsigned long ccu_mdiv_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ccu_mdiv *mdiv =3D hw_to_ccu_mdiv(hw); + unsigned long div, rate =3D parent_rate; + unsigned int m, d, i, v, val; + + regmap_read(mdiv->common.map, mdiv->common.reg, &val); + + m =3D val >> mdiv->m.shift; + m &=3D GENMASK(mdiv->m.width - 1, 0); + + d =3D val >> mdiv->d.shift; + d &=3D GENMASK(mdiv->d.width - 1, 0); + + i =3D val >> mdiv->i.shift; + i &=3D GENMASK(mdiv->i.width - 1, 0); + + v =3D val >> mdiv->v.shift; + v &=3D GENMASK(mdiv->v.width - 1, 0); + + rate =3D parent_rate * m; + div =3D d * i * v; + do_div(rate, div); + + return rate; +} + +static const struct clk_ops clk_mdiv_ops =3D { + .recalc_rate =3D ccu_mdiv_recalc_rate, +}; + +static struct ccu_mdiv pll_cpu0_clk =3D { + .m =3D TH_CCU_ARG(8, 12), + .d =3D TH_CCU_ARG(24, 3), + .i =3D TH_CCU_ARG(20, 3), + .v =3D TH_CCU_ARG(0, 6), + .common =3D { + .reg =3D 0x000, + .hw.init =3D CLK_HW_INIT("pll-cpu0", "osc24m", + &clk_mdiv_ops, + 0), + }, +}; + +static struct ccu_mdiv pll_cpu1_clk =3D { + .m =3D TH_CCU_ARG(8, 12), + .d =3D TH_CCU_ARG(24, 3), + .i =3D TH_CCU_ARG(20, 3), + .v =3D TH_CCU_ARG(0, 6), + .common =3D { + .reg =3D 0x010, + .hw.init =3D CLK_HW_INIT("pll-cpu1", "osc24m", + &clk_mdiv_ops, + 0), + }, +}; + +static struct ccu_mdiv pll_gmac_clk =3D { + .m =3D TH_CCU_ARG(8, 12), + .d =3D TH_CCU_ARG(24, 3), + .i =3D TH_CCU_ARG(20, 3), + .v =3D TH_CCU_ARG(0, 6), + .common =3D { + .reg =3D 0x020, + .hw.init =3D CLK_HW_INIT("pll-gmac", "osc24m", + &clk_mdiv_ops, + 0), + }, +}; + +static struct ccu_mdiv pll_video_clk =3D { + .m =3D TH_CCU_ARG(8, 12), + .d =3D TH_CCU_ARG(24, 3), + .i =3D TH_CCU_ARG(20, 3), + .v =3D TH_CCU_ARG(0, 6), + .common =3D { + .reg =3D 0x030, + .hw.init =3D CLK_HW_INIT("pll-video", "osc24m", + &clk_mdiv_ops, + 0), + }, +}; + +static struct ccu_mdiv pll_dpu0_clk =3D { + .m =3D TH_CCU_ARG(8, 12), + .d =3D TH_CCU_ARG(24, 3), + .i =3D TH_CCU_ARG(20, 3), + .v =3D TH_CCU_ARG(0, 6), + .common =3D { + .reg =3D 0x040, + .hw.init =3D CLK_HW_INIT("pll-dpu0", "osc24m", + &clk_mdiv_ops, + 0), + }, +}; + +static struct ccu_mdiv pll_dpu1_clk =3D { + .m =3D TH_CCU_ARG(8, 12), + .d =3D TH_CCU_ARG(24, 3), + .i =3D TH_CCU_ARG(20, 3), + .v =3D TH_CCU_ARG(0, 6), + .common =3D { + .reg =3D 0x050, + .hw.init =3D CLK_HW_INIT("pll-dpu1", "osc24m", + &clk_mdiv_ops, + 0), + }, +}; + +static struct ccu_mdiv pll_tee_clk =3D { + .m =3D TH_CCU_ARG(8, 12), + .d =3D TH_CCU_ARG(24, 3), + .i =3D TH_CCU_ARG(20, 3), + .v =3D TH_CCU_ARG(0, 6), + .common =3D { + .reg =3D 0x060, + .hw.init =3D CLK_HW_INIT("pll-tee", "osc24m", + &clk_mdiv_ops, + 0), + }, +}; + +static const char * const c910_i0_parents[] =3D { "pll-cpu0", "osc24m" }; +struct ccu_mux c910_i0_clk =3D { + .mux =3D TH_CCU_ARG(1, 1), + .common =3D { + .reg =3D 00100, + .hw.init =3D CLK_HW_INIT_PARENTS("c910-i0", + c910_i0_parents, + &ccu_mux_ops, + 0), + } +}; + +static const char * const c910_parents[] =3D { "c910-i0", "pll-cpu1" }; +struct ccu_mux c910_clk =3D { + .mux =3D TH_CCU_ARG(0, 1), + .common =3D { + .reg =3D 0x100, + .hw.init =3D CLK_HW_INIT_PARENTS("c910", + c910_parents, + &ccu_mux_ops, + 0), + } +}; + +static CCU_GATE(brom_clk, "brom", "ahb2", + 0x100, BIT(4), 0); + +static CCU_GATE(bmu_clk, "bmu", "axi4", + 0x100, BIT(5), 0); + +static const char * const ahb2_parents[] =3D { "pll-gmac", "osc24m" }; +static struct ccu_div ahb2_clk =3D { + .div =3D TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED), + .mux =3D TH_CCU_ARG(5, 1), + .common =3D { + .reg =3D 0x120, + .hw.init =3D CLK_HW_INIT_PARENTS("ahb2", + ahb2_parents, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div apb3_clk =3D { + .div =3D TH_CCU_ARG(0, 3), + .common =3D { + .reg =3D 0x130, + .hw.init =3D CLK_HW_INIT("apb3", "ahb2", + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div axi4_clk =3D { + .div =3D TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED), + .common =3D { + .reg =3D 0x134, + .hw.init =3D CLK_HW_INIT("axi4", "pll-gmac", + &ccu_div_ops, + 0), + }, +}; + +static CCU_GATE(aon2cpu_clk, "aon2cpu", "axi4", + 0x134, BIT(8), 0); + +static CCU_GATE(x2x_clk, "x2x", "axi4", + 0x134, BIT(7), 0); + +static const char * const axi_parents[] =3D { "pll-video", "osc24m" }; +static struct ccu_div axi_clk =3D { + .div =3D TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED), + .mux =3D TH_CCU_ARG(5, 1), + .common =3D { + .reg =3D 0x138, + .hw.init =3D CLK_HW_INIT_PARENTS("axi", + axi_parents, + &ccu_div_ops, + 0), + }, +}; + +static CCU_GATE(cpu2aon_clk, "cpu2aon", "axi", + 0x138, BIT(8), 0); + +static const char * const peri_ahb_parents[] =3D { "pll-gmac", "osc24m" }; +static struct ccu_div peri_ahb_clk =3D { + .enable =3D BIT(6), + .div =3D TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED), + .mux =3D TH_CCU_ARG(5, 1), + .common =3D { + .reg =3D 0x140, + .hw.init =3D CLK_HW_INIT_PARENTS("peri-ahb", + peri_ahb_parents, + &ccu_div_ops, + 0), + }, +}; + +static CCU_GATE(cpu2peri_clk, "cpu2peri", "axi4", + 0x140, BIT(9), 0); + +static struct ccu_div peri_apb_clk =3D { + .div =3D TH_CCU_ARG(0, 3), + .common =3D { + .reg =3D 0x150, + .hw.init =3D CLK_HW_INIT("peri-apb", "peri-ahb", + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div peri2apb_clk =3D { + .div =3D TH_CCU_DIV_FLAGS(4, 3, CLK_DIVIDER_ONE_BASED), + .common =3D { + .reg =3D 0x150, + .hw.init =3D CLK_HW_INIT("peri2apb", + "pll-gmac", + &ccu_div_ops, + 0), + }, +}; + +static CCU_GATE(peri_apb1_clk, "peri-apb1", "peri-ahb", + 0x150, BIT(9), 0); + +static CCU_GATE(peri_apb2_clk, "peri-apb2", "peri-ahb", + 0x150, BIT(10), 0); + +static CCU_GATE(peri_apb3_clk, "peri-apb3", "peri-ahb", + 0x150, BIT(11), 0); + +static CCU_GATE(peri_apb4_clk, "peri-apb4", "peri-ahb", + 0x150, BIT(12), 0); + +static CLK_FIXED_FACTOR_FW_NAME(osc12m_clk, "osc12m", "hosc", 2, 1, 0); + +static const char * const out_parents[] =3D { "osc24m", "osc12m" }; + +static struct ccu_div out1_clk =3D { + .enable =3D BIT(5), + .div =3D TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED), + .mux =3D TH_CCU_ARG(4, 1), + .common =3D { + .reg =3D 0x1b4, + .hw.init =3D CLK_HW_INIT_PARENTS("out1", + out_parents, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div out2_clk =3D { + .enable =3D BIT(5), + .div =3D TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED), + .mux =3D TH_CCU_ARG(4, 1), + .common =3D { + .reg =3D 0x1b8, + .hw.init =3D CLK_HW_INIT_PARENTS("out2", + out_parents, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div out3_clk =3D { + .enable =3D BIT(5), + .div =3D TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED), + .mux =3D TH_CCU_ARG(4, 1), + .common =3D { + .reg =3D 0x1bc, + .hw.init =3D CLK_HW_INIT_PARENTS("out3", + out_parents, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div out4_clk =3D { + .enable =3D BIT(5), + .div =3D TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED), + .mux =3D TH_CCU_ARG(4, 1), + .common =3D { + .reg =3D 0x1c0, + .hw.init =3D CLK_HW_INIT_PARENTS("out4", + out_parents, + &ccu_div_ops, + 0), + }, +}; + +static const char * const apb_parents[] =3D { "pll-gmac", "osc24m" }; +static struct ccu_div apb_clk =3D { + .enable =3D BIT(5), + .div =3D TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED), + .mux =3D TH_CCU_ARG(7, 1), + .common =3D { + .reg =3D 0x1c4, + .hw.init =3D CLK_HW_INIT_PARENTS("apb", + apb_parents, + &ccu_div_ops, + 0), + }, +}; + +static const char * const npu_parents[] =3D { "pll-gmac", "pll-video" }; +static struct ccu_div npu_clk =3D { + .enable =3D BIT(5), + .div =3D TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED), + .mux =3D TH_CCU_ARG(6, 1), + .common =3D { + .reg =3D 0x1c8, + .hw.init =3D CLK_HW_INIT_PARENTS("npu", + npu_parents, + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div vi_clk =3D { + .div =3D TH_CCU_DIV_FLAGS(16, 4, CLK_DIVIDER_ONE_BASED), + .common =3D { + .reg =3D 0x1d0, + .hw.init =3D CLK_HW_INIT("vi", + "pll-video", + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div vi_ahb_clk =3D { + .div =3D TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED), + .common =3D { + .reg =3D 0x1d0, + .hw.init =3D CLK_HW_INIT("vi-ahb", + "pll-video", + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div vo_axi_clk =3D { + .enable =3D BIT(5), + .div =3D TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED), + .common =3D { + .reg =3D 0x1dc, + .hw.init =3D CLK_HW_INIT("vo-axi", + "pll-video", + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div vp_apb_clk =3D { + .div =3D TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED), + .common =3D { + .reg =3D 0x1e0, + .hw.init =3D CLK_HW_INIT("vp-apb", + "pll-gmac", + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div vp_axi_clk =3D { + .enable =3D BIT(15), + .div =3D TH_CCU_DIV_FLAGS(8, 4, CLK_DIVIDER_ONE_BASED), + .common =3D { + .reg =3D 0x1e0, + .hw.init =3D CLK_HW_INIT("vp-axi", + "pll-video", + &ccu_div_ops, + 0), + }, +}; + +static CCU_GATE(cpu2vp_clk, "cpu2vp", "axi", + 0x1e0, BIT(13), 0); + +static struct ccu_div venc_clk =3D { + .enable =3D BIT(5), + .div =3D TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED), + .common =3D { + .reg =3D 0x1e4, + .hw.init =3D CLK_HW_INIT("venc", + "pll-gmac", + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div dpu0_clk =3D { + .div =3D TH_CCU_DIV_FLAGS(0, 8, CLK_DIVIDER_ONE_BASED), + .common =3D { + .reg =3D 0x1e8, + .hw.init =3D CLK_HW_INIT("dpu0", + "pll-dpu0", + &ccu_div_ops, + 0), + }, +}; + +static struct ccu_div dpu1_clk =3D { + .div =3D TH_CCU_DIV_FLAGS(0, 8, CLK_DIVIDER_ONE_BASED), + .common =3D { + .reg =3D 0x1ec, + .hw.init =3D CLK_HW_INIT("dpu1", + "pll-dpu1", + &ccu_div_ops, + 0), + }, +}; + +static CCU_GATE(mmc_clk, "mmc", "pll-video", 0x204, BIT(30), 0); +static CCU_GATE(gmac1_clk, "gmac1", "pll-gmac", 0x204, BIT(26), 0); +static CCU_GATE(padctrl1_clk, "padctrl1", "peri-apb", 0x204, BIT(24), 0); +static CCU_GATE(dsmart_clk, "dsmart", "peri-apb", 0x204, BIT(23), 0); +static CCU_GATE(padctrl0_clk, "padctrl0", "peri-apb", 0x204, BIT(22), 0); +static CCU_GATE(gmac_axi_clk, "gmac-axi", "axi4", 0x204, BIT(21), 0); +static CCU_GATE(gmac0_clk, "gmac0", "pll-gmac", 0x204, BIT(19), 0); +static CCU_GATE(pwm_clk, "pwm", "peri-apb", 0x204, BIT(18), 0); +static CCU_GATE(qspi0_clk, "qspi0", "pll-video", 0x204, BIT(17), 0); +static CCU_GATE(qspi1_clk, "qspi1", "pll-video", 0x204, BIT(16), 0); +static CCU_GATE(spi_clk, "spi", "pll-video", 0x204, BIT(15), 0); +static CCU_GATE(uart0_clk, "uart0", "peri-apb", 0x204, BIT(14), 0); +static CCU_GATE(uart1_clk, "uart1", "peri-apb", 0x204, BIT(13), 0); +static CCU_GATE(uart2_clk, "uart2", "peri-apb", 0x204, BIT(12), 0); +static CCU_GATE(uart3_clk, "uart3", "peri-apb", 0x204, BIT(11), 0); +static CCU_GATE(uart4_clk, "uart4", "peri-apb", 0x204, BIT(10), 0); +static CCU_GATE(uart5_clk, "uart5", "peri-apb", 0x204, BIT(9), 0); +static CCU_GATE(i2c0_clk, "i2c0", "peri-apb", 0x204, BIT(5), 0); +static CCU_GATE(i2c1_clk, "i2c1", "peri-apb", 0x204, BIT(4), 0); +static CCU_GATE(i2c2_clk, "i2c2", "peri-apb", 0x204, BIT(3), 0); +static CCU_GATE(i2c3_clk, "i2c3", "peri-apb", 0x204, BIT(2), 0); +static CCU_GATE(i2c4_clk, "i2c4", "peri-apb", 0x204, BIT(1), 0); +static CCU_GATE(i2c5_clk, "i2c5", "peri-apb", 0x204, BIT(0), 0); + +static CCU_GATE(spinlock_clk, "spinlock", "ahb2", 0x208, BIT(10), 0); +static CCU_GATE(dma_clk, "dma", "axi4", 0x208, BIT(8), 0); +static CCU_GATE(mbox0_clk, "mbox0", "apb3", 0x208, BIT(7), 0); +static CCU_GATE(mbox1_clk, "mbox1", "apb3", 0x208, BIT(6), 0); +static CCU_GATE(mbox2_clk, "mbox2", "apb3", 0x208, BIT(5), 0); +static CCU_GATE(mbox3_clk, "mbox3", "apb3", 0x208, BIT(4), 0); +static CCU_GATE(wdt0_clk, "wdt0", "apb3", 0x208, BIT(3), 0); +static CCU_GATE(wdt1_clk, "wdt1", "apb3", 0x208, BIT(2), 0); +static CCU_GATE(timer0_clk, "timer0", "apb3", 0x208, BIT(1), 0); +static CCU_GATE(timer1_clk, "timer1", "apb3", 0x208, BIT(0), 0); + +static CCU_GATE(sram0_clk, "sram0", "axi", 0x20c, BIT(4), 0); +static CCU_GATE(sram1_clk, "sram1", "axi", 0x20c, BIT(3), 0); +static CCU_GATE(sram2_clk, "sram2", "axi", 0x20c, BIT(2), 0); +static CCU_GATE(sram3_clk, "sram3", "axi", 0x20c, BIT(1), 0); + +static CLK_FIXED_FACTOR_HW(pll_gmac_100m_clk, "pll-gmac-100m", + &pll_gmac_clk.common.hw, + 10, 1, 0); + +static const char * const uart_parents[] =3D { "pll-gmac-100m", "osc24m" }; +struct ccu_mux uart_clk =3D { + .mux =3D TH_CCU_ARG(0, 1), + .common =3D { + .reg =3D 0x210, + .hw.init =3D CLK_HW_INIT_PARENTS("uart", + uart_parents, + &ccu_mux_ops, + 0), + } +}; + +static struct ccu_common *th1520_clks[] =3D { + &pll_cpu0_clk.common, + &pll_cpu1_clk.common, + &pll_gmac_clk.common, + &pll_video_clk.common, + &pll_dpu0_clk.common, + &pll_dpu1_clk.common, + &pll_tee_clk.common, + &c910_i0_clk.common, + &c910_clk.common, + &brom_clk.common, + &bmu_clk.common, + &ahb2_clk.common, + &apb3_clk.common, + &axi4_clk.common, + &aon2cpu_clk.common, + &x2x_clk.common, + &axi_clk.common, + &cpu2aon_clk.common, + &peri_ahb_clk.common, + &cpu2peri_clk.common, + &peri_apb_clk.common, + &peri2apb_clk.common, + &peri_apb1_clk.common, + &peri_apb2_clk.common, + &peri_apb3_clk.common, + &peri_apb4_clk.common, + &out1_clk.common, + &out2_clk.common, + &out3_clk.common, + &out4_clk.common, + &apb_clk.common, + &npu_clk.common, + &vi_clk.common, + &vi_ahb_clk.common, + &vo_axi_clk.common, + &vp_apb_clk.common, + &vp_axi_clk.common, + &cpu2vp_clk.common, + &venc_clk.common, + &dpu0_clk.common, + &dpu1_clk.common, + &mmc_clk.common, + &gmac1_clk.common, + &padctrl1_clk.common, + &dsmart_clk.common, + &padctrl0_clk.common, + &gmac_axi_clk.common, + &gmac0_clk.common, + &pwm_clk.common, + &qspi0_clk.common, + &qspi1_clk.common, + &spi_clk.common, + &uart0_clk.common, + &uart1_clk.common, + &uart2_clk.common, + &uart3_clk.common, + &uart4_clk.common, + &uart5_clk.common, + &i2c0_clk.common, + &i2c1_clk.common, + &i2c2_clk.common, + &i2c3_clk.common, + &i2c4_clk.common, + &i2c5_clk.common, + &spinlock_clk.common, + &dma_clk.common, + &mbox0_clk.common, + &mbox1_clk.common, + &mbox2_clk.common, + &mbox3_clk.common, + &wdt0_clk.common, + &wdt1_clk.common, + &timer0_clk.common, + &timer1_clk.common, + &sram0_clk.common, + &sram1_clk.common, + &sram2_clk.common, + &sram3_clk.common, + &uart_clk.common, +}; + +#define NR_CLKS (CLK_UART + 1) + +static struct clk_hw_onecell_data th1520_hw_clks =3D { + .hws =3D { + [CLK_OSC12M] =3D &osc12m_clk.hw, + [CLK_PLL_CPU0] =3D &pll_cpu0_clk.common.hw, + [CLK_PLL_CPU1] =3D &pll_cpu1_clk.common.hw, + [CLK_PLL_GMAC] =3D &pll_gmac_clk.common.hw, + [CLK_PLL_VIDEO] =3D &pll_video_clk.common.hw, + [CLK_PLL_DPU0] =3D &pll_dpu0_clk.common.hw, + [CLK_PLL_DPU1] =3D &pll_dpu1_clk.common.hw, + [CLK_PLL_TEE] =3D &pll_tee_clk.common.hw, + [CLK_C910_I0] =3D &c910_i0_clk.common.hw, + [CLK_C910] =3D &c910_clk.common.hw, + [CLK_BROM] =3D &brom_clk.common.hw, + [CLK_BMU] =3D &bmu_clk.common.hw, + [CLK_AHB2] =3D &ahb2_clk.common.hw, + [CLK_APB3] =3D &apb3_clk.common.hw, + [CLK_AXI4] =3D &axi4_clk.common.hw, + [CLK_AON2CPU] =3D &aon2cpu_clk.common.hw, + [CLK_X2X] =3D &x2x_clk.common.hw, + [CLK_AXI] =3D &axi_clk.common.hw, + [CLK_CPU2AON] =3D &cpu2aon_clk.common.hw, + [CLK_PERI_AHB] =3D &peri_ahb_clk.common.hw, + [CLK_CPU2PERI] =3D &cpu2peri_clk.common.hw, + [CLK_PERI_APB] =3D &peri_apb_clk.common.hw, + [CLK_PERI2APB] =3D &peri2apb_clk.common.hw, + [CLK_PERI_APB1] =3D &peri_apb1_clk.common.hw, + [CLK_PERI_APB2] =3D &peri_apb2_clk.common.hw, + [CLK_PERI_APB3] =3D &peri_apb3_clk.common.hw, + [CLK_PERI_APB4] =3D &peri_apb4_clk.common.hw, + [CLK_OUT1] =3D &out1_clk.common.hw, + [CLK_OUT2] =3D &out2_clk.common.hw, + [CLK_OUT3] =3D &out3_clk.common.hw, + [CLK_OUT4] =3D &out4_clk.common.hw, + [CLK_APB] =3D &apb_clk.common.hw, + [CLK_NPU] =3D &npu_clk.common.hw, + [CLK_VI] =3D &vi_clk.common.hw, + [CLK_VI_AHB] =3D &vi_ahb_clk.common.hw, + [CLK_VO_AXI] =3D &vo_axi_clk.common.hw, + [CLK_VP_APB] =3D &vp_apb_clk.common.hw, + [CLK_VP_AXI] =3D &vp_axi_clk.common.hw, + [CLK_CPU2VP] =3D &cpu2vp_clk.common.hw, + [CLK_VENC] =3D &venc_clk.common.hw, + [CLK_DPU0] =3D &dpu0_clk.common.hw, + [CLK_DPU1] =3D &dpu1_clk.common.hw, + [CLK_MMC] =3D &mmc_clk.common.hw, + [CLK_GMAC] =3D &gmac1_clk.common.hw, + [CLK_PADCTRL1] =3D &padctrl1_clk.common.hw, + [CLK_DSMART] =3D &dsmart_clk.common.hw, + [CLK_PADCTRL0] =3D &padctrl0_clk.common.hw, + [CLK_GMAC_AXI] =3D &gmac_axi_clk.common.hw, + [CLK_GMAC0] =3D &gmac0_clk.common.hw, + [CLK_PWM] =3D &pwm_clk.common.hw, + [CLK_QSPI0] =3D &qspi0_clk.common.hw, + [CLK_QSPI1] =3D &qspi1_clk.common.hw, + [CLK_SPI] =3D &spi_clk.common.hw, + [CLK_UART0] =3D &uart0_clk.common.hw, + [CLK_UART1] =3D &uart1_clk.common.hw, + [CLK_UART2] =3D &uart2_clk.common.hw, + [CLK_UART3] =3D &uart3_clk.common.hw, + [CLK_UART4] =3D &uart4_clk.common.hw, + [CLK_UART5] =3D &uart5_clk.common.hw, + [CLK_I2C0] =3D &i2c0_clk.common.hw, + [CLK_I2C1] =3D &i2c1_clk.common.hw, + [CLK_I2C2] =3D &i2c2_clk.common.hw, + [CLK_I2C3] =3D &i2c3_clk.common.hw, + [CLK_I2C4] =3D &i2c4_clk.common.hw, + [CLK_I2C5] =3D &i2c5_clk.common.hw, + [CLK_SPINLOCK] =3D &spinlock_clk.common.hw, + [CLK_DMA] =3D &dma_clk.common.hw, + [CLK_MBOX0] =3D &mbox0_clk.common.hw, + [CLK_MBOX1] =3D &mbox1_clk.common.hw, + [CLK_MBOX2] =3D &mbox2_clk.common.hw, + [CLK_MBOX3] =3D &mbox3_clk.common.hw, + [CLK_WDT0] =3D &wdt0_clk.common.hw, + [CLK_WDT1] =3D &wdt1_clk.common.hw, + [CLK_TIMER0] =3D &timer0_clk.common.hw, + [CLK_TIMER1] =3D &timer1_clk.common.hw, + [CLK_SRAM0] =3D &sram0_clk.common.hw, + [CLK_SRAM1] =3D &sram1_clk.common.hw, + [CLK_SRAM2] =3D &sram2_clk.common.hw, + [CLK_SRAM3] =3D &sram3_clk.common.hw, + [CLK_PLL_GMAC_100M] =3D &pll_gmac_100m_clk.hw, + [CLK_UART] =3D &uart_clk.common.hw, + }, + .num =3D NR_CLKS, +}; + +static const struct regmap_config config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .fast_io =3D true, +}; + +static int th1520_clock_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct regmap *map; + void __iomem *regs; + int ret, i; + + regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(regs)) + return PTR_ERR(regs); + + map =3D devm_regmap_init_mmio(dev, regs, &config); + if (IS_ERR(map)) + return PTR_ERR(map); + + for (i =3D 0; i < ARRAY_SIZE(th1520_clks); i++) + th1520_clks[i]->map =3D map; + + for (i =3D 0; i < th1520_hw_clks.num; i++) { + ret =3D devm_clk_hw_register(dev, th1520_hw_clks.hws[i]); + if (ret) + return ret; + } + + ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + &th1520_hw_clks); + if (ret) + return ret; + + return 0; +} + +static const struct of_device_id clk_match_table[] =3D { + { + .compatible =3D "thead,th1520-ccu", + }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, clk_match_table); + +static struct platform_driver th1520_clk_driver =3D { + .probe =3D th1520_clock_probe, + .driver =3D { + .name =3D "th1520-clk", + .of_match_table =3D clk_match_table, + }, +}; +module_platform_driver(th1520_clk_driver); + +MODULE_DESCRIPTION("T-HEAD th1520 Clock driver"); +MODULE_AUTHOR("Yangtao Li "); +MODULE_LICENSE("GPL"); diff --git a/include/dt-bindings/clock/th1520-clock.h b/include/dt-bindings= /clock/th1520-clock.h new file mode 100644 index 000000000000..e5a1e1c127fc --- /dev/null +++ b/include/dt-bindings/clock/th1520-clock.h @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Vivo Communication Technology Co. Ltd. + * Authors: Yangtao Li + */ + +#ifndef _DT_BINDINGS_CLK_TH1520_H_ +#define _DT_BINDINGS_CLK_TH1520_H_ + +#define CLK_PLL_CPU0 0 +#define CLK_PLL_CPU1 1 +#define CLK_PLL_GMAC 2 +#define CLK_PLL_VIDEO 3 +#define CLK_PLL_DPU0 4 +#define CLK_PLL_DPU1 5 +#define CLK_PLL_TEE 6 +#define CLK_C910_I0 7 +#define CLK_C910 8 +#define CLK_BROM 9 +#define CLK_BMU 10 +#define CLK_AHB2 11 +#define CLK_APB3 12 +#define CLK_AXI4 13 +#define CLK_AON2CPU 14 +#define CLK_X2X 15 +#define CLK_AXI 16 +#define CLK_CPU2AON 17 +#define CLK_PERI_AHB 18 +#define CLK_CPU2PERI 19 +#define CLK_PERI_APB 20 +#define CLK_PERI2APB 21 +#define CLK_PERI_APB1 22 +#define CLK_PERI_APB2 23 +#define CLK_PERI_APB3 24 +#define CLK_PERI_APB4 25 +#define CLK_OSC12M 26 +#define CLK_OUT1 27 +#define CLK_OUT2 28 +#define CLK_OUT3 29 +#define CLK_OUT4 30 +#define CLK_APB 31 +#define CLK_NPU 32 +#define CLK_VI 33 +#define CLK_VI_AHB 34 +#define CLK_VO_AXI 35 +#define CLK_VP_APB 36 +#define CLK_VP_AXI 37 +#define CLK_CPU2VP 38 +#define CLK_VENC 39 +#define CLK_DPU0 40 +#define CLK_DPU1 41 +#define CLK_MMC 42 +#define CLK_GMAC 43 +#define CLK_PADCTRL1 44 +#define CLK_DSMART 45 +#define CLK_PADCTRL0 46 +#define CLK_GMAC_AXI 47 +#define CLK_GMAC0 48 +#define CLK_PWM 49 +#define CLK_QSPI0 50 +#define CLK_QSPI1 51 +#define CLK_SPI 52 +#define CLK_UART0 53 +#define CLK_UART1 54 +#define CLK_UART2 55 +#define CLK_UART3 56 +#define CLK_UART4 57 +#define CLK_UART5 58 +#define CLK_I2C0 59 +#define CLK_I2C1 60 +#define CLK_I2C2 61 +#define CLK_I2C3 62 +#define CLK_I2C4 63 +#define CLK_I2C5 64 +#define CLK_SPINLOCK 65 +#define CLK_DMA 66 +#define CLK_MBOX0 67 +#define CLK_MBOX1 68 +#define CLK_MBOX2 69 +#define CLK_MBOX3 70 +#define CLK_WDT0 71 +#define CLK_WDT1 72 +#define CLK_TIMER0 73 +#define CLK_TIMER1 74 +#define CLK_SRAM0 75 +#define CLK_SRAM1 76 +#define CLK_SRAM2 77 +#define CLK_SRAM3 78 +#define CLK_PLL_GMAC_100M 79 +#define CLK_UART 80 + +#endif --=20 2.39.0 From nobody Sun Feb 8 18:44:02 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38B11C7EE24 for ; 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charset="utf-8" Wei and me would like to help support and maintain too. Cc: Icenowy Zheng Cc: Wei Fu Cc: Jisheng Zhang Signed-off-by: Yangtao Li --- MAINTAINERS | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index e1e51accec4f..dc35c654f78e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18155,11 +18155,15 @@ T: git https://git.kernel.org/pub/scm/linux/kerne= l/git/conor/linux.git/ F: Documentation/devicetree/bindings/riscv/ F: arch/riscv/boot/dts/ =20 -RISC-V THEAD SoC SUPPORT +RISC-V T-HEAD SOC SUPPORT M: Jisheng Zhang +M: Wei Fu +M: Yangtao Li L: linux-riscv@lists.infradead.org S: Maintained F: arch/riscv/boot/dts/thead/ +F: drivers/clk/clk-th1520.c +F: include/dt-bindings/clock/th1520-clock.h =20 RNBD BLOCK DRIVERS M: Md. Haris Iqbal --=20 2.39.0