From nobody Wed Dec 17 15:15:35 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61024C7EE2D for ; Fri, 12 May 2023 12:25:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241154AbjELMZz (ORCPT ); Fri, 12 May 2023 08:25:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54388 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241141AbjELMZa (ORCPT ); Fri, 12 May 2023 08:25:30 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB08C13294; Fri, 12 May 2023 05:25:02 -0700 (PDT) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34CBqgH9022835; Fri, 12 May 2023 12:24:55 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=Dbp+puz8VvkSOanxHS2LnYQBU3LwZbk3RTrmneyJX3Q=; b=NF5xajL0v6FP30+EkgoboICdJoymuqz/dIQqJGxTG6I95WcSy0IM9qiXx/9OLaXZvPpV H0pqdocQduCoYBLpT4pfzJLDQ8XgJp16VficATev8znW2FkVqSs8qdYlNkpOwWww0lFN fQGiPr6yfz49+Ov4/csRmenvaBJE4yJKZyr74qm0h83dFklivCZiDXv3PKS+Lyzv5olQ lA3oOj0NIB8BaI8Ggmjwf8e2GBXiDzRxOMZcOvdTojoMJy0eVs1sBkt0U7HzuW0m/rGM SgB62EvA9UblBeSTbbCdCJLzY6B74S9XQe0d3eY+9BiCYnNaZ6NZWpoVyKdOKBs7Dqpo Uw== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qh24h2g30-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 12 May 2023 12:24:54 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34CCOrsE032233 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 12 May 2023 12:24:53 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Fri, 12 May 2023 05:24:47 -0700 From: Taniya Das To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Richard Cochran , Conor Dooley , Andy Gross CC: Bjorn Andersson , Konrad Dybcio , Imran Shaik , , , , , , , , Taniya Das Subject: [PATCH V2 5/5] clk: qcom: Add GCC driver support for SDX75 Date: Fri, 12 May 2023 17:53:47 +0530 Message-ID: <20230512122347.1219-6-quic_tdas@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230512122347.1219-1-quic_tdas@quicinc.com> References: <20230512122347.1219-1-quic_tdas@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: PSKzBh296il4B_gHnWOnyknI8Kzbecre X-Proofpoint-ORIG-GUID: PSKzBh296il4B_gHnWOnyknI8Kzbecre X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-12_08,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 adultscore=0 priorityscore=1501 phishscore=0 impostorscore=0 suspectscore=0 malwarescore=0 bulkscore=0 mlxscore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305120103 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Imran Shaik Add Global Clock Controller (GCC) support for SDX75 platform. Signed-off-by: Imran Shaik Signed-off-by: Taniya Das --- Changes since V1: - Updated all the external clocks to index usage. - Updated the pcie pipe mux clk ops to clk_regmap_phy_mux_ops. - Updated the GDSC flags. - Updated the compatible and bindings header file name. drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-sdx75.c | 2970 ++++++++++++++++++++++++++++++++++ 3 files changed, 2979 insertions(+) create mode 100644 drivers/clk/qcom/gcc-sdx75.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 12be3e2371b3..61c760860750 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -679,6 +679,14 @@ config SDX_GCC_65 Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, SD/UFS, PCIe etc. =20 +config SDX_GCC_75 + tristate "SDX75 Global Clock Controller" + select QCOM_GDSC + help + Support for the global clock controller on SDX75 devices. + Say Y if you want to use peripheral devices such as UART, + SPI, I2C, USB, SD/eMMC, PCIe etc. + config SM_CAMCC_6350 tristate "SM6350 Camera Clock Controller" select SM_GCC_6350 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 9ff4c373ad95..1ee6e30eef0c 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -97,6 +97,7 @@ obj-$(CONFIG_SDM_LPASSCC_845) +=3D lpasscc-sdm845.o obj-$(CONFIG_SDM_VIDEOCC_845) +=3D videocc-sdm845.o obj-$(CONFIG_SDX_GCC_55) +=3D gcc-sdx55.o obj-$(CONFIG_SDX_GCC_65) +=3D gcc-sdx65.o +obj-$(CONFIG_SDX_GCC_75) +=3D gcc-sdx75.o obj-$(CONFIG_SM_CAMCC_6350) +=3D camcc-sm6350.o obj-$(CONFIG_SM_CAMCC_8250) +=3D camcc-sm8250.o obj-$(CONFIG_SM_CAMCC_8450) +=3D camcc-sm8450.o diff --git a/drivers/clk/qcom/gcc-sdx75.c b/drivers/clk/qcom/gcc-sdx75.c new file mode 100644 index 000000000000..b6772abdcec5 --- /dev/null +++ b/drivers/clk/qcom/gcc-sdx75.c @@ -0,0 +1,2970 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights re= served. + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_SLEEP_CLK, + DT_EMAC0_SGMIIPHY_MAC_RCLK, + DT_EMAC0_SGMIIPHY_MAC_TCLK, + DT_EMAC0_SGMIIPHY_RCLK, + DT_EMAC0_SGMIIPHY_TCLK, + DT_EMAC1_SGMIIPHY_MAC_RCLK, + DT_EMAC1_SGMIIPHY_MAC_TCLK, + DT_EMAC1_SGMIIPHY_RCLK, + DT_EMAC1_SGMIIPHY_TCLK, + DT_PCIE20_PHY_AUX_CLK, + DT_PCIE_1_PIPE_CLK, + DT_PCIE_2_PIPE_CLK, + DT_PCIE_PIPE_CLK, + DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, +}; + +enum { + P_BI_TCXO, + P_EMAC0_SGMIIPHY_MAC_RCLK, + P_EMAC0_SGMIIPHY_MAC_TCLK, + P_EMAC0_SGMIIPHY_RCLK, + P_EMAC0_SGMIIPHY_TCLK, + P_EMAC1_SGMIIPHY_MAC_RCLK, + P_EMAC1_SGMIIPHY_MAC_TCLK, + P_EMAC1_SGMIIPHY_RCLK, + P_EMAC1_SGMIIPHY_TCLK, + P_GPLL0_OUT_EVEN, + P_GPLL0_OUT_MAIN, + P_GPLL4_OUT_MAIN, + P_GPLL5_OUT_MAIN, + P_GPLL6_OUT_MAIN, + P_GPLL8_OUT_MAIN, + P_PCIE20_PHY_AUX_CLK, + P_PCIE_1_PIPE_CLK, + P_PCIE_2_PIPE_CLK, + P_PCIE_PIPE_CLK, + P_SLEEP_CLK, + P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, +}; + +static struct clk_alpha_pll gpll0 =3D { + .offset =3D 0x0, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .enable_reg =3D 0x7d000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpll0_out_even[] =3D { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpll0_out_even =3D { + .offset =3D 0x0, + .post_div_shift =3D 10, + .post_div_table =3D post_div_table_gpll0_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_gpll0_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll0_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &gpll0.clkr.hw, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static struct clk_alpha_pll gpll4 =3D { + .offset =3D 0x4000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .enable_reg =3D 0x7d000, + .enable_mask =3D BIT(4), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll4", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll5 =3D { + .offset =3D 0x5000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .enable_reg =3D 0x7d000, + .enable_mask =3D BIT(5), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll5", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll6 =3D { + .offset =3D 0x6000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .enable_reg =3D 0x7d000, + .enable_mask =3D BIT(6), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll6", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll8 =3D { + .offset =3D 0x8000, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr =3D { + .enable_reg =3D 0x7d000, + .enable_mask =3D BIT(8), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gpll8", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fixed_lucid_ole_ops, + }, + }, +}; + +static const struct parent_map gcc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL4_OUT_MAIN, 2 }, + { P_GPLL5_OUT_MAIN, 5 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll4.clkr.hw }, + { .hw =3D &gpll5.clkr.hw }, + { .hw =3D &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_SLEEP_CLK, 5 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpll0.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, + { .hw =3D &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_3[] =3D { + { .index =3D DT_BI_TCXO }, + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map gcc_parent_map_4[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_SLEEP_CLK, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_4[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpll0.clkr.hw }, + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct parent_map gcc_parent_map_5[] =3D { + { P_EMAC0_SGMIIPHY_RCLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_5[] =3D { + { .index =3D DT_EMAC0_SGMIIPHY_RCLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_6[] =3D { + { P_EMAC0_SGMIIPHY_TCLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_6[] =3D { + { .index =3D DT_EMAC0_SGMIIPHY_TCLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_7[] =3D { + { P_EMAC0_SGMIIPHY_MAC_RCLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_7[] =3D { + { .index =3D DT_EMAC0_SGMIIPHY_MAC_RCLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_8[] =3D { + { P_EMAC0_SGMIIPHY_MAC_TCLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_8[] =3D { + { .index =3D DT_EMAC0_SGMIIPHY_MAC_TCLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_9[] =3D { + { P_EMAC1_SGMIIPHY_RCLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_9[] =3D { + { .index =3D DT_EMAC1_SGMIIPHY_RCLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_10[] =3D { + { P_EMAC1_SGMIIPHY_TCLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_10[] =3D { + { .index =3D DT_EMAC1_SGMIIPHY_TCLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_11[] =3D { + { P_EMAC1_SGMIIPHY_MAC_RCLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_11[] =3D { + { .index =3D DT_EMAC1_SGMIIPHY_MAC_RCLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_12[] =3D { + { P_EMAC1_SGMIIPHY_MAC_TCLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_12[] =3D { + { .index =3D DT_EMAC1_SGMIIPHY_MAC_TCLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_15[] =3D { + { P_PCIE20_PHY_AUX_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_15[] =3D { + { .index =3D DT_PCIE20_PHY_AUX_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_17[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL6_OUT_MAIN, 2 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_17[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll6.clkr.hw }, + { .hw =3D &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_18[] =3D { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL8_OUT_MAIN, 2 }, + { P_GPLL0_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_18[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &gpll0.clkr.hw }, + { .hw =3D &gpll8.clkr.hw }, + { .hw =3D &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_19[] =3D { + { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_19[] =3D { + { .index =3D DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static struct clk_regmap_mux gcc_emac0_cc_sgmiiphy_rx_clk_src =3D { + .reg =3D 0x71060, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_5, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_cc_sgmiiphy_rx_clk_src", + .parent_data =3D gcc_parent_data_5, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_5), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_emac0_cc_sgmiiphy_tx_clk_src =3D { + .reg =3D 0x71058, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_6, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_cc_sgmiiphy_tx_clk_src", + .parent_data =3D gcc_parent_data_6, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_6), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_emac0_sgmiiphy_mac_rclk_src =3D { + .reg =3D 0x71098, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_7, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_sgmiiphy_mac_rclk_src", + .parent_data =3D gcc_parent_data_7, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_7), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_emac0_sgmiiphy_mac_tclk_src =3D { + .reg =3D 0x71094, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_8, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_sgmiiphy_mac_tclk_src", + .parent_data =3D gcc_parent_data_8, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_8), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_emac1_cc_sgmiiphy_rx_clk_src =3D { + .reg =3D 0x72060, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_9, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac1_cc_sgmiiphy_rx_clk_src", + .parent_data =3D gcc_parent_data_9, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_9), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_emac1_cc_sgmiiphy_tx_clk_src =3D { + .reg =3D 0x72058, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_10, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac1_cc_sgmiiphy_tx_clk_src", + .parent_data =3D gcc_parent_data_10, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_10), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_emac1_sgmiiphy_mac_rclk_src =3D { + .reg =3D 0x72098, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_11, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac1_sgmiiphy_mac_rclk_src", + .parent_data =3D gcc_parent_data_11, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_11), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_emac1_sgmiiphy_mac_tclk_src =3D { + .reg =3D 0x72094, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_12, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac1_sgmiiphy_mac_tclk_src", + .parent_data =3D gcc_parent_data_12, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_12), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src =3D { + .reg =3D 0x67084, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_PCIE_1_PIPE_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie_2_pipe_clk_src =3D { + .reg =3D 0x68050, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_2_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_PCIE_2_PIPE_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_pcie_aux_clk_src =3D { + .reg =3D 0x53074, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_15, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_aux_clk_src", + .parent_data =3D gcc_parent_data_15, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_15), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_pcie_pipe_clk_src =3D { + .reg =3D 0x53058, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_pipe_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_PCIE_PIPE_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_mux gcc_usb3_phy_pipe_clk_src =3D { + .reg =3D 0x27070, + .shift =3D 0, + .width =3D 2, + .parent_map =3D gcc_parent_map_19, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_phy_pipe_clk_src", + .parent_data =3D gcc_parent_data_19, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_19), + .ops =3D &clk_regmap_mux_closest_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_gcc_eee_emac0_clk_src[] =3D { + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_eee_emac0_clk_src =3D { + .cmd_rcgr =3D 0x710b0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_eee_emac0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_eee_emac0_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_eee_emac1_clk_src =3D { + .cmd_rcgr =3D 0x720b0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_eee_emac0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_eee_emac1_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_emac0_phy_aux_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_emac0_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0x7102c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_4, + .freq_tbl =3D ftbl_gcc_emac0_phy_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_phy_aux_clk_src", + .parent_data =3D gcc_parent_data_4, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_4), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_emac0_ptp_clk_src[] =3D { + F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), + F(125000000, P_GPLL4_OUT_MAIN, 4, 0, 0), + F(230400000, P_GPLL5_OUT_MAIN, 3.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_emac0_ptp_clk_src =3D { + .cmd_rcgr =3D 0x7107c, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_emac0_ptp_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_ptp_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_emac0_rgmii_clk_src[] =3D { + F(5000000, P_GPLL0_OUT_EVEN, 10, 1, 6), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(125000000, P_GPLL4_OUT_MAIN, 4, 0, 0), + F(250000000, P_GPLL4_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_emac0_rgmii_clk_src =3D { + .cmd_rcgr =3D 0x71064, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_emac0_rgmii_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_rgmii_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_emac1_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0x7202c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_4, + .freq_tbl =3D ftbl_gcc_emac0_phy_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac1_phy_aux_clk_src", + .parent_data =3D gcc_parent_data_4, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_4), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_emac1_ptp_clk_src =3D { + .cmd_rcgr =3D 0x7207c, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_emac0_ptp_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac1_ptp_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_emac1_rgmii_clk_src =3D { + .cmd_rcgr =3D 0x72064, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_1, + .freq_tbl =3D ftbl_gcc_emac0_rgmii_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac1_rgmii_clk_src", + .parent_data =3D gcc_parent_data_1, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_1), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_gp1_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_gp1_clk_src =3D { + .cmd_rcgr =3D 0x47004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp1_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_gp2_clk_src =3D { + .cmd_rcgr =3D 0x48004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp2_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_gp3_clk_src =3D { + .cmd_rcgr =3D 0x49004, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_gp1_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp3_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_1_aux_phy_clk_src =3D { + .cmd_rcgr =3D 0x67044, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_emac0_phy_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_aux_phy_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcie_1_phy_rchng_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src =3D { + .cmd_rcgr =3D 0x6706c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_pcie_1_phy_rchng_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_phy_rchng_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_2_aux_phy_clk_src =3D { + .cmd_rcgr =3D 0x68064, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_emac0_phy_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_2_aux_phy_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_2_phy_rchng_clk_src =3D { + .cmd_rcgr =3D 0x68038, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_pcie_1_phy_rchng_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_2_phy_rchng_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_aux_phy_clk_src =3D { + .cmd_rcgr =3D 0x5305c, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_emac0_phy_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_aux_phy_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_rchng_phy_clk_src =3D { + .cmd_rcgr =3D 0x53078, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_2, + .freq_tbl =3D ftbl_gcc_pcie_1_phy_rchng_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_rchng_phy_clk_src", + .parent_data =3D gcc_parent_data_2, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_2), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pdm2_clk_src =3D { + .cmd_rcgr =3D 0x34010, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_pdm2_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pdm2_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] =3D { + F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), + F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625), + F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75), + F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25), + F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75), + F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), + F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15), + F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s0_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src =3D { + .cmd_rcgr =3D 0x6c010, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s0_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s1_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src =3D { + .cmd_rcgr =3D 0x6c148, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s1_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s2_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src =3D { + .cmd_rcgr =3D 0x6c280, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s2_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s3_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src =3D { + .cmd_rcgr =3D 0x6c3b8, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s3_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s4_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src =3D { + .cmd_rcgr =3D 0x6c4f0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s4_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s5_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src =3D { + .cmd_rcgr =3D 0x6c628, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s5_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s6_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src =3D { + .cmd_rcgr =3D 0x6c760, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s6_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s7_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src =3D { + .cmd_rcgr =3D 0x6c898, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s7_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s8_clk_src_init =3D { + .name =3D "gcc_qupv3_wrap0_s8_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s8_clk_src =3D { + .cmd_rcgr =3D 0x6c9d0, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init =3D &gcc_qupv3_wrap0_s8_clk_src_init, +}; + +static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] =3D { + F(144000, P_BI_TCXO, 16, 3, 25), + F(400000, P_BI_TCXO, 12, 1, 4), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3), + F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0), + F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc1_apps_clk_src =3D { + .cmd_rcgr =3D 0x6b014, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_17, + .freq_tbl =3D ftbl_gcc_sdcc1_apps_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc1_apps_clk_src", + .parent_data =3D gcc_parent_data_17, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_17), + .ops =3D &clk_rcg2_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] =3D { + F(400000, P_BI_TCXO, 12, 1, 4), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + F(202000000, P_GPLL8_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc2_apps_clk_src =3D { + .cmd_rcgr =3D 0x6a018, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_18, + .freq_tbl =3D ftbl_gcc_sdcc2_apps_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc2_apps_clk_src", + .parent_data =3D gcc_parent_data_18, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_18), + .ops =3D &clk_rcg2_floor_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb30_master_clk_src[] =3D { + F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb30_master_clk_src =3D { + .cmd_rcgr =3D 0x27034, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_usb30_master_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_master_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 gcc_usb30_mock_utmi_clk_src =3D { + .cmd_rcgr =3D 0x2704c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_0, + .freq_tbl =3D ftbl_gcc_emac0_phy_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_mock_utmi_clk_src", + .parent_data =3D gcc_parent_data_0, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_0), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb3_phy_aux_clk_src[] =3D { + F(1000000, P_BI_TCXO, 1, 5, 96), + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb3_phy_aux_clk_src =3D { + .cmd_rcgr =3D 0x27074, + .mnd_width =3D 16, + .hid_width =3D 5, + .parent_map =3D gcc_parent_map_3, + .freq_tbl =3D ftbl_gcc_usb3_phy_aux_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_phy_aux_clk_src", + .parent_data =3D gcc_parent_data_3, + .num_parents =3D ARRAY_SIZE(gcc_parent_data_3), + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_regmap_div gcc_pcie_1_pipe_div2_clk_src =3D { + .reg =3D 0x67088, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_pipe_div2_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_1_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gcc_pcie_2_pipe_div2_clk_src =3D { + .reg =3D 0x68088, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_2_pipe_div2_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_2_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gcc_usb30_mock_utmi_postdiv_clk_src =3D { + .reg =3D 0x27064, + .shift =3D 0, + .width =3D 4, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_mock_utmi_postdiv_clk_src", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_mock_utmi_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gcc_boot_rom_ahb_clk =3D { + .halt_reg =3D 0x37004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x37004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(26), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_boot_rom_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_eee_emac0_clk =3D { + .halt_reg =3D 0x710ac, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x710ac, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_eee_emac0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_eee_emac0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_eee_emac1_clk =3D { + .halt_reg =3D 0x720ac, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x720ac, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_eee_emac1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_eee_emac1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_axi_clk =3D { + .halt_reg =3D 0x71018, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x71018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x71018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_cc_sgmiiphy_rx_clk =3D { + .halt_reg =3D 0x7105c, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x7105c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_cc_sgmiiphy_rx_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_emac0_cc_sgmiiphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_cc_sgmiiphy_tx_clk =3D { + .halt_reg =3D 0x71054, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x71054, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_cc_sgmiiphy_tx_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_emac0_cc_sgmiiphy_tx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_phy_aux_clk =3D { + .halt_reg =3D 0x71028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x71028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_emac0_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_ptp_clk =3D { + .halt_reg =3D 0x71044, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x71044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_ptp_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_emac0_ptp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_rgmii_clk =3D { + .halt_reg =3D 0x71050, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x71050, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_rgmii_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_emac0_rgmii_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_rpcs_rx_clk =3D { + .halt_reg =3D 0x710a0, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x710a0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_rpcs_rx_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_emac0_sgmiiphy_mac_rclk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_rpcs_tx_clk =3D { + .halt_reg =3D 0x7109c, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x7109c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_rpcs_tx_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_emac0_sgmiiphy_mac_tclk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_slv_ahb_clk =3D { + .halt_reg =3D 0x71024, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x71024, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x71024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_slv_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_xgxs_rx_clk =3D { + .halt_reg =3D 0x710a8, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x710a8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_xgxs_rx_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_emac0_sgmiiphy_mac_rclk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac0_xgxs_tx_clk =3D { + .halt_reg =3D 0x710a4, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x710a4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac0_xgxs_tx_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_emac0_sgmiiphy_mac_tclk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_axi_clk =3D { + .halt_reg =3D 0x72018, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x72018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x72018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac1_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_cc_sgmiiphy_rx_clk =3D { + .halt_reg =3D 0x7205c, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x7205c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac1_cc_sgmiiphy_rx_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_emac1_cc_sgmiiphy_rx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_cc_sgmiiphy_tx_clk =3D { + .halt_reg =3D 0x72054, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x72054, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac1_cc_sgmiiphy_tx_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_emac1_cc_sgmiiphy_tx_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_phy_aux_clk =3D { + .halt_reg =3D 0x72028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x72028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac1_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_emac1_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_ptp_clk =3D { + .halt_reg =3D 0x72044, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x72044, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac1_ptp_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_emac1_ptp_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_rgmii_clk =3D { + .halt_reg =3D 0x72050, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x72050, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac1_rgmii_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_emac1_rgmii_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_rpcs_rx_clk =3D { + .halt_reg =3D 0x720a0, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x720a0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac1_rpcs_rx_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_emac1_sgmiiphy_mac_rclk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_rpcs_tx_clk =3D { + .halt_reg =3D 0x7209c, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x7209c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac1_rpcs_tx_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_emac1_sgmiiphy_mac_tclk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_slv_ahb_clk =3D { + .halt_reg =3D 0x72024, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x72024, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x72024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac1_slv_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_xgxs_rx_clk =3D { + .halt_reg =3D 0x720a8, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x720a8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac1_xgxs_rx_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_emac1_sgmiiphy_mac_rclk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac1_xgxs_tx_clk =3D { + .halt_reg =3D 0x720a4, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x720a4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac1_xgxs_tx_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_emac1_sgmiiphy_mac_tclk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac_0_clkref_en =3D { + .halt_reg =3D 0x98108, + .halt_check =3D BRANCH_HALT_ENABLE, + .clkr =3D { + .enable_reg =3D 0x98108, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac_0_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_emac_1_clkref_en =3D { + .halt_reg =3D 0x9810c, + .halt_check =3D BRANCH_HALT_ENABLE, + .clkr =3D { + .enable_reg =3D 0x9810c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_emac_1_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp1_clk =3D { + .halt_reg =3D 0x47000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x47000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gp1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp2_clk =3D { + .halt_reg =3D 0x48000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x48000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gp2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp3_clk =3D { + .halt_reg =3D 0x49000, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x49000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_gp3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_gp3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_clkref_en =3D { + .halt_reg =3D 0x98004, + .halt_check =3D BRANCH_HALT_ENABLE, + .clkr =3D { + .enable_reg =3D 0x98004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_0_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_aux_clk =3D { + .halt_reg =3D 0x67038, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(22), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_1_aux_phy_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_cfg_ahb_clk =3D { + .halt_reg =3D 0x67034, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x67034, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(21), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_clkref_en =3D { + .halt_reg =3D 0x98114, + .halt_check =3D BRANCH_HALT_ENABLE, + .clkr =3D { + .enable_reg =3D 0x98114, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_mstr_axi_clk =3D { + .halt_reg =3D 0x67028, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(20), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_mstr_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_phy_rchng_clk =3D { + .halt_reg =3D 0x67068, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(24), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_phy_rchng_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_pipe_clk =3D { + .halt_reg =3D 0x6705c, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(23), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_1_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_pipe_div2_clk =3D { + .halt_reg =3D 0x6708c, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x7d020, + .enable_mask =3D BIT(3), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_pipe_div2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_1_pipe_div2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_slv_axi_clk =3D { + .halt_reg =3D 0x6701c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(19), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_slv_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk =3D { + .halt_reg =3D 0x67018, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(18), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_1_slv_q2a_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_2_aux_clk =3D { + .halt_reg =3D 0x68058, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(29), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_2_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_2_aux_phy_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_2_cfg_ahb_clk =3D { + .halt_reg =3D 0x68034, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x68034, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(28), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_2_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_2_clkref_en =3D { + .halt_reg =3D 0x98110, + .halt_check =3D BRANCH_HALT_ENABLE, + .clkr =3D { + .enable_reg =3D 0x98110, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_2_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_2_mstr_axi_clk =3D { + .halt_reg =3D 0x68028, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(8), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_2_mstr_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_2_phy_rchng_clk =3D { + .halt_reg =3D 0x68098, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(31), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_2_phy_rchng_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_2_phy_rchng_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_2_pipe_clk =3D { + .halt_reg =3D 0x6807c, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(30), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_2_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_2_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_2_pipe_div2_clk =3D { + .halt_reg =3D 0x6808c, + .halt_check =3D BRANCH_HALT_DELAY, + .clkr =3D { + .enable_reg =3D 0x7d020, + .enable_mask =3D BIT(4), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_2_pipe_div2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_2_pipe_div2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_2_slv_axi_clk =3D { + .halt_reg =3D 0x6801c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(26), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_2_slv_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_2_slv_q2a_axi_clk =3D { + .halt_reg =3D 0x68018, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(25), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_2_slv_q2a_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_aux_clk =3D { + .halt_reg =3D 0x5303c, + .halt_check =3D BRANCH_HALT_DELAY, + .hwcg_reg =3D 0x5303c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(15), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_cfg_ahb_clk =3D { + .halt_reg =3D 0x53034, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x53034, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(13), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_cfg_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_mstr_axi_clk =3D { + .halt_reg =3D 0x53028, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x53028, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(12), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_mstr_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_pipe_clk =3D { + .halt_reg =3D 0x5304c, + .halt_check =3D BRANCH_HALT_DELAY, + .hwcg_reg =3D 0x5304c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(17), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_rchng_phy_clk =3D { + .halt_reg =3D 0x53038, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x53038, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(14), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_rchng_phy_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_rchng_phy_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_sleep_clk =3D { + .halt_reg =3D 0x53048, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x53048, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(16), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_sleep_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pcie_aux_phy_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_slv_axi_clk =3D { + .halt_reg =3D 0x5301c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(11), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_slv_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_slv_q2a_axi_clk =3D { + .halt_reg =3D 0x53018, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x53018, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d010, + .enable_mask =3D BIT(10), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pcie_slv_q2a_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm2_clk =3D { + .halt_reg =3D 0x3400c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x3400c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pdm2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_pdm2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_ahb_clk =3D { + .halt_reg =3D 0x34004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x34004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pdm_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_xo4_clk =3D { + .halt_reg =3D 0x34008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x34008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_pdm_xo4_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_core_2x_clk =3D { + .halt_reg =3D 0x2d018, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(15), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_core_2x_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_core_clk =3D { + .halt_reg =3D 0x2d008, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(14), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_core_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s0_clk =3D { + .halt_reg =3D 0x6c004, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(16), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s1_clk =3D { + .halt_reg =3D 0x6c13c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(17), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s2_clk =3D { + .halt_reg =3D 0x6c274, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(18), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s2_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s3_clk =3D { + .halt_reg =3D 0x6c3ac, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(19), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s3_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s4_clk =3D { + .halt_reg =3D 0x6c4e4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(20), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s4_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s5_clk =3D { + .halt_reg =3D 0x6c61c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(21), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s5_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s6_clk =3D { + .halt_reg =3D 0x6c754, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(22), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s6_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s7_clk =3D { + .halt_reg =3D 0x6c88c, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(23), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s7_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s8_clk =3D { + .halt_reg =3D 0x6c9c4, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x7d020, + .enable_mask =3D BIT(7), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap0_s8_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_qupv3_wrap0_s8_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk =3D { + .halt_reg =3D 0x2d000, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2d000, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(12), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_0_m_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk =3D { + .halt_reg =3D 0x2d004, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x2d004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x7d008, + .enable_mask =3D BIT(13), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_qupv3_wrap_0_s_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ahb_clk =3D { + .halt_reg =3D 0x6b004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x6b004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc1_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_apps_clk =3D { + .halt_reg =3D 0x6b008, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x6b008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc1_apps_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_sdcc1_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_ahb_clk =3D { + .halt_reg =3D 0x6a010, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x6a010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc2_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_apps_clk =3D { + .halt_reg =3D 0x6a004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x6a004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_sdcc2_apps_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_sdcc2_apps_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb2_clkref_en =3D { + .halt_reg =3D 0x98008, + .halt_check =3D BRANCH_HALT_ENABLE, + .clkr =3D { + .enable_reg =3D 0x98008, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb2_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_master_clk =3D { + .halt_reg =3D 0x27018, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x27018, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_master_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_master_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_mock_utmi_clk =3D { + .halt_reg =3D 0x27030, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x27030, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_mock_utmi_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb30_mock_utmi_postdiv_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_mstr_axi_clk =3D { + .halt_reg =3D 0x27024, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x27024, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_mstr_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_sleep_clk =3D { + .halt_reg =3D 0x2702c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2702c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_sleep_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_slv_ahb_clk =3D { + .halt_reg =3D 0x27028, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x27028, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb30_slv_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_phy_aux_clk =3D { + .halt_reg =3D 0x27068, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x27068, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_phy_aux_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb3_phy_aux_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_phy_pipe_clk =3D { + .halt_reg =3D 0x2706c, + .halt_check =3D BRANCH_HALT_DELAY, + .hwcg_reg =3D 0x2706c, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x2706c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_phy_pipe_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_usb3_phy_pipe_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_clkref_en =3D { + .halt_reg =3D 0x98000, + .halt_check =3D BRANCH_HALT_ENABLE, + .clkr =3D { + .enable_reg =3D 0x98000, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb3_prim_clkref_en", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk =3D { + .halt_reg =3D 0x29004, + .halt_check =3D BRANCH_HALT, + .hwcg_reg =3D 0x29004, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x29004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_usb_phy_cfg_ahb2phy_clk", + .ops =3D &clk_branch2_aon_ops, + }, + }, +}; + +static struct gdsc gcc_emac0_gdsc =3D { + .gdscr =3D 0x71004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_emac0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_emac1_gdsc =3D { + .gdscr =3D 0x72004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_emac1_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_pcie_1_gdsc =3D { + .gdscr =3D 0x67004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_pcie_1_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_pcie_1_phy_gdsc =3D { + .gdscr =3D 0x56004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x2, + .pd =3D { + .name =3D "gcc_pcie_1_phy_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_pcie_2_gdsc =3D { + .gdscr =3D 0x68004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_pcie_2_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_pcie_2_phy_gdsc =3D { + .gdscr =3D 0x6e004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x2, + .pd =3D { + .name =3D "gcc_pcie_2_phy_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_pcie_gdsc =3D { + .gdscr =3D 0x53004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_pcie_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_pcie_phy_gdsc =3D { + .gdscr =3D 0x54004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x2, + .pd =3D { + .name =3D "gcc_pcie_phy_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_usb30_gdsc =3D { + .gdscr =3D 0x27004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "gcc_usb30_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D RETAIN_FF_ENABLE, +}; + +static struct gdsc gcc_usb3_phy_gdsc =3D { + .gdscr =3D 0x28008, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x2, + .pd =3D { + .name =3D "gcc_usb3_phy_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *gcc_sdx75_clocks[] =3D { + [GCC_BOOT_ROM_AHB_CLK] =3D &gcc_boot_rom_ahb_clk.clkr, + [GCC_EEE_EMAC0_CLK] =3D &gcc_eee_emac0_clk.clkr, + [GCC_EEE_EMAC0_CLK_SRC] =3D &gcc_eee_emac0_clk_src.clkr, + [GCC_EEE_EMAC1_CLK] =3D &gcc_eee_emac1_clk.clkr, + [GCC_EEE_EMAC1_CLK_SRC] =3D &gcc_eee_emac1_clk_src.clkr, + [GCC_EMAC0_AXI_CLK] =3D &gcc_emac0_axi_clk.clkr, + [GCC_EMAC0_CC_SGMIIPHY_RX_CLK] =3D &gcc_emac0_cc_sgmiiphy_rx_clk.clkr, + [GCC_EMAC0_CC_SGMIIPHY_RX_CLK_SRC] =3D &gcc_emac0_cc_sgmiiphy_rx_clk_src.= clkr, + [GCC_EMAC0_CC_SGMIIPHY_TX_CLK] =3D &gcc_emac0_cc_sgmiiphy_tx_clk.clkr, + [GCC_EMAC0_CC_SGMIIPHY_TX_CLK_SRC] =3D &gcc_emac0_cc_sgmiiphy_tx_clk_src.= clkr, + [GCC_EMAC0_PHY_AUX_CLK] =3D &gcc_emac0_phy_aux_clk.clkr, + [GCC_EMAC0_PHY_AUX_CLK_SRC] =3D &gcc_emac0_phy_aux_clk_src.clkr, + [GCC_EMAC0_PTP_CLK] =3D &gcc_emac0_ptp_clk.clkr, + [GCC_EMAC0_PTP_CLK_SRC] =3D &gcc_emac0_ptp_clk_src.clkr, + [GCC_EMAC0_RGMII_CLK] =3D &gcc_emac0_rgmii_clk.clkr, + [GCC_EMAC0_RGMII_CLK_SRC] =3D &gcc_emac0_rgmii_clk_src.clkr, + [GCC_EMAC0_RPCS_RX_CLK] =3D &gcc_emac0_rpcs_rx_clk.clkr, + [GCC_EMAC0_RPCS_TX_CLK] =3D &gcc_emac0_rpcs_tx_clk.clkr, + [GCC_EMAC0_SGMIIPHY_MAC_RCLK_SRC] =3D &gcc_emac0_sgmiiphy_mac_rclk_src.cl= kr, + [GCC_EMAC0_SGMIIPHY_MAC_TCLK_SRC] =3D &gcc_emac0_sgmiiphy_mac_tclk_src.cl= kr, + [GCC_EMAC0_SLV_AHB_CLK] =3D &gcc_emac0_slv_ahb_clk.clkr, + [GCC_EMAC0_XGXS_RX_CLK] =3D &gcc_emac0_xgxs_rx_clk.clkr, + [GCC_EMAC0_XGXS_TX_CLK] =3D &gcc_emac0_xgxs_tx_clk.clkr, + [GCC_EMAC1_AXI_CLK] =3D &gcc_emac1_axi_clk.clkr, + [GCC_EMAC1_CC_SGMIIPHY_RX_CLK] =3D &gcc_emac1_cc_sgmiiphy_rx_clk.clkr, + [GCC_EMAC1_CC_SGMIIPHY_RX_CLK_SRC] =3D &gcc_emac1_cc_sgmiiphy_rx_clk_src.= clkr, + [GCC_EMAC1_CC_SGMIIPHY_TX_CLK] =3D &gcc_emac1_cc_sgmiiphy_tx_clk.clkr, + [GCC_EMAC1_CC_SGMIIPHY_TX_CLK_SRC] =3D &gcc_emac1_cc_sgmiiphy_tx_clk_src.= clkr, + [GCC_EMAC1_PHY_AUX_CLK] =3D &gcc_emac1_phy_aux_clk.clkr, + [GCC_EMAC1_PHY_AUX_CLK_SRC] =3D &gcc_emac1_phy_aux_clk_src.clkr, + [GCC_EMAC1_PTP_CLK] =3D &gcc_emac1_ptp_clk.clkr, + [GCC_EMAC1_PTP_CLK_SRC] =3D &gcc_emac1_ptp_clk_src.clkr, + [GCC_EMAC1_RGMII_CLK] =3D &gcc_emac1_rgmii_clk.clkr, + [GCC_EMAC1_RGMII_CLK_SRC] =3D &gcc_emac1_rgmii_clk_src.clkr, + [GCC_EMAC1_RPCS_RX_CLK] =3D &gcc_emac1_rpcs_rx_clk.clkr, + [GCC_EMAC1_RPCS_TX_CLK] =3D &gcc_emac1_rpcs_tx_clk.clkr, + [GCC_EMAC1_SGMIIPHY_MAC_RCLK_SRC] =3D &gcc_emac1_sgmiiphy_mac_rclk_src.cl= kr, + [GCC_EMAC1_SGMIIPHY_MAC_TCLK_SRC] =3D &gcc_emac1_sgmiiphy_mac_tclk_src.cl= kr, + [GCC_EMAC1_SLV_AHB_CLK] =3D &gcc_emac1_slv_ahb_clk.clkr, + [GCC_EMAC1_XGXS_RX_CLK] =3D &gcc_emac1_xgxs_rx_clk.clkr, + [GCC_EMAC1_XGXS_TX_CLK] =3D &gcc_emac1_xgxs_tx_clk.clkr, + [GCC_EMAC_0_CLKREF_EN] =3D &gcc_emac_0_clkref_en.clkr, + [GCC_EMAC_1_CLKREF_EN] =3D &gcc_emac_1_clkref_en.clkr, + [GCC_GP1_CLK] =3D &gcc_gp1_clk.clkr, + [GCC_GP1_CLK_SRC] =3D &gcc_gp1_clk_src.clkr, + [GCC_GP2_CLK] =3D &gcc_gp2_clk.clkr, + [GCC_GP2_CLK_SRC] =3D &gcc_gp2_clk_src.clkr, + [GCC_GP3_CLK] =3D &gcc_gp3_clk.clkr, + [GCC_GP3_CLK_SRC] =3D &gcc_gp3_clk_src.clkr, + [GCC_PCIE_0_CLKREF_EN] =3D &gcc_pcie_0_clkref_en.clkr, + [GCC_PCIE_1_AUX_CLK] =3D &gcc_pcie_1_aux_clk.clkr, + [GCC_PCIE_1_AUX_PHY_CLK_SRC] =3D &gcc_pcie_1_aux_phy_clk_src.clkr, + [GCC_PCIE_1_CFG_AHB_CLK] =3D &gcc_pcie_1_cfg_ahb_clk.clkr, + [GCC_PCIE_1_CLKREF_EN] =3D &gcc_pcie_1_clkref_en.clkr, + [GCC_PCIE_1_MSTR_AXI_CLK] =3D &gcc_pcie_1_mstr_axi_clk.clkr, + [GCC_PCIE_1_PHY_RCHNG_CLK] =3D &gcc_pcie_1_phy_rchng_clk.clkr, + [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] =3D &gcc_pcie_1_phy_rchng_clk_src.clkr, + [GCC_PCIE_1_PIPE_CLK] =3D &gcc_pcie_1_pipe_clk.clkr, + [GCC_PCIE_1_PIPE_CLK_SRC] =3D &gcc_pcie_1_pipe_clk_src.clkr, + [GCC_PCIE_1_PIPE_DIV2_CLK] =3D &gcc_pcie_1_pipe_div2_clk.clkr, + [GCC_PCIE_1_PIPE_DIV2_CLK_SRC] =3D &gcc_pcie_1_pipe_div2_clk_src.clkr, + [GCC_PCIE_1_SLV_AXI_CLK] =3D &gcc_pcie_1_slv_axi_clk.clkr, + [GCC_PCIE_1_SLV_Q2A_AXI_CLK] =3D &gcc_pcie_1_slv_q2a_axi_clk.clkr, + [GCC_PCIE_2_AUX_CLK] =3D &gcc_pcie_2_aux_clk.clkr, + [GCC_PCIE_2_AUX_PHY_CLK_SRC] =3D &gcc_pcie_2_aux_phy_clk_src.clkr, + [GCC_PCIE_2_CFG_AHB_CLK] =3D &gcc_pcie_2_cfg_ahb_clk.clkr, + [GCC_PCIE_2_CLKREF_EN] =3D &gcc_pcie_2_clkref_en.clkr, + [GCC_PCIE_2_MSTR_AXI_CLK] =3D &gcc_pcie_2_mstr_axi_clk.clkr, + [GCC_PCIE_2_PHY_RCHNG_CLK] =3D &gcc_pcie_2_phy_rchng_clk.clkr, + [GCC_PCIE_2_PHY_RCHNG_CLK_SRC] =3D &gcc_pcie_2_phy_rchng_clk_src.clkr, + [GCC_PCIE_2_PIPE_CLK] =3D &gcc_pcie_2_pipe_clk.clkr, + [GCC_PCIE_2_PIPE_CLK_SRC] =3D &gcc_pcie_2_pipe_clk_src.clkr, + [GCC_PCIE_2_PIPE_DIV2_CLK] =3D &gcc_pcie_2_pipe_div2_clk.clkr, + [GCC_PCIE_2_PIPE_DIV2_CLK_SRC] =3D &gcc_pcie_2_pipe_div2_clk_src.clkr, + [GCC_PCIE_2_SLV_AXI_CLK] =3D &gcc_pcie_2_slv_axi_clk.clkr, + [GCC_PCIE_2_SLV_Q2A_AXI_CLK] =3D &gcc_pcie_2_slv_q2a_axi_clk.clkr, + [GCC_PCIE_AUX_CLK] =3D &gcc_pcie_aux_clk.clkr, + [GCC_PCIE_AUX_CLK_SRC] =3D &gcc_pcie_aux_clk_src.clkr, + [GCC_PCIE_AUX_PHY_CLK_SRC] =3D &gcc_pcie_aux_phy_clk_src.clkr, + [GCC_PCIE_CFG_AHB_CLK] =3D &gcc_pcie_cfg_ahb_clk.clkr, + [GCC_PCIE_MSTR_AXI_CLK] =3D &gcc_pcie_mstr_axi_clk.clkr, + [GCC_PCIE_PIPE_CLK] =3D &gcc_pcie_pipe_clk.clkr, + [GCC_PCIE_PIPE_CLK_SRC] =3D &gcc_pcie_pipe_clk_src.clkr, + [GCC_PCIE_RCHNG_PHY_CLK] =3D &gcc_pcie_rchng_phy_clk.clkr, + [GCC_PCIE_RCHNG_PHY_CLK_SRC] =3D &gcc_pcie_rchng_phy_clk_src.clkr, + [GCC_PCIE_SLEEP_CLK] =3D &gcc_pcie_sleep_clk.clkr, + [GCC_PCIE_SLV_AXI_CLK] =3D &gcc_pcie_slv_axi_clk.clkr, + [GCC_PCIE_SLV_Q2A_AXI_CLK] =3D &gcc_pcie_slv_q2a_axi_clk.clkr, + [GCC_PDM2_CLK] =3D &gcc_pdm2_clk.clkr, + [GCC_PDM2_CLK_SRC] =3D &gcc_pdm2_clk_src.clkr, + [GCC_PDM_AHB_CLK] =3D &gcc_pdm_ahb_clk.clkr, + [GCC_PDM_XO4_CLK] =3D &gcc_pdm_xo4_clk.clkr, + [GCC_QUPV3_WRAP0_CORE_2X_CLK] =3D &gcc_qupv3_wrap0_core_2x_clk.clkr, + [GCC_QUPV3_WRAP0_CORE_CLK] =3D &gcc_qupv3_wrap0_core_clk.clkr, + [GCC_QUPV3_WRAP0_S0_CLK] =3D &gcc_qupv3_wrap0_s0_clk.clkr, + [GCC_QUPV3_WRAP0_S0_CLK_SRC] =3D &gcc_qupv3_wrap0_s0_clk_src.clkr, + [GCC_QUPV3_WRAP0_S1_CLK] =3D &gcc_qupv3_wrap0_s1_clk.clkr, + [GCC_QUPV3_WRAP0_S1_CLK_SRC] =3D &gcc_qupv3_wrap0_s1_clk_src.clkr, + [GCC_QUPV3_WRAP0_S2_CLK] =3D &gcc_qupv3_wrap0_s2_clk.clkr, + [GCC_QUPV3_WRAP0_S2_CLK_SRC] =3D &gcc_qupv3_wrap0_s2_clk_src.clkr, + [GCC_QUPV3_WRAP0_S3_CLK] =3D &gcc_qupv3_wrap0_s3_clk.clkr, + [GCC_QUPV3_WRAP0_S3_CLK_SRC] =3D &gcc_qupv3_wrap0_s3_clk_src.clkr, + [GCC_QUPV3_WRAP0_S4_CLK] =3D &gcc_qupv3_wrap0_s4_clk.clkr, + [GCC_QUPV3_WRAP0_S4_CLK_SRC] =3D &gcc_qupv3_wrap0_s4_clk_src.clkr, + [GCC_QUPV3_WRAP0_S5_CLK] =3D &gcc_qupv3_wrap0_s5_clk.clkr, + [GCC_QUPV3_WRAP0_S5_CLK_SRC] =3D &gcc_qupv3_wrap0_s5_clk_src.clkr, + [GCC_QUPV3_WRAP0_S6_CLK] =3D &gcc_qupv3_wrap0_s6_clk.clkr, + [GCC_QUPV3_WRAP0_S6_CLK_SRC] =3D &gcc_qupv3_wrap0_s6_clk_src.clkr, + [GCC_QUPV3_WRAP0_S7_CLK] =3D &gcc_qupv3_wrap0_s7_clk.clkr, + [GCC_QUPV3_WRAP0_S7_CLK_SRC] =3D &gcc_qupv3_wrap0_s7_clk_src.clkr, + [GCC_QUPV3_WRAP0_S8_CLK] =3D &gcc_qupv3_wrap0_s8_clk.clkr, + [GCC_QUPV3_WRAP0_S8_CLK_SRC] =3D &gcc_qupv3_wrap0_s8_clk_src.clkr, + [GCC_QUPV3_WRAP_0_M_AHB_CLK] =3D &gcc_qupv3_wrap_0_m_ahb_clk.clkr, + [GCC_QUPV3_WRAP_0_S_AHB_CLK] =3D &gcc_qupv3_wrap_0_s_ahb_clk.clkr, + [GCC_SDCC1_AHB_CLK] =3D &gcc_sdcc1_ahb_clk.clkr, + [GCC_SDCC1_APPS_CLK] =3D &gcc_sdcc1_apps_clk.clkr, + [GCC_SDCC1_APPS_CLK_SRC] =3D &gcc_sdcc1_apps_clk_src.clkr, + [GCC_SDCC2_AHB_CLK] =3D &gcc_sdcc2_ahb_clk.clkr, + [GCC_SDCC2_APPS_CLK] =3D &gcc_sdcc2_apps_clk.clkr, + [GCC_SDCC2_APPS_CLK_SRC] =3D &gcc_sdcc2_apps_clk_src.clkr, + [GCC_USB2_CLKREF_EN] =3D &gcc_usb2_clkref_en.clkr, + [GCC_USB30_MASTER_CLK] =3D &gcc_usb30_master_clk.clkr, + [GCC_USB30_MASTER_CLK_SRC] =3D &gcc_usb30_master_clk_src.clkr, + [GCC_USB30_MOCK_UTMI_CLK] =3D &gcc_usb30_mock_utmi_clk.clkr, + [GCC_USB30_MOCK_UTMI_CLK_SRC] =3D &gcc_usb30_mock_utmi_clk_src.clkr, + [GCC_USB30_MOCK_UTMI_POSTDIV_CLK_SRC] =3D &gcc_usb30_mock_utmi_postdiv_cl= k_src.clkr, + [GCC_USB30_MSTR_AXI_CLK] =3D &gcc_usb30_mstr_axi_clk.clkr, + [GCC_USB30_SLEEP_CLK] =3D &gcc_usb30_sleep_clk.clkr, + [GCC_USB30_SLV_AHB_CLK] =3D &gcc_usb30_slv_ahb_clk.clkr, + [GCC_USB3_PHY_AUX_CLK] =3D &gcc_usb3_phy_aux_clk.clkr, + [GCC_USB3_PHY_AUX_CLK_SRC] =3D &gcc_usb3_phy_aux_clk_src.clkr, + [GCC_USB3_PHY_PIPE_CLK] =3D &gcc_usb3_phy_pipe_clk.clkr, + [GCC_USB3_PHY_PIPE_CLK_SRC] =3D &gcc_usb3_phy_pipe_clk_src.clkr, + [GCC_USB3_PRIM_CLKREF_EN] =3D &gcc_usb3_prim_clkref_en.clkr, + [GCC_USB_PHY_CFG_AHB2PHY_CLK] =3D &gcc_usb_phy_cfg_ahb2phy_clk.clkr, + [GPLL0] =3D &gpll0.clkr, + [GPLL0_OUT_EVEN] =3D &gpll0_out_even.clkr, + [GPLL4] =3D &gpll4.clkr, + [GPLL5] =3D &gpll5.clkr, + [GPLL6] =3D &gpll6.clkr, + [GPLL8] =3D &gpll8.clkr, +}; + +static struct gdsc *gcc_sdx75_gdscs[] =3D { + [GCC_EMAC0_GDSC] =3D &gcc_emac0_gdsc, + [GCC_EMAC1_GDSC] =3D &gcc_emac1_gdsc, + [GCC_PCIE_1_GDSC] =3D &gcc_pcie_1_gdsc, + [GCC_PCIE_1_PHY_GDSC] =3D &gcc_pcie_1_phy_gdsc, + [GCC_PCIE_2_GDSC] =3D &gcc_pcie_2_gdsc, + [GCC_PCIE_2_PHY_GDSC] =3D &gcc_pcie_2_phy_gdsc, + [GCC_PCIE_GDSC] =3D &gcc_pcie_gdsc, + [GCC_PCIE_PHY_GDSC] =3D &gcc_pcie_phy_gdsc, + [GCC_USB30_GDSC] =3D &gcc_usb30_gdsc, + [GCC_USB3_PHY_GDSC] =3D &gcc_usb3_phy_gdsc, +}; + +static const struct qcom_reset_map gcc_sdx75_resets[] =3D { + [GCC_EMAC0_BCR] =3D { 0x71000 }, + [GCC_EMAC0_RGMII_CLK_ARES] =3D { 0x71050, 2 }, + [GCC_EMAC1_BCR] =3D { 0x72000 }, + [GCC_EMMC_BCR] =3D { 0x6b000 }, + [GCC_PCIE_1_BCR] =3D { 0x67000 }, + [GCC_PCIE_1_LINK_DOWN_BCR] =3D { 0x9e700 }, + [GCC_PCIE_1_NOCSR_COM_PHY_BCR] =3D { 0x56120 }, + [GCC_PCIE_1_PHY_BCR] =3D { 0x56000 }, + [GCC_PCIE_2_BCR] =3D { 0x68000 }, + [GCC_PCIE_2_LINK_DOWN_BCR] =3D { 0x9f700 }, + [GCC_PCIE_2_NOCSR_COM_PHY_BCR] =3D { 0x6e130 }, + [GCC_PCIE_2_PHY_BCR] =3D { 0x6e000 }, + [GCC_PCIE_BCR] =3D { 0x53000 }, + [GCC_PCIE_LINK_DOWN_BCR] =3D { 0x87000 }, + [GCC_PCIE_NOCSR_COM_PHY_BCR] =3D { 0x88008 }, + [GCC_PCIE_PHY_BCR] =3D { 0x54000 }, + [GCC_PCIE_PHY_CFG_AHB_BCR] =3D { 0x88000 }, + [GCC_PCIE_PHY_COM_BCR] =3D { 0x88004 }, + [GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] =3D { 0x8800c }, + [GCC_QUSB2PHY_BCR] =3D { 0x2a000 }, + [GCC_TCSR_PCIE_BCR] =3D { 0x84000 }, + [GCC_USB30_BCR] =3D { 0x27000 }, + [GCC_USB3_PHY_BCR] =3D { 0x28000 }, + [GCC_USB3PHY_PHY_BCR] =3D { 0x28004 }, + [GCC_USB_PHY_CFG_AHB2PHY_BCR] =3D { 0x29000 }, +}; + +static const struct clk_rcg_dfs_data gcc_dfs_clocks[] =3D { + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src), + DEFINE_RCG_DFS(gcc_qupv3_wrap0_s8_clk_src), +}; + +static const struct regmap_config gcc_sdx75_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1f41f0, + .fast_io =3D true, +}; + +static const struct qcom_cc_desc gcc_sdx75_desc =3D { + .config =3D &gcc_sdx75_regmap_config, + .clks =3D gcc_sdx75_clocks, + .num_clks =3D ARRAY_SIZE(gcc_sdx75_clocks), + .resets =3D gcc_sdx75_resets, + .num_resets =3D ARRAY_SIZE(gcc_sdx75_resets), + .gdscs =3D gcc_sdx75_gdscs, + .num_gdscs =3D ARRAY_SIZE(gcc_sdx75_gdscs), +}; + +static const struct of_device_id gcc_sdx75_match_table[] =3D { + { .compatible =3D "qcom,sdx75-gcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gcc_sdx75_match_table); + +static int gcc_sdx75_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + regmap =3D qcom_cc_map(pdev, &gcc_sdx75_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + ret =3D qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, + ARRAY_SIZE(gcc_dfs_clocks)); + if (ret) + return ret; + + /* + * Keep clocks always enabled: + * gcc_ahb_pcie_link_clk + * gcc_xo_pcie_link_clk + */ + regmap_update_bits(regmap, 0x3e004, BIT(0), BIT(0)); + regmap_update_bits(regmap, 0x3e008, BIT(0), BIT(0)); + + return qcom_cc_really_probe(pdev, &gcc_sdx75_desc, regmap); +} + +static struct platform_driver gcc_sdx75_driver =3D { + .probe =3D gcc_sdx75_probe, + .driver =3D { + .name =3D "gcc-sdx75", + .of_match_table =3D gcc_sdx75_match_table, + }, +}; + +static int __init gcc_sdx75_init(void) +{ + return platform_driver_register(&gcc_sdx75_driver); +} +subsys_initcall(gcc_sdx75_init); + +static void __exit gcc_sdx75_exit(void) +{ + platform_driver_unregister(&gcc_sdx75_driver); +} +module_exit(gcc_sdx75_exit); + +MODULE_DESCRIPTION("QTI GCC SDX75 Driver"); +MODULE_LICENSE("GPL"); --=20 2.17.1