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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In order to setup the DSI clock, let's make the unused VCLK2 clock path configuration via CCF. The nocache option is removed from following clocks: - vclk2_sel - vclk2_input - vclk2_div - vclk2 - vclk_div1 - vclk2_div2_en - vclk2_div4_en - vclk2_div6_en - vclk2_div12_en - vclk2_div2 - vclk2_div4 - vclk2_div6 - vclk2_div12 - cts_encl_sel vclk2 and vclk2_div uses the newly introduced vclk regmap driver to handle the enable and reset bits. In order to set a rate on cts_encl via the vclk2 clock path, the NO_REPARENT flag is set on cts_encl_sel & vclk2_sel in order to keep CCF from selection a parent. The parents of cts_encl_sel & vclk2_sel are expected to be defined in DT. The following clock scheme is to be used for DSI: xtal \_ gp0_pll_dco \_ gp0_pll |- vclk2_sel | \_ vclk2_input | \_ vclk2_div | \_ vclk2 | \_ vclk2_div1 | \_ cts_encl_sel | \_ cts_encl -> to VPU LCD Encoder |- mipi_dsi_pxclk_sel \_ mipi_dsi_pxclk_div \_ mipi_dsi_pxclk -> to DSI controller The mipi_dsi_pxclk_div is set as RO in order to use the same GP0 for mipi_dsi_pxclk and vclk2_input. Signed-off-by: Neil Armstrong --- drivers/clk/meson/g12a.c | 43 ++++++++++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 17 deletions(-) diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index 5d62134335c1..552c8efb1ad8 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -22,6 +22,7 @@ #include "clk-regmap.h" #include "clk-cpu-dyndiv.h" #include "vid-pll-div.h" +#include "vclk.h" #include "meson-eeclk.h" #include "g12a.h" =20 @@ -3165,7 +3166,7 @@ static struct clk_regmap g12a_vclk2_sel =3D { .ops =3D &clk_regmap_mux_ops, .parent_hws =3D g12a_vclk_parent_hws, .num_parents =3D ARRAY_SIZE(g12a_vclk_parent_hws), - .flags =3D CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, + .flags =3D CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, }, }; =20 @@ -3193,7 +3194,7 @@ static struct clk_regmap g12a_vclk2_input =3D { .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &g12a_vclk2_sel.hw }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -3215,19 +3216,22 @@ static struct clk_regmap g12a_vclk_div =3D { }; =20 static struct clk_regmap g12a_vclk2_div =3D { - .data =3D &(struct clk_regmap_div_data){ + .data =3D &(struct clk_regmap_vclk_div_data){ .offset =3D HHI_VIID_CLK_DIV, .shift =3D 0, .width =3D 8, + .enable_bit_idx =3D 16, + .reset_bit_idx =3D 17, + .flags =3D CLK_DIVIDER_ROUND_CLOSEST, }, .hw.init =3D &(struct clk_init_data){ .name =3D "vclk2_div", - .ops =3D &clk_regmap_divider_ops, + .ops =3D &clk_regmap_vclk_div_ops, .parent_hws =3D (const struct clk_hw *[]) { &g12a_vclk2_input.hw }, .num_parents =3D 1, - .flags =3D CLK_GET_RATE_NOCACHE, + .flags =3D CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, }, }; =20 @@ -3246,16 +3250,17 @@ static struct clk_regmap g12a_vclk =3D { }; =20 static struct clk_regmap g12a_vclk2 =3D { - .data =3D &(struct clk_regmap_gate_data){ + .data =3D &(struct clk_regmap_vclk_data){ .offset =3D HHI_VIID_CLK_CNTL, - .bit_idx =3D 19, + .enable_bit_idx =3D 19, + .reset_bit_idx =3D 15, }, .hw.init =3D &(struct clk_init_data) { .name =3D "vclk2", - .ops =3D &clk_regmap_gate_ops, + .ops =3D &clk_regmap_vclk_ops, .parent_hws =3D (const struct clk_hw *[]) { &g12a_vclk2_div.hw }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags =3D CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, }, }; =20 @@ -3339,7 +3344,7 @@ static struct clk_regmap g12a_vclk2_div1 =3D { .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &g12a_vclk2.hw }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -3353,7 +3358,7 @@ static struct clk_regmap g12a_vclk2_div2_en =3D { .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &g12a_vclk2.hw }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -3367,7 +3372,7 @@ static struct clk_regmap g12a_vclk2_div4_en =3D { .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &g12a_vclk2.hw }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -3381,7 +3386,7 @@ static struct clk_regmap g12a_vclk2_div6_en =3D { .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &g12a_vclk2.hw }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -3395,7 +3400,7 @@ static struct clk_regmap g12a_vclk2_div12_en =3D { .ops =3D &clk_regmap_gate_ops, .parent_hws =3D (const struct clk_hw *[]) { &g12a_vclk2.hw }, .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -3461,6 +3466,7 @@ static struct clk_fixed_factor g12a_vclk2_div2 =3D { &g12a_vclk2_div2_en.hw }, .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -3474,6 +3480,7 @@ static struct clk_fixed_factor g12a_vclk2_div4 =3D { &g12a_vclk2_div4_en.hw }, .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -3487,6 +3494,7 @@ static struct clk_fixed_factor g12a_vclk2_div6 =3D { &g12a_vclk2_div6_en.hw }, .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -3500,6 +3508,7 @@ static struct clk_fixed_factor g12a_vclk2_div12 =3D { &g12a_vclk2_div12_en.hw }, .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -3561,7 +3570,7 @@ static struct clk_regmap g12a_cts_encl_sel =3D { .ops =3D &clk_regmap_mux_ops, .parent_hws =3D g12a_cts_parent_hws, .num_parents =3D ARRAY_SIZE(g12a_cts_parent_hws), - .flags =3D CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, + .flags =3D CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, }, }; =20 @@ -3717,7 +3726,7 @@ static struct clk_regmap g12a_mipi_dsi_pxclk_sel =3D { .ops =3D &clk_regmap_mux_ops, .parent_hws =3D g12a_mipi_dsi_pxclk_parent_hws, .num_parents =3D ARRAY_SIZE(g12a_mipi_dsi_pxclk_parent_hws), - .flags =3D CLK_SET_RATE_NO_REPARENT, + .flags =3D CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, }, }; =20 @@ -3729,7 +3738,7 @@ static struct clk_regmap g12a_mipi_dsi_pxclk_div =3D { }, .hw.init =3D &(struct clk_init_data){ .name =3D "mipi_dsi_pxclk_div", - .ops =3D &clk_regmap_divider_ops, + .ops =3D &clk_regmap_divider_ro_ops, .parent_hws =3D (const struct clk_hw *[]) { &g12a_mipi_dsi_pxclk_sel.hw }, --=20 2.34.1