From nobody Tue Dec 16 03:07:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 820AEC7EE2F for ; Tue, 30 May 2023 07:38:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229935AbjE3Hif (ORCPT ); Tue, 30 May 2023 03:38:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35042 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230329AbjE3HiT (ORCPT ); Tue, 30 May 2023 03:38:19 -0400 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6FFC9DB for ; Tue, 30 May 2023 00:38:17 -0700 (PDT) Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-30af20f5f67so912952f8f.1 for ; Tue, 30 May 2023 00:38:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685432296; x=1688024296; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=2/Rzsy455UWJxoydYIeagZhdFB/pfUgTfB7t2+UiAU4=; b=C6RCwuEb1eYa1ttEsUpZLRkJuPdxKNyRPnwbV1b/TV7SucFU8GuJZOYZmKYupVqUh4 fBLXDuP8C7sMxhzaLU2/NDLjmk6nH69VrMxFOgVJ924qnsksvGYBgn3ntLZszcOguI68 00N+iSk3cNqJw8qfc4mUJBnmg8Mx2nVt5y4uH9uoxchS6erzYC2j7vsf0LKnf00BCJ1R Zu3ggqcYXtEoNm1ZrJJQqzs/iJ4d51Cmc2zg+rwqrkI3yyF6lCck9fdckPvw6Y/Ey/7x DmdUW0RxmhUG5IUYsxllNiZRucLw39WN61gU60R73GIQsCpyONoguV6+h1pswdVY0xq8 jHuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685432296; x=1688024296; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2/Rzsy455UWJxoydYIeagZhdFB/pfUgTfB7t2+UiAU4=; b=ExyUlUxjQlETq0bxUa5ES4A7Zku3nEHVLaVEGavjb8LLB1kKs1AjxkPB9BPur2rjP1 dALFNitV1o65X9NpT2j8HmZ15K/QpUf/LNyjB+jNqw7CmO5mpyMQO3tAOfBeF2pMIVAS vRsphfTf5BJHGRxkHOvds9zvDJpX48E5KrWOn8TzorawuKw+lLb7Xih2StccKGvsEbRb 8rnk8Dmbtn7bCdot7Zf5eIzJ869Mu4Ew+UM0jekgNF7glBR9EUNafQjeO4Lv0GqM/jp1 Tvk4p4guhbeYiTPgfGQ0VC8RP87yFEaWgfu49tBfFsNEncUOaBROXsPU86OPCv5aNvp6 CGuA== X-Gm-Message-State: AC+VfDy68JYkOilOYtrHh9JeFxUSPiIGCMfpEOsp3tedBGHv0o9AUqGa TfkiTsBDYZbZE85ux70WIi+mKPRipW3a7qhXi8Whdw== X-Google-Smtp-Source: ACHHUZ6kHAz1oiPKEQXK33denrSn5kXBLF1cckfBI8jkzp4y43WjxLeKORl/3ABRzZa9UKhLM60xZQ== X-Received: by 2002:a5d:5508:0:b0:307:a5d1:dbae with SMTP id b8-20020a5d5508000000b00307a5d1dbaemr755726wrv.71.1685432295998; Tue, 30 May 2023 00:38:15 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id m4-20020a5d4a04000000b003079c402762sm2312013wrq.19.2023.05.30.00.38.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 May 2023 00:38:15 -0700 (PDT) From: Neil Armstrong Date: Tue, 30 May 2023 09:38:03 +0200 Subject: [PATCH v5 02/17] clk: meson: g12a: add CTS_ENCL & CTS_ENCL_SEL clocks MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-2-56eb7a4d5b8e@linaro.org> References: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-0-56eb7a4d5b8e@linaro.org> In-Reply-To: <20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v5-0-56eb7a4d5b8e@linaro.org> To: Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl , Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Airlie , Daniel Vetter , Philipp Zabel , Kishon Vijay Abraham I , Sam Ravnborg Cc: "Lukas F. Hartmann" , Nicolas Belin , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-phy@lists.infradead.org, Neil Armstrong X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4770; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=YshimAv78sTusx5XlbLyLaKmvGYFuT/Nlues9OXV98A=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBkdafdZGnB9zL+CgnVBMve1Z9B0LfgNI/N9xYPM8bx JoupRWiJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZHWn3QAKCRB33NvayMhJ0Rl7EA CJucqpVwIaz1WC0N5elAKMHy0ZF1CnPdHViDAjTl5eMgn20LIrKiWHzVEJCQYdpHUDvPsdsUjLbPol hIXuZOUC4KyTS/dVAwlapVMxSOTolFQQwFBSnc7u98i18ElJu9ONLburHqKdNdtdkvFMi7Q41+Uqu0 wkMxecsNgWxUJlN12Zgd0EoynpJEwy8Useyf8fSc5/XqIF96HpITRB4uPQIMVB7ONHwaLhY8vJD+Oe RsASCAup7UujZWZQor7gksEW4VRWO/EUNGzTIadFkHr6CfutBp0InSQtKXe52FIzLHaKXObS2LnvIM nWvRMq4HhG6zqQdY4sfxGJHJ31dkZUgSVxMW2yMejHhGENvttn/7pdaiiqvubrFyStRJK3+OEcFpMV stKm6BJpLUMogz21ysc7PNwmeqdFTiE0mI6ojBV5Gq8b/1rsFvD9L9T9qfNgCNDKtoWa5adCt5YTHe /3Pmva1VUIDOjHRRh4kfZi5bZPjcv3FZrG/AuogP0jux1bLPfg8FLnw2KVfEtZrMb+SjJYa3y/oYba kbqrXFMLJeiazu7xfDNoCkEc58zpXyWZXT2l2UB5ilAjGF+zMWQoo4Px5oZVxCsSo3w4ccC9A8LtB+ 0V9N6+2VgBCBU2zUhmOk9XGJomDJsx3sE2uErEJ0p5MhZZYOrP8Nz3r8QlHw== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add new CTS_ENCL & CTS_ENCL_SEL clocks for the G12A compatible SoCs, they are used to feed the VPU LCD Pixel encoder used for DSI display purposes. Signed-off-by: Neil Armstrong --- drivers/clk/meson/g12a.c | 40 ++++++++++++++++++++++++++++++++++++++++ drivers/clk/meson/g12a.h | 4 +++- 2 files changed, 43 insertions(+), 1 deletion(-) diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index d2e481ae2429..a132aad2aac9 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -3547,6 +3547,22 @@ static struct clk_regmap g12a_cts_encp_sel =3D { }, }; =20 +static struct clk_regmap g12a_cts_encl_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D HHI_VIID_CLK_DIV, + .mask =3D 0xf, + .shift =3D 12, + .table =3D mux_table_cts_sel, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cts_encl_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D g12a_cts_parent_hws, + .num_parents =3D ARRAY_SIZE(g12a_cts_parent_hws), + .flags =3D CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, + }, +}; + static struct clk_regmap g12a_cts_vdac_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D HHI_VIID_CLK_DIV, @@ -3626,6 +3642,22 @@ static struct clk_regmap g12a_cts_encp =3D { }, }; =20 +static struct clk_regmap g12a_cts_encl =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D HHI_VID_CLK_CNTL2, + .bit_idx =3D 3, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "cts_encl", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &g12a_cts_encl_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, + }, +}; + static struct clk_regmap g12a_cts_vdac =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D HHI_VID_CLK_CNTL2, @@ -4406,10 +4438,12 @@ static struct clk_hw_onecell_data g12a_hw_onecell_d= ata =3D { [CLKID_VCLK2_DIV12] =3D &g12a_vclk2_div12.hw, [CLKID_PRIV_CTS_ENCI_SEL] =3D &g12a_cts_enci_sel.hw, [CLKID_PRIV_CTS_ENCP_SEL] =3D &g12a_cts_encp_sel.hw, + [CLKID_PRIV_CTS_ENCL_SEL] =3D &g12a_cts_encl_sel.hw, [CLKID_PRIV_CTS_VDAC_SEL] =3D &g12a_cts_vdac_sel.hw, [CLKID_PRIV_HDMI_TX_SEL] =3D &g12a_hdmi_tx_sel.hw, [CLKID_CTS_ENCI] =3D &g12a_cts_enci.hw, [CLKID_CTS_ENCP] =3D &g12a_cts_encp.hw, + [CLKID_PRIV_CTS_ENCL] =3D &g12a_cts_encl.hw, [CLKID_CTS_VDAC] =3D &g12a_cts_vdac.hw, [CLKID_HDMI_TX] =3D &g12a_hdmi_tx.hw, [CLKID_PRIV_HDMI_SEL] =3D &g12a_hdmi_sel.hw, @@ -4635,10 +4669,12 @@ static struct clk_hw_onecell_data g12b_hw_onecell_d= ata =3D { [CLKID_VCLK2_DIV12] =3D &g12a_vclk2_div12.hw, [CLKID_PRIV_CTS_ENCI_SEL] =3D &g12a_cts_enci_sel.hw, [CLKID_PRIV_CTS_ENCP_SEL] =3D &g12a_cts_encp_sel.hw, + [CLKID_PRIV_CTS_ENCL_SEL] =3D &g12a_cts_encl_sel.hw, [CLKID_PRIV_CTS_VDAC_SEL] =3D &g12a_cts_vdac_sel.hw, [CLKID_PRIV_HDMI_TX_SEL] =3D &g12a_hdmi_tx_sel.hw, [CLKID_CTS_ENCI] =3D &g12a_cts_enci.hw, [CLKID_CTS_ENCP] =3D &g12a_cts_encp.hw, + [CLKID_PRIV_CTS_ENCL] =3D &g12a_cts_encl.hw, [CLKID_CTS_VDAC] =3D &g12a_cts_vdac.hw, [CLKID_HDMI_TX] =3D &g12a_hdmi_tx.hw, [CLKID_PRIV_HDMI_SEL] =3D &g12a_hdmi_sel.hw, @@ -4899,10 +4935,12 @@ static struct clk_hw_onecell_data sm1_hw_onecell_da= ta =3D { [CLKID_VCLK2_DIV12] =3D &g12a_vclk2_div12.hw, [CLKID_PRIV_CTS_ENCI_SEL] =3D &g12a_cts_enci_sel.hw, [CLKID_PRIV_CTS_ENCP_SEL] =3D &g12a_cts_encp_sel.hw, + [CLKID_PRIV_CTS_ENCL_SEL] =3D &g12a_cts_encl_sel.hw, [CLKID_PRIV_CTS_VDAC_SEL] =3D &g12a_cts_vdac_sel.hw, [CLKID_PRIV_HDMI_TX_SEL] =3D &g12a_hdmi_tx_sel.hw, [CLKID_CTS_ENCI] =3D &g12a_cts_enci.hw, [CLKID_CTS_ENCP] =3D &g12a_cts_encp.hw, + [CLKID_PRIV_CTS_ENCL] =3D &g12a_cts_encl.hw, [CLKID_CTS_VDAC] =3D &g12a_cts_vdac.hw, [CLKID_HDMI_TX] =3D &g12a_hdmi_tx.hw, [CLKID_PRIV_HDMI_SEL] =3D &g12a_hdmi_sel.hw, @@ -5133,10 +5171,12 @@ static struct clk_regmap *const g12a_clk_regmaps[] = =3D { &g12a_vclk2_div12_en, &g12a_cts_enci_sel, &g12a_cts_encp_sel, + &g12a_cts_encl_sel, &g12a_cts_vdac_sel, &g12a_hdmi_tx_sel, &g12a_cts_enci, &g12a_cts_encp, + &g12a_cts_encl, &g12a_cts_vdac, &g12a_hdmi_tx, &g12a_hdmi_sel, diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h index a57f4a9717db..9a3091fcaa41 100644 --- a/drivers/clk/meson/g12a.h +++ b/drivers/clk/meson/g12a.h @@ -265,8 +265,10 @@ #define CLKID_PRIV_NNA_CORE_CLK_SEL 265 #define CLKID_PRIV_NNA_CORE_CLK_DIV 266 #define CLKID_PRIV_MIPI_DSI_PXCLK_DIV 268 +#define CLKID_PRIV_CTS_ENCL 271 +#define CLKID_PRIV_CTS_ENCL_SEL 272 =20 -#define NR_CLKS 271 +#define NR_CLKS 273 =20 /* include the CLKIDs that have been made part of the DT binding */ #include --=20 2.34.1