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Wed, 10 May 2023 10:00:48 -0700 From: Shanker Donthineni To: Thomas Gleixner , Marc Zyngier CC: Sebastian Andrzej Siewior , Michael Walle , Shanker Donthineni , , Vikram Sethi , "Jason Sequeira" Subject: [PATCH v4 2/3] genirq: Encapsulate sparse bitmap handling Date: Wed, 10 May 2023 12:00:32 -0500 Message-ID: <20230510170033.3303076-3-sdonthineni@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230510170033.3303076-1-sdonthineni@nvidia.com> References: <20230510170033.3303076-1-sdonthineni@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D8:EE_|BN9PR12MB5082:EE_ X-MS-Office365-Filtering-Correlation-Id: 48b61b5b-9665-415c-5e5c-08db517822d4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: MdwbJRFOWrbQ3e6uOAw6g4Up2D27X/j9AIuZ79URFFCy4n6EbVqkC564NcILkfnjAlBXRSx9MqzD2hkI9gUKZu2qL2T03zap1dSwHaZ0xdluMGWMaawIoA77mkV5eGcTCwipOBlqZ0gxcrqw2eYVR25phDwG7nXce1gP2TMstCL9CvQMHUTpfOctQe0RLNz2yFonFvIfvVgjv9/gwnP4iv0t6YA6MAQVYEO8bEReG33nYUgbQNgqIL4n39dnqQGTLGnVPuBiqcW9AFeE9X2N/Zo5CZ0JRgSxW0RjqZFJl/MeGwW/OoITIbDjp9Q+fvI9OIp7WLwyIpN7SY+9g8HofmIdxW1bN7pjgbOSkTud/8Huy6jHbHE5S9/Un4FRupBRON6BC+Z9xMRoMsRxL4pInapfoVptIn+XLo58oICkr2TtXnfbalgiR+1olKhe2vVpj+J/jHMpfGrMTe9w+Fzz4WypIsz2kKGo9meEUC4aU0FOsYShGyWKJ4aItRn3fQcEoa9pLU5xbUTiwu/RKySyacW8oFKlQzf2L0N6RVgExfqJaDaDXfUfDJ7r5shFMIYQMpNwwPnog9MOEk8QkNlQt5l9kHhnSGwX8CTVEwBUlsyt3CLHm01F0SLi0JhbgurFSwaLvRxGDR3ee91DtuhVZmfCs2Uswa+G0LH2U3YnXiLI1jowykVsv0S1g7q7KkHGYimA44po/1vv02S1gGNNww== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230028)(4636009)(346002)(376002)(136003)(396003)(39860400002)(451199021)(36840700001)(40470700004)(46966006)(70206006)(70586007)(478600001)(110136005)(54906003)(82740400003)(7636003)(356005)(36860700001)(4326008)(316002)(47076005)(41300700001)(83380400001)(7696005)(426003)(336012)(6666004)(82310400005)(2616005)(40460700003)(8936002)(86362001)(8676002)(26005)(40480700001)(5660300002)(107886003)(1076003)(2906002)(186003)(36756003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2023 17:01:02.4388 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 48b61b5b-9665-415c-5e5c-08db517822d4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5082 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Move the open coded sparse bitmap handling into helper functions as a preparatory step for converting the sparse interrupt management to a maple tree. No functional change. Signed-off-by: Shanker Donthineni --- kernel/irq/internals.h | 4 ++-- kernel/irq/irqdesc.c | 28 +++++++++++++++++++--------- 2 files changed, 21 insertions(+), 11 deletions(-) diff --git a/kernel/irq/internals.h b/kernel/irq/internals.h index 51fc8c497c22..f3f2090dd2de 100644 --- a/kernel/irq/internals.h +++ b/kernel/irq/internals.h @@ -12,9 +12,9 @@ #include =20 #ifdef CONFIG_SPARSE_IRQ -# define IRQ_BITMAP_BITS (NR_IRQS + 8196) +# define MAX_SPARSE_IRQS (NR_IRQS + 8196) #else -# define IRQ_BITMAP_BITS NR_IRQS +# define MAX_SPARSE_IRQS NR_IRQS #endif =20 #define istate core_internal_state__do_not_mess_with_it diff --git a/kernel/irq/irqdesc.c b/kernel/irq/irqdesc.c index f4cb34c87ae7..a741a37d3641 100644 --- a/kernel/irq/irqdesc.c +++ b/kernel/irq/irqdesc.c @@ -131,7 +131,18 @@ int nr_irqs =3D NR_IRQS; EXPORT_SYMBOL_GPL(nr_irqs); =20 static DEFINE_MUTEX(sparse_irq_lock); -static DECLARE_BITMAP(allocated_irqs, IRQ_BITMAP_BITS); +static DECLARE_BITMAP(allocated_irqs, MAX_SPARSE_IRQS); + +static int irq_find_free_area(unsigned int from, unsigned int cnt) +{ + return bitmap_find_next_zero_area(allocated_irqs, MAX_SPARSE_IRQS, + from, cnt, 0); +} + +static unsigned int irq_find_next_irq(unsigned int offset) +{ + return find_next_bit(allocated_irqs, nr_irqs, offset); +} =20 #ifdef CONFIG_SPARSE_IRQ =20 @@ -517,7 +528,7 @@ static int alloc_descs(unsigned int start, unsigned int= cnt, int node, =20 static int irq_expand_nr_irqs(unsigned int nr) { - if (nr > IRQ_BITMAP_BITS) + if (nr > MAX_SPARSE_IRQS) return -ENOMEM; nr_irqs =3D nr; return 0; @@ -535,11 +546,11 @@ int __init early_irq_init(void) printk(KERN_INFO "NR_IRQS: %d, nr_irqs: %d, preallocated irqs: %d\n", NR_IRQS, nr_irqs, initcnt); =20 - if (WARN_ON(nr_irqs > IRQ_BITMAP_BITS)) - nr_irqs =3D IRQ_BITMAP_BITS; + if (WARN_ON(nr_irqs > MAX_SPARSE_IRQS)) + nr_irqs =3D MAX_SPARSE_IRQS; =20 - if (WARN_ON(initcnt > IRQ_BITMAP_BITS)) - initcnt =3D IRQ_BITMAP_BITS; + if (WARN_ON(initcnt > MAX_SPARSE_IRQS)) + initcnt =3D MAX_SPARSE_IRQS; =20 if (initcnt > nr_irqs) nr_irqs =3D initcnt; @@ -812,8 +823,7 @@ __irq_alloc_descs(int irq, unsigned int from, unsigned = int cnt, int node, =20 mutex_lock(&sparse_irq_lock); =20 - start =3D bitmap_find_next_zero_area(allocated_irqs, IRQ_BITMAP_BITS, - from, cnt, 0); + start =3D irq_find_free_area(from, cnt); ret =3D -EEXIST; if (irq >=3D0 && start !=3D irq) goto unlock; @@ -838,7 +848,7 @@ EXPORT_SYMBOL_GPL(__irq_alloc_descs); */ unsigned int irq_get_next_irq(unsigned int offset) { - return find_next_bit(allocated_irqs, nr_irqs, offset); + return irq_find_next_irq(offset); } =20 struct irq_desc * --=20 2.25.1