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Wed, 10 May 2023 07:23:01 -0700 From: Peter De Schrijver To: Peter De Schrijver , Thierry Reding , Jonathan Hunter CC: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joe Perches , , , Subject: [PATCH v3 1/6] dt-bindings: mailbox: tegra: Document Tegra264 HSP Date: Wed, 10 May 2023 17:22:43 +0300 Message-ID: <20230510142248.183629-2-pdeschrijver@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230510142248.183629-1-pdeschrijver@nvidia.com> References: <20230510142248.183629-1-pdeschrijver@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT069:EE_|IA1PR12MB6306:EE_ X-MS-Office365-Filtering-Correlation-Id: 64adb8ae-803e-4c8a-61a6-08db5162170a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: WMunmwWJmQsqr0ULoUyFp3feIUiC6Rvb8akeb2lDIdGJrKa5adYuZIPIyFp4J8dL0lKdKbf7BO643LUWdTYzzTRb4EF2S2yidY+0itMf4wUIj0p94leDZm0+FiTpXyyyS0kt4bxXwMDm4Uwnd07qZl/peebNohAkigpuXFT0E+s7H0GXca+Po6wCsp/J9Hv65OhU6HDBug02yt8FecgzH+j+HrP+AGblQTSjzk3Ym3b/HPouf17jNJH6hpOt4QKoDL9O7+lNOTM/2WloZP6HrQePTTiaV6WyBb2ObaHIAVshmvULBi4BRpnz2X3sQ3twxIEkYkBZAQ2q0hI1am8Lp2Qpz3dZ0VU/1QyiQrf4gx7mBhKZPB86iCRKSPL8PK7OLE25r659EqHAyiM+RszRJimeunbFsBcIXTfMHKq9sc3VPfXvBAwXGue3hdot09yXgLAFlOErVbfg6YOwanY2j78zUUirKuQBpYmsTbclGOU8VDIAUg+Vc7zech/ENjcZZUo/JRrSBLwQeC1MYMLYcSXw2VpXqeD2iQhnKrtlhZjF/72aZnlprwWSXP9wtIxSCYru4Y4NZfo8A4OXaMmlr6la7uQN2mTamUuiISQ4u6gIM5GOrqf5XcGct+4AOkgoxPuqYZUv20/wvX2us/34bC+4Hhfuwzul3MP3v/C4OYP9tSikI4caF7HzzaFY8h+mznBsssWNmT1UXOAJmBVSVotIXg1vU3nayyzxRzHvO/WF4Y6Ex45zkquZUEpjtSUC X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230028)(4636009)(346002)(396003)(376002)(136003)(39860400002)(451199021)(40470700004)(36840700001)(46966006)(41300700001)(26005)(2906002)(4744005)(186003)(15650500001)(40480700001)(1076003)(5660300002)(40460700003)(82740400003)(8936002)(8676002)(110136005)(54906003)(478600001)(36860700001)(83380400001)(2616005)(336012)(426003)(47076005)(36756003)(7636003)(356005)(6666004)(82310400005)(7696005)(86362001)(70206006)(70586007)(316002)(6636002)(4326008);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2023 14:23:13.7164 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 64adb8ae-803e-4c8a-61a6-08db5162170a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT069.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6306 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the compatible string for the HSP block found on the Tegra264 SoC. The HSP block in Tegra264 is not register compatible with the one in Tegra194 or Tegra234 hence there is no fallback compatibility string. Signed-off-by: Peter De Schrijver --- .../devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.= yaml b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml index a3e87516d637..2d14fc948999 100644 --- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml +++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml @@ -66,6 +66,7 @@ properties: oneOf: - const: nvidia,tegra186-hsp - const: nvidia,tegra194-hsp + - const: nvidia,tegra264-hsp - items: - const: nvidia,tegra234-hsp - const: nvidia,tegra194-hsp --=20 2.34.1 From nobody Wed Feb 11 10:42:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19AE6C77B7D for ; Wed, 10 May 2023 14:23:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237413AbjEJOXd (ORCPT ); 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Wed, 10 May 2023 07:23:08 -0700 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Wed, 10 May 2023 07:23:08 -0700 Received: from 44189d9-lcedt.nvidia.com (10.127.8.9) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server id 15.2.986.37 via Frontend Transport; Wed, 10 May 2023 07:23:06 -0700 From: Peter De Schrijver To: Peter De Schrijver , , CC: Stefan Kristiansson , , , Subject: [PATCH v3 2/6] mailbox: tegra: add support for Tegra264 Date: Wed, 10 May 2023 17:22:44 +0300 Message-ID: <20230510142248.183629-3-pdeschrijver@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230510142248.183629-1-pdeschrijver@nvidia.com> References: <20230510142248.183629-1-pdeschrijver@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT069:EE_|SN7PR12MB6839:EE_ X-MS-Office365-Filtering-Correlation-Id: 3e6f2bfe-025d-410b-c92d-08db51621922 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2023 14:23:17.2162 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3e6f2bfe-025d-410b-c92d-08db51621922 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT069.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6839 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Stefan Kristiansson Tegra264 has a slightly different doorbell register layout than previous chips. Signed-off-by: Stefan Kristiansson Signed-off-by: Peter De Schrijver --- drivers/mailbox/tegra-hsp.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/mailbox/tegra-hsp.c b/drivers/mailbox/tegra-hsp.c index 573481e436f5..7f98e7436d94 100644 --- a/drivers/mailbox/tegra-hsp.c +++ b/drivers/mailbox/tegra-hsp.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2023, NVIDIA CORPORATION. All rights reserved. */ =20 #include @@ -97,6 +97,7 @@ struct tegra_hsp_soc { const struct tegra_hsp_db_map *map; bool has_per_mb_ie; bool has_128_bit_mb; + unsigned int reg_stride; }; =20 struct tegra_hsp { @@ -279,7 +280,7 @@ tegra_hsp_doorbell_create(struct tegra_hsp *hsp, const = char *name, return ERR_PTR(-ENOMEM); =20 offset =3D (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) * SZ_64K; - offset +=3D index * 0x100; + offset +=3D index * hsp->soc->reg_stride; =20 db->channel.regs =3D hsp->regs + offset; db->channel.hsp =3D hsp; @@ -916,24 +917,35 @@ static const struct tegra_hsp_soc tegra186_hsp_soc = =3D { .map =3D tegra186_hsp_db_map, .has_per_mb_ie =3D false, .has_128_bit_mb =3D false, + .reg_stride =3D 0x100, }; =20 static const struct tegra_hsp_soc tegra194_hsp_soc =3D { .map =3D tegra186_hsp_db_map, .has_per_mb_ie =3D true, .has_128_bit_mb =3D false, + .reg_stride =3D 0x100, }; =20 static const struct tegra_hsp_soc tegra234_hsp_soc =3D { .map =3D tegra186_hsp_db_map, .has_per_mb_ie =3D false, .has_128_bit_mb =3D true, + .reg_stride =3D 0x100, +}; + +static const struct tegra_hsp_soc tegra264_hsp_soc =3D { + .map =3D tegra186_hsp_db_map, + .has_per_mb_ie =3D false, + .has_128_bit_mb =3D true, + .reg_stride =3D 0x1000, }; =20 static const struct of_device_id tegra_hsp_match[] =3D { { .compatible =3D "nvidia,tegra186-hsp", .data =3D &tegra186_hsp_soc }, { .compatible =3D "nvidia,tegra194-hsp", .data =3D &tegra194_hsp_soc }, { .compatible =3D "nvidia,tegra234-hsp", .data =3D &tegra234_hsp_soc }, + { .compatible =3D "nvidia,tegra264-hsp", .data =3D &tegra264_hsp_soc }, { } }; =20 --=20 2.34.1 From nobody Wed Feb 11 10:42:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F191BC77B7D for ; Wed, 10 May 2023 14:23:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237456AbjEJOXi (ORCPT ); Wed, 10 May 2023 10:23:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54514 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237418AbjEJOXZ (ORCPT ); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2023 14:23:21.7498 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fff87bc0-1afd-492a-5416-08db51621bdb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT036.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6876 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Stefan Kristiansson Add support for Tegra264 to the fuse handling code. Signed-off-by: Stefan Kristiansson Signed-off-by: Peter De Schrijver --- drivers/soc/tegra/fuse/tegra-apbmisc.c | 3 ++- include/soc/tegra/fuse.h | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/soc/tegra/fuse/tegra-apbmisc.c b/drivers/soc/tegra/fus= e/tegra-apbmisc.c index 4591c5bcb690..eb0a1d924526 100644 --- a/drivers/soc/tegra/fuse/tegra-apbmisc.c +++ b/drivers/soc/tegra/fuse/tegra-apbmisc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved. */ =20 #include @@ -62,6 +62,7 @@ bool tegra_is_silicon(void) switch (tegra_get_chip_id()) { case TEGRA194: case TEGRA234: + case TEGRA264: if (tegra_get_platform() =3D=3D 0) return true; =20 diff --git a/include/soc/tegra/fuse.h b/include/soc/tegra/fuse.h index a63de5da8124..3a513be50243 100644 --- a/include/soc/tegra/fuse.h +++ b/include/soc/tegra/fuse.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2012-2023, NVIDIA CORPORATION. All rights reserved. */ =20 #ifndef __SOC_TEGRA_FUSE_H__ @@ -17,6 +17,7 @@ #define TEGRA186 0x18 #define TEGRA194 0x19 #define TEGRA234 0x23 +#define TEGRA264 0x26 =20 #define TEGRA_FUSE_SKU_CALIB_0 0xf0 #define TEGRA30_FUSE_SATA_CALIB 0x124 --=20 2.34.1 From nobody Wed Feb 11 10:42:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F41DBC77B7D for ; Wed, 10 May 2023 14:23:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237383AbjEJOXt (ORCPT ); Wed, 10 May 2023 10:23:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54426 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237437AbjEJOXc (ORCPT ); Wed, 10 May 2023 10:23:32 -0400 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2073.outbound.protection.outlook.com [40.107.92.73]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1E60735A9; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2023 14:23:25.9759 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ccc222b6-503c-47ff-a6f9-08db51621e56 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7383 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add bindings for DRAM MRQ GSC support. Co-developed-by: Stefan Kristiansson Signed-off-by: Stefan Kristiansson Signed-off-by: Peter De Schrijver --- .../nvidia,tegra264-bpmp-shmem.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/reserved-memory/nvidi= a,tegra264-bpmp-shmem.yaml diff --git a/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra= 264-bpmp-shmem.yaml b/Documentation/devicetree/bindings/reserved-memory/nvi= dia,tegra264-bpmp-shmem.yaml new file mode 100644 index 000000000000..4087459c01db --- /dev/null +++ b/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpm= p-shmem.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reserved-memory/nvidia,tegra264-bpmp-sh= mem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tegra CPU-NS - BPMP IPC reserved memory + +maintainers: + - Peter De Schrijver + +description: | + Define a memory region used for communication between CPU-NS and BPMP. + Typically this node is created by the bootloader as the physical address + has to be known to both CPU-NS and BPMP for correct IPC operation. + The memory region is defined using a child node under /reserved-memory. + The sub-node is named shmem@
. + +allOf: + - $ref: reserved-memory.yaml + +properties: + compatible: + const: nvidia,tegra264-bpmp-shmem + + reg: + description: The physical address and size of the shared SDRAM region + +unevaluatedProperties: false + +required: + - compatible + - reg + - no-map + +examples: + - | + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + dram_cpu_bpmp_mail: shmem@f1be0000 { + compatible =3D "nvidia,tegra264-bpmp-shmem"; + reg =3D <0x0 0xf1be0000 0x0 0x2000>; + no-map; + }; + }; +... --=20 2.34.1 From nobody Wed Feb 11 10:42:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42338C7EE26 for ; Wed, 10 May 2023 14:24:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237352AbjEJOYG (ORCPT ); Wed, 10 May 2023 10:24:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54976 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237474AbjEJOXq (ORCPT ); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2023 14:23:32.2559 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 28045f8f-c61c-4b68-6f3b-08db5162221e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT091.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5862 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add memory-region property to the tegra186-bpmp binding to support DRAM MRQ GSCs. Co-developed-by: Stefan Kristiansson Signed-off-by: Stefan Kristiansson Signed-off-by: Peter De Schrijver --- .../firmware/nvidia,tegra186-bpmp.yaml | 37 +++++++++++++++++-- 1 file changed, 34 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpm= p.yaml b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.ya= ml index 833c07f1685c..f3e02c9d090d 100644 --- a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml +++ b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml @@ -57,8 +57,11 @@ description: | "#address-cells" or "#size-cells" property. =20 The shared memory area for the IPC TX and RX between CPU and BPMP are - predefined and work on top of sysram, which is an SRAM inside the - chip. See ".../sram/sram.yaml" for the bindings. + predefined and work on top of either sysram, which is an SRAM inside the + chip, or in normal SDRAM. + See ".../sram/sram.yaml" for the bindings for the SRAM case. + See "../reserved-memory/nvidia,tegra264-bpmp-shmem.yaml" for bindings for + the SDRAM case. =20 properties: compatible: @@ -81,6 +84,11 @@ properties: minItems: 2 maxItems: 2 =20 + memory-region: + description: phandle to reserved memory region used for IPC between + CPU-NS and BPMP. + maxItems: 1 + "#clock-cells": const: 1 =20 @@ -115,10 +123,15 @@ properties: =20 additionalProperties: false =20 +oneOf: + - required: + - memory-region + - required: + - shmem + required: - compatible - mboxes - - shmem - "#clock-cells" - "#power-domain-cells" - "#reset-cells" @@ -184,3 +197,21 @@ examples: #thermal-sensor-cells =3D <1>; }; }; + + - | + #include + + bpmp { + compatible =3D "nvidia,tegra186-bpmp"; + interconnects =3D <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; + interconnect-names =3D "read", "write", "dma-mem", "dma-write"; + mboxes =3D <&hsp_top1 TEGRA_HSP_MBOX_TYPE_DB + TEGRA_HSP_DB_MASTER_BPMP>; + memory-region =3D <&dram_cpu_bpmp_mail>; + #clock-cells =3D <1>; + #power-domain-cells =3D <1>; + #reset-cells =3D <1>; + }; --=20 2.34.1 From nobody Wed Feb 11 10:42:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3824DC77B7D for ; Wed, 10 May 2023 14:24:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237485AbjEJOYR (ORCPT ); Wed, 10 May 2023 10:24:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55946 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237453AbjEJOX7 (ORCPT ); Wed, 10 May 2023 10:23:59 -0400 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2065.outbound.protection.outlook.com [40.107.237.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 300B7DD96; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2023 14:23:37.3746 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 68c5e5b0-07a3-4662-54e0-08db51622524 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT111.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6984 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Implement support for DRAM MRQ GSCs. Signed-off-by: Peter De Schrijver --- drivers/firmware/tegra/bpmp-tegra186.c | 214 +++++++++++++++++-------- drivers/firmware/tegra/bpmp.c | 4 +- 2 files changed, 153 insertions(+), 65 deletions(-) diff --git a/drivers/firmware/tegra/bpmp-tegra186.c b/drivers/firmware/tegr= a/bpmp-tegra186.c index 2e26199041cd..43e2563575fc 100644 --- a/drivers/firmware/tegra/bpmp-tegra186.c +++ b/drivers/firmware/tegra/bpmp-tegra186.c @@ -4,8 +4,11 @@ */ =20 #include +#include #include +#include #include +#include =20 #include #include @@ -13,12 +16,13 @@ =20 #include "bpmp-private.h" =20 +enum tegra_bpmp_mem_type { TEGRA_INVALID, TEGRA_SRAM, TEGRA_RMEM }; + struct tegra186_bpmp { struct tegra_bpmp *parent; =20 struct { - struct gen_pool *pool; - void __iomem *virt; + void *virt; dma_addr_t phys; } tx, rx; =20 @@ -26,6 +30,12 @@ struct tegra186_bpmp { struct mbox_client client; struct mbox_chan *channel; } mbox; + + struct { + struct gen_pool *tx, *rx; + } sram; + + enum tegra_bpmp_mem_type type; }; =20 static inline struct tegra_bpmp * @@ -118,8 +128,8 @@ static int tegra186_bpmp_channel_init(struct tegra_bpmp= _channel *channel, queue_size =3D tegra_ivc_total_queue_size(message_size); offset =3D queue_size * index; =20 - iosys_map_set_vaddr_iomem(&rx, priv->rx.virt + offset); - iosys_map_set_vaddr_iomem(&tx, priv->tx.virt + offset); + iosys_map_set_vaddr_iomem(&rx, (void __iomem *)priv->rx.virt + offset); + iosys_map_set_vaddr_iomem(&tx, (void __iomem *)priv->tx.virt + offset); =20 err =3D tegra_ivc_init(channel->ivc, NULL, &rx, priv->rx.phys + offset, &= tx, priv->tx.phys + offset, 1, message_size, tegra186_bpmp_ivc_notify, @@ -158,64 +168,171 @@ static void mbox_handle_rx(struct mbox_client *clien= t, void *data) tegra_bpmp_handle_rx(bpmp); } =20 -static int tegra186_bpmp_init(struct tegra_bpmp *bpmp) +static void tegra186_bpmp_channel_deinit(struct tegra_bpmp *bpmp) +{ + int i; + struct tegra186_bpmp *priv =3D bpmp->priv; + + for (i =3D 0; i < bpmp->threaded.count; i++) { + if (!bpmp->threaded_channels[i].bpmp) + continue; + + tegra186_bpmp_channel_cleanup(&bpmp->threaded_channels[i]); + } + + tegra186_bpmp_channel_cleanup(bpmp->rx_channel); + tegra186_bpmp_channel_cleanup(bpmp->tx_channel); + + if (priv->type =3D=3D TEGRA_SRAM) { + gen_pool_free(priv->sram.tx, (unsigned long)priv->tx.virt, 4096); + gen_pool_free(priv->sram.rx, (unsigned long)priv->rx.virt, 4096); + } else if (priv->type =3D=3D TEGRA_RMEM) { + memunmap(priv->tx.virt); + } +} + +static int tegra186_bpmp_channel_setup(struct tegra_bpmp *bpmp) { - struct tegra186_bpmp *priv; unsigned int i; int err; =20 - priv =3D devm_kzalloc(bpmp->dev, sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; + err =3D tegra186_bpmp_channel_init(bpmp->tx_channel, bpmp, + bpmp->soc->channels.cpu_tx.offset); + if (err < 0) + return err; =20 - bpmp->priv =3D priv; - priv->parent =3D bpmp; + err =3D tegra186_bpmp_channel_init(bpmp->rx_channel, bpmp, + bpmp->soc->channels.cpu_rx.offset); + if (err < 0) { + tegra186_bpmp_channel_cleanup(bpmp->tx_channel); + return err; + } + + for (i =3D 0; i < bpmp->threaded.count; i++) { + unsigned int index =3D bpmp->soc->channels.thread.offset + i; =20 - priv->tx.pool =3D of_gen_pool_get(bpmp->dev->of_node, "shmem", 0); - if (!priv->tx.pool) { + err =3D tegra186_bpmp_channel_init(&bpmp->threaded_channels[i], + bpmp, index); + if (err < 0) + break; + } + + if (err < 0) + tegra186_bpmp_channel_deinit(bpmp); + + return err; +} + +static void tegra186_bpmp_reset_channels(struct tegra_bpmp *bpmp) +{ + unsigned int i; + + tegra186_bpmp_channel_reset(bpmp->tx_channel); + tegra186_bpmp_channel_reset(bpmp->rx_channel); + + for (i =3D 0; i < bpmp->threaded.count; i++) + tegra186_bpmp_channel_reset(&bpmp->threaded_channels[i]); +} + +static int tegra186_bpmp_sram_init(struct tegra_bpmp *bpmp) +{ + int err; + struct tegra186_bpmp *priv =3D bpmp->priv; + + priv->sram.tx =3D of_gen_pool_get(bpmp->dev->of_node, "shmem", 0); + if (!priv->sram.tx) { dev_err(bpmp->dev, "TX shmem pool not found\n"); return -EPROBE_DEFER; } =20 - priv->tx.virt =3D (void __iomem *)gen_pool_dma_alloc(priv->tx.pool, 4096,= &priv->tx.phys); + priv->tx.virt =3D gen_pool_dma_alloc(priv->sram.tx, 4096, &priv->tx.phys); if (!priv->tx.virt) { dev_err(bpmp->dev, "failed to allocate from TX pool\n"); return -ENOMEM; } =20 - priv->rx.pool =3D of_gen_pool_get(bpmp->dev->of_node, "shmem", 1); - if (!priv->rx.pool) { + priv->sram.rx =3D of_gen_pool_get(bpmp->dev->of_node, "shmem", 1); + if (!priv->sram.rx) { dev_err(bpmp->dev, "RX shmem pool not found\n"); err =3D -EPROBE_DEFER; goto free_tx; } =20 - priv->rx.virt =3D (void __iomem *)gen_pool_dma_alloc(priv->rx.pool, 4096,= &priv->rx.phys); + priv->rx.virt =3D gen_pool_dma_alloc(priv->sram.rx, 4096, &priv->rx.phys); if (!priv->rx.virt) { dev_err(bpmp->dev, "failed to allocate from RX pool\n"); err =3D -ENOMEM; goto free_tx; } =20 - err =3D tegra186_bpmp_channel_init(bpmp->tx_channel, bpmp, - bpmp->soc->channels.cpu_tx.offset); - if (err < 0) - goto free_rx; + priv->type =3D TEGRA_SRAM; =20 - err =3D tegra186_bpmp_channel_init(bpmp->rx_channel, bpmp, - bpmp->soc->channels.cpu_rx.offset); - if (err < 0) - goto cleanup_tx_channel; + return 0; =20 - for (i =3D 0; i < bpmp->threaded.count; i++) { - unsigned int index =3D bpmp->soc->channels.thread.offset + i; +free_tx: + gen_pool_free(priv->sram.tx, (unsigned long)priv->tx.virt, 4096); =20 - err =3D tegra186_bpmp_channel_init(&bpmp->threaded_channels[i], - bpmp, index); + return err; +} + +static enum tegra_bpmp_mem_type tegra186_bpmp_dram_init(struct tegra_bpmp = *bpmp) +{ + int err; + struct resource res; + struct device_node *np; + struct tegra186_bpmp *priv =3D bpmp->priv; + + np =3D of_parse_phandle(bpmp->dev->of_node, "memory-region", 0); + if (!np) + return TEGRA_INVALID; + + err =3D of_address_to_resource(np, 0, &res); + if (err) { + dev_warn(bpmp->dev, "Parsing memory region returned: %d\n", err); + return TEGRA_INVALID; + } + + if ((res.end - res.start + 1) < 0x2000) { + dev_warn(bpmp->dev, "DRAM region less than 0x2000 bytes\n"); + return TEGRA_INVALID; + } + + priv->tx.phys =3D res.start; + priv->rx.phys =3D res.start + 0x1000; + + priv->tx.virt =3D memremap(priv->tx.phys, res.end - res.start + 1, MEMREM= AP_WC); + if (priv->tx.virt =3D=3D NULL) { + dev_warn(bpmp->dev, "DRAM region mapping failed\n"); + return TEGRA_INVALID; + } + priv->rx.virt =3D priv->tx.virt + 0x1000; + + return TEGRA_RMEM; +} + +static int tegra186_bpmp_init(struct tegra_bpmp *bpmp) +{ + struct tegra186_bpmp *priv; + int err; + + priv =3D devm_kzalloc(bpmp->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + bpmp->priv =3D priv; + priv->parent =3D bpmp; + + priv->type =3D tegra186_bpmp_dram_init(bpmp); + if (priv->type =3D=3D TEGRA_INVALID) { + err =3D tegra186_bpmp_sram_init(bpmp); if (err < 0) - goto cleanup_channels; + return err; } =20 + err =3D tegra186_bpmp_channel_setup(bpmp); + if (err < 0) + return err; + /* mbox registration */ priv->mbox.client.dev =3D bpmp->dev; priv->mbox.client.rx_callback =3D mbox_handle_rx; @@ -226,51 +343,22 @@ static int tegra186_bpmp_init(struct tegra_bpmp *bpmp) if (IS_ERR(priv->mbox.channel)) { err =3D PTR_ERR(priv->mbox.channel); dev_err(bpmp->dev, "failed to get HSP mailbox: %d\n", err); - goto cleanup_channels; + tegra186_bpmp_channel_deinit(bpmp); + return err; } =20 - tegra186_bpmp_channel_reset(bpmp->tx_channel); - tegra186_bpmp_channel_reset(bpmp->rx_channel); - - for (i =3D 0; i < bpmp->threaded.count; i++) - tegra186_bpmp_channel_reset(&bpmp->threaded_channels[i]); + tegra186_bpmp_reset_channels(bpmp); =20 return 0; - -cleanup_channels: - for (i =3D 0; i < bpmp->threaded.count; i++) { - if (!bpmp->threaded_channels[i].bpmp) - continue; - - tegra186_bpmp_channel_cleanup(&bpmp->threaded_channels[i]); - } - - tegra186_bpmp_channel_cleanup(bpmp->rx_channel); -cleanup_tx_channel: - tegra186_bpmp_channel_cleanup(bpmp->tx_channel); -free_rx: - gen_pool_free(priv->rx.pool, (unsigned long)priv->rx.virt, 4096); -free_tx: - gen_pool_free(priv->tx.pool, (unsigned long)priv->tx.virt, 4096); - - return err; } =20 static void tegra186_bpmp_deinit(struct tegra_bpmp *bpmp) { struct tegra186_bpmp *priv =3D bpmp->priv; - unsigned int i; =20 mbox_free_channel(priv->mbox.channel); =20 - for (i =3D 0; i < bpmp->threaded.count; i++) - tegra186_bpmp_channel_cleanup(&bpmp->threaded_channels[i]); - - tegra186_bpmp_channel_cleanup(bpmp->rx_channel); - tegra186_bpmp_channel_cleanup(bpmp->tx_channel); - - gen_pool_free(priv->rx.pool, (unsigned long)priv->rx.virt, 4096); - gen_pool_free(priv->tx.pool, (unsigned long)priv->tx.virt, 4096); + tegra186_bpmp_channel_deinit(bpmp); } =20 static int tegra186_bpmp_resume(struct tegra_bpmp *bpmp) diff --git a/drivers/firmware/tegra/bpmp.c b/drivers/firmware/tegra/bpmp.c index 8b5e5daa9fae..17bd3590aaa2 100644 --- a/drivers/firmware/tegra/bpmp.c +++ b/drivers/firmware/tegra/bpmp.c @@ -735,6 +735,8 @@ static int tegra_bpmp_probe(struct platform_device *pde= v) if (!bpmp->threaded_channels) return -ENOMEM; =20 + platform_set_drvdata(pdev, bpmp); + err =3D bpmp->soc->ops->init(bpmp); if (err < 0) return err; @@ -758,8 +760,6 @@ static int tegra_bpmp_probe(struct platform_device *pde= v) =20 dev_info(&pdev->dev, "firmware: %.*s\n", (int)sizeof(tag), tag); =20 - platform_set_drvdata(pdev, bpmp); - err =3D of_platform_default_populate(pdev->dev.of_node, NULL, &pdev->dev); if (err < 0) goto free_mrq; --=20 2.34.1