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Wed, 10 May 2023 04:38:05 -0700 From: Peter De Schrijver To: Peter De Schrijver , , , CC: , , , , , Subject: [PATCH v2 6/6] firmware: tegra: bpmp: Add support for DRAM MRQ GSCs Date: Wed, 10 May 2023 14:31:36 +0300 Message-ID: <20230510113129.4167493-7-pdeschrijver@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230510113129.4167493-1-pdeschrijver@nvidia.com> References: <20230510113129.4167493-1-pdeschrijver@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT017:EE_|SJ2PR12MB8159:EE_ X-MS-Office365-Filtering-Correlation-Id: 1c07478e-1fee-4d70-1854-08db514b0f9b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: mF9FBREuGlQiICNv4qZo/KVasuSpksZFU5Pup4uX57OdCzSehJ9neXzd2uMM/Ms4atVr283Go29heQ46FwmzTxzGIJRpUaQEDAHeDejy1bP//mLKA5UvM7b24v2FhuKJfOfNcQMxMDSMqXw1SSmPaktKY5MehnJsZcSFEiMRJ+TKsDBCZj/fClK3elQiQb6QzhfSYzrl/vHIjMaIb7gMrKwcyxjAvzbnSOprN+6lIdg9zUXUgm20Zln56/7XXJxoNzE83yJd8cP10MXHimVBCwqSDMGJGvopvtjymXURkyeh47SgQSWRxON7QlsoJfPGOTWDAj7qjV4DTd1bUTP4cRBGfwWGGn0E/hG4OWxYcziWKGTMTWtpeSmQjr/CcD/zE84pNEMH1XtcK2M1SR/feO0ooCdDsh+fQWav9Yobr3Jas/AzEehJ3a1OKsQteXa65+/Jz2xx/cKZ02RK9lApZMa28usRDagywNOJOGVlLYY18COovFqqJ/jCmvOn//Pli3+cZ1RzoV4uDkQfE/7+l4gdik3PvgXyVo4XEhO1/zT/YTBCbPSVnPKd/GYYsdIP6DTDsKil6fr1T2FutzOqTGLrktbTD8nDMiRgza38z4w26AgvsVbb87eTG/Ybk7ebQtPZq232oA96aMcZestvxZt4/+DLXVZppNPEWlEmyoX/sd+z4y2yJpCS3whCQV7rR3v72u0f1BE9aK62wZpVBQ== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230028)(4636009)(136003)(396003)(376002)(346002)(39860400002)(451199021)(46966006)(36840700001)(40470700004)(83380400001)(82310400005)(6666004)(36756003)(336012)(426003)(47076005)(36860700001)(86362001)(40480700001)(7636003)(82740400003)(186003)(356005)(26005)(2616005)(40460700003)(107886003)(1076003)(7696005)(70206006)(110136005)(8936002)(2906002)(70586007)(54906003)(4326008)(41300700001)(6636002)(316002)(5660300002)(8676002)(478600001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2023 11:38:22.7401 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1c07478e-1fee-4d70-1854-08db514b0f9b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT017.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8159 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Implement support for DRAM MRQ GSCs. Signed-off-by: Peter De Schrijver --- drivers/firmware/tegra/bpmp-tegra186.c | 214 +++++++++++++++++-------- drivers/firmware/tegra/bpmp.c | 4 +- 2 files changed, 153 insertions(+), 65 deletions(-) diff --git a/drivers/firmware/tegra/bpmp-tegra186.c b/drivers/firmware/tegr= a/bpmp-tegra186.c index 2e26199041cd..43e2563575fc 100644 --- a/drivers/firmware/tegra/bpmp-tegra186.c +++ b/drivers/firmware/tegra/bpmp-tegra186.c @@ -4,8 +4,11 @@ */ =20 #include +#include #include +#include #include +#include =20 #include #include @@ -13,12 +16,13 @@ =20 #include "bpmp-private.h" =20 +enum tegra_bpmp_mem_type { TEGRA_INVALID, TEGRA_SRAM, TEGRA_RMEM }; + struct tegra186_bpmp { struct tegra_bpmp *parent; =20 struct { - struct gen_pool *pool; - void __iomem *virt; + void *virt; dma_addr_t phys; } tx, rx; =20 @@ -26,6 +30,12 @@ struct tegra186_bpmp { struct mbox_client client; struct mbox_chan *channel; } mbox; + + struct { + struct gen_pool *tx, *rx; + } sram; + + enum tegra_bpmp_mem_type type; }; =20 static inline struct tegra_bpmp * @@ -118,8 +128,8 @@ static int tegra186_bpmp_channel_init(struct tegra_bpmp= _channel *channel, queue_size =3D tegra_ivc_total_queue_size(message_size); offset =3D queue_size * index; =20 - iosys_map_set_vaddr_iomem(&rx, priv->rx.virt + offset); - iosys_map_set_vaddr_iomem(&tx, priv->tx.virt + offset); + iosys_map_set_vaddr_iomem(&rx, (void __iomem *)priv->rx.virt + offset); + iosys_map_set_vaddr_iomem(&tx, (void __iomem *)priv->tx.virt + offset); =20 err =3D tegra_ivc_init(channel->ivc, NULL, &rx, priv->rx.phys + offset, &= tx, priv->tx.phys + offset, 1, message_size, tegra186_bpmp_ivc_notify, @@ -158,64 +168,171 @@ static void mbox_handle_rx(struct mbox_client *clien= t, void *data) tegra_bpmp_handle_rx(bpmp); } =20 -static int tegra186_bpmp_init(struct tegra_bpmp *bpmp) +static void tegra186_bpmp_channel_deinit(struct tegra_bpmp *bpmp) +{ + int i; + struct tegra186_bpmp *priv =3D bpmp->priv; + + for (i =3D 0; i < bpmp->threaded.count; i++) { + if (!bpmp->threaded_channels[i].bpmp) + continue; + + tegra186_bpmp_channel_cleanup(&bpmp->threaded_channels[i]); + } + + tegra186_bpmp_channel_cleanup(bpmp->rx_channel); + tegra186_bpmp_channel_cleanup(bpmp->tx_channel); + + if (priv->type =3D=3D TEGRA_SRAM) { + gen_pool_free(priv->sram.tx, (unsigned long)priv->tx.virt, 4096); + gen_pool_free(priv->sram.rx, (unsigned long)priv->rx.virt, 4096); + } else if (priv->type =3D=3D TEGRA_RMEM) { + memunmap(priv->tx.virt); + } +} + +static int tegra186_bpmp_channel_setup(struct tegra_bpmp *bpmp) { - struct tegra186_bpmp *priv; unsigned int i; int err; =20 - priv =3D devm_kzalloc(bpmp->dev, sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; + err =3D tegra186_bpmp_channel_init(bpmp->tx_channel, bpmp, + bpmp->soc->channels.cpu_tx.offset); + if (err < 0) + return err; =20 - bpmp->priv =3D priv; - priv->parent =3D bpmp; + err =3D tegra186_bpmp_channel_init(bpmp->rx_channel, bpmp, + bpmp->soc->channels.cpu_rx.offset); + if (err < 0) { + tegra186_bpmp_channel_cleanup(bpmp->tx_channel); + return err; + } + + for (i =3D 0; i < bpmp->threaded.count; i++) { + unsigned int index =3D bpmp->soc->channels.thread.offset + i; =20 - priv->tx.pool =3D of_gen_pool_get(bpmp->dev->of_node, "shmem", 0); - if (!priv->tx.pool) { + err =3D tegra186_bpmp_channel_init(&bpmp->threaded_channels[i], + bpmp, index); + if (err < 0) + break; + } + + if (err < 0) + tegra186_bpmp_channel_deinit(bpmp); + + return err; +} + +static void tegra186_bpmp_reset_channels(struct tegra_bpmp *bpmp) +{ + unsigned int i; + + tegra186_bpmp_channel_reset(bpmp->tx_channel); + tegra186_bpmp_channel_reset(bpmp->rx_channel); + + for (i =3D 0; i < bpmp->threaded.count; i++) + tegra186_bpmp_channel_reset(&bpmp->threaded_channels[i]); +} + +static int tegra186_bpmp_sram_init(struct tegra_bpmp *bpmp) +{ + int err; + struct tegra186_bpmp *priv =3D bpmp->priv; + + priv->sram.tx =3D of_gen_pool_get(bpmp->dev->of_node, "shmem", 0); + if (!priv->sram.tx) { dev_err(bpmp->dev, "TX shmem pool not found\n"); return -EPROBE_DEFER; } =20 - priv->tx.virt =3D (void __iomem *)gen_pool_dma_alloc(priv->tx.pool, 4096,= &priv->tx.phys); + priv->tx.virt =3D gen_pool_dma_alloc(priv->sram.tx, 4096, &priv->tx.phys); if (!priv->tx.virt) { dev_err(bpmp->dev, "failed to allocate from TX pool\n"); return -ENOMEM; } =20 - priv->rx.pool =3D of_gen_pool_get(bpmp->dev->of_node, "shmem", 1); - if (!priv->rx.pool) { + priv->sram.rx =3D of_gen_pool_get(bpmp->dev->of_node, "shmem", 1); + if (!priv->sram.rx) { dev_err(bpmp->dev, "RX shmem pool not found\n"); err =3D -EPROBE_DEFER; goto free_tx; } =20 - priv->rx.virt =3D (void __iomem *)gen_pool_dma_alloc(priv->rx.pool, 4096,= &priv->rx.phys); + priv->rx.virt =3D gen_pool_dma_alloc(priv->sram.rx, 4096, &priv->rx.phys); if (!priv->rx.virt) { dev_err(bpmp->dev, "failed to allocate from RX pool\n"); err =3D -ENOMEM; goto free_tx; } =20 - err =3D tegra186_bpmp_channel_init(bpmp->tx_channel, bpmp, - bpmp->soc->channels.cpu_tx.offset); - if (err < 0) - goto free_rx; + priv->type =3D TEGRA_SRAM; =20 - err =3D tegra186_bpmp_channel_init(bpmp->rx_channel, bpmp, - bpmp->soc->channels.cpu_rx.offset); - if (err < 0) - goto cleanup_tx_channel; + return 0; =20 - for (i =3D 0; i < bpmp->threaded.count; i++) { - unsigned int index =3D bpmp->soc->channels.thread.offset + i; +free_tx: + gen_pool_free(priv->sram.tx, (unsigned long)priv->tx.virt, 4096); =20 - err =3D tegra186_bpmp_channel_init(&bpmp->threaded_channels[i], - bpmp, index); + return err; +} + +static enum tegra_bpmp_mem_type tegra186_bpmp_dram_init(struct tegra_bpmp = *bpmp) +{ + int err; + struct resource res; + struct device_node *np; + struct tegra186_bpmp *priv =3D bpmp->priv; + + np =3D of_parse_phandle(bpmp->dev->of_node, "memory-region", 0); + if (!np) + return TEGRA_INVALID; + + err =3D of_address_to_resource(np, 0, &res); + if (err) { + dev_warn(bpmp->dev, "Parsing memory region returned: %d\n", err); + return TEGRA_INVALID; + } + + if ((res.end - res.start + 1) < 0x2000) { + dev_warn(bpmp->dev, "DRAM region less than 0x2000 bytes\n"); + return TEGRA_INVALID; + } + + priv->tx.phys =3D res.start; + priv->rx.phys =3D res.start + 0x1000; + + priv->tx.virt =3D memremap(priv->tx.phys, res.end - res.start + 1, MEMREM= AP_WC); + if (priv->tx.virt =3D=3D NULL) { + dev_warn(bpmp->dev, "DRAM region mapping failed\n"); + return TEGRA_INVALID; + } + priv->rx.virt =3D priv->tx.virt + 0x1000; + + return TEGRA_RMEM; +} + +static int tegra186_bpmp_init(struct tegra_bpmp *bpmp) +{ + struct tegra186_bpmp *priv; + int err; + + priv =3D devm_kzalloc(bpmp->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + bpmp->priv =3D priv; + priv->parent =3D bpmp; + + priv->type =3D tegra186_bpmp_dram_init(bpmp); + if (priv->type =3D=3D TEGRA_INVALID) { + err =3D tegra186_bpmp_sram_init(bpmp); if (err < 0) - goto cleanup_channels; + return err; } =20 + err =3D tegra186_bpmp_channel_setup(bpmp); + if (err < 0) + return err; + /* mbox registration */ priv->mbox.client.dev =3D bpmp->dev; priv->mbox.client.rx_callback =3D mbox_handle_rx; @@ -226,51 +343,22 @@ static int tegra186_bpmp_init(struct tegra_bpmp *bpmp) if (IS_ERR(priv->mbox.channel)) { err =3D PTR_ERR(priv->mbox.channel); dev_err(bpmp->dev, "failed to get HSP mailbox: %d\n", err); - goto cleanup_channels; + tegra186_bpmp_channel_deinit(bpmp); + return err; } =20 - tegra186_bpmp_channel_reset(bpmp->tx_channel); - tegra186_bpmp_channel_reset(bpmp->rx_channel); - - for (i =3D 0; i < bpmp->threaded.count; i++) - tegra186_bpmp_channel_reset(&bpmp->threaded_channels[i]); + tegra186_bpmp_reset_channels(bpmp); =20 return 0; - -cleanup_channels: - for (i =3D 0; i < bpmp->threaded.count; i++) { - if (!bpmp->threaded_channels[i].bpmp) - continue; - - tegra186_bpmp_channel_cleanup(&bpmp->threaded_channels[i]); - } - - tegra186_bpmp_channel_cleanup(bpmp->rx_channel); -cleanup_tx_channel: - tegra186_bpmp_channel_cleanup(bpmp->tx_channel); -free_rx: - gen_pool_free(priv->rx.pool, (unsigned long)priv->rx.virt, 4096); -free_tx: - gen_pool_free(priv->tx.pool, (unsigned long)priv->tx.virt, 4096); - - return err; } =20 static void tegra186_bpmp_deinit(struct tegra_bpmp *bpmp) { struct tegra186_bpmp *priv =3D bpmp->priv; - unsigned int i; =20 mbox_free_channel(priv->mbox.channel); =20 - for (i =3D 0; i < bpmp->threaded.count; i++) - tegra186_bpmp_channel_cleanup(&bpmp->threaded_channels[i]); - - tegra186_bpmp_channel_cleanup(bpmp->rx_channel); - tegra186_bpmp_channel_cleanup(bpmp->tx_channel); - - gen_pool_free(priv->rx.pool, (unsigned long)priv->rx.virt, 4096); - gen_pool_free(priv->tx.pool, (unsigned long)priv->tx.virt, 4096); + tegra186_bpmp_channel_deinit(bpmp); } =20 static int tegra186_bpmp_resume(struct tegra_bpmp *bpmp) diff --git a/drivers/firmware/tegra/bpmp.c b/drivers/firmware/tegra/bpmp.c index 8b5e5daa9fae..17bd3590aaa2 100644 --- a/drivers/firmware/tegra/bpmp.c +++ b/drivers/firmware/tegra/bpmp.c @@ -735,6 +735,8 @@ static int tegra_bpmp_probe(struct platform_device *pde= v) if (!bpmp->threaded_channels) return -ENOMEM; =20 + platform_set_drvdata(pdev, bpmp); + err =3D bpmp->soc->ops->init(bpmp); if (err < 0) return err; @@ -758,8 +760,6 @@ static int tegra_bpmp_probe(struct platform_device *pde= v) =20 dev_info(&pdev->dev, "firmware: %.*s\n", (int)sizeof(tag), tag); =20 - platform_set_drvdata(pdev, bpmp); - err =3D of_platform_default_populate(pdev->dev.of_node, NULL, &pdev->dev); if (err < 0) goto free_mrq; --=20 2.34.1