From nobody Wed Feb 11 10:43:55 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C62AC77B7C for ; Wed, 10 May 2023 10:44:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236735AbjEJKok (ORCPT ); Wed, 10 May 2023 06:44:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52134 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236676AbjEJKod (ORCPT ); Wed, 10 May 2023 06:44:33 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DFE0D7AA7; Wed, 10 May 2023 03:44:30 -0700 (PDT) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34AAHSs4019002; Wed, 10 May 2023 10:44:28 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=YIHnMmHMw/x+gAuRqtxvwzS2d+0swEIvuLoxNhcrLiA=; b=o434+bksF/9LHUM3OvSrC61c4+B44scZSGjpncQ4pt5+k5KEcOlvvu6Ju5PTsOla0/44 t1lsXLNJbOOcO5WcGzDQp+N97ejcrruZzTGEEHmBfXWuu9pR7tbOcCX21yer/Ff2tdOC YMO+jaHmFMIZPaF6mwm515kyGeMnv6pNwPKs9+3mVvaXQBwkZpmS3LnptgK+o0m55pEs YvU51NoxIJP/FyJpG8sboEHlLgPDVcicHwRfOdgWyC8TYjYJ4zRviRdTf0WtjaiLx+FQ 6tTCQnP+I6oZZ1pif6wu3pvr9teuLlvlnVvSVKwL9Ym2O5Sk9FDhK90NmHGbvXbkoI0h mg== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qg5mprfux-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 10 May 2023 10:44:27 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34AAiRGb014280 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 10 May 2023 10:44:27 GMT Received: from devipriy-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Wed, 10 May 2023 03:44:22 -0700 From: Devi Priya To: , , , , , , , , CC: , , , , , Subject: [PATCH 2/2] arm64: dts: qcom: ipq9574: add support for RDP418 variant Date: Wed, 10 May 2023 16:13:59 +0530 Message-ID: <20230510104359.16678-3-quic_devipriy@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230510104359.16678-1-quic_devipriy@quicinc.com> References: <20230510104359.16678-1-quic_devipriy@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: zlYGBBt4uPtory1UWCjUzR4c76fAgymt X-Proofpoint-GUID: zlYGBBt4uPtory1UWCjUzR4c76fAgymt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-10_04,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 phishscore=0 mlxlogscore=999 clxscore=1015 suspectscore=0 malwarescore=0 mlxscore=0 adultscore=0 lowpriorityscore=0 impostorscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305100085 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the initial device tree support for the Reference Design Platform (RDP) 418 based on IPQ9574 family of SoCs. This patch adds support for Console UART, SPI NOR, eMMC and SMPA1 regulator node. Co-developed-by: Anusha Rao Signed-off-by: Anusha Rao Signed-off-by: Devi Priya --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts | 124 ++++++++++++++++++++ 2 files changed, 125 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 4d7789a06186..29c862035861 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D ipq6018-cp01-c1.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq8074-hk01.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq8074-hk10-c1.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq8074-hk10-c2.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp418.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp433.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-alcatel-idol347.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts b/arch/arm64/boot/= dts/qcom/ipq9574-rdp418.dts new file mode 100644 index 000000000000..2b093e02637b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * IPQ9574 RDP418 board device tree source + * + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights res= erved. + */ + +/dts-v1/; + +#include "ipq9574.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C2"; + compatible =3D "qcom,ipq9574-ap-al02-c2", "qcom,ipq9574"; + + aliases { + serial0 =3D &blsp1_uart2; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; +}; + +&blsp1_spi0 { + pinctrl-0 =3D <&spi_0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + flash@0 { + compatible =3D "micron,n25q128a11", "jedec,spi-nor"; + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <1>; + spi-max-frequency =3D <50000000>; + }; +}; + +&blsp1_uart2 { + pinctrl-0 =3D <&uart2_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&rpm_requests { + regulators { + compatible =3D "qcom,rpm-mp5496-regulators"; + + ipq9574_s1: s1 { + /* + * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bo= otloaders. + * During regulator registration, kernel not knowing the initial voltage, + * considers it as zero and brings up the regulators with minimum suppor= ted voltage. + * Update the regulator-min-microvolt with SVS voltage of 725mV so that + * the regulators are brought up with 725mV which is sufficient for all = the + * corner parts to operate at 800MHz + */ + regulator-min-microvolt =3D <725000>; + regulator-max-microvolt =3D <1075000>; + }; + }; +}; + +&sdhc_1 { + pinctrl-0 =3D <&sdc_default_state>; + pinctrl-names =3D "default"; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + max-frequency =3D <384000000>; + bus-width =3D <8>; + status =3D "okay"; +}; + +&sleep_clk { + clock-frequency =3D <32000>; +}; + +&tlmm { + sdc_default_state: sdc-default-state { + clk-pins { + pins =3D "gpio5"; + function =3D "sdc_clk"; + drive-strength =3D <8>; + bias-disable; + }; + + cmd-pins { + pins =3D "gpio4"; + function =3D "sdc_cmd"; + drive-strength =3D <8>; + bias-pull-up; + }; + + data-pins { + pins =3D "gpio0", "gpio1", "gpio2", + "gpio3", "gpio6", "gpio7", + "gpio8", "gpio9"; + function =3D "sdc_data"; + drive-strength =3D <8>; + bias-pull-up; + }; + + rclk-pins { + pins =3D "gpio10"; + function =3D "sdc_rclk"; + drive-strength =3D <8>; + bias-pull-down; + }; + }; + + spi_0_pins: spi-0-state { + pins =3D "gpio11", "gpio12", "gpio13", "gpio14"; + function =3D "blsp0_spi"; + drive-strength =3D <8>; + bias-disable; + }; +}; + +&xo_board_clk { + clock-frequency =3D <24000000>; +}; --=20 2.17.1