From nobody Wed Feb 11 12:14:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A0B8C77B75 for ; Wed, 10 May 2023 01:53:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235495AbjEJBxf convert rfc822-to-8bit (ORCPT ); Tue, 9 May 2023 21:53:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59756 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235364AbjEJBxW (ORCPT ); Tue, 9 May 2023 21:53:22 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20A1B35B3; Tue, 9 May 2023 18:53:21 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id B60DC24E289; Wed, 10 May 2023 09:53:14 +0800 (CST) Received: from EXMBX062.cuchost.com (172.16.6.62) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 10 May 2023 09:53:14 +0800 Received: from ubuntu.localdomain (183.27.98.219) by EXMBX062.cuchost.com (172.16.6.62) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 10 May 2023 09:53:13 +0800 From: Changhuang Liang To: Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou CC: Walker Chen , Changhuang Liang , Hal Feng , , , Subject: [PATCH v3 1/5] dt-bindings: power: Add JH7110 AON PMU support Date: Tue, 9 May 2023 18:53:07 -0700 Message-ID: <20230510015311.27505-2-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230510015311.27505-1-changhuang.liang@starfivetech.com> References: <20230510015311.27505-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.98.219] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX062.cuchost.com (172.16.6.62) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add AON PMU for StarFive JH7110 SoC, it can be used to turn on/off DPHY rx/tx power switch, and it don't need the property of interrupts. It also can use syscon operation. Signed-off-by: Changhuang Liang --- .../bindings/power/starfive,jh7110-pmu.yaml | 28 +++++++++++++++++-- .../dt-bindings/power/starfive,jh7110-pmu.h | 5 +++- 2 files changed, 29 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.ya= ml b/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml index 98eb8b4110e7..0591a4e9db6c 100644 --- a/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml +++ b/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml @@ -8,6 +8,7 @@ title: StarFive JH7110 Power Management Unit =20 maintainers: - Walker Chen + - Changhuang Liang =20 description: | StarFive JH7110 SoC includes support for multiple power domains which ca= n be @@ -15,8 +16,13 @@ description: | =20 properties: compatible: - enum: - - starfive,jh7110-pmu + oneOf: + - enum: + - starfive,jh7110-pmu + - items: + - enum: + - starfive,jh7110-aon-syscon + - const: syscon =20 reg: maxItems: 1 @@ -30,9 +36,18 @@ properties: required: - compatible - reg - - interrupts - "#power-domain-cells" =20 +allOf: + - if: + properties: + compatible: + contains: + const: starfive,jh7110-pmu + then: + required: + - interrupts + additionalProperties: false =20 examples: @@ -43,3 +58,10 @@ examples: interrupts =3D <111>; #power-domain-cells =3D <1>; }; + + - | + aon_syscon: syscon@17010000 { + compatible =3D "starfive,jh7110-aon-syscon", "syscon"; + reg =3D <0x17010000 0x1000>; + #power-domain-cells =3D <1>; + }; diff --git a/include/dt-bindings/power/starfive,jh7110-pmu.h b/include/dt-b= indings/power/starfive,jh7110-pmu.h index 132bfe401fc8..341e2a0676ba 100644 --- a/include/dt-bindings/power/starfive,jh7110-pmu.h +++ b/include/dt-bindings/power/starfive,jh7110-pmu.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ /* - * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. * Author: Walker Chen */ #ifndef __DT_BINDINGS_POWER_JH7110_POWER_H__ @@ -14,4 +14,7 @@ #define JH7110_PD_ISP 5 #define JH7110_PD_VENC 6 =20 +#define JH7110_PD_DPHY_TX 0 +#define JH7110_PD_DPHY_RX 1 + #endif --=20 2.25.1 From nobody Wed Feb 11 12:14:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 194BCC7EE26 for ; Wed, 10 May 2023 01:53:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235211AbjEJBxV convert rfc822-to-8bit (ORCPT ); Tue, 9 May 2023 21:53:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59708 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229549AbjEJBxT (ORCPT ); Tue, 9 May 2023 21:53:19 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2FFC91721; Tue, 9 May 2023 18:53:18 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 5D5AF24E1BD; Wed, 10 May 2023 09:53:15 +0800 (CST) Received: from EXMBX062.cuchost.com (172.16.6.62) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 10 May 2023 09:53:15 +0800 Received: from ubuntu.localdomain (183.27.98.219) by EXMBX062.cuchost.com (172.16.6.62) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 10 May 2023 09:53:14 +0800 From: Changhuang Liang To: Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou CC: Walker Chen , Changhuang Liang , Hal Feng , , , Subject: [PATCH v3 2/5] soc: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE Date: Tue, 9 May 2023 18:53:08 -0700 Message-ID: <20230510015311.27505-3-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230510015311.27505-1-changhuang.liang@starfivetech.com> References: <20230510015311.27505-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.98.219] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX062.cuchost.com (172.16.6.62) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Using ARCH_FOO symbol is preferred than SOC_FOO. Reviewed-by: Conor Dooley Reviewed-by: Walker Chen Signed-off-by: Changhuang Liang --- drivers/soc/starfive/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/starfive/Kconfig b/drivers/soc/starfive/Kconfig index bdb96dc4c989..1e9b0c414fec 100644 --- a/drivers/soc/starfive/Kconfig +++ b/drivers/soc/starfive/Kconfig @@ -3,8 +3,8 @@ config JH71XX_PMU bool "Support PMU for StarFive JH71XX Soc" depends on PM - depends on SOC_STARFIVE || COMPILE_TEST - default SOC_STARFIVE + depends on ARCH_STARFIVE || COMPILE_TEST + default ARCH_STARFIVE select PM_GENERIC_DOMAINS help Say 'y' here to enable support power domain support. --=20 2.25.1 From nobody Wed Feb 11 12:14:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BE87C7EE23 for ; Wed, 10 May 2023 01:53:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235471AbjEJBxY convert rfc822-to-8bit (ORCPT ); Tue, 9 May 2023 21:53:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229561AbjEJBxU (ORCPT ); Tue, 9 May 2023 21:53:20 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3085735B3; Tue, 9 May 2023 18:53:18 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 2108624E240; Wed, 10 May 2023 09:53:16 +0800 (CST) Received: from EXMBX062.cuchost.com (172.16.6.62) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 10 May 2023 09:53:16 +0800 Received: from ubuntu.localdomain (183.27.98.219) by EXMBX062.cuchost.com (172.16.6.62) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 10 May 2023 09:53:15 +0800 From: Changhuang Liang To: Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou CC: Walker Chen , Changhuang Liang , Hal Feng , , , Subject: [PATCH v3 3/5] soc: starfive: Extract JH7110 pmu private operations Date: Tue, 9 May 2023 18:53:09 -0700 Message-ID: <20230510015311.27505-4-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230510015311.27505-1-changhuang.liang@starfivetech.com> References: <20230510015311.27505-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.98.219] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX062.cuchost.com (172.16.6.62) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Move JH7110 private operation into private data of compatible. Convenient to add AON PMU which would not have interrupts property. Signed-off-by: Changhuang Liang Reviewed-by: Walker Chen --- drivers/soc/starfive/jh71xx_pmu.c | 89 +++++++++++++++++++++---------- 1 file changed, 62 insertions(+), 27 deletions(-) diff --git a/drivers/soc/starfive/jh71xx_pmu.c b/drivers/soc/starfive/jh71x= x_pmu.c index 7d5f50d71c0d..0dbdcc0d2c91 100644 --- a/drivers/soc/starfive/jh71xx_pmu.c +++ b/drivers/soc/starfive/jh71xx_pmu.c @@ -51,9 +51,17 @@ struct jh71xx_domain_info { u8 bit; }; =20 +struct jh71xx_pmu; +struct jh71xx_pmu_dev; + struct jh71xx_pmu_match_data { const struct jh71xx_domain_info *domain_info; int num_domains; + unsigned int pmu_status; + int (*pmu_parse_irq)(struct platform_device *pdev, + struct jh71xx_pmu *pmu); + int (*pmu_set_state)(struct jh71xx_pmu_dev *pmd, + u32 mask, bool on); }; =20 struct jh71xx_pmu { @@ -79,12 +87,12 @@ static int jh71xx_pmu_get_state(struct jh71xx_pmu_dev *= pmd, u32 mask, bool *is_o if (!mask) return -EINVAL; =20 - *is_on =3D readl(pmu->base + JH71XX_PMU_CURR_POWER_MODE) & mask; + *is_on =3D readl(pmu->base + pmu->match_data->pmu_status) & mask; =20 return 0; } =20 -static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool= on) +static int jh7110_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool= on) { struct jh71xx_pmu *pmu =3D pmd->pmu; unsigned long flags; @@ -92,22 +100,8 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *= pmd, u32 mask, bool on) u32 mode; u32 encourage_lo; u32 encourage_hi; - bool is_on; int ret; =20 - ret =3D jh71xx_pmu_get_state(pmd, mask, &is_on); - if (ret) { - dev_dbg(pmu->dev, "unable to get current state for %s\n", - pmd->genpd.name); - return ret; - } - - if (is_on =3D=3D on) { - dev_dbg(pmu->dev, "pm domain [%s] is already %sable status.\n", - pmd->genpd.name, on ? "en" : "dis"); - return 0; - } - spin_lock_irqsave(&pmu->lock, flags); =20 /* @@ -166,6 +160,29 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev = *pmd, u32 mask, bool on) return 0; } =20 +static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool= on) +{ + struct jh71xx_pmu *pmu =3D pmd->pmu; + const struct jh71xx_pmu_match_data *match_data =3D pmu->match_data; + bool is_on; + int ret; + + ret =3D jh71xx_pmu_get_state(pmd, mask, &is_on); + if (ret) { + dev_dbg(pmu->dev, "unable to get current state for %s\n", + pmd->genpd.name); + return ret; + } + + if (is_on =3D=3D on) { + dev_dbg(pmu->dev, "pm domain [%s] is already %sable status.\n", + pmd->genpd.name, on ? "en" : "dis"); + return 0; + } + + return match_data->pmu_set_state(pmd, mask, on); +} + static int jh71xx_pmu_on(struct generic_pm_domain *genpd) { struct jh71xx_pmu_dev *pmd =3D container_of(genpd, @@ -226,6 +243,25 @@ static irqreturn_t jh71xx_pmu_interrupt(int irq, void = *data) return IRQ_HANDLED; } =20 +static int jh7110_pmu_parse_irq(struct platform_device *pdev, struct jh71x= x_pmu *pmu) +{ + struct device *dev =3D &pdev->dev; + int ret; + + pmu->irq =3D platform_get_irq(pdev, 0); + if (pmu->irq < 0) + return pmu->irq; + + ret =3D devm_request_irq(dev, pmu->irq, jh71xx_pmu_interrupt, + 0, pdev->name, pmu); + if (ret) + dev_err(dev, "failed to request irq\n"); + + jh71xx_pmu_int_enable(pmu, JH71XX_PMU_INT_ALL_MASK & ~JH71XX_PMU_INT_PCH_= FAIL, true); + + return 0; +} + static int jh71xx_pmu_init_domain(struct jh71xx_pmu *pmu, int index) { struct jh71xx_pmu_dev *pmd; @@ -275,19 +311,18 @@ static int jh71xx_pmu_probe(struct platform_device *p= dev) if (IS_ERR(pmu->base)) return PTR_ERR(pmu->base); =20 - pmu->irq =3D platform_get_irq(pdev, 0); - if (pmu->irq < 0) - return pmu->irq; - - ret =3D devm_request_irq(dev, pmu->irq, jh71xx_pmu_interrupt, - 0, pdev->name, pmu); - if (ret) - dev_err(dev, "failed to request irq\n"); + spin_lock_init(&pmu->lock); =20 match_data =3D of_device_get_match_data(dev); if (!match_data) return -EINVAL; =20 + ret =3D match_data->pmu_parse_irq(pdev, pmu); + if (ret) { + dev_err(dev, "failed to parse irq\n"); + return ret; + } + pmu->genpd =3D devm_kcalloc(dev, match_data->num_domains, sizeof(struct generic_pm_domain *), GFP_KERNEL); @@ -307,9 +342,6 @@ static int jh71xx_pmu_probe(struct platform_device *pde= v) } } =20 - spin_lock_init(&pmu->lock); - jh71xx_pmu_int_enable(pmu, JH71XX_PMU_INT_ALL_MASK & ~JH71XX_PMU_INT_PCH_= FAIL, true); - ret =3D of_genpd_add_provider_onecell(np, &pmu->genpd_data); if (ret) { dev_err(dev, "failed to register genpd driver: %d\n", ret); @@ -357,6 +389,9 @@ static const struct jh71xx_domain_info jh7110_power_dom= ains[] =3D { static const struct jh71xx_pmu_match_data jh7110_pmu =3D { .num_domains =3D ARRAY_SIZE(jh7110_power_domains), .domain_info =3D jh7110_power_domains, + .pmu_status =3D JH71XX_PMU_CURR_POWER_MODE, + .pmu_parse_irq =3D jh7110_pmu_parse_irq, + .pmu_set_state =3D jh7110_pmu_set_state, }; =20 static const struct of_device_id jh71xx_pmu_of_match[] =3D { --=20 2.25.1 From nobody Wed Feb 11 12:14:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93751C7EE22 for ; Wed, 10 May 2023 01:53:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235487AbjEJBx0 convert rfc822-to-8bit (ORCPT ); Tue, 9 May 2023 21:53:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59718 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234570AbjEJBxU (ORCPT ); Tue, 9 May 2023 21:53:20 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E08CD3A85; Tue, 9 May 2023 18:53:18 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 665C224E1D4; Wed, 10 May 2023 09:53:17 +0800 (CST) Received: from EXMBX062.cuchost.com (172.16.6.62) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 10 May 2023 09:53:17 +0800 Received: from ubuntu.localdomain (183.27.98.219) by EXMBX062.cuchost.com (172.16.6.62) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 10 May 2023 09:53:16 +0800 From: Changhuang Liang To: Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou CC: Walker Chen , Changhuang Liang , Hal Feng , , , Subject: [PATCH v3 4/5] soc: starfive: Add JH7110 AON PMU support Date: Tue, 9 May 2023 18:53:10 -0700 Message-ID: <20230510015311.27505-5-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230510015311.27505-1-changhuang.liang@starfivetech.com> References: <20230510015311.27505-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.98.219] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX062.cuchost.com (172.16.6.62) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add AON PMU for StarFive JH7110 SoC. It can be used to turn on/off the dphy rx/tx power switch. Reviewed-by: Walker Chen Signed-off-by: Changhuang Liang --- MAINTAINERS | 1 + drivers/soc/starfive/jh71xx_pmu.c | 57 ++++++++++++++++++++++++++++--- 2 files changed, 53 insertions(+), 5 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 4c0b39c44957..ce0befe39394 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19939,6 +19939,7 @@ F: include/dt-bindings/reset/starfive?jh71*.h =20 STARFIVE JH71XX PMU CONTROLLER DRIVER M: Walker Chen +M: Changhuang Liang S: Supported F: Documentation/devicetree/bindings/power/starfive* F: drivers/soc/starfive/jh71xx_pmu.c diff --git a/drivers/soc/starfive/jh71xx_pmu.c b/drivers/soc/starfive/jh71x= x_pmu.c index 0dbdcc0d2c91..c7b474409cf7 100644 --- a/drivers/soc/starfive/jh71xx_pmu.c +++ b/drivers/soc/starfive/jh71xx_pmu.c @@ -2,7 +2,7 @@ /* * StarFive JH71XX PMU (Power Management Unit) Controller Driver * - * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. */ =20 #include @@ -24,6 +24,9 @@ #define JH71XX_PMU_EVENT_STATUS 0x88 #define JH71XX_PMU_INT_STATUS 0x8C =20 +/* aon pmu register offset */ +#define JH71XX_AON_PMU_SWITCH 0x00 + /* sw encourage cfg */ #define JH71XX_PMU_SW_ENCOURAGE_EN_LO 0x05 #define JH71XX_PMU_SW_ENCOURAGE_EN_HI 0x50 @@ -160,6 +163,26 @@ static int jh7110_pmu_set_state(struct jh71xx_pmu_dev = *pmd, u32 mask, bool on) return 0; } =20 +static int jh7110_aon_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, = bool on) +{ + struct jh71xx_pmu *pmu =3D pmd->pmu; + unsigned long flags; + u32 val; + + spin_lock_irqsave(&pmu->lock, flags); + val =3D readl(pmu->base + JH71XX_AON_PMU_SWITCH); + + if (on) + val |=3D mask; + else + val &=3D ~mask; + + writel(val, pmu->base + JH71XX_AON_PMU_SWITCH); + spin_unlock_irqrestore(&pmu->lock, flags); + + return 0; +} + static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool= on) { struct jh71xx_pmu *pmu =3D pmd->pmu; @@ -317,10 +340,12 @@ static int jh71xx_pmu_probe(struct platform_device *p= dev) if (!match_data) return -EINVAL; =20 - ret =3D match_data->pmu_parse_irq(pdev, pmu); - if (ret) { - dev_err(dev, "failed to parse irq\n"); - return ret; + if (match_data->pmu_parse_irq) { + ret =3D match_data->pmu_parse_irq(pdev, pmu); + if (ret) { + dev_err(dev, "failed to parse irq\n"); + return ret; + } } =20 pmu->genpd =3D devm_kcalloc(dev, match_data->num_domains, @@ -394,10 +419,31 @@ static const struct jh71xx_pmu_match_data jh7110_pmu = =3D { .pmu_set_state =3D jh7110_pmu_set_state, }; =20 +static const struct jh71xx_domain_info jh7110_aon_power_domains[] =3D { + [JH7110_PD_DPHY_TX] =3D { + .name =3D "DPHY-TX", + .bit =3D 30, + }, + [JH7110_PD_DPHY_RX] =3D { + .name =3D "DPHY-RX", + .bit =3D 31, + }, +}; + +static const struct jh71xx_pmu_match_data jh7110_aon_pmu =3D { + .num_domains =3D ARRAY_SIZE(jh7110_aon_power_domains), + .domain_info =3D jh7110_aon_power_domains, + .pmu_status =3D JH71XX_AON_PMU_SWITCH, + .pmu_set_state =3D jh7110_aon_pmu_set_state, +}; + static const struct of_device_id jh71xx_pmu_of_match[] =3D { { .compatible =3D "starfive,jh7110-pmu", .data =3D (void *)&jh7110_pmu, + }, { + .compatible =3D "starfive,jh7110-aon-syscon", + .data =3D (void *)&jh7110_aon_pmu, }, { /* sentinel */ } @@ -414,5 +460,6 @@ static struct platform_driver jh71xx_pmu_driver =3D { builtin_platform_driver(jh71xx_pmu_driver); =20 MODULE_AUTHOR("Walker Chen "); +MODULE_AUTHOR("Changhuang Liang "); MODULE_DESCRIPTION("StarFive JH71XX PMU Driver"); MODULE_LICENSE("GPL"); --=20 2.25.1 From nobody Wed Feb 11 12:14:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C606C77B75 for ; Wed, 10 May 2023 01:53:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235514AbjEJBx3 convert rfc822-to-8bit (ORCPT ); Tue, 9 May 2023 21:53:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59720 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233875AbjEJBxU (ORCPT ); Tue, 9 May 2023 21:53:20 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C44E3A8B; Tue, 9 May 2023 18:53:19 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 33ECF7FFD; Wed, 10 May 2023 09:53:18 +0800 (CST) Received: from EXMBX062.cuchost.com (172.16.6.62) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 10 May 2023 09:53:18 +0800 Received: from ubuntu.localdomain (183.27.98.219) by EXMBX062.cuchost.com (172.16.6.62) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Wed, 10 May 2023 09:53:17 +0800 From: Changhuang Liang To: Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou CC: Walker Chen , Changhuang Liang , Hal Feng , , , Subject: [PATCH v3 5/5] riscv: dts: starfive: jh7110: Add AON PMU node Date: Tue, 9 May 2023 18:53:11 -0700 Message-ID: <20230510015311.27505-6-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230510015311.27505-1-changhuang.liang@starfivetech.com> References: <20230510015311.27505-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.98.219] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX062.cuchost.com (172.16.6.62) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add AON PMU node to configure power. It can be used to turn on/off dphy rx/tx power switch. It also can use syscon operation. Reviewed-by: Walker Chen Signed-off-by: Changhuang Liang --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts= /starfive/jh7110.dtsi index 4c5fdb905da8..d31257d4dcfc 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -486,6 +486,12 @@ aoncrg: clock-controller@17000000 { #reset-cells =3D <1>; }; =20 + aon_syscon: syscon@17010000 { + compatible =3D "starfive,jh7110-aon-syscon", "syscon"; + reg =3D <0x0 0x17010000 0x0 0x1000>; + #power-domain-cells =3D <1>; + }; + aongpio: pinctrl@17020000 { compatible =3D "starfive,jh7110-aon-pinctrl"; reg =3D <0x0 0x17020000 0x0 0x10000>; --=20 2.25.1