From nobody Wed Feb 11 14:55:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52497C7EE24 for ; Tue, 9 May 2023 18:25:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234984AbjEISZe (ORCPT ); Tue, 9 May 2023 14:25:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234911AbjEISZY (ORCPT ); Tue, 9 May 2023 14:25:24 -0400 Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 99320E4E for ; Tue, 9 May 2023 11:25:22 -0700 (PDT) Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-643a1fed360so3361916b3a.3 for ; Tue, 09 May 2023 11:25:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1683656722; x=1686248722; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=26y59v9qUKc2CpO6S7UVQsEMURpLsKbwKkIt33el4rQ=; b=DLepPrV+ewXWR/9YrNdLZsky9GdViwY78UMcLP8j0su7F5/fgByJg64fORBjd2IOJn baXSJfWCoS84zI5g4AKPEviwFoxWDo28hKgTsxXDlKqNt2cvtpiDtxqGDT24IyaWTlzD FnfD51zlWKvj5VLu8Rc/FFtHOH3uNeC62mi/YWw3Rjn9Oot+ZYAqX88ZxMsWK8z8yyiR LibeL7cF4bShgGhQs7y6ZW2yiO46kN7/2rQEUNM77IdNMWcUshAIbv93HuNR+cQr6YxQ 1za0EaBwOeLdGnDvu/tvHk5EDsUQ2yXfuUPderpKOYp9leoKqfAN+i/sDjr5C8H7Upon EuOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683656722; x=1686248722; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=26y59v9qUKc2CpO6S7UVQsEMURpLsKbwKkIt33el4rQ=; b=CSmPFmg8Po3Pkjjy2oOP8gm//cuphq7HPpxouVxIDB/uOdB9AtXHAXwTY+ltbl5J/r 0lUWRKZTVaJIDjZ4Q5tZCeJTLrrpssae5aVzRQVGRZrJaRyP8zPcEraQ4N2l5EgofuIw 1Mtdioy+jT0vCnlCTmdkCFPUvZTJxRhieMWitpn1wlf3f6p0pQ9YnIY0nzY4NGBwrqFD eQZ+bSeQaidrasELsEsD3FcFx5RMmRDByX7rCzZob8w77MfYqMtmx5JyZDTjgW+sQiUH jyqPylfApI3qtSezL69MvTwouHyr64INCdE4mnuBPzF9wA4vyp4Mz1LwRpvL9ZFl3Bf5 VhwQ== X-Gm-Message-State: AC+VfDyX3J24HpybUiDCqRycEjY2/qJEHrZU59GQ5PpvWJYhvKGnCRlt k3SHsiuFmeVo7LP+OL4lzcBTkQ== X-Google-Smtp-Source: ACHHUZ4Rc0x+ekHb+pf/Jq9jIVtRwLVZ76o+axXE34SjBCZ7M6BlLSO316QuMtQlI9a78xap+duh0w== X-Received: by 2002:a05:6a00:2401:b0:63d:3339:e967 with SMTP id z1-20020a056a00240100b0063d3339e967mr18559445pfh.19.1683656722049; Tue, 09 May 2023 11:25:22 -0700 (PDT) Received: from evan.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id q12-20020a63cc4c000000b0051eff0a70d7sm1633559pgi.94.2023.05.09.11.25.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 May 2023 11:25:21 -0700 (PDT) From: Evan Green To: Palmer Dabbelt Cc: Evan Green , Andrew Jones , Albert Ou , Andrew Bresticker , Celeste Liu , Conor Dooley , Heiko Stuebner , Jonathan Corbet , Palmer Dabbelt , Paul Walmsley , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v2 3/3] RISC-V: hwprobe: Expose Zba, Zbb, and Zbs Date: Tue, 9 May 2023 11:25:03 -0700 Message-Id: <20230509182504.2997252-4-evan@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230509182504.2997252-1-evan@rivosinc.com> References: <20230509182504.2997252-1-evan@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add two new bits to the IMA_EXT_0 key for ZBA, ZBB, and ZBS extensions. These are accurately reported per CPU. Signed-off-by: Evan Green Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley Reviewed-by: Heiko Stuebner --- Changes in v2: - Fixed typo s/supporte/supported/ (Conor) - Fixed copypasta s/IMA_ZBB/EXT_ZBB/ (Conor) - Added Zbs Documentation/riscv/hwprobe.rst | 10 ++++++ arch/riscv/include/uapi/asm/hwprobe.h | 3 ++ arch/riscv/kernel/sys_riscv.c | 48 +++++++++++++++++++++++---- 3 files changed, 54 insertions(+), 7 deletions(-) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.= rst index 9f0dd62dcb5d..fb25670ef0e5 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -64,6 +64,16 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defin= ed by version 2.2 of the RISC-V ISA manual. =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension= is + supported, as defined in version 1.0 of the Bit-Manipulation ISA + extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZBB`: The Zbb extension is supported, as d= efined + in version 1.0 of the Bit-Manipulation ISA extensions. + + * :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as d= efined + in version 1.0 of the Bit-Manipulation ISA extensions. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 8d745a4ad8a2..853f8f6d9a42 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -25,6 +25,9 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_KEY_IMA_EXT_0 4 #define RISCV_HWPROBE_IMA_FD (1 << 0) #define RISCV_HWPROBE_IMA_C (1 << 1) +#define RISCV_HWPROBE_EXT_ZBA (1 << 2) +#define RISCV_HWPROBE_EXT_ZBB (1 << 3) +#define RISCV_HWPROBE_EXT_ZBS (1 << 4) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 5db29683ebee..fe655db19ab4 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -121,6 +121,46 @@ static void hwprobe_arch_id(struct riscv_hwprobe *pair, pair->value =3D id; } =20 +static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, + const struct cpumask *cpus) +{ + int cpu; + u64 missing =3D 0; + + pair->value =3D 0; + if (has_fpu()) + pair->value |=3D RISCV_HWPROBE_IMA_FD; + + if (riscv_isa_extension_available(NULL, c)) + pair->value |=3D RISCV_HWPROBE_IMA_C; + + /* + * Loop through and record extensions that 1) anyone has, and 2) anyone + * doesn't have. + */ + for_each_cpu(cpu, cpus) { + struct riscv_isainfo *isainfo =3D &hart_isa[cpu]; + + if (riscv_isa_extension_available(isainfo->isa, ZBA)) + pair->value |=3D RISCV_HWPROBE_EXT_ZBA; + else + missing |=3D RISCV_HWPROBE_EXT_ZBA; + + if (riscv_isa_extension_available(isainfo->isa, ZBB)) + pair->value |=3D RISCV_HWPROBE_EXT_ZBB; + else + missing |=3D RISCV_HWPROBE_EXT_ZBB; + + if (riscv_isa_extension_available(isainfo->isa, ZBS)) + pair->value |=3D RISCV_HWPROBE_EXT_ZBS; + else + missing |=3D RISCV_HWPROBE_EXT_ZBS; + } + + /* Now turn off reporting features if any CPU is missing it. */ + pair->value &=3D ~missing; +} + static u64 hwprobe_misaligned(const struct cpumask *cpus) { int cpu; @@ -164,13 +204,7 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pai= r, break; =20 case RISCV_HWPROBE_KEY_IMA_EXT_0: - pair->value =3D 0; - if (has_fpu()) - pair->value |=3D RISCV_HWPROBE_IMA_FD; - - if (riscv_isa_extension_available(NULL, c)) - pair->value |=3D RISCV_HWPROBE_IMA_C; - + hwprobe_isa_ext0(pair, cpus); break; =20 case RISCV_HWPROBE_KEY_CPUPERF_0: --=20 2.25.1