From nobody Wed Feb 11 12:08:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF057C7EE22 for ; Tue, 9 May 2023 07:27:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232888AbjEIH1M (ORCPT ); Tue, 9 May 2023 03:27:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48678 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230258AbjEIH1B (ORCPT ); Tue, 9 May 2023 03:27:01 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D4CAA49E6; Tue, 9 May 2023 00:26:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1683617218; x=1715153218; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xRUkUYnc+8xTekZnYPspesKZs9NIUTdTYiUhc1lgC3g=; b=UCYpUfyB+r6wI1bZtAt19OJkEHwcMIJikGj9ErLaNj6gJBef/WdlqZN3 vPvvlsVD1Y6v6CBHrXEPjikTttgbHEMwGmkRA7Vg9lyUAPxKo9XnFqgdi YWl94/NKMyjeEEsLiivlUPYlnTAKtuNZNP73oO5cwPbEJu4PMb1eGsqj+ 5sTGwC/mb8dRaYgSAdEhwUrTNAItQtLcDrtkcCD1o2bnhDGlSpRYnnQoz eVQy9O+je5YOKSCwacMm8bDebqt7E4MINp6GAlEJ0ZGtynilIXs9V7C3x R6BNl0D+w1bU0NhDEVr7ITguf9xaxAzCGkzp1zsPVb2F8PRM2gRlK75of Q==; X-IronPort-AV: E=Sophos;i="5.99,261,1677567600"; d="scan'208";a="212523839" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 May 2023 00:26:57 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Tue, 9 May 2023 00:26:56 -0700 Received: from soft-dev3-1.microsemi.net (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Tue, 9 May 2023 00:26:54 -0700 From: Horatiu Vultur To: , , CC: , , , , , , , , Horatiu Vultur Subject: [PATCH net-next 1/3] net: lan966x: Add ES0 VCAP model Date: Tue, 9 May 2023 09:26:43 +0200 Message-ID: <20230509072645.3245949-2-horatiu.vultur@microchip.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20230509072645.3245949-1-horatiu.vultur@microchip.com> References: <20230509072645.3245949-1-horatiu.vultur@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Provide ES0 (egress stage 0) VCAP model for lan966x. This provides rewriting functionality in the gress path. Signed-off-by: Horatiu Vultur --- .../microchip/lan966x/lan966x_vcap_ag_api.c | 264 +++++++++++++++++- .../net/ethernet/microchip/vcap/vcap_ag_api.h | 67 +++-- 2 files changed, 301 insertions(+), 30 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_vcap_ag_api.c b= /drivers/net/ethernet/microchip/lan966x/lan966x_vcap_ag_api.c index 66400a082d029..fb6851b94528c 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_vcap_ag_api.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_vcap_ag_api.c @@ -2121,6 +2121,69 @@ static const struct vcap_field is2_smac_sip6_keyfiel= d[] =3D { }, }; =20 +static const struct vcap_field es0_vid_keyfield[] =3D { + [VCAP_KF_IF_EGR_PORT_NO] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 4, + }, + [VCAP_KF_IF_IGR_PORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 4, + .width =3D 4, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 8, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 9, + .width =3D 8, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 17, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 18, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 19, + .width =3D 12, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 31, + .width =3D 1, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 32, + .width =3D 3, + }, + [VCAP_KF_L3_DPL_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 35, + .width =3D 1, + }, + [VCAP_KF_RTP_ID] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 36, + .width =3D 10, + }, + [VCAP_KF_PDU_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 46, + .width =3D 4, + }, +}; + /* keyfield_set */ static const struct vcap_set is1_keyfield_set[] =3D { [VCAP_KFS_NORMAL] =3D { @@ -2228,6 +2291,14 @@ static const struct vcap_set is2_keyfield_set[] =3D { }, }; =20 +static const struct vcap_set es0_keyfield_set[] =3D { + [VCAP_KFS_VID] =3D { + .type_id =3D -1, + .sw_per_item =3D 1, + .sw_cnt =3D 1, + }, +}; + /* keyfield_set map */ static const struct vcap_field *is1_keyfield_set_map[] =3D { [VCAP_KFS_NORMAL] =3D is1_normal_keyfield, @@ -2255,6 +2326,10 @@ static const struct vcap_field *is2_keyfield_set_map= [] =3D { [VCAP_KFS_SMAC_SIP6] =3D is2_smac_sip6_keyfield, }; =20 +static const struct vcap_field *es0_keyfield_set_map[] =3D { + [VCAP_KFS_VID] =3D es0_vid_keyfield, +}; + /* keyfield_set map sizes */ static int is1_keyfield_set_map_size[] =3D { [VCAP_KFS_NORMAL] =3D ARRAY_SIZE(is1_normal_keyfield), @@ -2282,6 +2357,10 @@ static int is2_keyfield_set_map_size[] =3D { [VCAP_KFS_SMAC_SIP6] =3D ARRAY_SIZE(is2_smac_sip6_keyfield), }; =20 +static int es0_keyfield_set_map_size[] =3D { + [VCAP_KFS_VID] =3D ARRAY_SIZE(es0_vid_keyfield), +}; + /* actionfields */ static const struct vcap_field is1_s1_actionfield[] =3D { [VCAP_AF_TYPE] =3D { @@ -2522,6 +2601,94 @@ static const struct vcap_field is2_smac_sip_actionfi= eld[] =3D { }, }; =20 +static const struct vcap_field es0_vid_actionfield[] =3D { + [VCAP_AF_PUSH_OUTER_TAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 2, + }, + [VCAP_AF_PUSH_INNER_TAG] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 2, + .width =3D 1, + }, + [VCAP_AF_TAG_A_TPID_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 3, + .width =3D 2, + }, + [VCAP_AF_TAG_A_VID_SEL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 5, + .width =3D 1, + }, + [VCAP_AF_TAG_A_PCP_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 6, + .width =3D 2, + }, + [VCAP_AF_TAG_A_DEI_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 8, + .width =3D 2, + }, + [VCAP_AF_TAG_B_TPID_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 10, + .width =3D 2, + }, + [VCAP_AF_TAG_B_VID_SEL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 12, + .width =3D 1, + }, + [VCAP_AF_TAG_B_PCP_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 13, + .width =3D 2, + }, + [VCAP_AF_TAG_B_DEI_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 15, + .width =3D 2, + }, + [VCAP_AF_VID_A_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 17, + .width =3D 12, + }, + [VCAP_AF_PCP_A_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 29, + .width =3D 3, + }, + [VCAP_AF_DEI_A_VAL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 32, + .width =3D 1, + }, + [VCAP_AF_VID_B_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 33, + .width =3D 12, + }, + [VCAP_AF_PCP_B_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 45, + .width =3D 3, + }, + [VCAP_AF_DEI_B_VAL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 48, + .width =3D 1, + }, + [VCAP_AF_ESDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 49, + .width =3D 8, + }, +}; + /* actionfield_set */ static const struct vcap_set is1_actionfield_set[] =3D { [VCAP_AFS_S1] =3D { @@ -2544,6 +2711,14 @@ static const struct vcap_set is2_actionfield_set[] = =3D { }, }; =20 +static const struct vcap_set es0_actionfield_set[] =3D { + [VCAP_AFS_VID] =3D { + .type_id =3D -1, + .sw_per_item =3D 1, + .sw_cnt =3D 1, + }, +}; + /* actionfield_set map */ static const struct vcap_field *is1_actionfield_set_map[] =3D { [VCAP_AFS_S1] =3D is1_s1_actionfield, @@ -2554,6 +2729,10 @@ static const struct vcap_field *is2_actionfield_set_= map[] =3D { [VCAP_AFS_SMAC_SIP] =3D is2_smac_sip_actionfield, }; =20 +static const struct vcap_field *es0_actionfield_set_map[] =3D { + [VCAP_AFS_VID] =3D es0_vid_actionfield, +}; + /* actionfield_set map size */ static int is1_actionfield_set_map_size[] =3D { [VCAP_AFS_S1] =3D ARRAY_SIZE(is1_s1_actionfield), @@ -2564,6 +2743,10 @@ static int is2_actionfield_set_map_size[] =3D { [VCAP_AFS_SMAC_SIP] =3D ARRAY_SIZE(is2_smac_sip_actionfield), }; =20 +static int es0_actionfield_set_map_size[] =3D { + [VCAP_AFS_VID] =3D ARRAY_SIZE(es0_vid_actionfield), +}; + /* Type Groups */ static const struct vcap_typegroup is1_x4_keyfield_set_typegroups[] =3D { { @@ -2659,6 +2842,10 @@ static const struct vcap_typegroup is2_x1_keyfield_s= et_typegroups[] =3D { {} }; =20 +static const struct vcap_typegroup es0_x1_keyfield_set_typegroups[] =3D { + {} +}; + static const struct vcap_typegroup *is1_keyfield_set_typegroups[] =3D { [4] =3D is1_x4_keyfield_set_typegroups, [2] =3D is1_x2_keyfield_set_typegroups, @@ -2673,6 +2860,11 @@ static const struct vcap_typegroup *is2_keyfield_set= _typegroups[] =3D { [5] =3D NULL, }; =20 +static const struct vcap_typegroup *es0_keyfield_set_typegroups[] =3D { + [1] =3D es0_x1_keyfield_set_typegroups, + [2] =3D NULL, +}; + static const struct vcap_typegroup is1_x1_actionfield_set_typegroups[] =3D= { {} }; @@ -2700,6 +2892,10 @@ static const struct vcap_typegroup is2_x1_actionfiel= d_set_typegroups[] =3D { {} }; =20 +static const struct vcap_typegroup es0_x1_actionfield_set_typegroups[] =3D= { + {} +}; + static const struct vcap_typegroup *is1_actionfield_set_typegroups[] =3D { [1] =3D is1_x1_actionfield_set_typegroups, [5] =3D NULL, @@ -2711,6 +2907,11 @@ static const struct vcap_typegroup *is2_actionfield_= set_typegroups[] =3D { [5] =3D NULL, }; =20 +static const struct vcap_typegroup *es0_actionfield_set_typegroups[] =3D { + [1] =3D es0_x1_actionfield_set_typegroups, + [2] =3D NULL, +}; + /* Keyfieldset names */ static const char * const vcap_keyfield_set_names[] =3D { [VCAP_KFS_NO_VALUE] =3D "(None)", @@ -2743,6 +2944,7 @@ static const char * const vcap_keyfield_set_names[] = =3D { [VCAP_KFS_RT] =3D "VCAP_KFS_RT", [VCAP_KFS_SMAC_SIP4] =3D "VCAP_KFS_SMAC_SIP4", [VCAP_KFS_SMAC_SIP6] =3D "VCAP_KFS_SMAC_SIP6", + [VCAP_KFS_VID] =3D "VCAP_KFS_VID", }; =20 /* Actionfieldset names */ @@ -2751,9 +2953,11 @@ static const char * const vcap_actionfield_set_names= [] =3D { [VCAP_AFS_BASE_TYPE] =3D "VCAP_AFS_BASE_TYPE", [VCAP_AFS_CLASSIFICATION] =3D "VCAP_AFS_CLASSIFICATION", [VCAP_AFS_CLASS_REDUCED] =3D "VCAP_AFS_CLASS_REDUCED", + [VCAP_AFS_ES0] =3D "VCAP_AFS_ES0", [VCAP_AFS_FULL] =3D "VCAP_AFS_FULL", [VCAP_AFS_S1] =3D "VCAP_AFS_S1", [VCAP_AFS_SMAC_SIP] =3D "VCAP_AFS_SMAC_SIP", + [VCAP_AFS_VID] =3D "VCAP_AFS_VID", }; =20 /* Keyfield names */ @@ -2774,6 +2978,7 @@ static const char * const vcap_keyfield_names[] =3D { [VCAP_KF_8021Q_PCP1] =3D "8021Q_PCP1", [VCAP_KF_8021Q_PCP2] =3D "8021Q_PCP2", [VCAP_KF_8021Q_PCP_CLS] =3D "8021Q_PCP_CLS", + [VCAP_KF_8021Q_TPID] =3D "8021Q_TPID", [VCAP_KF_8021Q_TPID0] =3D "8021Q_TPID0", [VCAP_KF_8021Q_TPID1] =3D "8021Q_TPID1", [VCAP_KF_8021Q_TPID2] =3D "8021Q_TPID2", @@ -2799,6 +3004,7 @@ static const char * const vcap_keyfield_names[] =3D { [VCAP_KF_HOST_MATCH] =3D "HOST_MATCH", [VCAP_KF_IF_EGR_PORT_MASK] =3D "IF_EGR_PORT_MASK", [VCAP_KF_IF_EGR_PORT_MASK_RNG] =3D "IF_EGR_PORT_MASK_RNG", + [VCAP_KF_IF_EGR_PORT_NO] =3D "IF_EGR_PORT_NO", [VCAP_KF_IF_IGR_PORT] =3D "IF_IGR_PORT", [VCAP_KF_IF_IGR_PORT_MASK] =3D "IF_IGR_PORT_MASK", [VCAP_KF_IF_IGR_PORT_MASK_L3] =3D "IF_IGR_PORT_MASK_L3", @@ -2873,7 +3079,9 @@ static const char * const vcap_keyfield_names[] =3D { [VCAP_KF_OAM_OPCODE] =3D "OAM_OPCODE", [VCAP_KF_OAM_VER] =3D "OAM_VER", [VCAP_KF_OAM_Y1731_IS] =3D "OAM_Y1731_IS", + [VCAP_KF_PDU_TYPE] =3D "PDU_TYPE", [VCAP_KF_PROT_ACTIVE] =3D "PROT_ACTIVE", + [VCAP_KF_RTP_ID] =3D "RTP_ID", [VCAP_KF_RT_FRMID] =3D "RT_FRMID", [VCAP_KF_RT_TYPE] =3D "RT_TYPE", [VCAP_KF_RT_VLAN_IDX] =3D "RT_VLAN_IDX", @@ -2891,18 +3099,25 @@ static const char * const vcap_actionfield_names[] = =3D { [VCAP_AF_COPY_PORT_NUM] =3D "COPY_PORT_NUM", [VCAP_AF_COPY_QUEUE_NUM] =3D "COPY_QUEUE_NUM", [VCAP_AF_CPU_COPY_ENA] =3D "CPU_COPY_ENA", + [VCAP_AF_CPU_QU] =3D "CPU_QU", [VCAP_AF_CPU_QUEUE_NUM] =3D "CPU_QUEUE_NUM", [VCAP_AF_CUSTOM_ACE_TYPE_ENA] =3D "CUSTOM_ACE_TYPE_ENA", + [VCAP_AF_DEI_A_VAL] =3D "DEI_A_VAL", + [VCAP_AF_DEI_B_VAL] =3D "DEI_B_VAL", + [VCAP_AF_DEI_C_VAL] =3D "DEI_C_VAL", [VCAP_AF_DEI_ENA] =3D "DEI_ENA", [VCAP_AF_DEI_VAL] =3D "DEI_VAL", [VCAP_AF_DLR_SEL] =3D "DLR_SEL", [VCAP_AF_DP_ENA] =3D "DP_ENA", [VCAP_AF_DP_VAL] =3D "DP_VAL", [VCAP_AF_DSCP_ENA] =3D "DSCP_ENA", + [VCAP_AF_DSCP_SEL] =3D "DSCP_SEL", [VCAP_AF_DSCP_VAL] =3D "DSCP_VAL", [VCAP_AF_ES2_REW_CMD] =3D "ES2_REW_CMD", + [VCAP_AF_ESDX] =3D "ESDX", [VCAP_AF_FWD_KILL_ENA] =3D "FWD_KILL_ENA", [VCAP_AF_FWD_MODE] =3D "FWD_MODE", + [VCAP_AF_FWD_SEL] =3D "FWD_SEL", [VCAP_AF_HIT_ME_ONCE] =3D "HIT_ME_ONCE", [VCAP_AF_HOST_MATCH] =3D "HOST_MATCH", [VCAP_AF_IGNORE_PIPELINE_CTRL] =3D "IGNORE_PIPELINE_CTRL", @@ -2912,6 +3127,7 @@ static const char * const vcap_actionfield_names[] = =3D { [VCAP_AF_ISDX_ENA] =3D "ISDX_ENA", [VCAP_AF_ISDX_REPLACE_ENA] =3D "ISDX_REPLACE_ENA", [VCAP_AF_ISDX_VAL] =3D "ISDX_VAL", + [VCAP_AF_LOOP_ENA] =3D "LOOP_ENA", [VCAP_AF_LRN_DIS] =3D "LRN_DIS", [VCAP_AF_MAP_IDX] =3D "MAP_IDX", [VCAP_AF_MAP_KEY] =3D "MAP_KEY", @@ -2928,15 +3144,23 @@ static const char * const vcap_actionfield_names[] = =3D { [VCAP_AF_OAM_SEL] =3D "OAM_SEL", [VCAP_AF_PAG_OVERRIDE_MASK] =3D "PAG_OVERRIDE_MASK", [VCAP_AF_PAG_VAL] =3D "PAG_VAL", + [VCAP_AF_PCP_A_VAL] =3D "PCP_A_VAL", + [VCAP_AF_PCP_B_VAL] =3D "PCP_B_VAL", + [VCAP_AF_PCP_C_VAL] =3D "PCP_C_VAL", [VCAP_AF_PCP_ENA] =3D "PCP_ENA", [VCAP_AF_PCP_VAL] =3D "PCP_VAL", + [VCAP_AF_PIPELINE_ACT] =3D "PIPELINE_ACT", [VCAP_AF_PIPELINE_FORCE_ENA] =3D "PIPELINE_FORCE_ENA", [VCAP_AF_PIPELINE_PT] =3D "PIPELINE_PT", [VCAP_AF_POLICE_ENA] =3D "POLICE_ENA", [VCAP_AF_POLICE_IDX] =3D "POLICE_IDX", [VCAP_AF_POLICE_REMARK] =3D "POLICE_REMARK", [VCAP_AF_POLICE_VCAP_ONLY] =3D "POLICE_VCAP_ONLY", + [VCAP_AF_POP_VAL] =3D "POP_VAL", [VCAP_AF_PORT_MASK] =3D "PORT_MASK", + [VCAP_AF_PUSH_CUSTOMER_TAG] =3D "PUSH_CUSTOMER_TAG", + [VCAP_AF_PUSH_INNER_TAG] =3D "PUSH_INNER_TAG", + [VCAP_AF_PUSH_OUTER_TAG] =3D "PUSH_OUTER_TAG", [VCAP_AF_QOS_ENA] =3D "QOS_ENA", [VCAP_AF_QOS_VAL] =3D "QOS_VAL", [VCAP_AF_REW_OP] =3D "REW_OP", @@ -2945,7 +3169,24 @@ static const char * const vcap_actionfield_names[] = =3D { [VCAP_AF_SFID_VAL] =3D "SFID_VAL", [VCAP_AF_SGID_ENA] =3D "SGID_ENA", [VCAP_AF_SGID_VAL] =3D "SGID_VAL", + [VCAP_AF_SWAP_MACS_ENA] =3D "SWAP_MACS_ENA", + [VCAP_AF_TAG_A_DEI_SEL] =3D "TAG_A_DEI_SEL", + [VCAP_AF_TAG_A_PCP_SEL] =3D "TAG_A_PCP_SEL", + [VCAP_AF_TAG_A_TPID_SEL] =3D "TAG_A_TPID_SEL", + [VCAP_AF_TAG_A_VID_SEL] =3D "TAG_A_VID_SEL", + [VCAP_AF_TAG_B_DEI_SEL] =3D "TAG_B_DEI_SEL", + [VCAP_AF_TAG_B_PCP_SEL] =3D "TAG_B_PCP_SEL", + [VCAP_AF_TAG_B_TPID_SEL] =3D "TAG_B_TPID_SEL", + [VCAP_AF_TAG_B_VID_SEL] =3D "TAG_B_VID_SEL", + [VCAP_AF_TAG_C_DEI_SEL] =3D "TAG_C_DEI_SEL", + [VCAP_AF_TAG_C_PCP_SEL] =3D "TAG_C_PCP_SEL", + [VCAP_AF_TAG_C_TPID_SEL] =3D "TAG_C_TPID_SEL", + [VCAP_AF_TAG_C_VID_SEL] =3D "TAG_C_VID_SEL", [VCAP_AF_TYPE] =3D "TYPE", + [VCAP_AF_UNTAG_VID_ENA] =3D "UNTAG_VID_ENA", + [VCAP_AF_VID_A_VAL] =3D "VID_A_VAL", + [VCAP_AF_VID_B_VAL] =3D "VID_B_VAL", + [VCAP_AF_VID_C_VAL] =3D "VID_C_VAL", [VCAP_AF_VID_REPLACE_ENA] =3D "VID_REPLACE_ENA", [VCAP_AF_VID_VAL] =3D "VID_VAL", [VCAP_AF_VLAN_POP_CNT] =3D "VLAN_POP_CNT", @@ -2996,11 +3237,32 @@ const struct vcap_info lan966x_vcaps[] =3D { .keyfield_set_typegroups =3D is2_keyfield_set_typegroups, .actionfield_set_typegroups =3D is2_actionfield_set_typegroups, }, + [VCAP_TYPE_ES0] =3D { + .name =3D "es0", + .rows =3D 256, + .sw_count =3D 1, + .sw_width =3D 96, + .sticky_width =3D 1, + .act_width =3D 65, + .default_cnt =3D 8, + .require_cnt_dis =3D 0, + .version =3D 1, + .keyfield_set =3D es0_keyfield_set, + .keyfield_set_size =3D ARRAY_SIZE(es0_keyfield_set), + .actionfield_set =3D es0_actionfield_set, + .actionfield_set_size =3D ARRAY_SIZE(es0_actionfield_set), + .keyfield_set_map =3D es0_keyfield_set_map, + .keyfield_set_map_size =3D es0_keyfield_set_map_size, + .actionfield_set_map =3D es0_actionfield_set_map, + .actionfield_set_map_size =3D es0_actionfield_set_map_size, + .keyfield_set_typegroups =3D es0_keyfield_set_typegroups, + .actionfield_set_typegroups =3D es0_actionfield_set_typegroups, + }, }; =20 const struct vcap_statistics lan966x_vcap_stats =3D { .name =3D "lan966x", - .count =3D 2, + .count =3D 3, .keyfield_set_names =3D vcap_keyfield_set_names, .actionfield_set_names =3D vcap_actionfield_set_names, .keyfield_names =3D vcap_keyfield_names, diff --git a/drivers/net/ethernet/microchip/vcap/vcap_ag_api.h b/drivers/ne= t/ethernet/microchip/vcap/vcap_ag_api.h index a556c4419986e..c3569a4c7b695 100644 --- a/drivers/net/ethernet/microchip/vcap/vcap_ag_api.h +++ b/drivers/net/ethernet/microchip/vcap/vcap_ag_api.h @@ -3,8 +3,8 @@ * Microchip VCAP API */ =20 -/* This file is autogenerated by cml-utils 2023-02-16 11:41:14 +0100. - * Commit ID: be85f176b3a151fa748dcaf97c8824a5c2e065f3 +/* This file is autogenerated by cml-utils 2023-03-13 10:16:42 +0100. + * Commit ID: 259f0efd6d6d91bfbf62858de153cc757b6bffa3 (dirty) */ =20 #ifndef __VCAP_AG_API__ @@ -51,6 +51,7 @@ enum vcap_keyfield_set { VCAP_KFS_RT, /* lan966x is1 X1 */ VCAP_KFS_SMAC_SIP4, /* lan966x is2 X1 */ VCAP_KFS_SMAC_SIP6, /* lan966x is2 X2 */ + VCAP_KFS_VID, /* lan966x es0 X1 */ }; =20 /* List of keyfields with description @@ -79,7 +80,7 @@ enum vcap_keyfield_set { * Second DEI in multiple vlan tags (inner tag) * VCAP_KF_8021Q_DEI2: W1, sparx5: is0 * Third DEI in multiple vlan tags (not always available) - * VCAP_KF_8021Q_DEI_CLS: W1, sparx5: is2/es2, lan966x: is2 + * VCAP_KF_8021Q_DEI_CLS: W1, sparx5: is2/es2, lan966x: is2/es0 * Classified DEI * VCAP_KF_8021Q_PCP0: W3, sparx5: is0, lan966x: is1 * First PCP in multiple vlan tags (outer tag or default port tag) @@ -87,7 +88,7 @@ enum vcap_keyfield_set { * Second PCP in multiple vlan tags (inner tag) * VCAP_KF_8021Q_PCP2: W3, sparx5: is0 * Third PCP in multiple vlan tags (not always available) - * VCAP_KF_8021Q_PCP_CLS: W3, sparx5: is2/es2, lan966x: is2 + * VCAP_KF_8021Q_PCP_CLS: W3, sparx5: is2/es2, lan966x: is2/es0 * Classified PCP * VCAP_KF_8021Q_TPID: W3, sparx5: es0 * TPID for outer tag: 0: Customer TPID 1: Service TPID (88A8 or program= mable) @@ -104,7 +105,7 @@ enum vcap_keyfield_set { * VCAP_KF_8021Q_VID2: W12, sparx5: is0 * Third VID in multiple vlan tags (not always available) * VCAP_KF_8021Q_VID_CLS: sparx5 is2 W13, sparx5 es0 W13, sparx5 es2 W13, - * lan966x is2 W12 + * lan966x is2 W12, lan966x es0 W12 * Classified VID * VCAP_KF_8021Q_VLAN_DBL_TAGGED_IS: W1, lan966x: is1 * Set if frame has two or more Q-tags. Independent of port VLAN awarene= ss @@ -146,10 +147,10 @@ enum vcap_keyfield_set { * VCAP_KF_IF_EGR_PORT_MASK_RNG: W3, sparx5: es2 * Select which 32 port group is available in IF_EGR_PORT (or virtual po= rts or * CPU queue) - * VCAP_KF_IF_EGR_PORT_NO: W7, sparx5: es0 + * VCAP_KF_IF_EGR_PORT_NO: sparx5 es0 W7, lan966x es0 W4 * Egress port number * VCAP_KF_IF_IGR_PORT: sparx5 is0 W7, sparx5 es2 W9, lan966x is1 W3, lan9= 66x - * is2 W4 + * is2 W4, lan966x es0 W4 * Sparx5: Logical ingress port number retrieved from * ANA_CL::PORT_ID_CFG.LPORT_NUM or ERLEG, LAN966x: ingress port nunmber * VCAP_KF_IF_IGR_PORT_MASK: sparx5 is0 W65, sparx5 is2 W32, sparx5 is2 W6= 5, @@ -178,11 +179,12 @@ enum vcap_keyfield_set { * Payload after IPv6 header * VCAP_KF_IP_SNAP_IS: W1, sparx5: is0, lan966x: is1 * Set if frame is IPv4, IPv6, or SNAP frame - * VCAP_KF_ISDX_CLS: W12, sparx5: is2/es0/es2 + * VCAP_KF_ISDX_CLS: sparx5 is2 W12, sparx5 es0 W12, sparx5 es2 W12, lan96= 6x es0 + * W8 * Classified ISDX - * VCAP_KF_ISDX_GT0_IS: W1, sparx5: is2/es0/es2, lan966x: is2 + * VCAP_KF_ISDX_GT0_IS: W1, sparx5: is2/es0/es2, lan966x: is2/es0 * Set if classified ISDX > 0 - * VCAP_KF_L2_BC_IS: W1, sparx5: is0/is2/es2, lan966x: is1/is2 + * VCAP_KF_L2_BC_IS: W1, sparx5: is0/is2/es2, lan966x: is1/is2/es0 * Set if frame's destination MAC address is the broadcast address * (FF-FF-FF-FF-FF-FF). * VCAP_KF_L2_DMAC: W48, sparx5: is0/is2/es2, lan966x: is1/is2 @@ -195,7 +197,7 @@ enum vcap_keyfield_set { * LLC header and data after up to two VLAN tags and the type/length fie= ld * VCAP_KF_L2_MAC: W48, lan966x: is1 * MAC address (FIRST=3D1: SMAC, FIRST=3D0: DMAC) - * VCAP_KF_L2_MC_IS: W1, sparx5: is0/is2/es2, lan966x: is1/is2 + * VCAP_KF_L2_MC_IS: W1, sparx5: is0/is2/es2, lan966x: is1/is2/es0 * Set if frame's destination MAC address is a multicast address (bit 40= =3D 1). * VCAP_KF_L2_PAYLOAD0: W16, lan966x: is2 * Payload bytes 0-1 after the frame's EtherType @@ -213,7 +215,7 @@ enum vcap_keyfield_set { * SNAP header after LLC header (AA-AA-03) * VCAP_KF_L3_DIP_EQ_SIP_IS: W1, sparx5: is2/es2, lan966x: is2 * Set if Src IP matches Dst IP address - * VCAP_KF_L3_DPL_CLS: W1, sparx5: es0/es2 + * VCAP_KF_L3_DPL_CLS: W1, sparx5: es0/es2, lan966x: es0 * The frames drop precedence level * VCAP_KF_L3_DSCP: W6, sparx5: is0, lan966x: is1 * Frame's DSCP value @@ -330,8 +332,12 @@ enum vcap_keyfield_set { * Frame's OAM version * VCAP_KF_OAM_Y1731_IS: W1, sparx5: is2/es2, lan966x: is2 * Set if frame's EtherType =3D 0x8902 + * VCAP_KF_PDU_TYPE: W4, lan966x: es0 + * PDU type value (none, OAM CCM, MRP, DLR, RTE, IPv4, IPv6, OAM non-CCM) * VCAP_KF_PROT_ACTIVE: W1, sparx5: es0/es2 * Protection is active + * VCAP_KF_RTP_ID: W10, lan966x: es0 + * Classified RTP_ID * VCAP_KF_RT_FRMID: W32, lan966x: is1 * Profinet or OPC-UA FrameId * VCAP_KF_RT_TYPE: W2, lan966x: is1 @@ -470,7 +476,9 @@ enum vcap_key_field { VCAP_KF_OAM_OPCODE, VCAP_KF_OAM_VER, VCAP_KF_OAM_Y1731_IS, + VCAP_KF_PDU_TYPE, VCAP_KF_PROT_ACTIVE, + VCAP_KF_RTP_ID, VCAP_KF_RT_FRMID, VCAP_KF_RT_TYPE, VCAP_KF_RT_VLAN_IDX, @@ -489,6 +497,7 @@ enum vcap_actionfield_set { VCAP_AFS_FULL, /* sparx5 is0 X3 */ VCAP_AFS_S1, /* lan966x is1 X1 */ VCAP_AFS_SMAC_SIP, /* lan966x is2 X1 */ + VCAP_AFS_VID, /* lan966x es0 X1 */ }; =20 /* List of actionfields with description @@ -523,9 +532,9 @@ enum vcap_actionfield_set { * while bits 1:0 control first lookup. Encoding per lookup: 0: Disabled= . 1: * Extract 40 bytes after position corresponding to the location of the = IPv4 * header and use as key. 2: Extract 40 bytes after SMAC and use as key - * VCAP_AF_DEI_A_VAL: W1, sparx5: es0 + * VCAP_AF_DEI_A_VAL: W1, sparx5: es0, lan966x: es0 * DEI used in ES0 tag A. See TAG_A_DEI_SEL. - * VCAP_AF_DEI_B_VAL: W1, sparx5: es0 + * VCAP_AF_DEI_B_VAL: W1, sparx5: es0, lan966x: es0 * DEI used in ES0 tag B. See TAG_B_DEI_SEL. * VCAP_AF_DEI_C_VAL: W1, sparx5: es0 * DEI used in ES0 tag C. See TAG_C_DEI_SEL. @@ -556,7 +565,7 @@ enum vcap_actionfield_set { * VCAP_AF_ES2_REW_CMD: W3, sparx5: es2 * Command forwarded to REW: 0: No action. 1: SWAP MAC addresses. 2: Do = L2CP * DMAC translation when entering or leaving a tunnel. - * VCAP_AF_ESDX: W13, sparx5: es0 + * VCAP_AF_ESDX: sparx5 es0 W13, lan966x es0 W8 * Egress counter index. Used to index egress counter set as defined in * REW::STAT_CFG. * VCAP_AF_FWD_KILL_ENA: W1, lan966x: is2 @@ -652,9 +661,9 @@ enum vcap_actionfield_set { * (input) AND ~PAG_OVERRIDE_MASK) OR (PAG_VAL AND PAG_OVERRIDE_MASK) * VCAP_AF_PAG_VAL: W8, sparx5: is0, lan966x: is1 * See PAG_OVERRIDE_MASK. - * VCAP_AF_PCP_A_VAL: W3, sparx5: es0 + * VCAP_AF_PCP_A_VAL: W3, sparx5: es0, lan966x: es0 * PCP used in ES0 tag A. See TAG_A_PCP_SEL. - * VCAP_AF_PCP_B_VAL: W3, sparx5: es0 + * VCAP_AF_PCP_B_VAL: W3, sparx5: es0, lan966x: es0 * PCP used in ES0 tag B. See TAG_B_PCP_SEL. * VCAP_AF_PCP_C_VAL: W3, sparx5: es0 * PCP used in ES0 tag C. See TAG_C_PCP_SEL. @@ -691,10 +700,10 @@ enum vcap_actionfield_set { * Selects tag C mode: 0: Do not push tag C. 1: Push tag C if * IFH.VSTAX.TAG.WAS_TAGGED =3D 1. 2: Push tag C if IFH.VSTAX.TAG.WAS_TA= GGED =3D 0. * 3: Push tag C if UNTAG_VID_ENA =3D 0 or (C-TAG.VID ! =3D VID_C_VAL). - * VCAP_AF_PUSH_INNER_TAG: W1, sparx5: es0 + * VCAP_AF_PUSH_INNER_TAG: W1, sparx5: es0, lan966x: es0 * Controls inner tagging. 0: Do not push ES0 tag B as inner tag. 1: Pus= h ES0 * tag B as inner tag. - * VCAP_AF_PUSH_OUTER_TAG: W2, sparx5: es0 + * VCAP_AF_PUSH_OUTER_TAG: W2, sparx5: es0, lan966x: es0 * Controls outer tagging. 0: No ES0 tag A: Port tag is allowed if enabl= ed on * port. 1: ES0 tag A: Push ES0 tag A. No port tag. 2: Force port tag: A= lways * push port tag. No ES0 tag A. 3: Force untag: Never push port tag or E= S0 tag @@ -720,29 +729,29 @@ enum vcap_actionfield_set { * VCAP_AF_SWAP_MACS_ENA: W1, sparx5: es0 * This setting is only active when FWD_SEL =3D 1 or FWD_SEL =3D 2 and P= IPELINE_ACT * =3D LBK_ASM. 0: No action. 1: Swap MACs and clear bit 40 in new SMAC. - * VCAP_AF_TAG_A_DEI_SEL: W3, sparx5: es0 + * VCAP_AF_TAG_A_DEI_SEL: sparx5 es0 W3, lan966x es0 W2 * Selects PCP for ES0 tag A. 0: Classified DEI. 1: DEI_A_VAL. 2: DP and= QoS * mapped to PCP (per port table). 3: DP. - * VCAP_AF_TAG_A_PCP_SEL: W3, sparx5: es0 + * VCAP_AF_TAG_A_PCP_SEL: sparx5 es0 W3, lan966x es0 W2 * Selects PCP for ES0 tag A. 0: Classified PCP. 1: PCP_A_VAL. 2: DP and= QoS * mapped to PCP (per port table). 3: QoS class. - * VCAP_AF_TAG_A_TPID_SEL: W3, sparx5: es0 + * VCAP_AF_TAG_A_TPID_SEL: sparx5 es0 W3, lan966x es0 W2 * Selects TPID for ES0 tag A: 0: 0x8100. 1: 0x88A8. 2: Custom * (REW:PORT:PORT_VLAN_CFG.PORT_TPID). 3: If IFH.TAG_TYPE =3D 0 then 0x8= 100 else * custom. - * VCAP_AF_TAG_A_VID_SEL: W2, sparx5: es0 + * VCAP_AF_TAG_A_VID_SEL: sparx5 es0 W2, lan966x es0 W1 * Selects VID for ES0 tag A. 0: Classified VID + VID_A_VAL. 1: VID_A_VA= L. - * VCAP_AF_TAG_B_DEI_SEL: W3, sparx5: es0 + * VCAP_AF_TAG_B_DEI_SEL: sparx5 es0 W3, lan966x es0 W2 * Selects PCP for ES0 tag B. 0: Classified DEI. 1: DEI_B_VAL. 2: DP and= QoS * mapped to PCP (per port table). 3: DP. - * VCAP_AF_TAG_B_PCP_SEL: W3, sparx5: es0 + * VCAP_AF_TAG_B_PCP_SEL: sparx5 es0 W3, lan966x es0 W2 * Selects PCP for ES0 tag B. 0: Classified PCP. 1: PCP_B_VAL. 2: DP and= QoS * mapped to PCP (per port table). 3: QoS class. - * VCAP_AF_TAG_B_TPID_SEL: W3, sparx5: es0 + * VCAP_AF_TAG_B_TPID_SEL: sparx5 es0 W3, lan966x es0 W2 * Selects TPID for ES0 tag B. 0: 0x8100. 1: 0x88A8. 2: Custom * (REW:PORT:PORT_VLAN_CFG.PORT_TPID). 3: If IFH.TAG_TYPE =3D 0 then 0x8= 100 else * custom. - * VCAP_AF_TAG_B_VID_SEL: W2, sparx5: es0 + * VCAP_AF_TAG_B_VID_SEL: sparx5 es0 W2, lan966x es0 W1 * Selects VID for ES0 tag B. 0: Classified VID + VID_B_VAL. 1: VID_B_VA= L. * VCAP_AF_TAG_C_DEI_SEL: W3, sparx5: es0 * Selects DEI source for ES0 tag C. 0: Classified DEI. 1: DEI_C_VAL. 2: @@ -770,9 +779,9 @@ enum vcap_actionfield_set { * VCAP_AF_UNTAG_VID_ENA: W1, sparx5: es0 * Controls insertion of tag C. Untag or insert mode can be selected. See * PUSH_CUSTOMER_TAG. - * VCAP_AF_VID_A_VAL: W12, sparx5: es0 + * VCAP_AF_VID_A_VAL: W12, sparx5: es0, lan966x: es0 * VID used in ES0 tag A. See TAG_A_VID_SEL. - * VCAP_AF_VID_B_VAL: W12, sparx5: es0 + * VCAP_AF_VID_B_VAL: W12, sparx5: es0, lan966x: es0 * VID used in ES0 tag B. See TAG_B_VID_SEL. * VCAP_AF_VID_C_VAL: W12, sparx5: es0 * VID used in ES0 tag C. See TAG_C_VID_SEL. --=20 2.38.0 From nobody Wed Feb 11 12:08:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E06F2C77B75 for ; Tue, 9 May 2023 07:27:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233401AbjEIH1Q (ORCPT ); Tue, 9 May 2023 03:27:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48692 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229460AbjEIH1C (ORCPT ); Tue, 9 May 2023 03:27:02 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20F47659F; Tue, 9 May 2023 00:27:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1683617220; x=1715153220; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rMbvF74XxIM4pJRj6ktpHcOKv3IrPzBVtco4vwIgD1g=; b=lUp1RlKwv5QTRzt5UX4L7TBKU4nGA2ankDlDnIYNHMgsNbyKzrfDxwOd 6ycqBwlrBiFd2bxPIU3reBWOvqZOM8uIOSWwRz9ohsVt3BNQ9HblLsCwA 7+Pv8uX9spbuX6xlgrKZ3q77iCoI+QPEadnHNjpLztVBVy7plBxrknSlp 8RkgXTc9lq94shnsBYXTgpobzuwU+ueCB8Pi+o07n1/iVXRPd6IAZmzRF TyLiBfL7fdgHPlXzBf6JgXG8+cwHeHkRkdQ07qj2xDuYHroMZBdBlvA0Q GaPhVoZoCQUZWeqp1hdjtkoOTp0p1AsatJlPOp7ymjxg+dXqgqiukFIM3 A==; X-IronPort-AV: E=Sophos;i="5.99,261,1677567600"; d="scan'208";a="212523853" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 May 2023 00:26:59 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Tue, 9 May 2023 00:26:59 -0700 Received: from soft-dev3-1.microsemi.net (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Tue, 9 May 2023 00:26:56 -0700 From: Horatiu Vultur To: , , CC: , , , , , , , , Horatiu Vultur Subject: [PATCH net-next 2/3] net: lan966x: Add ES0 VCAP keyset configuration for lan966x Date: Tue, 9 May 2023 09:26:44 +0200 Message-ID: <20230509072645.3245949-3-horatiu.vultur@microchip.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20230509072645.3245949-1-horatiu.vultur@microchip.com> References: <20230509072645.3245949-1-horatiu.vultur@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add ES0 VCAP port keyset configuration for lan966x and also update debugfs to show the keyset configuration. Signed-off-by: Horatiu Vultur --- .../ethernet/microchip/lan966x/lan966x_main.h | 3 + .../ethernet/microchip/lan966x/lan966x_regs.h | 15 ++++ .../microchip/lan966x/lan966x_vcap_debugfs.c | 23 ++++++ .../microchip/lan966x/lan966x_vcap_impl.c | 82 +++++++++++++++++++ 4 files changed, 123 insertions(+) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h b/driver= s/net/ethernet/microchip/lan966x/lan966x_main.h index c977c70abc3dc..882d5a08e7d51 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_main.h +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_main.h @@ -101,6 +101,9 @@ #define LAN966X_VCAP_CID_IS2_L1 VCAP_CID_INGRESS_STAGE2_L1 /* IS2 lookup 1= */ #define LAN966X_VCAP_CID_IS2_MAX (VCAP_CID_INGRESS_STAGE2_L2 - 1) /* IS2 M= ax */ =20 +#define LAN966X_VCAP_CID_ES0_L0 VCAP_CID_EGRESS_L0 /* ES0 lookup 0 */ +#define LAN966X_VCAP_CID_ES0_MAX (VCAP_CID_EGRESS_L1 - 1) /* ES0 Max */ + /* MAC table entry types. * ENTRYTYPE_NORMAL is subject to aging. * ENTRYTYPE_LOCKED is not subject to aging. diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_regs.h b/driver= s/net/ethernet/microchip/lan966x/lan966x_regs.h index f99f88b5caa88..2220391802766 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_regs.h +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_regs.h @@ -1471,12 +1471,27 @@ enum lan966x_target { /* REW:PORT:PORT_CFG */ #define REW_PORT_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 8= , 0, 1, 4) =20 +#define REW_PORT_CFG_ES0_EN BIT(4) +#define REW_PORT_CFG_ES0_EN_SET(x)\ + FIELD_PREP(REW_PORT_CFG_ES0_EN, x) +#define REW_PORT_CFG_ES0_EN_GET(x)\ + FIELD_GET(REW_PORT_CFG_ES0_EN, x) + #define REW_PORT_CFG_NO_REWRITE BIT(0) #define REW_PORT_CFG_NO_REWRITE_SET(x)\ FIELD_PREP(REW_PORT_CFG_NO_REWRITE, x) #define REW_PORT_CFG_NO_REWRITE_GET(x)\ FIELD_GET(REW_PORT_CFG_NO_REWRITE, x) =20 +/* REW:COMMON:STAT_CFG */ +#define REW_STAT_CFG __REG(TARGET_REW, 0, 1, 3072, 0, 1, 528,= 520, 0, 1, 4) + +#define REW_STAT_CFG_STAT_MODE GENMASK(1, 0) +#define REW_STAT_CFG_STAT_MODE_SET(x)\ + FIELD_PREP(REW_STAT_CFG_STAT_MODE, x) +#define REW_STAT_CFG_STAT_MODE_GET(x)\ + FIELD_GET(REW_STAT_CFG_STAT_MODE, x) + /* SYS:SYSTEM:RESET_CFG */ #define SYS_RESET_CFG __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168,= 0, 0, 1, 4) =20 diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_vcap_debugfs.c = b/drivers/net/ethernet/microchip/lan966x/lan966x_vcap_debugfs.c index d90c08cfcf142..ac525ff1503e6 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_vcap_debugfs.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_vcap_debugfs.c @@ -190,6 +190,26 @@ static void lan966x_vcap_is2_port_keys(struct lan966x_= port *port, out->prf(out->dst, "\n"); } =20 +static void lan966x_vcap_es0_port_keys(struct lan966x_port *port, + struct vcap_admin *admin, + struct vcap_output_print *out) +{ + struct lan966x *lan966x =3D port->lan966x; + u32 val; + + out->prf(out->dst, " port[%d] (%s): ", port->chip_port, + netdev_name(port->dev)); + + val =3D lan_rd(lan966x, REW_PORT_CFG(port->chip_port)); + out->prf(out->dst, "\n state: "); + if (REW_PORT_CFG_ES0_EN_GET(val)) + out->prf(out->dst, "on"); + else + out->prf(out->dst, "off"); + + out->prf(out->dst, "\n"); +} + int lan966x_vcap_port_info(struct net_device *dev, struct vcap_admin *admin, struct vcap_output_print *out) @@ -210,6 +230,9 @@ int lan966x_vcap_port_info(struct net_device *dev, case VCAP_TYPE_IS1: lan966x_vcap_is1_port_keys(port, admin, out); break; + case VCAP_TYPE_ES0: + lan966x_vcap_es0_port_keys(port, admin, out); + break; default: out->prf(out->dst, " no info\n"); break; diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_vcap_impl.c b/d= rivers/net/ethernet/microchip/lan966x/lan966x_vcap_impl.c index 7ea8e86336091..a4414f63c9b1c 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_vcap_impl.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_vcap_impl.c @@ -10,6 +10,12 @@ =20 #define LAN966X_IS1_LOOKUPS 3 #define LAN966X_IS2_LOOKUPS 2 +#define LAN966X_ES0_LOOKUPS 1 + +#define LAN966X_STAT_ESDX_GRN_BYTES 0x300 +#define LAN966X_STAT_ESDX_GRN_PKTS 0x301 +#define LAN966X_STAT_ESDX_YEL_BYTES 0x302 +#define LAN966X_STAT_ESDX_YEL_PKTS 0x303 =20 static struct lan966x_vcap_inst { enum vcap_type vtype; /* type of vcap */ @@ -20,6 +26,14 @@ static struct lan966x_vcap_inst { int count; /* number of available addresses */ bool ingress; /* is vcap in the ingress path */ } lan966x_vcap_inst_cfg[] =3D { + { + .vtype =3D VCAP_TYPE_ES0, + .tgt_inst =3D 0, + .lookups =3D LAN966X_ES0_LOOKUPS, + .first_cid =3D LAN966X_VCAP_CID_ES0_L0, + .last_cid =3D LAN966X_VCAP_CID_ES0_MAX, + .count =3D 64, + }, { .vtype =3D VCAP_TYPE_IS1, /* IS1-0 */ .tgt_inst =3D 1, @@ -279,6 +293,8 @@ lan966x_vcap_validate_keyset(struct net_device *dev, err =3D lan966x_vcap_is2_get_port_keysets(dev, lookup, &keysetlist, l3_proto); break; + case VCAP_TYPE_ES0: + return kslist->keysets[0]; default: pr_err("vcap type: %s not supported\n", lan966x_vcaps[admin->vtype].name); @@ -338,6 +354,14 @@ static void lan966x_vcap_is2_add_default_fields(struct= lan966x_port *port, VCAP_BIT_0); } =20 +static void lan966x_vcap_es0_add_default_fields(struct lan966x_port *port, + struct vcap_admin *admin, + struct vcap_rule *rule) +{ + vcap_rule_add_key_u32(rule, VCAP_KF_IF_EGR_PORT_NO, + port->chip_port, GENMASK(4, 0)); +} + static void lan966x_vcap_add_default_fields(struct net_device *dev, struct vcap_admin *admin, struct vcap_rule *rule) @@ -351,6 +375,9 @@ static void lan966x_vcap_add_default_fields(struct net_= device *dev, case VCAP_TYPE_IS2: lan966x_vcap_is2_add_default_fields(port, admin, rule); break; + case VCAP_TYPE_ES0: + lan966x_vcap_es0_add_default_fields(port, admin, rule); + break; default: pr_err("vcap type: %s not supported\n", lan966x_vcaps[admin->vtype].name); @@ -366,6 +393,40 @@ static void lan966x_vcap_cache_erase(struct vcap_admin= *admin) memset(&admin->cache.counter, 0, sizeof(admin->cache.counter)); } =20 +/* The ESDX counter is only used/incremented if the frame has been classif= ied + * with an ISDX > 0 (e.g by a rule in IS0). This is not mentioned in the + * datasheet. + */ +static void lan966x_es0_read_esdx_counter(struct lan966x *lan966x, + struct vcap_admin *admin, u32 id) +{ + u32 counter; + + id =3D id & 0xff; /* counter limit */ + mutex_lock(&lan966x->stats_lock); + lan_wr(SYS_STAT_CFG_STAT_VIEW_SET(id), lan966x, SYS_STAT_CFG); + counter =3D lan_rd(lan966x, SYS_CNT(LAN966X_STAT_ESDX_GRN_PKTS)) + + lan_rd(lan966x, SYS_CNT(LAN966X_STAT_ESDX_YEL_PKTS)); + mutex_unlock(&lan966x->stats_lock); + if (counter) + admin->cache.counter =3D counter; +} + +static void lan966x_es0_write_esdx_counter(struct lan966x *lan966x, + struct vcap_admin *admin, u32 id) +{ + id =3D id & 0xff; /* counter limit */ + + mutex_lock(&lan966x->stats_lock); + lan_wr(SYS_STAT_CFG_STAT_VIEW_SET(id), lan966x, SYS_STAT_CFG); + lan_wr(0, lan966x, SYS_CNT(LAN966X_STAT_ESDX_GRN_BYTES)); + lan_wr(admin->cache.counter, lan966x, + SYS_CNT(LAN966X_STAT_ESDX_GRN_PKTS)); + lan_wr(0, lan966x, SYS_CNT(LAN966X_STAT_ESDX_YEL_BYTES)); + lan_wr(0, lan966x, SYS_CNT(LAN966X_STAT_ESDX_YEL_PKTS)); + mutex_unlock(&lan966x->stats_lock); +} + static void lan966x_vcap_cache_write(struct net_device *dev, struct vcap_admin *admin, enum vcap_selection sel, @@ -398,6 +459,9 @@ static void lan966x_vcap_cache_write(struct net_device = *dev, admin->cache.sticky =3D admin->cache.counter > 0; lan_wr(admin->cache.counter, lan966x, VCAP_CNT_DAT(admin->tgt_inst, 0)); + + if (admin->vtype =3D=3D VCAP_TYPE_ES0) + lan966x_es0_write_esdx_counter(lan966x, admin, start); break; default: break; @@ -437,6 +501,9 @@ static void lan966x_vcap_cache_read(struct net_device *= dev, admin->cache.counter =3D lan_rd(lan966x, VCAP_CNT_DAT(instance, 0)); admin->cache.sticky =3D admin->cache.counter > 0; + + if (admin->vtype =3D=3D VCAP_TYPE_ES0) + lan966x_es0_read_esdx_counter(lan966x, admin, start); } } =20 @@ -625,6 +692,12 @@ static void lan966x_vcap_port_key_deselection(struct l= an966x *lan966x, lan_wr(0, lan966x, ANA_VCAP_S2_CFG(p)); =20 break; + case VCAP_TYPE_ES0: + for (int p =3D 0; p < lan966x->num_phys_ports; ++p) + lan_rmw(REW_PORT_CFG_ES0_EN_SET(false), + REW_PORT_CFG_ES0_EN, lan966x, + REW_PORT_CFG(p)); + break; default: pr_err("vcap type: %s not supported\n", lan966x_vcaps[admin->vtype].name); @@ -674,9 +747,18 @@ int lan966x_vcap_init(struct lan966x *lan966x) lan_rmw(ANA_VCAP_CFG_S1_ENA_SET(true), ANA_VCAP_CFG_S1_ENA, lan966x, ANA_VCAP_CFG(lan966x->ports[p]->chip_port)); + + lan_rmw(REW_PORT_CFG_ES0_EN_SET(true), + REW_PORT_CFG_ES0_EN, lan966x, + REW_PORT_CFG(lan966x->ports[p]->chip_port)); } } =20 + /* Statistics: Use ESDX from ES0 if hit, otherwise no counting */ + lan_rmw(REW_STAT_CFG_STAT_MODE_SET(1), + REW_STAT_CFG_STAT_MODE, lan966x, + REW_STAT_CFG); + lan966x->vcap_ctrl =3D ctrl; =20 return 0; --=20 2.38.0 From nobody Wed Feb 11 12:08:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B43DC77B75 for ; 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X-IronPort-AV: E=Sophos;i="5.99,261,1677567600"; d="scan'208";a="210306086" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 May 2023 00:27:02 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Tue, 9 May 2023 00:27:01 -0700 Received: from soft-dev3-1.microsemi.net (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Tue, 9 May 2023 00:26:59 -0700 From: Horatiu Vultur To: , , CC: , , , , , , , , Horatiu Vultur Subject: [PATCH net-next 3/3] net: lan966x: Add TC support for ES0 VCAP Date: Tue, 9 May 2023 09:26:45 +0200 Message-ID: <20230509072645.3245949-4-horatiu.vultur@microchip.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20230509072645.3245949-1-horatiu.vultur@microchip.com> References: <20230509072645.3245949-1-horatiu.vultur@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable the TC command to use the lan966x ES0 VCAP. Currently support only one action which is vlan pop, other will be added later. Signed-off-by: Horatiu Vultur --- .../microchip/lan966x/lan966x_tc_flower.c | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/drivers/net/ethernet/microchip/lan966x/lan966x_tc_flower.c b/d= rivers/net/ethernet/microchip/lan966x/lan966x_tc_flower.c index 47b2f7579dd23..96b3def6c4741 100644 --- a/drivers/net/ethernet/microchip/lan966x/lan966x_tc_flower.c +++ b/drivers/net/ethernet/microchip/lan966x/lan966x_tc_flower.c @@ -5,6 +5,8 @@ #include "vcap_api_client.h" #include "vcap_tc.h" =20 +#define LAN966X_FORCE_UNTAGED 3 + static bool lan966x_tc_is_known_etype(struct vcap_tc_flower_parse_usage *s= t, u16 etype) { @@ -29,6 +31,8 @@ static bool lan966x_tc_is_known_etype(struct vcap_tc_flow= er_parse_usage *st, return true; } break; + case VCAP_TYPE_ES0: + return true; default: NL_SET_ERR_MSG_MOD(st->fco->common.extack, "VCAP type not supported"); @@ -318,6 +322,9 @@ static int lan966x_tc_set_actionset(struct vcap_admin *= admin, case VCAP_TYPE_IS2: aset =3D VCAP_AFS_BASE_TYPE; break; + case VCAP_TYPE_ES0: + aset =3D VCAP_AFS_VID; + break; default: return -EINVAL; } @@ -353,6 +360,10 @@ static int lan966x_tc_add_rule_link_target(struct vcap= _admin *admin, /* Add IS2 specific PAG key (for chaining rules from IS1) */ return vcap_rule_add_key_u32(vrule, VCAP_KF_LOOKUP_PAG, link_val, ~0); + case VCAP_TYPE_ES0: + /* Add ES0 specific ISDX key (for chaining rules from IS1) */ + return vcap_rule_add_key_u32(vrule, VCAP_KF_ISDX_CLS, + link_val, ~0); default: break; } @@ -389,6 +400,18 @@ static int lan966x_tc_add_rule_link(struct vcap_contro= l *vctrl, 0xff); if (err) return err; + } else if (admin->vtype =3D=3D VCAP_TYPE_IS1 && + to_admin->vtype =3D=3D VCAP_TYPE_ES0) { + /* This works for IS1->ES0 */ + err =3D vcap_rule_add_action_u32(vrule, VCAP_AF_ISDX_ADD_VAL, + diff); + if (err) + return err; + + err =3D vcap_rule_add_action_bit(vrule, VCAP_AF_ISDX_REPLACE_ENA, + VCAP_BIT_1); + if (err) + return err; } else { NL_SET_ERR_MSG_MOD(f->common.extack, "Unsupported chain destination"); @@ -398,6 +421,23 @@ static int lan966x_tc_add_rule_link(struct vcap_contro= l *vctrl, return err; } =20 +static int lan966x_tc_add_rule_counter(struct vcap_admin *admin, + struct vcap_rule *vrule) +{ + int err =3D 0; + + switch (admin->vtype) { + case VCAP_TYPE_ES0: + err =3D vcap_rule_mod_action_u32(vrule, VCAP_AF_ESDX, + vrule->id); + break; + default: + break; + } + + return err; +} + static int lan966x_tc_flower_add(struct lan966x_port *port, struct flow_cls_offload *f, struct vcap_admin *admin, @@ -465,6 +505,21 @@ static int lan966x_tc_flower_add(struct lan966x_port *= port, if (err) goto out; =20 + break; + case FLOW_ACTION_VLAN_POP: + if (admin->vtype !=3D VCAP_TYPE_ES0) { + NL_SET_ERR_MSG_MOD(f->common.extack, + "Cannot use vlan pop on non es0"); + err =3D -EOPNOTSUPP; + goto out; + } + + /* Force untag */ + err =3D vcap_rule_add_action_u32(vrule, VCAP_AF_PUSH_OUTER_TAG, + LAN966X_FORCE_UNTAGED); + if (err) + goto out; + break; default: NL_SET_ERR_MSG_MOD(f->common.extack, @@ -474,6 +529,12 @@ static int lan966x_tc_flower_add(struct lan966x_port *= port, } } =20 + err =3D lan966x_tc_add_rule_counter(admin, vrule); + if (err) { + vcap_set_tc_exterr(f, vrule); + goto out; + } + err =3D vcap_val_rule(vrule, l3_proto); if (err) { vcap_set_tc_exterr(f, vrule); --=20 2.38.0