From nobody Wed Feb 11 14:44:36 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 573F0C7EE24 for ; Sun, 7 May 2023 18:34:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231480AbjEGSeU (ORCPT ); Sun, 7 May 2023 14:34:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229460AbjEGSeR (ORCPT ); Sun, 7 May 2023 14:34:17 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 024D36E82; Sun, 7 May 2023 11:34:17 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 8C0C460FB1; Sun, 7 May 2023 18:34:16 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6F72FC433A1; Sun, 7 May 2023 18:34:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1683484456; bh=BANIf+ASt30mN5iS/NWLlkQ2ov0wGoxCBBMNfEgEvLk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iI2gauWXX+FpvZGeuZivJ5XIu/c/TN8lfj5WAK9mc72mvIoGhJH2S9uYQDOJymWlE LulXx6JEDOKWhOmWkm7ja3YdWQHbNavQi1lD0RN7dvxG8QSXcuyUX0ecMFHWUJ8HTO OoN3SPK/P+sGNQHeOzRFx4kXJmF/y3Gr2muWMdu2FKCJWiJSK0jsnib5zH5siuLnOO 7HITT5jeGH4riYtTIBC35hmL1GsO0GU0ZlnKYhCbOJcrp/xXMa7bgArhNC9LnfHqXh tNUJe8EbpWaj8kXhIthunrRBkly54fbXcirV3z//8Z9Ol1HTI4LTT7FyVxoiJxahnq iw3IQNL5k9ZwA== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [PATCH 1/5] irqchip/sifive-plic: Support T-HEAD's C910 PLIC Date: Mon, 8 May 2023 02:23:00 +0800 Message-Id: <20230507182304.2934-2-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230507182304.2934-1-jszhang@kernel.org> References: <20230507182304.2934-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The T-HEAD's C910 PLIC still needs the delegation bit settingto allow access from S-mode, but it doesn't need the edge quirk. Signed-off-by: Jisheng Zhang --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 4 ++++ drivers/irqchip/irq-sifive-plic.c | 1 + 2 files changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,= plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/si= five,plic-1.0.0.yaml index f75736a061af..64b43a3c3748 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml @@ -62,6 +62,10 @@ properties: - starfive,jh7110-plic - canaan,k210-plic - const: sifive,plic-1.0.0 + - items: + - enum: + - thead,light-plic + - const: thead,c910-plic - items: - enum: - allwinner,sun20i-d1-plic diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive= -plic.c index e1484905b7bd..71afa2a584d9 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -569,6 +569,7 @@ static int __init plic_init(struct device_node *node, } =20 IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init); +IRQCHIP_DECLARE(thead_c910_plic, "thead,c910-plic", plic_init); IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy syst= ems */ =20 static int __init plic_edge_init(struct device_node *node, --=20 2.40.0 From nobody Wed Feb 11 14:44:36 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98105C77B75 for ; Sun, 7 May 2023 18:34:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231564AbjEGSeY (ORCPT ); Sun, 7 May 2023 14:34:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44314 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231472AbjEGSeU (ORCPT ); Sun, 7 May 2023 14:34:20 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 096EA9EE8; Sun, 7 May 2023 11:34:20 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 8FAF86119E; Sun, 7 May 2023 18:34:19 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6F993C433D2; Sun, 7 May 2023 18:34:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1683484459; bh=Cwi9G0RC9sDhCBbFheRaOVgx+rmiAvtJuPLG5ht1r7Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uNMPk3ntZAVS8YwlGv7g0/1DxLS+CXoeUiidi4/241Adf5EX2uPx2Ky9DwASPEh9P tlnzGdYjzsgWdMnSbcVsFbQBkNwMNDiI4ceLzELguWR78J0trAbI/463xvg2mGEKSz bUdNrvv8fgJ7YTZYWyWPg5bPNCyr7rMZyvkSM4VEzTtEX2/1HjNb7bq8J4HL9Hl83z SEaXt+7YLPVlPuSIBZ6vLJEZFk75f2J/oqpDKppyCOxKVxYoOd9z/H5zbisZ0NmT2P 5XW600//wLg/3j+ctQVwLf0s7QvgsztjxL+oa3vs58PktKJBcGCOY6YdVjk/GD7Hl8 pdupIoJGBLpbQ== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [PATCH 2/5] riscv: Add the T-HEAD SoC family Kconfig option Date: Mon, 8 May 2023 02:23:01 +0800 Message-Id: <20230507182304.2934-3-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230507182304.2934-1-jszhang@kernel.org> References: <20230507182304.2934-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The first SoC in the T-HEAD series is light(a.k.a th1520), containing quad T-HEAD C910 cores. Signed-off-by: Jisheng Zhang --- arch/riscv/Kconfig.socs | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 1cf69f958f10..ce10a38dff37 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -41,6 +41,12 @@ config ARCH_SUNXI This enables support for Allwinner sun20i platform hardware, including boards based on the D1 and D1s SoCs. =20 +config ARCH_THEAD + bool "T-HEAD RISC-V SoCs" + select ERRATA_THEAD + help + This enables support for the RISC-V based T-HEAD SoCs. + config ARCH_VIRT def_bool SOC_VIRT =20 --=20 2.40.0 From nobody Wed Feb 11 14:44:36 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB3A0C7EE2D for ; Sun, 7 May 2023 18:34:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231787AbjEGSef (ORCPT ); Sun, 7 May 2023 14:34:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44660 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231589AbjEGSe2 (ORCPT ); Sun, 7 May 2023 14:34:28 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 104D912EAC; Sun, 7 May 2023 11:34:23 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 96DF261C83; Sun, 7 May 2023 18:34:22 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 71598C433A4; Sun, 7 May 2023 18:34:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1683484462; bh=hMtC0Fu67Ii4QODNt4TY01t+H41Ind3v5j5PxzFdpSo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ovLIV0PTmRvfxI7HsIK6QLdI/x4ljE/SK0Jg2V0ARdAGfrlS3CZilmQM/32IFMq+A WlVlZuEoJVqZXmqU32H/VXoJ7IgSCGhYaSPmBQ4G6to7lu1jUbM48S5Jq94ZUnHdYN Aom5m73N8SoJsLXA/Oacb9/iFWLLbrk1xoraF54lwTpU1Slo4FzdZF26p/Uc5TciBW YTVil1CUM66u7JlO854mFzcvOPMr7hJ63kK50wdlaP4HsDu0zXZeBFp8YV/CPaWAeB afmtA297pcCMApjOu2XVYeuJ9e0ILPeS8I+kpIM2V2DKlaTjJb3uFBHawQEdHztZ+O X2txNSRdBNT7A== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [PATCH 3/5] riscv: dts: add initial T-HEAD light SoC device tree Date: Mon, 8 May 2023 02:23:02 +0800 Message-Id: <20230507182304.2934-4-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230507182304.2934-1-jszhang@kernel.org> References: <20230507182304.2934-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add initial device tree for the light(a.k.a TH1520) RISC-V SoC by T-HEAD. Signed-off-by: Jisheng Zhang --- arch/riscv/boot/dts/thead/light.dtsi | 454 +++++++++++++++++++++++++++ 1 file changed, 454 insertions(+) create mode 100644 arch/riscv/boot/dts/thead/light.dtsi diff --git a/arch/riscv/boot/dts/thead/light.dtsi b/arch/riscv/boot/dts/the= ad/light.dtsi new file mode 100644 index 000000000000..cdf6d8b04d22 --- /dev/null +++ b/arch/riscv/boot/dts/thead/light.dtsi @@ -0,0 +1,454 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + * Copyright (C) 2023 Jisheng Zhang + */ + +/ { + compatible =3D "thead,light"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus: cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + timebase-frequency =3D <3000000>; + + c910_0: cpu@0 { + compatible =3D "thead,c910", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + reg =3D <0>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache>; + mmu-type =3D "riscv,sv39"; + + cpu0_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + c910_1: cpu@1 { + compatible =3D "thead,c910", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + reg =3D <1>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache>; + mmu-type =3D "riscv,sv39"; + + cpu1_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + c910_2: cpu@2 { + compatible =3D "thead,c910", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + reg =3D <2>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache>; + mmu-type =3D "riscv,sv39"; + + cpu2_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + c910_3: cpu@3 { + compatible =3D "thead,c910", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + reg =3D <3>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache>; + mmu-type =3D "riscv,sv39"; + + cpu3_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&c910_0>; + }; + + core1 { + cpu =3D <&c910_1>; + }; + + core2 { + cpu =3D <&c910_2>; + }; + + core3 { + cpu =3D <&c910_3>; + }; + }; + }; + + l2_cache: l2-cache { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + }; + + osc: oscillator { + compatible =3D "fixed-clock"; + clock-output-names =3D "osc_24m"; + #clock-cells =3D <0>; + }; + + osc_32k: 32k-oscillator { + compatible =3D "fixed-clock"; + clock-output-names =3D "osc_32k"; + #clock-cells =3D <0>; + }; + + apb_clk: apb-clk-clock { + compatible =3D "fixed-clock"; + clock-output-names =3D "apb_clk"; + #clock-cells =3D <0>; + }; + + uart_sclk: uart-sclk-clock { + compatible =3D "fixed-clock"; + clock-output-names =3D "uart_sclk"; + #clock-cells =3D <0>; + }; + + soc { + compatible =3D "simple-bus"; + interrupt-parent =3D <&plic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + reset: reset-sample { + compatible =3D "thead,reset-sample"; + entry-reg =3D <0xff 0xff019050>; + entry-cnt =3D <4>; + control-reg =3D <0xff 0xff015004>; + control-val =3D <0x1c>; + csr-copy =3D <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>; + }; + + plic: interrupt-controller@ffd8000000 { + compatible =3D "thead,c910-plic"; + reg =3D <0xff 0xd8000000 0x0 0x01000000>; + interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>; + interrupt-controller; + #interrupt-cells =3D <1>; + riscv,ndev =3D <240>; + }; + + clint: timer@ffdc000000 { + compatible =3D "thead,c900-clint"; + reg =3D <0xff 0xdc000000 0x0 0x00010000>; + interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>; + }; + + uart0: serial@ffe7014000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0xff 0xe7014000 0x0 0x4000>; + interrupts =3D <36>; + clocks =3D <&uart_sclk>; + clock-names =3D "baudclk"; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart1: serial@ffe7f00000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0xff 0xe7f00000 0x0 0x4000>; + interrupts =3D <37>; + clocks =3D <&uart_sclk>; + clock-names =3D "baudclk"; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart3: serial@ffe7f04000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0xff 0xe7f04000 0x0 0x4000>; + interrupts =3D <39>; + clocks =3D <&uart_sclk>; + clock-names =3D "baudclk"; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + gpio2: gpio@ffe7f34000 { + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0xff 0xe7f34000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + portc: gpio-controller@0 { + compatible =3D "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells =3D <2>; + ngpios =3D <32>; + reg =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D <58>; + }; + }; + + gpio3: gpio@ffe7f38000 { + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0xff 0xe7f38000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + portd: gpio-controller@0 { + compatible =3D "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells =3D <2>; + ngpios =3D <32>; + reg =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D <59>; + }; + }; + + gpio0: gpio@ffec005000 { + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0xff 0xec005000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + porta: gpio-controller@0 { + compatible =3D "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells =3D <2>; + ngpios =3D <32>; + reg =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D <56>; + }; + }; + + gpio1: gpio@ffec006000 { + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0xff 0xec006000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + portb: gpio-controller@0 { + compatible =3D "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells =3D <2>; + ngpios =3D <32>; + reg =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D <57>; + }; + }; + + uart2: serial@ffec010000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0xff 0xec010000 0x0 0x4000>; + interrupts =3D <38>; + clocks =3D <&uart_sclk>; + clock-names =3D "baudclk"; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + dmac0: dmac@ffefc00000 { + compatible =3D "snps,axi-dma-1.01a"; + reg =3D <0xff 0xefc00000 0x0 0x1000>; + interrupts =3D <27>; + clocks =3D <&apb_clk>, <&apb_clk>; + clock-names =3D "core-clk", "cfgr-clk"; + #dma-cells =3D <1>; + dma-channels =3D <4>; + snps,block-size =3D <65536 65536 65536 65536>; + snps,priority =3D <0 1 2 3>; + snps,dma-masters =3D <1>; + snps,data-width =3D <4>; + snps,axi-max-burst-len =3D <16>; + status =3D "disabled"; + }; + + timer0: timer@ffefc32000 { + compatible =3D "snps,dw-apb-timer"; + reg =3D <0xff 0xefc32000 0x0 0x14>; + clocks =3D <&apb_clk>; + clock-names =3D "timer"; + interrupts =3D <16>; + status =3D "disabled"; + }; + + timer1: timer@ffefc32014 { + compatible =3D "snps,dw-apb-timer"; + reg =3D <0xff 0xefc32014 0x0 0x14>; + clocks =3D <&apb_clk>; + clock-names =3D "timer"; + interrupts =3D <17>; + status =3D "disabled"; + }; + + timer2: timer@ffefc32028 { + compatible =3D "snps,dw-apb-timer"; + reg =3D <0xff 0xefc32028 0x0 0x14>; + clocks =3D <&apb_clk>; + clock-names =3D "timer"; + interrupts =3D <18>; + status =3D "disabled"; + }; + + timer3: timer@ffefc3203c { + compatible =3D "snps,dw-apb-timer"; + reg =3D <0xff 0xefc3203c 0x0 0x14>; + clocks =3D <&apb_clk>; + clock-names =3D "timer"; + interrupts =3D <19>; + status =3D "disabled"; + }; + + uart4: serial@fff7f08000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0xff 0xf7f08000 0x0 0x4000>; + interrupts =3D <40>; + clocks =3D <&uart_sclk>; + clock-names =3D "baudclk"; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart5: serial@fff7f0c000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0xff 0xf7f0c000 0x0 0x4000>; + interrupts =3D <41>; + clocks =3D <&uart_sclk>; + clock-names =3D "baudclk"; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + timer4: timer@ffffc33000 { + compatible =3D "snps,dw-apb-timer"; + reg =3D <0xff 0xffc33000 0x0 0x14>; + clocks =3D <&apb_clk>; + clock-names =3D "timer"; + interrupts =3D <20>; + status =3D "disabled"; + }; + + timer5: timer@ffffc33014 { + compatible =3D "snps,dw-apb-timer"; + reg =3D <0xff 0xffc33014 0x0 0x14>; + clocks =3D <&apb_clk>; + clock-names =3D "timer"; + interrupts =3D <21>; + status =3D "disabled"; + }; + + timer6: timer@ffffc33028 { + compatible =3D "snps,dw-apb-timer"; + reg =3D <0xff 0xffc33028 0x0 0x14>; + clocks =3D <&apb_clk>; + clock-names =3D "timer"; + interrupts =3D <22>; + status =3D "disabled"; + }; + + timer7: timer@ffffc3303c { + compatible =3D "snps,dw-apb-timer"; + reg =3D <0xff 0xffc3303c 0x0 0x14>; + clocks =3D <&apb_clk>; + clock-names =3D "timer"; + interrupts =3D <23>; + status =3D "disabled"; + }; + + ao_gpio0: gpio@fffff41000 { + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0xff 0xfff41000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + porte: gpio-controller@0 { + compatible =3D "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells =3D <2>; + ngpios =3D <32>; + reg =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D <76>; + }; + }; + + ao_gpio1: gpio@fffff52000 { + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0xff 0xfff52000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + portf: gpio-controller@0 { + compatible =3D "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells =3D <2>; + ngpios =3D <32>; + reg =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D <55>; + }; + }; + }; +}; --=20 2.40.0 From nobody Wed Feb 11 14:44:36 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D681C7EE24 for ; Sun, 7 May 2023 18:34:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231829AbjEGSeh (ORCPT ); Sun, 7 May 2023 14:34:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44870 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231686AbjEGSed (ORCPT ); Sun, 7 May 2023 14:34:33 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 326527A82; Sun, 7 May 2023 11:34:26 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 8FBD460FB1; Sun, 7 May 2023 18:34:25 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 763F4C4339C; Sun, 7 May 2023 18:34:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1683484465; bh=2RFGJcRC8JFrMMqTRjHn7GAHKS+k26LwNQvh7lnf8Oo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EaLyerAZnN7eLruXlnT2hQfLIKGVwmdNkkKVAuDGkjPSWrzxycJZVouATTBG8A06h IXzKSkNlQaualCy4W0yX1WkhhPH7BJ0nejUz+wkKrSv89OLb4AxcuJ7l/mUeiP/sBQ De1b18YxQMbnoLvBjJuq5GbjH8Whca2XNuA3XRk57I4ZmWGEseVkt1AmmQ0yYERPM2 1yqt/moQtM8VkLFpvAt1MABtkqACsxpNvAnOAYp14l7VqbjIzNZW8bacdY8G42tLsb lIw9CtZdfdJwwskl7BHrFHHHlXgLNklDiX1BaWB3yJFfHy27LdXf3YuVVNjBrTdOPU V8YkFhtw+7WUg== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [PATCH 4/5] riscv: dts: thead: add sipeed Lichee Pi 4A board device tree Date: Mon, 8 May 2023 02:23:03 +0800 Message-Id: <20230507182304.2934-5-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230507182304.2934-1-jszhang@kernel.org> References: <20230507182304.2934-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core module which is powered by T-HEAD's light(a.k.a TH1520) SoC. Add minimal device tree files for the core module and the development board. Support basic uart/gpio/dmac drivers, so supports booting to a basic shell. Signed-off-by: Jisheng Zhang --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/thead/Makefile | 2 + .../dts/thead/light-lichee-module-4a.dtsi | 38 +++++++++++++++++++ .../boot/dts/thead/light-lichee-pi-4a.dts | 32 ++++++++++++++++ 4 files changed, 73 insertions(+) create mode 100644 arch/riscv/boot/dts/thead/Makefile create mode 100644 arch/riscv/boot/dts/thead/light-lichee-module-4a.dtsi create mode 100644 arch/riscv/boot/dts/thead/light-lichee-pi-4a.dts diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index f0d9f89054f8..1e884868ccba 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -2,6 +2,7 @@ subdir-y +=3D allwinner subdir-y +=3D sifive subdir-y +=3D starfive +subdir-y +=3D thead subdir-y +=3D canaan subdir-y +=3D microchip subdir-y +=3D renesas diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead= /Makefile new file mode 100644 index 000000000000..9e00acc714cc --- /dev/null +++ b/arch/riscv/boot/dts/thead/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_THEAD) +=3D light-lichee-pi-4a.dtb diff --git a/arch/riscv/boot/dts/thead/light-lichee-module-4a.dtsi b/arch/r= iscv/boot/dts/thead/light-lichee-module-4a.dtsi new file mode 100644 index 000000000000..24c9971e0fb5 --- /dev/null +++ b/arch/riscv/boot/dts/thead/light-lichee-module-4a.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Jisheng Zhang + */ + +/dts-v1/; + +#include "light.dtsi" + +/ { + model =3D "Sipeed Lichee Module 4A"; + compatible =3D "sipeed,lichee-module-4a", "thead,light"; + + memory@0 { + device_type =3D "memory"; + reg =3D <0x0 0x00000000 0x2 0x00000000>; + }; +}; + +&osc { + clock-frequency =3D <24000000>; +}; + +&osc_32k { + clock-frequency =3D <32768>; +}; + +&apb_clk { + clock-frequency =3D <62500000>; +}; + +&uart_sclk { + clock-frequency =3D <100000000>; +}; + +&dmac0 { + status =3D "okay"; +}; diff --git a/arch/riscv/boot/dts/thead/light-lichee-pi-4a.dts b/arch/riscv/= boot/dts/thead/light-lichee-pi-4a.dts new file mode 100644 index 000000000000..4f0ba2149d2d --- /dev/null +++ b/arch/riscv/boot/dts/thead/light-lichee-pi-4a.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Jisheng Zhang + */ + +#include "light-lichee-module-4a.dtsi" + +/ { + model =3D "Sipeed Lichee Pi 4A"; + compatible =3D "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,l= ight"; + + aliases { + gpio0 =3D &gpio0; + gpio1 =3D &gpio1; + gpio2 =3D &gpio2; + gpio3 =3D &gpio3; + serial0 =3D &uart0; + serial1 =3D &uart1; + serial2 =3D &uart2; + serial3 =3D &uart3; + serial4 =3D &uart4; + serial5 =3D &uart5; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; +}; + +&uart0 { + status =3D "okay"; +}; --=20 2.40.0 From nobody Wed Feb 11 14:44:36 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF671C77B7C for ; Sun, 7 May 2023 18:34:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231826AbjEGSet (ORCPT ); Sun, 7 May 2023 14:34:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45148 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231738AbjEGSel (ORCPT ); Sun, 7 May 2023 14:34:41 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F2216E93; Sun, 7 May 2023 11:34:29 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 9497B61C67; Sun, 7 May 2023 18:34:28 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 752CDC433EF; Sun, 7 May 2023 18:34:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1683484468; bh=5Ctl8xQn5Up2BfcQEPensi3ZFyebX1h9yHH8JgAlfCU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GehbaZeik0nSLoZNom/ZTCM0VHsqmpTwh5xbhVcQl8OSoZhhfGUog1cH08s3zpl9V AYYIaMPmJcU0f9YlzCeDy43U1obqTFYZuMNO6BLy7OLdemKuctVdAhuXzNl91nIk62 f0/LCnyxwniZuHwxfdasaHd1uO8ajjSp7ZlqAocn/0g8dYAIOj/KdknmHwjXJv4cMe mGhaaMYZZRYLfOLwvXe8Yq7Bb8pbFmVo0SKNXgUgYcKoTVshRXYHWsumOOXy2437oz NrBtzurbpkuyUC1FAY2ko5fqepWgZO7UtRtMfNu4/bLTB3EVX5zoMdIDZlWHBHyPth Hp7vTxangetyg== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [PATCH 5/5] MAINTAINERS: add entry for T-HEAD RISC-V SoC Date: Mon, 8 May 2023 02:23:04 +0800 Message-Id: <20230507182304.2934-6-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230507182304.2934-1-jszhang@kernel.org> References: <20230507182304.2934-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" I would like to temporarily maintain the T-HEAD RISC-V SoC support. Signed-off-by: Jisheng Zhang --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7e0b87d5aa2e..e1e51accec4f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18155,6 +18155,12 @@ T: git https://git.kernel.org/pub/scm/linux/kernel= /git/conor/linux.git/ F: Documentation/devicetree/bindings/riscv/ F: arch/riscv/boot/dts/ =20 +RISC-V THEAD SoC SUPPORT +M: Jisheng Zhang +L: linux-riscv@lists.infradead.org +S: Maintained +F: arch/riscv/boot/dts/thead/ + RNBD BLOCK DRIVERS M: Md. Haris Iqbal M: Jack Wang --=20 2.40.0