From nobody Wed Feb 11 09:01:12 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5537C77B7F for ; Sat, 6 May 2023 12:36:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232707AbjEFMgR (ORCPT ); Sat, 6 May 2023 08:36:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56704 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232203AbjEFMgB (ORCPT ); Sat, 6 May 2023 08:36:01 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D2D3156AE for ; Sat, 6 May 2023 05:36:00 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (unknown [IPv6:2001:b07:2ed:14ed:c5f8:7372:f042:90a2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 9C4666605768; Sat, 6 May 2023 13:35:58 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1683376559; bh=t3Yo6cHQoAoNoCUG2dmavZcbfM5oNhDdyemwXNrxsEk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TA0OSQ+r1egaFrnrkXsfudrxFQ1dfQXE4pqUVvrUAIIyXn95v0jETcPsd3lh+Nekk fVchpG1ap5zb/9CMm57IJGAwDdd9TnJ1apkENyJRxAJvUTCm5w4+gAX8LZiyq4gpIw HY6KftkAxOhJBwxL27fJOeVqTHZ13m9DUEtsn8SwqkCC8oEp5k5xDOdvb7gHu+F/GL I4+Nja7m9X0D/2vwvXsno6OQpcliseQXAphWNY4DC1huzWX0y8i0hgNXEXbkHWWfOB Z5yJ2NACaVS76sEaE9gFH9u6RVkIxC9sTSfbocyt6pk8RuHJcbBdSHjwjKoDBO/km4 87+Kg5dFz43Ag== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com Subject: [PATCH v3 05/11] drm/mediatek: gamma: Enable the Gamma LUT table only after programming Date: Sat, 6 May 2023 14:35:43 +0200 Message-Id: <20230506123549.101727-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230506123549.101727-1-angelogioacchino.delregno@collabora.com> References: <20230506123549.101727-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Move the write to DISP_GAMMA_CFG to enable the Gamma LUT to after programming the actual table to avoid potential visual glitches during table modification. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index 60ccea8c1e1a..1592614b6de7 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -71,12 +71,12 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev) void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct d= rm_crtc_state *state) { struct mtk_disp_gamma *gamma =3D dev_get_drvdata(dev); - unsigned int i, reg; + unsigned int i; struct drm_color_lut *lut; void __iomem *lut_base; bool lut_diff; u16 lut_size; - u32 word; + u32 cfg_val, word; =20 /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) @@ -90,9 +90,7 @@ void mtk_gamma_set_common(struct device *dev, void __iome= m *regs, struct drm_crt lut_size =3D LUT_SIZE_DEFAULT; } =20 - reg =3D readl(regs + DISP_GAMMA_CFG); - reg =3D reg | GAMMA_LUT_EN; - writel(reg, regs + DISP_GAMMA_CFG); + cfg_val =3D readl(regs + DISP_GAMMA_CFG); lut_base =3D regs + DISP_GAMMA_LUT; lut =3D (struct drm_color_lut *)state->gamma_lut->data; for (i =3D 0; i < lut_size; i++) { @@ -122,6 +120,11 @@ void mtk_gamma_set_common(struct device *dev, void __i= omem *regs, struct drm_crt } writel(word, (lut_base + i * 4)); } + + /* Enable the gamma table */ + cfg_val =3D cfg_val | GAMMA_LUT_EN; + + writel(cfg_val, regs + DISP_GAMMA_CFG); } =20 void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) --=20 2.40.1