From nobody Wed Feb 11 17:46:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF0E0C77B75 for ; Sat, 6 May 2023 01:10:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231192AbjEFBKI (ORCPT ); Fri, 5 May 2023 21:10:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44708 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230196AbjEFBJy (ORCPT ); Fri, 5 May 2023 21:09:54 -0400 Received: from mail-il1-x136.google.com (mail-il1-x136.google.com [IPv6:2607:f8b0:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 35B5C76A2 for ; Fri, 5 May 2023 18:09:53 -0700 (PDT) Received: by mail-il1-x136.google.com with SMTP id e9e14a558f8ab-331333e6bf1so6076355ab.3 for ; Fri, 05 May 2023 18:09:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683335392; x=1685927392; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NisaWLzWuQ0RLSEQ949UB4sRB725O5JKOWjH/0XJDqY=; b=Np1rKEPbU7aa82z3Sb5nU58RP4e43ySPy3mQRqPzZICYad31TTute8Nn91XSsDTlj8 hejh2NS3TPTsk990WiIBTXCaACA26iBJNlmF0noaxaUOzwn/ad0DEKDt2m8WZVIU3fLE U+hc1ghuV5M/fSOj5JgUwWcqPFIvSBy3v5qg43vsKEIJQa2y8LomY/NbwJfDKnhQdw9w RvK63f4m74sjdd3bhZ6dukBxHfZhPuuGbyoQu/G++dXbbJnrBTmp2RFBQlbwXrJDfdVv 6KcpDyvDlTKhezV5gzZy7/KAawbWZJ5HmcJJJEVrzFqbS66cr6/hdLgdpGM7B7HcRHOc M7uA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683335392; x=1685927392; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NisaWLzWuQ0RLSEQ949UB4sRB725O5JKOWjH/0XJDqY=; b=eoTUpuc6WxrINaOM2rEBtg65ZG1cCgVzfPuimWHs/aGGpfLIh3MzXesczrSpT2YER3 HFRwWdom8MwLm72CqdrtTqoLorr14IfFpAeREF1ZoTf/ZkGrqWwlTkTVDFrpwKwkR9pE uSncmDP6WwyyRavqZjAzSLISHiTFjsjZlR7v3HFqHEMmTKfwXROD1WXkZMsIt/kORlF7 weP4nO8mFoE29WrSP5eHglhTyFeU+5SsYXgwGYoCJVZVmuc8HIJAxWQptxrrJVec994b pF0UNpWF9qStEGQBFoTHjVPMLpYacaLXAACG5diMf8e81ZZstJL6MTOXibdxQbxSKwNX r39w== X-Gm-Message-State: AC+VfDxoZ0XCjTe57fuZSSHOksaAhE0msssaAwI+KKGmYnP1JXCy0iXe RDXkZW5tFXirV1wXIV+fKuk= X-Google-Smtp-Source: ACHHUZ6BC2SZ0HW2iiPkX1xIA2IyCU/D+31hzAOHllsssoB8rHA1toCbGsFQ9+d3F/rYpXA35SqcnA== X-Received: by 2002:a5d:94c9:0:b0:769:bdaa:a4d9 with SMTP id y9-20020a5d94c9000000b00769bdaaa4d9mr1819301ior.12.1683335392457; Fri, 05 May 2023 18:09:52 -0700 (PDT) Received: from aford-B741.lan ([2601:447:d001:897f:34a2:3894:45cc:c002]) by smtp.gmail.com with ESMTPSA id r11-20020a5e950b000000b00760ed929d0bsm335735ioj.2.2023.05.05.18.09.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 18:09:52 -0700 (PDT) From: Adam Ford To: dri-devel@lists.freedesktop.org Cc: aford@beaconembedded.com, Adam Ford , Chen-Yu Tsai , Frieder Schrempf , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , Inki Dae , Jagan Teki , Marek Szyprowski , linux-kernel@vger.kernel.org Subject: [PATCH V4 6/6] drm: bridge: samsung-dsim: Support non-burst mode Date: Fri, 5 May 2023 20:09:33 -0500 Message-Id: <20230506010933.170939-7-aford173@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230506010933.170939-1-aford173@gmail.com> References: <20230506010933.170939-1-aford173@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The high-speed clock is hard-coded to the burst-clock frequency specified in the device tree. However, when using devices like certain bridge chips without burst mode and varying resolutions and refresh rates, it may be necessary to set the high-speed clock dynamically based on the desired pixel clock for the connected device. This also removes the need to set a clock speed from the device tree for non-burst mode operation, since the pixel clock rate is the rate requested from the attached device like a bridge chip. This should have no impact for people using burst-mode and setting the burst clock rate is still required for those users. Lastly, if the burst clock is 0, and the clock is set from the pixel clock, cache the clock rate configured from of samsung_dsim_set_pll in order to properly calculate the blanking. Signed-off-by: Adam Ford Tested-by: Chen-Yu Tsai Tested-by: Frieder Schrempf Reviewed-by: Frieder Schrempf --- drivers/gpu/drm/bridge/samsung-dsim.c | 21 +++++++++++++++++---- include/drm/bridge/samsung-dsim.h | 1 + 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge= /samsung-dsim.c index 1b98c4e040b0..b79db009c98b 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -654,16 +654,28 @@ static unsigned long samsung_dsim_set_pll(struct sams= ung_dsim *dsi, reg =3D samsung_dsim_read(dsi, DSIM_STATUS_REG); } while ((reg & DSIM_PLL_STABLE) =3D=3D 0); =20 + dsi->hs_clock =3D fout; + return fout; } =20 static int samsung_dsim_enable_clock(struct samsung_dsim *dsi) { - unsigned long hs_clk, byte_clk, esc_clk; + unsigned long hs_clk, byte_clk, esc_clk, pix_clk; unsigned long esc_div; u32 reg; + struct drm_display_mode *m =3D &dsi->mode; + int bpp =3D mipi_dsi_pixel_format_to_bpp(dsi->format); + + /* m->clock is in KHz */ + pix_clk =3D m->clock * 1000; + + /* Use burst_clk_rate if available, otherwise use the pix_clk */ + if (dsi->burst_clk_rate) + hs_clk =3D samsung_dsim_set_pll(dsi, dsi->burst_clk_rate); + else + hs_clk =3D samsung_dsim_set_pll(dsi, DIV_ROUND_UP(pix_clk * bpp, dsi->la= nes)); =20 - hs_clk =3D samsung_dsim_set_pll(dsi, dsi->burst_clk_rate); if (!hs_clk) { dev_err(dsi->dev, "failed to configure DSI PLL\n"); return -EFAULT; @@ -952,7 +964,7 @@ static void samsung_dsim_set_display_mode(struct samsun= g_dsim *dsi) u32 reg; =20 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { - int byte_clk_khz =3D dsi->burst_clk_rate / 1000 / 8; + int byte_clk_khz =3D dsi->hs_clock / 1000 / 8; int hfp =3D (m->hsync_start - m->hdisplay) * byte_clk_khz / m->clock; int hbp =3D (m->htotal - m->hsync_end) * byte_clk_khz / m->clock; int hsa =3D (m->hsync_end - m->hsync_start) * byte_clk_khz / m->clock; @@ -1801,10 +1813,11 @@ static int samsung_dsim_parse_dt(struct samsung_dsi= m *dsi) return PTR_ERR(pll_clk); } =20 + /* If it doesn't exist, use pixel clock instead of failing */ ret =3D samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency", &dsi->burst_clk_rate); if (ret < 0) - return ret; + dsi->burst_clk_rate =3D 0; =20 ret =3D samsung_dsim_of_read_u32(node, "samsung,esc-clock-frequency", &dsi->esc_clk_rate); diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung= -dsim.h index 76ea8a1720cc..14176e6e9040 100644 --- a/include/drm/bridge/samsung-dsim.h +++ b/include/drm/bridge/samsung-dsim.h @@ -94,6 +94,7 @@ struct samsung_dsim { =20 u32 pll_clk_rate; u32 burst_clk_rate; + u32 hs_clock; u32 esc_clk_rate; u32 lanes; u32 mode_flags; --=20 2.39.2