From nobody Wed Feb 11 16:25:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1303EC77B7D for ; Sat, 6 May 2023 01:09:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229975AbjEFBJr (ORCPT ); Fri, 5 May 2023 21:09:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44500 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229831AbjEFBJo (ORCPT ); Fri, 5 May 2023 21:09:44 -0400 Received: from mail-io1-xd35.google.com (mail-io1-xd35.google.com [IPv6:2607:f8b0:4864:20::d35]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E20F31992 for ; Fri, 5 May 2023 18:09:43 -0700 (PDT) Received: by mail-io1-xd35.google.com with SMTP id ca18e2360f4ac-7665e607d1bso58814939f.3 for ; Fri, 05 May 2023 18:09:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683335383; x=1685927383; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dygmSIeKyL1Qr6osm0gPJv6LRBfSTNTnVZ/IpsRKoBs=; b=ECqinSGCsX0qECfmy038ywMxEDwdpTB190ZZqG5QL1XmuGVCktNau+CsIl4GIYM9OI gjkBObZL7341QL8Jaqw5EU5YVGF3SrNnjHy9COUKrlpZOd/v0pqf1FkH4+p2H5IEqF8n Oskj2y9WJrHu2HUVJz98kEQB6gj531C1fwdHDGnJuZEqSXjAmZDJ8iYbyZQkWGuwRaDD kl138V3pPgJioZe65KuRg1gUAF67H3k577ME6aURmKdw5rcTcTaiaezncdCOjg/8sWQE t0XWyJvil0UmK0Mn8FAhGv/3pU66nVnTn0er45WgJ69j0pOhMjeqKUMLaZsUYAzwXeGj 45Xw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683335383; x=1685927383; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dygmSIeKyL1Qr6osm0gPJv6LRBfSTNTnVZ/IpsRKoBs=; b=g6adONjFsqb5iCkQmS2htUaKVsopngRpq00lgH4eXEhMZ4/0HRG8KkQYQ+QWD00lAS SA2ufSwqPYTMg7PDmfTQUZvBFQNTT5GC21PVbe+e4osuuRaV/itIZ4/BNvk7/LDnUg8g Uv8fEhDgALHK1nG3H9WmIs4+N+Fs5jXFLP+LPdFa/Rt2lMbdW8H3MoRejKFTnLBb9gNS ClSTCyJYG3TVRvDw/fKmtioysxlUyD9eNn9uZjbx1tT4u9/iANAfhz2hbcw0DboI78hW aNVxnAlg8alNqHoJ9HZDXGDyHI6w5Zm7aUX/T2jtbFTEvrsU/MfHDz14U8gPSeypcF4J eEjg== X-Gm-Message-State: AC+VfDyYL4r5wrQoxiSeKjWkIJr0PSh5XADv8VTxTvtT5TVYPfGKk+oI qzRhSmVicSgy9j/smHGZmBmL6gb3iay0vQ== X-Google-Smtp-Source: ACHHUZ7oSDAQyaal9wPN8nKtlLWJ+VhEZSVCcwcoE7UQGWo/2zNH+Nt/9PDTwIT7iTtwNg6zy2iAjw== X-Received: by 2002:a5d:9c09:0:b0:763:92eb:f81e with SMTP id 9-20020a5d9c09000000b0076392ebf81emr1978405ioe.8.1683335383115; Fri, 05 May 2023 18:09:43 -0700 (PDT) Received: from aford-B741.lan ([2601:447:d001:897f:34a2:3894:45cc:c002]) by smtp.gmail.com with ESMTPSA id r11-20020a5e950b000000b00760ed929d0bsm335735ioj.2.2023.05.05.18.09.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 18:09:42 -0700 (PDT) From: Adam Ford To: dri-devel@lists.freedesktop.org Cc: aford@beaconembedded.com, Lucas Stach , Adam Ford , Chen-Yu Tsai , Frieder Schrempf , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , Inki Dae , Jagan Teki , Marek Szyprowski , Marek Vasut , linux-kernel@vger.kernel.org Subject: [PATCH V4 1/6] drm: bridge: samsung-dsim: fix blanking packet size calculation Date: Fri, 5 May 2023 20:09:28 -0500 Message-Id: <20230506010933.170939-2-aford173@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230506010933.170939-1-aford173@gmail.com> References: <20230506010933.170939-1-aford173@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Lucas Stach Scale the blanking packet sizes to match the ratio between HS clock and DPI interface clock. The controller seems to do internal scaling to the number of active lanes, so we don't take those into account. Signed-off-by: Lucas Stach Signed-off-by: Adam Ford Tested-by: Chen-Yu Tsai Tested-by: Frieder Schrempf --- drivers/gpu/drm/bridge/samsung-dsim.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge= /samsung-dsim.c index e0a402a85787..2be3b58624c3 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -874,17 +874,29 @@ static void samsung_dsim_set_display_mode(struct sams= ung_dsim *dsi) u32 reg; =20 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { + int byte_clk_khz =3D dsi->burst_clk_rate / 1000 / 8; + int hfp =3D (m->hsync_start - m->hdisplay) * byte_clk_khz / m->clock; + int hbp =3D (m->htotal - m->hsync_end) * byte_clk_khz / m->clock; + int hsa =3D (m->hsync_end - m->hsync_start) * byte_clk_khz / m->clock; + + /* remove packet overhead when possible */ + hfp =3D max(hfp - 6, 0); + hbp =3D max(hbp - 6, 0); + hsa =3D max(hsa - 6, 0); + + dev_dbg(dsi->dev, "calculated hfp: %u, hbp: %u, hsa: %u", + hfp, hbp, hsa); + reg =3D DSIM_CMD_ALLOW(0xf) | DSIM_STABLE_VFP(m->vsync_start - m->vdisplay) | DSIM_MAIN_VBP(m->vtotal - m->vsync_end); samsung_dsim_write(dsi, DSIM_MVPORCH_REG, reg); =20 - reg =3D DSIM_MAIN_HFP(m->hsync_start - m->hdisplay) - | DSIM_MAIN_HBP(m->htotal - m->hsync_end); + reg =3D DSIM_MAIN_HFP(hfp) | DSIM_MAIN_HBP(hbp); samsung_dsim_write(dsi, DSIM_MHPORCH_REG, reg); =20 reg =3D DSIM_MAIN_VSA(m->vsync_end - m->vsync_start) - | DSIM_MAIN_HSA(m->hsync_end - m->hsync_start); + | DSIM_MAIN_HSA(hsa); samsung_dsim_write(dsi, DSIM_MSYNC_REG, reg); } reg =3D DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) | --=20 2.39.2 From nobody Wed Feb 11 16:25:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C84FC7EE26 for ; Sat, 6 May 2023 01:09:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229967AbjEFBJy (ORCPT ); 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Fri, 05 May 2023 18:09:44 -0700 (PDT) From: Adam Ford To: dri-devel@lists.freedesktop.org Cc: aford@beaconembedded.com, Adam Ford , Lucas Stach , Chen-Yu Tsai , Frieder Schrempf , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , Inki Dae , Jagan Teki , Marek Szyprowski , linux-kernel@vger.kernel.org Subject: [PATCH V4 2/6] drm: bridge: samsung-dsim: Fix PMS Calculator on imx8m[mnp] Date: Fri, 5 May 2023 20:09:29 -0500 Message-Id: <20230506010933.170939-3-aford173@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230506010933.170939-1-aford173@gmail.com> References: <20230506010933.170939-1-aford173@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" According to Table 13-45 of the i.MX8M Mini Reference Manual, the min and max values for M and the frequency range for the VCO_out calculator were incorrect. This information was contradicted in other parts of the mini, nano and plus manuals. After reaching out to my NXP Rep, when confronting him about discrepencies in the Nano manual, he responded with: "Yes it is definitely wrong, the one that is part of the NOTE in MIPI_DPHY_M_PLLPMS register table against PMS_P, PMS_M and PMS_S is not correct. I will report this to Doc team, the one customer should be take into account is the Table 13-40 DPHY PLL Parameters and the Note above." These updated values also match what is used in the NXP downstream kernel. To fix this, make new variables to hold the min and max values of m and the minimum value of VCO_out, and update the PMS calculator to use these new variables instead of using hard-coded values to keep the backwards compatibility with other parts using this driver. Fixes: 4d562c70c4dc ("drm: bridge: samsung-dsim: Add i.MX8M Mini/Nano suppo= rt") Signed-off-by: Adam Ford Reviewed-by: Lucas Stach Tested-by: Chen-Yu Tsai Tested-by: Frieder Schrempf Reviewed-by: Frieder Schrempf --- drivers/gpu/drm/bridge/samsung-dsim.c | 22 ++++++++++++++++++++-- include/drm/bridge/samsung-dsim.h | 3 +++ 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge= /samsung-dsim.c index 2be3b58624c3..bf4b33d2de76 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -405,6 +405,9 @@ static const struct samsung_dsim_driver_data exynos3_ds= i_driver_data =3D { .num_bits_resol =3D 11, .pll_p_offset =3D 13, .reg_values =3D reg_values, + .m_min =3D 41, + .m_max =3D 125, + .min_freq =3D 500, }; =20 static const struct samsung_dsim_driver_data exynos4_dsi_driver_data =3D { @@ -418,6 +421,9 @@ static const struct samsung_dsim_driver_data exynos4_ds= i_driver_data =3D { .num_bits_resol =3D 11, .pll_p_offset =3D 13, .reg_values =3D reg_values, + .m_min =3D 41, + .m_max =3D 125, + .min_freq =3D 500, }; =20 static const struct samsung_dsim_driver_data exynos5_dsi_driver_data =3D { @@ -429,6 +435,9 @@ static const struct samsung_dsim_driver_data exynos5_ds= i_driver_data =3D { .num_bits_resol =3D 11, .pll_p_offset =3D 13, .reg_values =3D reg_values, + .m_min =3D 41, + .m_max =3D 125, + .min_freq =3D 500, }; =20 static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = =3D { @@ -441,6 +450,9 @@ static const struct samsung_dsim_driver_data exynos5433= _dsi_driver_data =3D { .num_bits_resol =3D 12, .pll_p_offset =3D 13, .reg_values =3D exynos5433_reg_values, + .m_min =3D 41, + .m_max =3D 125, + .min_freq =3D 500, }; =20 static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = =3D { @@ -453,6 +465,9 @@ static const struct samsung_dsim_driver_data exynos5422= _dsi_driver_data =3D { .num_bits_resol =3D 12, .pll_p_offset =3D 13, .reg_values =3D exynos5422_reg_values, + .m_min =3D 41, + .m_max =3D 125, + .min_freq =3D 500, }; =20 static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data =3D { @@ -469,6 +484,9 @@ static const struct samsung_dsim_driver_data imx8mm_dsi= _driver_data =3D { */ .pll_p_offset =3D 14, .reg_values =3D imx8mm_dsim_reg_values, + .m_min =3D 64, + .m_max =3D 1023, + .min_freq =3D 1050, }; =20 static const struct samsung_dsim_driver_data * @@ -547,12 +565,12 @@ static unsigned long samsung_dsim_pll_find_pms(struct= samsung_dsim *dsi, tmp =3D (u64)fout * (_p << _s); do_div(tmp, fin); _m =3D tmp; - if (_m < 41 || _m > 125) + if (_m < driver_data->m_min || _m > driver_data->m_max) continue; =20 tmp =3D (u64)_m * fin; do_div(tmp, _p); - if (tmp < 500 * MHZ || + if (tmp < driver_data->min_freq * MHZ || tmp > driver_data->max_freq * MHZ) continue; =20 diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung= -dsim.h index ba5484de2b30..a1a5b2b89a7a 100644 --- a/include/drm/bridge/samsung-dsim.h +++ b/include/drm/bridge/samsung-dsim.h @@ -54,11 +54,14 @@ struct samsung_dsim_driver_data { unsigned int has_freqband:1; unsigned int has_clklane_stop:1; unsigned int num_clks; + unsigned int min_freq; unsigned int max_freq; unsigned int wait_for_reset; unsigned int num_bits_resol; unsigned int pll_p_offset; const unsigned int *reg_values; + u16 m_min; + u16 m_max; }; =20 struct samsung_dsim_host_ops { --=20 2.39.2 From nobody Wed Feb 11 16:25:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B1CDC77B7D for ; Sat, 6 May 2023 01:09:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230516AbjEFBJ5 (ORCPT ); Fri, 5 May 2023 21:09:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44554 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230028AbjEFBJs (ORCPT ); Fri, 5 May 2023 21:09:48 -0400 Received: from mail-io1-xd30.google.com (mail-io1-xd30.google.com [IPv6:2607:f8b0:4864:20::d30]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A19D27299 for ; Fri, 5 May 2023 18:09:47 -0700 (PDT) Received: by mail-io1-xd30.google.com with SMTP id ca18e2360f4ac-766692684e1so62741639f.3 for ; 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charset="utf-8" Make the pll-clock-frequency optional. If it's present, use it to maintain backwards compatibility with existing hardware. If it is absent, read clock rate of "sclk_mipi" to determine the rate. Signed-off-by: Adam Ford Tested-by: Chen-Yu Tsai Tested-by: Frieder Schrempf Reviewed-by: Frieder Schrempf --- drivers/gpu/drm/bridge/samsung-dsim.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge= /samsung-dsim.c index bf4b33d2de76..2dc02a9e37c0 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -1726,12 +1726,20 @@ static int samsung_dsim_parse_dt(struct samsung_dsi= m *dsi) { struct device *dev =3D dsi->dev; struct device_node *node =3D dev->of_node; + struct clk *pll_clk; int ret; =20 ret =3D samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency", &dsi->pll_clk_rate); - if (ret < 0) - return ret; + + /* If it doesn't exist, read it from the clock instead of failing */ + if (ret < 0) { + pll_clk =3D devm_clk_get(dev, "sclk_mipi"); + if (!IS_ERR(pll_clk)) + dsi->pll_clk_rate =3D clk_get_rate(pll_clk); + else + return PTR_ERR(pll_clk); + } =20 ret =3D samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency", &dsi->burst_clk_rate); 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Fri, 05 May 2023 18:09:48 -0700 (PDT) Received: from aford-B741.lan ([2601:447:d001:897f:34a2:3894:45cc:c002]) by smtp.gmail.com with ESMTPSA id r11-20020a5e950b000000b00760ed929d0bsm335735ioj.2.2023.05.05.18.09.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 18:09:48 -0700 (PDT) From: Adam Ford To: dri-devel@lists.freedesktop.org Cc: aford@beaconembedded.com, Adam Ford , Frieder Schrempf , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , Inki Dae , Jagan Teki , Marek Szyprowski , linux-kernel@vger.kernel.org Subject: [PATCH V4 4/6] drm: bridge: samsung-dsim: Select GENERIC_PHY_MIPI_DPHY Date: Fri, 5 May 2023 20:09:31 -0500 Message-Id: <20230506010933.170939-5-aford173@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230506010933.170939-1-aford173@gmail.com> References: <20230506010933.170939-1-aford173@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In order to support variable DPHY timings, it's necessary to enable GENERIC_PHY_MIPI_DPHY so phy_mipi_dphy_get_default_config can be used to determine the nominal values for a given resolution and refresh rate. Signed-off-by: Adam Ford Tested-by: Frieder Schrempf Reviewed-by: Frieder Schrempf --- drivers/gpu/drm/bridge/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index f076a09afac0..82c68b042444 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -227,6 +227,7 @@ config DRM_SAMSUNG_DSIM select DRM_KMS_HELPER select DRM_MIPI_DSI select DRM_PANEL_BRIDGE + select GENERIC_PHY_MIPI_DPHY help The Samsung MIPI DSIM bridge controller driver. This MIPI DSIM bridge can be found it on Exynos SoCs and --=20 2.39.2 From nobody Wed Feb 11 16:25:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F7ACC77B75 for ; Sat, 6 May 2023 01:10:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230371AbjEFBKF (ORCPT ); Fri, 5 May 2023 21:10:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44688 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230122AbjEFBJx (ORCPT ); Fri, 5 May 2023 21:09:53 -0400 Received: from mail-io1-xd2a.google.com (mail-io1-xd2a.google.com [IPv6:2607:f8b0:4864:20::d2a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 846711FE6 for ; Fri, 5 May 2023 18:09:51 -0700 (PDT) Received: by mail-io1-xd2a.google.com with SMTP id ca18e2360f4ac-76664801e6fso178370039f.1 for ; Fri, 05 May 2023 18:09:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683335391; x=1685927391; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2cFA3Um2lIdvmaDIYnJ1SJljeFjsoyn/PLEYyBBm4Zo=; b=hGXrvyNo6Q/h4FDvN/Im3VWcgJh0f8K9Zwpp77Jqy/zw4wNxxA+O9ldY61gewakOk/ arM9ZJIECobX4YqhP7NM+I5JgBdxTZUb6gvfAzDoOtWaLJ3rDEPMTOdQ/TOl+YUimeOd G9albcJd01HiaiWv5fAFuIqseHQ4T0nQmRqXNUlc1qFEAx3Gz5qGD7uPq4FC7JnxsXvi dud8BhsjyRLSxmkzTumaS0nZQ6I9kxr4lheNi5qULfAE4P7rrhe7nxHJVZQquaMLMkEz U/gF54me+XJrxW2zBqTXLaTIzop9CA9855Z4rzF3LWvWuls7T7d3UzHg8atyBJ0uq6Jn 06hQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683335391; x=1685927391; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2cFA3Um2lIdvmaDIYnJ1SJljeFjsoyn/PLEYyBBm4Zo=; b=i95MAwQPLnEr86rkKQPMhc1LozEDfQhLdbjQoQEVupQlLBleog+VirjTQy1exwFNFA 1l0K2OqeUmavQQS/FY3qM1wO3f53Gnmqm/5DOpNdPF85wylTReE4cBDF5FyQRru6opgh WfYwjgXNdOHZdKPrvC/YxFmgdAnCBtCRfhUvNnQPf5YkEubN4FIpUdODx4/CoCLxg3Nz vKF5RmIiu2f7tyzPACfFRPQzqfQH3HVZF6j53hGseeE3VIc7ma+BkB4hSj/u1j6Ed9dK mLfQ1gtkNTud2zJ/ekQEjUiE4d4euUR5dcC5OYEIknnrRB0FjlASSOyL27D51W7eQ5Xp AX3Q== X-Gm-Message-State: AC+VfDxZeBABHWdbhMFtICSvsT9RAIme4Oi6AHADwuEILKvGgoShZuWo 5IucauFF2Nz+tbC6V3YjYjg= X-Google-Smtp-Source: ACHHUZ65ExZlME3j2nFJmuLKcP9QlBrZyQ0Q8lgIuopACIQsTo53d4ciEfViSfJY1EtramnsVptGog== X-Received: by 2002:a5d:9301:0:b0:752:ee32:322d with SMTP id l1-20020a5d9301000000b00752ee32322dmr1834930ion.18.1683335390713; Fri, 05 May 2023 18:09:50 -0700 (PDT) Received: from aford-B741.lan ([2601:447:d001:897f:34a2:3894:45cc:c002]) by smtp.gmail.com with ESMTPSA id r11-20020a5e950b000000b00760ed929d0bsm335735ioj.2.2023.05.05.18.09.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 18:09:50 -0700 (PDT) From: Adam Ford To: dri-devel@lists.freedesktop.org Cc: aford@beaconembedded.com, Adam Ford , Chen-Yu Tsai , Frieder Schrempf , Michael Walle , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , Inki Dae , Jagan Teki , Marek Szyprowski , Marek Vasut , linux-kernel@vger.kernel.org Subject: [PATCH V4 5/6] drm: bridge: samsung-dsim: Dynamically configure DPHY timing Date: Fri, 5 May 2023 20:09:32 -0500 Message-Id: <20230506010933.170939-6-aford173@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230506010933.170939-1-aford173@gmail.com> References: <20230506010933.170939-1-aford173@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The DPHY timings are currently hard coded. Since the input clock can be variable, the phy timings need to be variable too. Add an additional variable to the driver data to enable this feature to prevent breaking boards that don't support it. The phy_mipi_dphy_get_default_config function configures the DPHY timings in pico-seconds, and a small macro converts those timings into clock cycles based on the pixel clock rate. Signed-off-by: Adam Ford Tested-by: Chen-Yu Tsai Tested-by: Frieder Schrempf Reviewed-by: Frieder Schrempf Tested-by: Michael Walle --- drivers/gpu/drm/bridge/samsung-dsim.c | 74 ++++++++++++++++++++++++--- include/drm/bridge/samsung-dsim.h | 1 + 2 files changed, 68 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge= /samsung-dsim.c index 2dc02a9e37c0..1b98c4e040b0 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -218,6 +218,8 @@ =20 #define OLD_SCLK_MIPI_CLK_NAME "pll_clk" =20 +#define PS_TO_CYCLE(ps, hz) DIV64_U64_ROUND_CLOSEST(((ps) * (hz)), 1000000= 000000ULL) + static const char *const clk_names[5] =3D { "bus_clk", "sclk_mipi", @@ -487,6 +489,7 @@ static const struct samsung_dsim_driver_data imx8mm_dsi= _driver_data =3D { .m_min =3D 64, .m_max =3D 1023, .min_freq =3D 1050, + .dynamic_dphy =3D 1, }; =20 static const struct samsung_dsim_driver_data * @@ -698,13 +701,50 @@ static void samsung_dsim_set_phy_ctrl(struct samsung_= dsim *dsi) const struct samsung_dsim_driver_data *driver_data =3D dsi->driver_data; const unsigned int *reg_values =3D driver_data->reg_values; u32 reg; + struct drm_display_mode *m =3D &dsi->mode; + int bpp =3D mipi_dsi_pixel_format_to_bpp(dsi->format); + struct phy_configure_opts_mipi_dphy cfg; + int clk_prepare, lpx, clk_zero, clk_post, clk_trail; + int hs_exit, hs_prepare, hs_zero, hs_trail; + unsigned long long clock_in_hz =3D m->clock * 1000; =20 if (driver_data->has_freqband) return; =20 + /* The dynamic_phy has the ability to adjust PHY Timing settings */ + if (driver_data->dynamic_dphy) { + phy_mipi_dphy_get_default_config(clock_in_hz, bpp, dsi->lanes, &cfg); + + /* + * TODO: + * The tech reference manual for i.MX8M Mini/Nano/Plus + * doesn't state what the definition of the PHYTIMING + * bits are beyond their address and bit position. + * After reviewing NXP's downstream code, it appears + * that the various PHYTIMING registers take the number + * of cycles and use various dividers on them. This + * calculation does not result in an exact match to the + * downstream code, but it is very close, and it appears + * to sync at a variety of resolutions. If someone + * can get a more accurate mathematical equation needed + * for these registers, this should be updated. + */ + + lpx =3D PS_TO_CYCLE(cfg.lpx, clock_in_hz); + hs_exit =3D PS_TO_CYCLE(cfg.hs_exit, clock_in_hz); + clk_prepare =3D PS_TO_CYCLE(cfg.clk_prepare, clock_in_hz); + clk_zero =3D PS_TO_CYCLE(cfg.clk_zero, clock_in_hz); + clk_post =3D PS_TO_CYCLE(cfg.clk_post, clock_in_hz); + clk_trail =3D PS_TO_CYCLE(cfg.clk_trail, clock_in_hz); + hs_prepare =3D PS_TO_CYCLE(cfg.hs_prepare, clock_in_hz); + hs_zero =3D PS_TO_CYCLE(cfg.hs_zero, clock_in_hz); + hs_trail =3D PS_TO_CYCLE(cfg.hs_trail, clock_in_hz); + } + /* B D-PHY: D-PHY Master & Slave Analog Block control */ reg =3D reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] | reg_values[PHYCTRL_SLEW_UP]; + samsung_dsim_write(dsi, DSIM_PHYCTRL_REG, reg); =20 /* @@ -712,7 +752,11 @@ static void samsung_dsim_set_phy_ctrl(struct samsung_d= sim *dsi) * T HS-EXIT: Time that the transmitter drives LP-11 following a HS * burst */ - reg =3D reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT]; + if (driver_data->dynamic_dphy) + reg =3D DSIM_PHYTIMING_LPX(lpx) | DSIM_PHYTIMING_HS_EXIT(hs_exit); + else + reg =3D reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT]; + samsung_dsim_write(dsi, DSIM_PHYTIMING_REG, reg); =20 /* @@ -728,10 +772,17 @@ static void samsung_dsim_set_phy_ctrl(struct samsung_= dsim *dsi) * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after * the last payload clock bit of a HS transmission burst */ - reg =3D reg_values[PHYTIMING_CLK_PREPARE] | - reg_values[PHYTIMING_CLK_ZERO] | - reg_values[PHYTIMING_CLK_POST] | - reg_values[PHYTIMING_CLK_TRAIL]; + if (driver_data->dynamic_dphy) { + reg =3D DSIM_PHYTIMING1_CLK_PREPARE(clk_prepare) | + DSIM_PHYTIMING1_CLK_ZERO(clk_zero) | + DSIM_PHYTIMING1_CLK_POST(clk_post) | + DSIM_PHYTIMING1_CLK_TRAIL(clk_trail); + } else { + reg =3D reg_values[PHYTIMING_CLK_PREPARE] | + reg_values[PHYTIMING_CLK_ZERO] | + reg_values[PHYTIMING_CLK_POST] | + reg_values[PHYTIMING_CLK_TRAIL]; + } =20 samsung_dsim_write(dsi, DSIM_PHYTIMING1_REG, reg); =20 @@ -744,8 +795,17 @@ static void samsung_dsim_set_phy_ctrl(struct samsung_d= sim *dsi) * T HS-TRAIL: Time that the transmitter drives the flipped differential * state after last payload data bit of a HS transmission burst */ - reg =3D reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] | - reg_values[PHYTIMING_HS_TRAIL]; + + if (driver_data->dynamic_dphy) { + reg =3D DSIM_PHYTIMING2_HS_PREPARE(hs_prepare) | + DSIM_PHYTIMING2_HS_ZERO(hs_zero) | + DSIM_PHYTIMING2_HS_TRAIL(hs_trail); + } else { + reg =3D reg_values[PHYTIMING_HS_PREPARE] | + reg_values[PHYTIMING_HS_ZERO] | + reg_values[PHYTIMING_HS_TRAIL]; + } + samsung_dsim_write(dsi, DSIM_PHYTIMING2_REG, reg); } =20 diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung= -dsim.h index a1a5b2b89a7a..76ea8a1720cc 100644 --- a/include/drm/bridge/samsung-dsim.h +++ b/include/drm/bridge/samsung-dsim.h @@ -62,6 +62,7 @@ struct samsung_dsim_driver_data { const unsigned int *reg_values; u16 m_min; u16 m_max; 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charset="utf-8" The high-speed clock is hard-coded to the burst-clock frequency specified in the device tree. However, when using devices like certain bridge chips without burst mode and varying resolutions and refresh rates, it may be necessary to set the high-speed clock dynamically based on the desired pixel clock for the connected device. This also removes the need to set a clock speed from the device tree for non-burst mode operation, since the pixel clock rate is the rate requested from the attached device like a bridge chip. This should have no impact for people using burst-mode and setting the burst clock rate is still required for those users. Lastly, if the burst clock is 0, and the clock is set from the pixel clock, cache the clock rate configured from of samsung_dsim_set_pll in order to properly calculate the blanking. Signed-off-by: Adam Ford Tested-by: Chen-Yu Tsai Tested-by: Frieder Schrempf Reviewed-by: Frieder Schrempf --- drivers/gpu/drm/bridge/samsung-dsim.c | 21 +++++++++++++++++---- include/drm/bridge/samsung-dsim.h | 1 + 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge= /samsung-dsim.c index 1b98c4e040b0..b79db009c98b 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -654,16 +654,28 @@ static unsigned long samsung_dsim_set_pll(struct sams= ung_dsim *dsi, reg =3D samsung_dsim_read(dsi, DSIM_STATUS_REG); } while ((reg & DSIM_PLL_STABLE) =3D=3D 0); =20 + dsi->hs_clock =3D fout; + return fout; } =20 static int samsung_dsim_enable_clock(struct samsung_dsim *dsi) { - unsigned long hs_clk, byte_clk, esc_clk; + unsigned long hs_clk, byte_clk, esc_clk, pix_clk; unsigned long esc_div; u32 reg; + struct drm_display_mode *m =3D &dsi->mode; + int bpp =3D mipi_dsi_pixel_format_to_bpp(dsi->format); + + /* m->clock is in KHz */ + pix_clk =3D m->clock * 1000; + + /* Use burst_clk_rate if available, otherwise use the pix_clk */ + if (dsi->burst_clk_rate) + hs_clk =3D samsung_dsim_set_pll(dsi, dsi->burst_clk_rate); + else + hs_clk =3D samsung_dsim_set_pll(dsi, DIV_ROUND_UP(pix_clk * bpp, dsi->la= nes)); =20 - hs_clk =3D samsung_dsim_set_pll(dsi, dsi->burst_clk_rate); if (!hs_clk) { dev_err(dsi->dev, "failed to configure DSI PLL\n"); return -EFAULT; @@ -952,7 +964,7 @@ static void samsung_dsim_set_display_mode(struct samsun= g_dsim *dsi) u32 reg; =20 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { - int byte_clk_khz =3D dsi->burst_clk_rate / 1000 / 8; + int byte_clk_khz =3D dsi->hs_clock / 1000 / 8; int hfp =3D (m->hsync_start - m->hdisplay) * byte_clk_khz / m->clock; int hbp =3D (m->htotal - m->hsync_end) * byte_clk_khz / m->clock; int hsa =3D (m->hsync_end - m->hsync_start) * byte_clk_khz / m->clock; @@ -1801,10 +1813,11 @@ static int samsung_dsim_parse_dt(struct samsung_dsi= m *dsi) return PTR_ERR(pll_clk); } =20 + /* If it doesn't exist, use pixel clock instead of failing */ ret =3D samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency", &dsi->burst_clk_rate); if (ret < 0) - return ret; + dsi->burst_clk_rate =3D 0; =20 ret =3D samsung_dsim_of_read_u32(node, "samsung,esc-clock-frequency", &dsi->esc_clk_rate); diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung= -dsim.h index 76ea8a1720cc..14176e6e9040 100644 --- a/include/drm/bridge/samsung-dsim.h +++ b/include/drm/bridge/samsung-dsim.h @@ -94,6 +94,7 @@ struct samsung_dsim { =20 u32 pll_clk_rate; u32 burst_clk_rate; + u32 hs_clock; u32 esc_clk_rate; u32 lanes; u32 mode_flags; --=20 2.39.2