From nobody Thu Dec 18 08:54:17 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13314C77B7C for ; Fri, 5 May 2023 05:21:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230311AbjEEFVj (ORCPT ); Fri, 5 May 2023 01:21:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229588AbjEEFVd (ORCPT ); Fri, 5 May 2023 01:21:33 -0400 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::228]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 622B911B7A; Thu, 4 May 2023 22:21:31 -0700 (PDT) Received: (Authenticated sender: me@crly.cz) by mail.gandi.net (Postfix) with ESMTPSA id 1156A1BF206; Fri, 5 May 2023 05:21:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crly.cz; s=gm1; t=1683264089; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BTishZVtaZFYmhTS+E1QiU0pRfLyhtvgErYcS+oT66w=; b=GVdpRfQ/+vgBYi++UmvBh4Y77lLLjV4XQnUR02Wa1uGtdEboJRUvP2SlRJqgIndYgUV7bf A2HTns2I7UbKS8wBlemmnZEVKfAQDxFLWchJe5CBss/g2qHVcGZjEtFngnl/tApm5H8A7l fMbdVIExXmZwm74jiCf44UO/+ppvgyZWEhUYttjca9+sE05nsLhCUAX/tChhhoMZSOUlmk LoG9YlW1mwJ9vQ4thicJrxVG/+NP+VBSlzEwpgc9VNK0+58Wfufl+OGVUnyzqIysybzLW5 0ddVdLLGX5DO5ASd1DlaX3OvGdxNMjBUEteikOQ/aIIu5ZpKtgOV0NtS3LVIqQ== From: Roman Beranek To: Maxime Ripard , David Airlie , Daniel Vetter , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski Cc: Frank Oltmanns , Icenowy Zheng , Ondrej Jirman , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 1/4] clk: sunxi-ng: a64: force select PLL_MIPI in TCON0 mux Date: Fri, 5 May 2023 07:21:07 +0200 Message-Id: <20230505052110.67514-2-me@crly.cz> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20230505052110.67514-1-me@crly.cz> References: <20230505052110.67514-1-me@crly.cz> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" TCON0's source clock can be fed from either PLL_MIPI, or PLL_VIDEO0(2X), however MIPI DSI output only seems to work when PLL_MIPI is selected and thus the choice must be hardcoded in. Currently, this driver can't propagate rate change from N-K-M clocks (such as PLL_MIPI) upwards. This prevents PLL_VIDEO0 from participating in setting of the TCON0 data clock rate, limiting the precision with which a target pixel clock can be matched. For outputs with fixed TCON0 divider, that is DSI and LVDS, the dotclock can deviate up to 8% off target. Signed-off-by: Roman Beranek Acked-by: Maxime Ripard Reviewed-by: Jernej Skrabec Tested-by: Frank Oltmanns --- drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/c= cu-sun50i-a64.c index 41519185600a..eb36f8f77d55 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c @@ -528,11 +528,18 @@ static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_par= ents, 0x104, 0, 4, 24, 3, BIT(31), CLK_SET_RATE_PARENT); =20 +/* + * DSI output seems to work only when PLL_MIPI selected. Set it and prevent + * the mux from reparenting. + */ +#define SUN50I_A64_TCON0_CLK_REG 0x118 + static const char * const tcon0_parents[] =3D { "pll-mipi", "pll-video0-2x= " }; static const u8 tcon0_table[] =3D { 0, 2, }; static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents, tcon0_table, 0x118, 24, 3, BIT(31), - CLK_SET_RATE_PARENT); + CLK_SET_RATE_PARENT | + CLK_SET_RATE_NO_REPARENT); =20 static const char * const tcon1_parents[] =3D { "pll-video0", "pll-video1"= }; static const u8 tcon1_table[] =3D { 0, 2, }; @@ -953,6 +960,11 @@ static int sun50i_a64_ccu_probe(struct platform_device= *pdev) =20 writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG); =20 + /* Set PLL MIPI as parent for TCON0 */ + val =3D readl(reg + SUN50I_A64_TCON0_CLK_REG); + val &=3D ~GENMASK(26, 24); + writel(val | (0 << 24), reg + SUN50I_A64_TCON0_CLK_REG); + ret =3D devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_a64_ccu_desc); if (ret) return ret; --=20 2.32.0 (Apple Git-132) From nobody Thu Dec 18 08:54:17 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F4112C7EE22 for ; Fri, 5 May 2023 05:21:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230194AbjEEFVv (ORCPT ); Fri, 5 May 2023 01:21:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230296AbjEEFVi (ORCPT ); Fri, 5 May 2023 01:21:38 -0400 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 41959199D; Thu, 4 May 2023 22:21:34 -0700 (PDT) Received: (Authenticated sender: me@crly.cz) by mail.gandi.net (Postfix) with ESMTPSA id 1D8731BF209; Fri, 5 May 2023 05:21:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crly.cz; s=gm1; t=1683264093; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/oot7a6jjkHYrhgmWeZp0eSKNEBceRdK+riq6iDjoiY=; b=LochVUyvd29nALvDfn6vrXXHq8NtkMhpSDMjMhWh8muXxnY0iuJCA7KVuy3wPIENCLmP3N +lvbJmrzSwmyTeS5AaNyYHEsB49wA7QGY/c/CEgmx7UZCjRIGdX9kg6/e4lGcR2h09P55p 43o+qi54mr4oBU8/hTWMPBwQD39D9UFqqK61RNBDdtFLjUAm9AgZfkpkrcGLiyJH6jwugb EimAaRpvYJ8/3G396KPd31KsYBZYFc6blToQOVp6ad5lvxRAkASW/rpYr0bcb+A3uOGQeX in4wnSIVtSphv98NnFa/DZ1Mfbe6CJ0yPDlY/00Seah2KihwxL3uRRZ3c6vaVQ== From: Roman Beranek To: Maxime Ripard , David Airlie , Daniel Vetter , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski Cc: Frank Oltmanns , Icenowy Zheng , Ondrej Jirman , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/4] ARM: dts: sunxi: rename tcon's clock output Date: Fri, 5 May 2023 07:21:08 +0200 Message-Id: <20230505052110.67514-3-me@crly.cz> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20230505052110.67514-1-me@crly.cz> References: <20230505052110.67514-1-me@crly.cz> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" While the rate of TCON0's DCLK matches dotclock for parallel and LVDS outputs, this doesn't hold for DSI. According manuals from Allwinner, DCLK is an abbreviation of Data Clock, not dotclock, so go with that instead. Signed-off-by: Roman Beranek Acked-by: Jernej Skrabec Acked-by: Maxime Ripard Tested-by: Frank Oltmanns --- arch/arm/boot/dts/sun5i.dtsi | 2 +- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +- arch/arm/boot/dts/sun8i-a83t.dtsi | 2 +- arch/arm/boot/dts/sun8i-v3s.dtsi | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 250d6b87ab4d..2f901a013676 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -286,7 +286,7 @@ tcon0: lcd-controller@1c0c000 { clock-names =3D "ahb", "tcon-ch0", "tcon-ch1"; - clock-output-names =3D "tcon-pixel-clock"; + clock-output-names =3D "tcon-data-clock"; #clock-cells =3D <0>; status =3D "disabled"; =20 diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i= -a23-a33.dtsi index f630ab55bb6a..ddc87cc15e51 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -190,7 +190,7 @@ tcon0: lcd-controller@1c0c000 { clock-names =3D "ahb", "tcon-ch0", "lvds-alt"; - clock-output-names =3D "tcon-pixel-clock"; + clock-output-names =3D "tcon-data-clock"; #clock-cells =3D <0>; resets =3D <&ccu RST_BUS_LCD>, <&ccu RST_BUS_LVDS>; diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a8= 3t.dtsi index 82fdb04122ca..94eb3bfc989e 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -456,7 +456,7 @@ tcon0: lcd-controller@1c0c000 { interrupts =3D ; clocks =3D <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; clock-names =3D "ahb", "tcon-ch0"; - clock-output-names =3D "tcon-pixel-clock"; + clock-output-names =3D "tcon-data-clock"; #clock-cells =3D <0>; resets =3D <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; reset-names =3D "lcd", "lvds"; diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s= .dtsi index db194c606fdc..ab2a0e1235e4 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -191,7 +191,7 @@ tcon0: lcd-controller@1c0c000 { <&ccu CLK_TCON0>; clock-names =3D "ahb", "tcon-ch0"; - clock-output-names =3D "tcon-pixel-clock"; + clock-output-names =3D "tcon-data-clock"; #clock-cells =3D <0>; resets =3D <&ccu RST_BUS_TCON0>; reset-names =3D "lcd"; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boo= t/dts/allwinner/sun50i-a64.dtsi index 62f45f71ec65..e3b17575699c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -407,7 +407,7 @@ tcon0: lcd-controller@1c0c000 { interrupts =3D ; clocks =3D <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; clock-names =3D "ahb", "tcon-ch0"; - clock-output-names =3D "tcon-pixel-clock"; + clock-output-names =3D "tcon-data-clock"; #clock-cells =3D <0>; resets =3D <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; reset-names =3D "lcd", "lvds"; --=20 2.32.0 (Apple Git-132) From nobody Thu Dec 18 08:54:17 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31590C77B75 for ; Fri, 5 May 2023 05:21:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230385AbjEEFVy (ORCPT ); Fri, 5 May 2023 01:21:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53996 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230332AbjEEFVn (ORCPT ); Fri, 5 May 2023 01:21:43 -0400 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::228]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A639150DF; Thu, 4 May 2023 22:21:37 -0700 (PDT) Received: (Authenticated sender: me@crly.cz) by mail.gandi.net (Postfix) with ESMTPSA id 2CD8E1BF20C; Fri, 5 May 2023 05:21:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crly.cz; s=gm1; t=1683264096; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=S31SO6KDsoAFCVqHr2y4SszRxMON8Fz0nC5PH2vEKG4=; b=UnPM7SnFVStghWutpcf4hvBzU3LYMgQUjXbbWf1gInkUfhbufwCME6gRJjJNdHHyxvjwQH srRdc0HcI59+WIyw7lYsIuwzWPrHcUNtRAHYxCSgOu/KMHv59fxCwJs01lHIN4N3yxgm8i cMWk0AvthS+LafJ1DmiQ0e7MNDln4zyNYOYODIK6uq9Elb+bh6/EH3zFkP3NXMPeUG2VO/ O/TKMCDhzKatHr+hZ7qI3w/pJEgM73hns5rkVm3TEq9EMastRfLlObcqy0Kxfa59BLx/e4 x+3LOJIPgOt2iP9UA/8RlnJBrA9fWT10KyWkBN5QkUzNOUOwjrdaZUHTaBiZww== From: Roman Beranek To: Maxime Ripard , David Airlie , Daniel Vetter , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski Cc: Frank Oltmanns , Icenowy Zheng , Ondrej Jirman , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 3/4] drm: sun4i: rename sun4i_dotclock to sun4i_tcon_dclk Date: Fri, 5 May 2023 07:21:09 +0200 Message-Id: <20230505052110.67514-4-me@crly.cz> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20230505052110.67514-1-me@crly.cz> References: <20230505052110.67514-1-me@crly.cz> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" While the rate of TCON0's DCLK matches dotclock for parallel and LVDS outputs, this doesn't hold for DSI. The 'D' in DCLK actually stands for 'Data' according to Allwinner's manuals. The clock is mostly referred to as dclk throughout this driver already anyway, so stick with that. Signed-off-by: Roman Beranek Tested-by: Frank Oltmanns --- drivers/gpu/drm/sun4i/Makefile | 2 +- drivers/gpu/drm/sun4i/sun4i_tcon.c | 10 +++++----- .../drm/sun4i/{sun4i_dotclock.c =3D> sun4i_tcon_dclk.c} | 2 +- .../drm/sun4i/{sun4i_dotclock.h =3D> sun4i_tcon_dclk.h} | 0 4 files changed, 7 insertions(+), 7 deletions(-) rename drivers/gpu/drm/sun4i/{sun4i_dotclock.c =3D> sun4i_tcon_dclk.c} (99= %) rename drivers/gpu/drm/sun4i/{sun4i_dotclock.h =3D> sun4i_tcon_dclk.h} (10= 0%) diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile index 0d04f2447b01..bad7497a0d11 100644 --- a/drivers/gpu/drm/sun4i/Makefile +++ b/drivers/gpu/drm/sun4i/Makefile @@ -19,7 +19,7 @@ sun8i-mixer-y +=3D sun8i_mixer.o sun8i_ui_layer.o \ sun8i_vi_scaler.o sun8i_csc.o =20 sun4i-tcon-y +=3D sun4i_crtc.o -sun4i-tcon-y +=3D sun4i_dotclock.o +sun4i-tcon-y +=3D sun4i_tcon_dclk.o sun4i-tcon-y +=3D sun4i_lvds.o sun4i-tcon-y +=3D sun4i_tcon.o sun4i-tcon-y +=3D sun4i_rgb.o diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun= 4i_tcon.c index 523a6d787921..eec26b1faa4b 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -31,12 +31,12 @@ #include =20 #include "sun4i_crtc.h" -#include "sun4i_dotclock.h" #include "sun4i_drv.h" #include "sun4i_lvds.h" #include "sun4i_rgb.h" #include "sun4i_tcon.h" #include "sun6i_mipi_dsi.h" +#include "sun4i_tcon_dclk.h" #include "sun8i_tcon_top.h" #include "sunxi_engine.h" =20 @@ -1237,14 +1237,14 @@ static int sun4i_tcon_bind(struct device *dev, stru= ct device *master, ret =3D sun4i_tcon_init_irq(dev, tcon); if (ret) { dev_err(dev, "Couldn't init our TCON interrupts\n"); - goto err_free_dotclock; + goto err_free_dclk; } =20 tcon->crtc =3D sun4i_crtc_init(drm, engine, tcon); if (IS_ERR(tcon->crtc)) { dev_err(dev, "Couldn't create our CRTC\n"); ret =3D PTR_ERR(tcon->crtc); - goto err_free_dotclock; + goto err_free_dclk; } =20 if (tcon->quirks->has_channel_0) { @@ -1264,7 +1264,7 @@ static int sun4i_tcon_bind(struct device *dev, struct= device *master, of_node_put(remote); =20 if (ret < 0) - goto err_free_dotclock; + goto err_free_dclk; } =20 if (tcon->quirks->needs_de_be_mux) { @@ -1290,7 +1290,7 @@ static int sun4i_tcon_bind(struct device *dev, struct= device *master, =20 return 0; =20 -err_free_dotclock: +err_free_dclk: if (tcon->quirks->has_channel_0) sun4i_dclk_free(tcon); err_free_clocks: diff --git a/drivers/gpu/drm/sun4i/sun4i_dotclock.c b/drivers/gpu/drm/sun4i= /sun4i_tcon_dclk.c similarity index 99% rename from drivers/gpu/drm/sun4i/sun4i_dotclock.c rename to drivers/gpu/drm/sun4i/sun4i_tcon_dclk.c index 417ade3d2565..03d7de1911cd 100644 --- a/drivers/gpu/drm/sun4i/sun4i_dotclock.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon_dclk.c @@ -10,7 +10,7 @@ #include =20 #include "sun4i_tcon.h" -#include "sun4i_dotclock.h" +#include "sun4i_tcon_dclk.h" =20 struct sun4i_dclk { struct clk_hw hw; diff --git a/drivers/gpu/drm/sun4i/sun4i_dotclock.h b/drivers/gpu/drm/sun4i= /sun4i_tcon_dclk.h similarity index 100% rename from drivers/gpu/drm/sun4i/sun4i_dotclock.h rename to drivers/gpu/drm/sun4i/sun4i_tcon_dclk.h --=20 2.32.0 (Apple Git-132) From nobody Thu Dec 18 08:54:17 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60E4DC77B75 for ; Fri, 5 May 2023 05:22:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230365AbjEEFV7 (ORCPT ); Fri, 5 May 2023 01:21:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230350AbjEEFVr (ORCPT ); Fri, 5 May 2023 01:21:47 -0400 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::228]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC71314E77; Thu, 4 May 2023 22:21:40 -0700 (PDT) Received: (Authenticated sender: me@crly.cz) by mail.gandi.net (Postfix) with ESMTPSA id 3AE901BF208; Fri, 5 May 2023 05:21:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crly.cz; s=gm1; t=1683264099; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=MA7Dv2Qs3SnMl09WxFtijC9xKkxYGB+hhEONwk+AOpE=; b=KRxGZnPIwFPcXwsh95D8QJGiTws0jL1SgdggYOeNdxHN2tLFu4HCSu5X7f9udRmDknwQ8j PGD3r6spEUAp6+4VkbtTk7vhSjD7fZvmpXSRF7Y+wJP+eXOM9OtiXUA2ee6EvjVeOcSC60 T8p8Np2hXSMdk6AggOc+AMiOUamTC5KZHkVw4Z3VjNoCVMlak3YJEt9rkw2jSAHZCMjgdy pxMaby2+q96VF3MvfXHhEHaJ07BbQ2DTFqFCz+3zkZg/7uf5LFYlnCTKurKb1dBHdh5Ltd NBpVVWhjcdsQvg8+ysJszRpAQdvIX8kFInl1XnOGZ0UAebddt4DaHhQFQrvffQ== From: Roman Beranek To: Maxime Ripard , David Airlie , Daniel Vetter , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski Cc: Frank Oltmanns , Icenowy Zheng , Ondrej Jirman , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 4/4] drm: sun4i: calculate proper DCLK rate for DSI Date: Fri, 5 May 2023 07:21:10 +0200 Message-Id: <20230505052110.67514-5-me@crly.cz> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20230505052110.67514-1-me@crly.cz> References: <20230505052110.67514-1-me@crly.cz> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In DSI mode, TCON0's data clock is required to run at 1/4 the per-lane bit rate. Signed-off-by: Roman Beranek Tested-by: Frank Oltmanns --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 36 +++++++++++++++++------------- 1 file changed, 21 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun= 4i_tcon.c index eec26b1faa4b..b263de7a8237 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -291,18 +291,6 @@ static int sun4i_tcon_get_clk_delay(const struct drm_d= isplay_mode *mode, return delay; } =20 -static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon, - const struct drm_display_mode *mode) -{ - /* Configure the dot clock */ - clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); - - /* Set the resolution */ - regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, - SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) | - SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); -} - static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon, const struct drm_connector *connector) { @@ -367,10 +355,18 @@ static void sun4i_tcon0_mode_set_cpu(struct sun4i_tco= n *tcon, u32 block_space, start_delay; u32 tcon_div; =20 + /* + * dclk is required to run at 1/4 the DSI per-lane bit rate. + */ tcon->dclk_min_div =3D SUN6I_DSI_TCON_DIV; tcon->dclk_max_div =3D SUN6I_DSI_TCON_DIV; + clk_set_rate(tcon->dclk, mode->crtc_clock * 1000 * (bpp / lanes) + / SUN6I_DSI_TCON_DIV); =20 - sun4i_tcon0_mode_set_common(tcon, mode); + /* Set the resolution */ + regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, + SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) | + SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); =20 /* Set dithering if needed */ sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); @@ -438,7 +434,12 @@ static void sun4i_tcon0_mode_set_lvds(struct sun4i_tco= n *tcon, =20 tcon->dclk_min_div =3D 7; tcon->dclk_max_div =3D 7; - sun4i_tcon0_mode_set_common(tcon, mode); + clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); + + /* Set the resolution */ + regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, + SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) | + SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); =20 /* Set dithering if needed */ sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); @@ -515,7 +516,12 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon= *tcon, =20 tcon->dclk_min_div =3D tcon->quirks->dclk_min_div; tcon->dclk_max_div =3D 127; - sun4i_tcon0_mode_set_common(tcon, mode); + clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); + + /* Set the resolution */ + regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, + SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) | + SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); =20 /* Set dithering if needed */ sun4i_tcon0_mode_set_dithering(tcon, connector); --=20 2.32.0 (Apple Git-132)