From nobody Thu Dec 18 21:33:40 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CBAAC77B7C for ; Thu, 4 May 2023 20:40:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231361AbjEDUjv (ORCPT ); Thu, 4 May 2023 16:39:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54072 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231284AbjEDUjX (ORCPT ); Thu, 4 May 2023 16:39:23 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3CAF714E6A; Thu, 4 May 2023 13:34:02 -0700 (PDT) Received: from localhost (unknown [188.27.34.213]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id 9FCAF6605704; Thu, 4 May 2023 21:07:20 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1683230840; bh=AwLdMI2guFpG/vA2CRiv4Le+UC8eSUAMFfhScPFNJkY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DaHfg5Laf5SSLYlmXIzZS2f4+r3H37WatrEOUsZ1pCFtSD1FX2E00sbD389SjlD6W WrXqiYlFm2xNab0Te++19xgXRzeTDfcsQT464YM6ZdDct9Fp9GL2FKRnmJpLrI2pAa x36YbyILRzPo69Za8Om4Xl1KCDw4UXrZkvg5KukdpzyjL0CVaFOXaYNTMX7am7nEys JxTqbHpaMXayhcpXhxHoblvOSWfth1Ri8YSJZqC1wlC2EMuEe+D1pcDHxS7MGaBk5v 9He++Q3njHS2zQpUBiqePbHqMS6+touTJ9jyotgO3HmkvEI/Vd+iaKCn3bQq4r2tcZ wXPU5sAugpgTQ== From: Cristian Ciocaltea To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Philipp Zabel , Sebastian Reichel , Shreeya Patel , Kever Yang , Finley Xiao , Vincent Legoll Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 8/8] arm64: dts: rockchip: Add rk3588 OTP node Date: Thu, 4 May 2023 23:06:48 +0300 Message-Id: <20230504200648.1119866-9-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230504200648.1119866-1-cristian.ciocaltea@collabora.com> References: <20230504200648.1119866-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add DT node for Rockchip RK3588/RK3588S OTP memory. Co-developed-by: Finley Xiao Signed-off-by: Finley Xiao Signed-off-by: Cristian Ciocaltea Tested-by: Vincent Legoll --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 54 +++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dt= s/rockchip/rk3588s.dtsi index 767084a1ec43..d842988af418 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -1822,6 +1822,60 @@ spi4: spi@fecb0000 { status =3D "disabled"; }; =20 + otp: efuse@fecc0000 { + compatible =3D "rockchip,rk3588-otp"; + reg =3D <0x0 0xfecc0000 0x0 0x400>; + clocks =3D <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, + <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; + clock-names =3D "otp", "apb_pclk", "phy", "arb"; + resets =3D <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, + <&cru SRST_OTPC_ARB>; + reset-names =3D "otp", "apb", "arb"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + cpu_code: cpu-code@2 { + reg =3D <0x02 0x2>; + }; + + otp_id: id@7 { + reg =3D <0x07 0x10>; + }; + + otp_cpu_version: cpu-version@1c { + reg =3D <0x1c 0x1>; + bits =3D <3 3>; + }; + + cpub0_leakage: cpu-leakage@17 { + reg =3D <0x17 0x1>; + }; + + cpub1_leakage: cpu-leakage@18 { + reg =3D <0x18 0x1>; + }; + + cpul_leakage: cpu-leakage@19 { + reg =3D <0x19 0x1>; + }; + + log_leakage: log-leakage@1a { + reg =3D <0x1a 0x1>; + }; + + gpu_leakage: gpu-leakage@1b { + reg =3D <0x1b 0x1>; + }; + + npu_leakage: npu-leakage@28 { + reg =3D <0x28 0x1>; + }; + + codec_leakage: codec-leakage@29 { + reg =3D <0x29 0x1>; + }; + }; + dmac2: dma-controller@fed10000 { compatible =3D "arm,pl330", "arm,primecell"; reg =3D <0x0 0xfed10000 0x0 0x4000>; --=20 2.40.0