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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT115.mail.protection.outlook.com (10.13.173.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6363.26 via Frontend Transport; Thu, 4 May 2023 11:01:30 +0000 Received: from BLR-5CG113396H.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 4 May 2023 06:00:35 -0500 From: Ravi Bangoria To: CC: , , , , , , , , , , , , , , , , Subject: [PATCH v4 1/4] perf/core: Rework forwarding of {task|cpu}-clock events Date: Thu, 4 May 2023 16:30:00 +0530 Message-ID: <20230504110003.2548-2-ravi.bangoria@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230504110003.2548-1-ravi.bangoria@amd.com> References: <20230504110003.2548-1-ravi.bangoria@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT115:EE_|SA1PR12MB7409:EE_ X-MS-Office365-Filtering-Correlation-Id: 573ad5bb-c92b-49b9-9e73-08db4c8eea3d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 May 2023 11:01:30.1249 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 573ad5bb-c92b-49b9-9e73-08db4c8eea3d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT115.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7409 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently, PERF_TYPE_SOFTWARE is treated specially since task-clock and cpu-clock events are interfaced through it but internally gets forwarded to their own pmus. Rework this by overwriting event->attr.type in perf_swevent_init() which will cause perf_init_event() to retry with updated type and event will automatically get forwarded to right pmu. With the change, SW pmu no longer needs to be treated specially and can be included in 'pmu_idr' list. Suggested-by: Peter Zijlstra Signed-off-by: Ravi Bangoria --- include/linux/perf_event.h | 10 +++++ kernel/events/core.c | 77 ++++++++++++++++++++------------------ 2 files changed, 51 insertions(+), 36 deletions(-) diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index d5628a7b5eaa..5c8a748f51ac 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -295,6 +295,8 @@ struct perf_event_pmu_context; =20 struct perf_output_handle; =20 +#define PMU_NULL_DEV ((void *)(~0)) + /** * struct pmu - generic performance monitoring unit */ @@ -827,6 +829,14 @@ struct perf_event { void *security; #endif struct list_head sb_list; + + /* + * Certain events gets forwarded to another pmu internally by over- + * writing kernel copy of event->attr.type without user being aware + * of it. event->orig_type contains original 'type' requested by + * user. + */ + __u32 orig_type; #endif /* CONFIG_PERF_EVENTS */ }; =20 diff --git a/kernel/events/core.c b/kernel/events/core.c index 435815d3be3f..0695bb9fbbb6 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -6647,7 +6647,7 @@ static void perf_sigtrap(struct perf_event *event) return; =20 send_sig_perf((void __user *)event->pending_addr, - event->attr.type, event->attr.sig_data); + event->orig_type, event->attr.sig_data); } =20 /* @@ -9951,6 +9951,9 @@ static void sw_perf_event_destroy(struct perf_event *= event) swevent_hlist_put(); } =20 +static struct pmu perf_cpu_clock; /* fwd declaration */ +static struct pmu perf_task_clock; + static int perf_swevent_init(struct perf_event *event) { u64 event_id =3D event->attr.config; @@ -9966,7 +9969,10 @@ static int perf_swevent_init(struct perf_event *even= t) =20 switch (event_id) { case PERF_COUNT_SW_CPU_CLOCK: + event->attr.type =3D perf_cpu_clock.type; + return -ENOENT; case PERF_COUNT_SW_TASK_CLOCK: + event->attr.type =3D perf_task_clock.type; return -ENOENT; =20 default: @@ -11086,7 +11092,7 @@ static void cpu_clock_event_read(struct perf_event = *event) =20 static int cpu_clock_event_init(struct perf_event *event) { - if (event->attr.type !=3D PERF_TYPE_SOFTWARE) + if (event->attr.type !=3D perf_cpu_clock.type) return -ENOENT; =20 if (event->attr.config !=3D PERF_COUNT_SW_CPU_CLOCK) @@ -11107,6 +11113,7 @@ static struct pmu perf_cpu_clock =3D { .task_ctx_nr =3D perf_sw_context, =20 .capabilities =3D PERF_PMU_CAP_NO_NMI, + .dev =3D PMU_NULL_DEV, =20 .event_init =3D cpu_clock_event_init, .add =3D cpu_clock_event_add, @@ -11167,7 +11174,7 @@ static void task_clock_event_read(struct perf_event= *event) =20 static int task_clock_event_init(struct perf_event *event) { - if (event->attr.type !=3D PERF_TYPE_SOFTWARE) + if (event->attr.type !=3D perf_task_clock.type) return -ENOENT; =20 if (event->attr.config !=3D PERF_COUNT_SW_TASK_CLOCK) @@ -11188,6 +11195,7 @@ static struct pmu perf_task_clock =3D { .task_ctx_nr =3D perf_sw_context, =20 .capabilities =3D PERF_PMU_CAP_NO_NMI, + .dev =3D PMU_NULL_DEV, =20 .event_init =3D task_clock_event_init, .add =3D task_clock_event_add, @@ -11415,31 +11423,31 @@ int perf_pmu_register(struct pmu *pmu, const char= *name, int type) goto unlock; =20 pmu->type =3D -1; - if (!name) - goto skip_type; + if (WARN_ONCE(!name, "Can not register anonymous pmu.\n")) { + ret =3D -EINVAL; + goto free_pdc; + } + pmu->name =3D name; =20 - if (type !=3D PERF_TYPE_SOFTWARE) { - if (type >=3D 0) - max =3D type; + if (type >=3D 0) + max =3D type; =20 - ret =3D idr_alloc(&pmu_idr, pmu, max, 0, GFP_KERNEL); - if (ret < 0) - goto free_pdc; + ret =3D idr_alloc(&pmu_idr, pmu, max, 0, GFP_KERNEL); + if (ret < 0) + goto free_pdc; =20 - WARN_ON(type >=3D 0 && ret !=3D type); + WARN_ON(type >=3D 0 && ret !=3D type); =20 - type =3D ret; - } + type =3D ret; pmu->type =3D type; =20 - if (pmu_bus_running) { + if (pmu_bus_running && !pmu->dev) { ret =3D pmu_dev_alloc(pmu); if (ret) goto free_idr; } =20 -skip_type: ret =3D -ENOMEM; pmu->cpu_pmu_context =3D alloc_percpu(struct perf_cpu_pmu_context); if (!pmu->cpu_pmu_context) @@ -11481,16 +11489,7 @@ int perf_pmu_register(struct pmu *pmu, const char = *name, int type) if (!pmu->event_idx) pmu->event_idx =3D perf_event_idx_default; =20 - /* - * Ensure the TYPE_SOFTWARE PMUs are at the head of the list, - * since these cannot be in the IDR. This way the linear search - * is fast, provided a valid software event is provided. - */ - if (type =3D=3D PERF_TYPE_SOFTWARE || !name) - list_add_rcu(&pmu->entry, &pmus); - else - list_add_tail_rcu(&pmu->entry, &pmus); - + list_add_rcu(&pmu->entry, &pmus); atomic_set(&pmu->exclusive_cnt, 0); ret =3D 0; unlock: @@ -11499,12 +11498,13 @@ int perf_pmu_register(struct pmu *pmu, const char= *name, int type) return ret; =20 free_dev: - device_del(pmu->dev); - put_device(pmu->dev); + if (pmu->dev && pmu->dev !=3D PMU_NULL_DEV) { + device_del(pmu->dev); + put_device(pmu->dev); + } =20 free_idr: - if (pmu->type !=3D PERF_TYPE_SOFTWARE) - idr_remove(&pmu_idr, pmu->type); + idr_remove(&pmu_idr, pmu->type); =20 free_pdc: free_percpu(pmu->pmu_disable_count); @@ -11525,9 +11525,8 @@ void perf_pmu_unregister(struct pmu *pmu) synchronize_rcu(); =20 free_percpu(pmu->pmu_disable_count); - if (pmu->type !=3D PERF_TYPE_SOFTWARE) - idr_remove(&pmu_idr, pmu->type); - if (pmu_bus_running) { + idr_remove(&pmu_idr, pmu->type); + if (pmu_bus_running && pmu->dev && pmu->dev !=3D PMU_NULL_DEV) { if (pmu->nr_addr_filters) device_remove_file(pmu->dev, &dev_attr_nr_addr_filters); device_del(pmu->dev); @@ -11601,6 +11600,12 @@ static struct pmu *perf_init_event(struct perf_eve= nt *event) =20 idx =3D srcu_read_lock(&pmus_srcu); =20 + /* + * Save original type before calling pmu->event_init() since certain + * pmus overwrites event->attr.type to forward event to another pmu. + */ + event->orig_type =3D event->attr.type; + /* Try parent's PMU first: */ if (event->parent && event->parent->pmu) { pmu =3D event->parent->pmu; @@ -13640,8 +13645,8 @@ void __init perf_event_init(void) perf_event_init_all_cpus(); init_srcu_struct(&pmus_srcu); perf_pmu_register(&perf_swevent, "software", PERF_TYPE_SOFTWARE); - perf_pmu_register(&perf_cpu_clock, NULL, -1); - perf_pmu_register(&perf_task_clock, NULL, -1); + perf_pmu_register(&perf_cpu_clock, "cpu_clock", -1); + perf_pmu_register(&perf_task_clock, "task_clock", -1); perf_tp_register(); perf_event_init_cpu(smp_processor_id()); register_reboot_notifier(&perf_reboot_notifier); @@ -13684,7 +13689,7 @@ static int __init perf_event_sysfs_init(void) goto unlock; =20 list_for_each_entry(pmu, &pmus, entry) { - if (!pmu->name || pmu->type < 0) + if (pmu->dev) continue; =20 ret =3D pmu_dev_alloc(pmu); --=20 2.40.0