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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT115.mail.protection.outlook.com (10.13.173.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6363.26 via Frontend Transport; Thu, 4 May 2023 11:01:30 +0000 Received: from BLR-5CG113396H.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 4 May 2023 06:00:35 -0500 From: Ravi Bangoria To: CC: , , , , , , , , , , , , , , , , Subject: [PATCH v4 1/4] perf/core: Rework forwarding of {task|cpu}-clock events Date: Thu, 4 May 2023 16:30:00 +0530 Message-ID: <20230504110003.2548-2-ravi.bangoria@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230504110003.2548-1-ravi.bangoria@amd.com> References: <20230504110003.2548-1-ravi.bangoria@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT115:EE_|SA1PR12MB7409:EE_ X-MS-Office365-Filtering-Correlation-Id: 573ad5bb-c92b-49b9-9e73-08db4c8eea3d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 May 2023 11:01:30.1249 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 573ad5bb-c92b-49b9-9e73-08db4c8eea3d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT115.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7409 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently, PERF_TYPE_SOFTWARE is treated specially since task-clock and cpu-clock events are interfaced through it but internally gets forwarded to their own pmus. Rework this by overwriting event->attr.type in perf_swevent_init() which will cause perf_init_event() to retry with updated type and event will automatically get forwarded to right pmu. With the change, SW pmu no longer needs to be treated specially and can be included in 'pmu_idr' list. Suggested-by: Peter Zijlstra Signed-off-by: Ravi Bangoria --- include/linux/perf_event.h | 10 +++++ kernel/events/core.c | 77 ++++++++++++++++++++------------------ 2 files changed, 51 insertions(+), 36 deletions(-) diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index d5628a7b5eaa..5c8a748f51ac 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -295,6 +295,8 @@ struct perf_event_pmu_context; =20 struct perf_output_handle; =20 +#define PMU_NULL_DEV ((void *)(~0)) + /** * struct pmu - generic performance monitoring unit */ @@ -827,6 +829,14 @@ struct perf_event { void *security; #endif struct list_head sb_list; + + /* + * Certain events gets forwarded to another pmu internally by over- + * writing kernel copy of event->attr.type without user being aware + * of it. event->orig_type contains original 'type' requested by + * user. + */ + __u32 orig_type; #endif /* CONFIG_PERF_EVENTS */ }; =20 diff --git a/kernel/events/core.c b/kernel/events/core.c index 435815d3be3f..0695bb9fbbb6 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -6647,7 +6647,7 @@ static void perf_sigtrap(struct perf_event *event) return; =20 send_sig_perf((void __user *)event->pending_addr, - event->attr.type, event->attr.sig_data); + event->orig_type, event->attr.sig_data); } =20 /* @@ -9951,6 +9951,9 @@ static void sw_perf_event_destroy(struct perf_event *= event) swevent_hlist_put(); } =20 +static struct pmu perf_cpu_clock; /* fwd declaration */ +static struct pmu perf_task_clock; + static int perf_swevent_init(struct perf_event *event) { u64 event_id =3D event->attr.config; @@ -9966,7 +9969,10 @@ static int perf_swevent_init(struct perf_event *even= t) =20 switch (event_id) { case PERF_COUNT_SW_CPU_CLOCK: + event->attr.type =3D perf_cpu_clock.type; + return -ENOENT; case PERF_COUNT_SW_TASK_CLOCK: + event->attr.type =3D perf_task_clock.type; return -ENOENT; =20 default: @@ -11086,7 +11092,7 @@ static void cpu_clock_event_read(struct perf_event = *event) =20 static int cpu_clock_event_init(struct perf_event *event) { - if (event->attr.type !=3D PERF_TYPE_SOFTWARE) + if (event->attr.type !=3D perf_cpu_clock.type) return -ENOENT; =20 if (event->attr.config !=3D PERF_COUNT_SW_CPU_CLOCK) @@ -11107,6 +11113,7 @@ static struct pmu perf_cpu_clock =3D { .task_ctx_nr =3D perf_sw_context, =20 .capabilities =3D PERF_PMU_CAP_NO_NMI, + .dev =3D PMU_NULL_DEV, =20 .event_init =3D cpu_clock_event_init, .add =3D cpu_clock_event_add, @@ -11167,7 +11174,7 @@ static void task_clock_event_read(struct perf_event= *event) =20 static int task_clock_event_init(struct perf_event *event) { - if (event->attr.type !=3D PERF_TYPE_SOFTWARE) + if (event->attr.type !=3D perf_task_clock.type) return -ENOENT; =20 if (event->attr.config !=3D PERF_COUNT_SW_TASK_CLOCK) @@ -11188,6 +11195,7 @@ static struct pmu perf_task_clock =3D { .task_ctx_nr =3D perf_sw_context, =20 .capabilities =3D PERF_PMU_CAP_NO_NMI, + .dev =3D PMU_NULL_DEV, =20 .event_init =3D task_clock_event_init, .add =3D task_clock_event_add, @@ -11415,31 +11423,31 @@ int perf_pmu_register(struct pmu *pmu, const char= *name, int type) goto unlock; =20 pmu->type =3D -1; - if (!name) - goto skip_type; + if (WARN_ONCE(!name, "Can not register anonymous pmu.\n")) { + ret =3D -EINVAL; + goto free_pdc; + } + pmu->name =3D name; =20 - if (type !=3D PERF_TYPE_SOFTWARE) { - if (type >=3D 0) - max =3D type; + if (type >=3D 0) + max =3D type; =20 - ret =3D idr_alloc(&pmu_idr, pmu, max, 0, GFP_KERNEL); - if (ret < 0) - goto free_pdc; + ret =3D idr_alloc(&pmu_idr, pmu, max, 0, GFP_KERNEL); + if (ret < 0) + goto free_pdc; =20 - WARN_ON(type >=3D 0 && ret !=3D type); + WARN_ON(type >=3D 0 && ret !=3D type); =20 - type =3D ret; - } + type =3D ret; pmu->type =3D type; =20 - if (pmu_bus_running) { + if (pmu_bus_running && !pmu->dev) { ret =3D pmu_dev_alloc(pmu); if (ret) goto free_idr; } =20 -skip_type: ret =3D -ENOMEM; pmu->cpu_pmu_context =3D alloc_percpu(struct perf_cpu_pmu_context); if (!pmu->cpu_pmu_context) @@ -11481,16 +11489,7 @@ int perf_pmu_register(struct pmu *pmu, const char = *name, int type) if (!pmu->event_idx) pmu->event_idx =3D perf_event_idx_default; =20 - /* - * Ensure the TYPE_SOFTWARE PMUs are at the head of the list, - * since these cannot be in the IDR. This way the linear search - * is fast, provided a valid software event is provided. - */ - if (type =3D=3D PERF_TYPE_SOFTWARE || !name) - list_add_rcu(&pmu->entry, &pmus); - else - list_add_tail_rcu(&pmu->entry, &pmus); - + list_add_rcu(&pmu->entry, &pmus); atomic_set(&pmu->exclusive_cnt, 0); ret =3D 0; unlock: @@ -11499,12 +11498,13 @@ int perf_pmu_register(struct pmu *pmu, const char= *name, int type) return ret; =20 free_dev: - device_del(pmu->dev); - put_device(pmu->dev); + if (pmu->dev && pmu->dev !=3D PMU_NULL_DEV) { + device_del(pmu->dev); + put_device(pmu->dev); + } =20 free_idr: - if (pmu->type !=3D PERF_TYPE_SOFTWARE) - idr_remove(&pmu_idr, pmu->type); + idr_remove(&pmu_idr, pmu->type); =20 free_pdc: free_percpu(pmu->pmu_disable_count); @@ -11525,9 +11525,8 @@ void perf_pmu_unregister(struct pmu *pmu) synchronize_rcu(); =20 free_percpu(pmu->pmu_disable_count); - if (pmu->type !=3D PERF_TYPE_SOFTWARE) - idr_remove(&pmu_idr, pmu->type); - if (pmu_bus_running) { + idr_remove(&pmu_idr, pmu->type); + if (pmu_bus_running && pmu->dev && pmu->dev !=3D PMU_NULL_DEV) { if (pmu->nr_addr_filters) device_remove_file(pmu->dev, &dev_attr_nr_addr_filters); device_del(pmu->dev); @@ -11601,6 +11600,12 @@ static struct pmu *perf_init_event(struct perf_eve= nt *event) =20 idx =3D srcu_read_lock(&pmus_srcu); =20 + /* + * Save original type before calling pmu->event_init() since certain + * pmus overwrites event->attr.type to forward event to another pmu. + */ + event->orig_type =3D event->attr.type; + /* Try parent's PMU first: */ if (event->parent && event->parent->pmu) { pmu =3D event->parent->pmu; @@ -13640,8 +13645,8 @@ void __init perf_event_init(void) perf_event_init_all_cpus(); init_srcu_struct(&pmus_srcu); perf_pmu_register(&perf_swevent, "software", PERF_TYPE_SOFTWARE); - perf_pmu_register(&perf_cpu_clock, NULL, -1); - perf_pmu_register(&perf_task_clock, NULL, -1); + perf_pmu_register(&perf_cpu_clock, "cpu_clock", -1); + perf_pmu_register(&perf_task_clock, "task_clock", -1); perf_tp_register(); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 May 2023 11:02:01.3259 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e91ea1b6-3655-427e-8358-08db4c8efcd6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT115.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7675 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Although, IBS pmus can be invoked via their own interface, indirect IBS invocation via core pmu events is also supported with fixed set of events: cpu-cycles:p, r076:p (same as cpu-cycles:p) and r0C1:p (micro-ops) for user convenience. This indirect IBS invocation is broken since commit 66d258c5b048 ("perf/core: Optimize perf_init_event()"), which added RAW pmu under 'pmu_idr' list and thus if event_init() fails with RAW pmu, it started returning error instead of trying other pmus. Forward precise events from core pmu to IBS by overwriting 'type' and 'config' in the kernel copy of perf_event_attr. Overwriting will cause perf_init_event() to retry with updated 'type' and 'config', which will automatically forward event to IBS pmu. Without patch: $ sudo ./perf record -C 0 -e r076:p -- sleep 1 Error: The r076:p event is not supported. With patch: $ sudo ./perf record -C 0 -e r076:p -- sleep 1 [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 0.341 MB perf.data (37 samples) ] Fixes: 66d258c5b048 ("perf/core: Optimize perf_init_event()") Reported-by: Stephane Eranian Signed-off-by: Ravi Bangoria --- arch/x86/events/amd/core.c | 2 +- arch/x86/events/amd/ibs.c | 53 +++++++++++++++---------------- arch/x86/include/asm/perf_event.h | 2 ++ 3 files changed, 29 insertions(+), 28 deletions(-) diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c index bccea57dee81..abadd5f23425 100644 --- a/arch/x86/events/amd/core.c +++ b/arch/x86/events/amd/core.c @@ -374,7 +374,7 @@ static int amd_pmu_hw_config(struct perf_event *event) =20 /* pass precise event sampling to ibs: */ if (event->attr.precise_ip && get_ibs_caps()) - return -ENOENT; + return forward_event_to_ibs(event); =20 if (has_branch_stack(event) && !x86_pmu.lbr_nr) return -EOPNOTSUPP; diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 64582954b5f6..371014802191 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -190,7 +190,7 @@ static struct perf_ibs *get_ibs_pmu(int type) } =20 /* - * Use IBS for precise event sampling: + * core pmu config -> IBS config * * perf record -a -e cpu-cycles:p ... # use ibs op counting cycle count * perf record -a -e r076:p ... # same as -e cpu-cycles:p @@ -199,25 +199,9 @@ static struct perf_ibs *get_ibs_pmu(int type) * IbsOpCntCtl (bit 19) of IBS Execution Control Register (IbsOpCtl, * MSRC001_1033) is used to select either cycle or micro-ops counting * mode. - * - * The rip of IBS samples has skid 0. Thus, IBS supports precise - * levels 1 and 2 and the PERF_EFLAGS_EXACT is set. In rare cases the - * rip is invalid when IBS was not able to record the rip correctly. - * We clear PERF_EFLAGS_EXACT and take the rip from pt_regs then. - * */ -static int perf_ibs_precise_event(struct perf_event *event, u64 *config) +static int core_pmu_ibs_config(struct perf_event *event, u64 *config) { - switch (event->attr.precise_ip) { - case 0: - return -ENOENT; - case 1: - case 2: - break; - default: - return -EOPNOTSUPP; - } - switch (event->attr.type) { case PERF_TYPE_HARDWARE: switch (event->attr.config) { @@ -243,22 +227,37 @@ static int perf_ibs_precise_event(struct perf_event *= event, u64 *config) return -EOPNOTSUPP; } =20 +/* + * The rip of IBS samples has skid 0. Thus, IBS supports precise + * levels 1 and 2 and the PERF_EFLAGS_EXACT is set. In rare cases the + * rip is invalid when IBS was not able to record the rip correctly. + * We clear PERF_EFLAGS_EXACT and take the rip from pt_regs then. + */ +int forward_event_to_ibs(struct perf_event *event) +{ + u64 config =3D 0; + + if (!event->attr.precise_ip || event->attr.precise_ip > 2) + return -EOPNOTSUPP; + + if (!core_pmu_ibs_config(event, &config)) { + event->attr.type =3D perf_ibs_op.pmu.type; + event->attr.config =3D config; + } + return -ENOENT; +} + static int perf_ibs_init(struct perf_event *event) { struct hw_perf_event *hwc =3D &event->hw; struct perf_ibs *perf_ibs; u64 max_cnt, config; - int ret; =20 perf_ibs =3D get_ibs_pmu(event->attr.type); - if (perf_ibs) { - config =3D event->attr.config; - } else { - perf_ibs =3D &perf_ibs_op; - ret =3D perf_ibs_precise_event(event, &config); - if (ret) - return ret; - } + if (!perf_ibs) + return -ENOENT; + + config =3D event->attr.config; =20 if (event->pmu !=3D &perf_ibs->pmu) return -ENOENT; diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_= event.h index 8fc15ed5e60b..fc86248215e2 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -475,8 +475,10 @@ struct pebs_xmm { =20 #ifdef CONFIG_X86_LOCAL_APIC extern u32 get_ibs_caps(void); +extern int forward_event_to_ibs(struct perf_event *event); #else static inline u32 get_ibs_caps(void) { return 0; } +static inline int forward_event_to_ibs(struct perf_event *event) { return = -ENOENT; } #endif =20 #ifdef CONFIG_PERF_EVENTS --=20 2.40.0 From nobody Fri Dec 19 06:12:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C003FC77B78 for ; Thu, 4 May 2023 11:02:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230007AbjEDLCf (ORCPT ); Thu, 4 May 2023 07:02:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37022 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230151AbjEDLC2 (ORCPT ); Thu, 4 May 2023 07:02:28 -0400 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2075.outbound.protection.outlook.com [40.107.223.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E0EE959FD; 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Thu, 4 May 2023 11:02:05 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT041.mail.protection.outlook.com (10.13.172.98) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6363.26 via Frontend Transport; Thu, 4 May 2023 11:02:05 +0000 Received: from BLR-5CG113396H.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 4 May 2023 06:01:58 -0500 From: Ravi Bangoria To: CC: , , , , , , , , , , , , , , , , Subject: [PATCH v4 3/4] perf/core: Remove pmu linear searching code Date: Thu, 4 May 2023 16:30:02 +0530 Message-ID: <20230504110003.2548-4-ravi.bangoria@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230504110003.2548-1-ravi.bangoria@amd.com> References: <20230504110003.2548-1-ravi.bangoria@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT041:EE_|MN0PR12MB5739:EE_ X-MS-Office365-Filtering-Correlation-Id: 1bd4861e-c8fa-45f1-9c6f-08db4c8eff44 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 May 2023 11:02:05.4029 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1bd4861e-c8fa-45f1-9c6f-08db4c8eff44 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT041.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5739 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Searching for the right pmu by iterating over all pmus is no longer required since all pmus now *must* be present in the 'pmu_idr' list. So, remove linear searching code. Signed-off-by: Ravi Bangoria Tested-by: Nathan Chancellor --- kernel/events/core.c | 37 +++++++++++++------------------------ 1 file changed, 13 insertions(+), 24 deletions(-) diff --git a/kernel/events/core.c b/kernel/events/core.c index 0695bb9fbbb6..eba2b8595115 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -11630,38 +11630,27 @@ static struct pmu *perf_init_event(struct perf_ev= ent *event) } =20 again: + ret =3D -ENOENT; rcu_read_lock(); pmu =3D idr_find(&pmu_idr, type); rcu_read_unlock(); - if (pmu) { - if (event->attr.type !=3D type && type !=3D PERF_TYPE_RAW && - !(pmu->capabilities & PERF_PMU_CAP_EXTENDED_HW_TYPE)) - goto fail; - - ret =3D perf_try_init_event(pmu, event); - if (ret =3D=3D -ENOENT && event->attr.type !=3D type && !extended_type) { - type =3D event->attr.type; - goto again; - } + if (!pmu) + goto fail; =20 - if (ret) - pmu =3D ERR_PTR(ret); + if (event->attr.type !=3D type && type !=3D PERF_TYPE_RAW && + !(pmu->capabilities & PERF_PMU_CAP_EXTENDED_HW_TYPE)) + goto fail; =20 - goto unlock; + ret =3D perf_try_init_event(pmu, event); + if (ret =3D=3D -ENOENT && event->attr.type !=3D type && !extended_type) { + type =3D event->attr.type; + goto again; } =20 - list_for_each_entry_rcu(pmu, &pmus, entry, lockdep_is_held(&pmus_srcu)) { - ret =3D perf_try_init_event(pmu, event); - if (!ret) - goto unlock; - - if (ret !=3D -ENOENT) { - pmu =3D ERR_PTR(ret); - goto unlock; - } - } fail: - pmu =3D ERR_PTR(-ENOENT); + if (ret) + pmu =3D ERR_PTR(ret); + unlock: srcu_read_unlock(&pmus_srcu, idx); =20 --=20 2.40.0 From nobody Fri Dec 19 06:12:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91CBFC77B78 for ; Thu, 4 May 2023 11:02:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230227AbjEDLCk (ORCPT ); Thu, 4 May 2023 07:02:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37072 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229818AbjEDLC3 (ORCPT ); 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Thu, 4 May 2023 06:02:05 -0500 From: Ravi Bangoria To: CC: , , , , , , , , , , , , , , , , Subject: [PATCH v4 4/4] perf test: Add selftest to test IBS invocation via core pmu events Date: Thu, 4 May 2023 16:30:03 +0530 Message-ID: <20230504110003.2548-5-ravi.bangoria@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230504110003.2548-1-ravi.bangoria@amd.com> References: <20230504110003.2548-1-ravi.bangoria@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT107:EE_|MW6PR12MB7085:EE_ X-MS-Office365-Filtering-Correlation-Id: b26d038f-26c7-4558-eb2e-08db4c8f0345 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ztBrKU972wZgouYdGXP/k9n8Ome4c09i3AZqZt2VbOdkpYnCsHw2DGVMppEBghg0hXbKoHt/yKw1Ej/YP5veajNT6SgpY+6yqTWXvsLI8LfoOA+lyrAJMj7o/QtNjtuFgv4TfXPEm/TVDfNt9Jpm9+WR0oSboejO5D6gHvipQal/bJ3AaQo+M3oYbBqJfgka3yQO7epYELhGtrD4N7p0C3uiaxjRj0DExP61PYyCY+e7Ayx2HlwYhSMRlx2mmeFOX474lQ9f/k07LyzvFQbjqcN+FEoKEGMFYFCkMA9lPv4Z319RaDOcpwXGU4EWP41etmuzIAI2uT6ynBB1fZAPANDJN7TelJUYibliaXwG7IHqZo6oMlyJVNnSTIoswzr2CNG3zyiqn2cyRDjRtlZRzV6n416AS3aE7gWWl3FsZphIxOj8Isn3CZryjFDZrJj0PVKeIcG7Q0XLpy3RgPi9302pQ00sw3BFNzHVICebcHOtKVlJ6AKtQ0WpdZ1NXAYK5eR63CrMRgFQ4HwK3HxFeW24VDlTuCH9hwJVAzF4g0X1gFEM8yjwzuymj3GMeynAw90f2fP/7JnVymYvxbVF4XsU3LBXZcmkCKwC3D3Xt8cLWCB/lCEekc983t3U7guyVwnKZ4LrlDW3UFh/LEpZflBjnef/1SkU78Ig4UkW0Zu8E9aixOw4Pmb+/x7Kr1CL7sFBMBNn/1ChfwMsLzYFONRXPcKRCWN7edx1kEbS0qg= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(396003)(376002)(136003)(39860400002)(346002)(451199021)(36840700001)(46966006)(40470700004)(478600001)(54906003)(36756003)(7696005)(70586007)(70206006)(6916009)(4326008)(316002)(82740400003)(41300700001)(5660300002)(1076003)(44832011)(8936002)(8676002)(7416002)(81166007)(82310400005)(40480700001)(86362001)(26005)(186003)(16526019)(356005)(2906002)(336012)(47076005)(2616005)(426003)(36860700001)(40460700003)(83380400001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 May 2023 11:02:12.1224 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b26d038f-26c7-4558-eb2e-08db4c8f0345 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT107.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB7085 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" IBS pmu can be invoked via fixed set of core pmu events with 'precise_ip' set to 1. Add a simple event open test for all these events. Without kernel fix: $ sudo ./perf test -vv 76 76: AMD IBS via core pmu : --- start --- test child forked, pid 6553 Using CPUID AuthenticAMD-25-1-1 type: 0x0, config: 0x0, fd: 3 - Pass type: 0x0, config: 0x1, fd: -1 - Pass type: 0x4, config: 0x76, fd: -1 - Fail type: 0x4, config: 0xc1, fd: -1 - Fail type: 0x4, config: 0x12, fd: -1 - Pass test child finished with -1 ---- end ---- AMD IBS via core pmu: FAILED! With kernel fix: $ sudo ./perf test -vv 76 76: AMD IBS via core pmu : --- start --- test child forked, pid 7526 Using CPUID AuthenticAMD-25-1-1 type: 0x0, config: 0x0, fd: 3 - Pass type: 0x0, config: 0x1, fd: -1 - Pass type: 0x4, config: 0x76, fd: 3 - Pass type: 0x4, config: 0xc1, fd: 3 - Pass type: 0x4, config: 0x12, fd: -1 - Pass test child finished with 0 ---- end ---- AMD IBS via core pmu: Ok Signed-off-by: Ravi Bangoria --- tools/perf/arch/x86/include/arch-tests.h | 1 + tools/perf/arch/x86/tests/Build | 1 + .../arch/x86/tests/amd-ibs-via-core-pmu.c | 71 +++++++++++++++++++ tools/perf/arch/x86/tests/arch-tests.c | 2 + 4 files changed, 75 insertions(+) create mode 100644 tools/perf/arch/x86/tests/amd-ibs-via-core-pmu.c diff --git a/tools/perf/arch/x86/include/arch-tests.h b/tools/perf/arch/x86= /include/arch-tests.h index 902e9ea9b99e..93d3b8877baa 100644 --- a/tools/perf/arch/x86/include/arch-tests.h +++ b/tools/perf/arch/x86/include/arch-tests.h @@ -11,6 +11,7 @@ int test__intel_pt_pkt_decoder(struct test_suite *test, i= nt subtest); int test__intel_pt_hybrid_compat(struct test_suite *test, int subtest); int test__bp_modify(struct test_suite *test, int subtest); int test__x86_sample_parsing(struct test_suite *test, int subtest); +int test__amd_ibs_via_core_pmu(struct test_suite *test, int subtest); =20 extern struct test_suite *arch_tests[]; =20 diff --git a/tools/perf/arch/x86/tests/Build b/tools/perf/arch/x86/tests/Bu= ild index 6f4e8636c3bf..fd02d8181718 100644 --- a/tools/perf/arch/x86/tests/Build +++ b/tools/perf/arch/x86/tests/Build @@ -5,3 +5,4 @@ perf-y +=3D arch-tests.o perf-y +=3D sample-parsing.o perf-$(CONFIG_AUXTRACE) +=3D insn-x86.o intel-pt-test.o perf-$(CONFIG_X86_64) +=3D bp-modify.o +perf-y +=3D amd-ibs-via-core-pmu.o diff --git a/tools/perf/arch/x86/tests/amd-ibs-via-core-pmu.c b/tools/perf/= arch/x86/tests/amd-ibs-via-core-pmu.c new file mode 100644 index 000000000000..2902798ca5c1 --- /dev/null +++ b/tools/perf/arch/x86/tests/amd-ibs-via-core-pmu.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "arch-tests.h" +#include "linux/perf_event.h" +#include "tests/tests.h" +#include "pmu.h" +#include "pmus.h" +#include "../perf-sys.h" +#include "debug.h" + +#define NR_SUB_TESTS 5 + +static struct sub_tests { + int type; + unsigned long config; + bool valid; +} sub_tests[NR_SUB_TESTS] =3D { + { PERF_TYPE_HARDWARE, PERF_COUNT_HW_CPU_CYCLES, true }, + { PERF_TYPE_HARDWARE, PERF_COUNT_HW_INSTRUCTIONS, false }, + { PERF_TYPE_RAW, 0x076, true }, + { PERF_TYPE_RAW, 0x0C1, true }, + { PERF_TYPE_RAW, 0x012, false }, +}; + +static int event_open(int type, unsigned long config) +{ + struct perf_event_attr attr; + + memset(&attr, 0, sizeof(struct perf_event_attr)); + attr.type =3D type; + attr.size =3D sizeof(struct perf_event_attr); + attr.config =3D config; + attr.disabled =3D 1; + attr.precise_ip =3D 1; + attr.sample_type =3D PERF_SAMPLE_IP | PERF_SAMPLE_TID; + attr.sample_period =3D 100000; + + return sys_perf_event_open(&attr, -1, 0, -1, 0); +} + +int test__amd_ibs_via_core_pmu(struct test_suite *test __maybe_unused, + int subtest __maybe_unused) +{ + struct perf_pmu *ibs_pmu; + int ret =3D TEST_OK; + int fd, i; + + if (list_empty(&pmus)) + perf_pmu__scan(NULL); + + ibs_pmu =3D perf_pmu__find("ibs_op"); + if (!ibs_pmu) + return TEST_SKIP; + + for (i =3D 0; i < NR_SUB_TESTS; i++) { + fd =3D event_open(sub_tests[i].type, sub_tests[i].config); + pr_debug("type: 0x%x, config: 0x%lx, fd: %d - ", sub_tests[i].type, + sub_tests[i].config, fd); + if ((sub_tests[i].valid && fd =3D=3D -1) || + (!sub_tests[i].valid && fd > 0)) { + pr_debug("Fail\n"); + ret =3D TEST_FAIL; + } else { + pr_debug("Pass\n"); + } + + if (fd > 0) + close(fd); + } + + return ret; +} diff --git a/tools/perf/arch/x86/tests/arch-tests.c b/tools/perf/arch/x86/t= ests/arch-tests.c index aae6ea0fe52b..b5c85ab8d92e 100644 --- a/tools/perf/arch/x86/tests/arch-tests.c +++ b/tools/perf/arch/x86/tests/arch-tests.c @@ -22,6 +22,7 @@ struct test_suite suite__intel_pt =3D { DEFINE_SUITE("x86 bp modify", bp_modify); #endif DEFINE_SUITE("x86 Sample parsing", x86_sample_parsing); +DEFINE_SUITE("AMD IBS via core pmu", amd_ibs_via_core_pmu); =20 struct test_suite *arch_tests[] =3D { #ifdef HAVE_DWARF_UNWIND_SUPPORT @@ -35,5 +36,6 @@ struct test_suite *arch_tests[] =3D { &suite__bp_modify, #endif &suite__x86_sample_parsing, + &suite__amd_ibs_via_core_pmu, NULL, }; --=20 2.40.0