From nobody Mon Feb 9 02:20:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9C89C77B7C for ; Thu, 4 May 2023 08:30:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229723AbjEDIad (ORCPT ); Thu, 4 May 2023 04:30:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38364 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229645AbjEDIaG (ORCPT ); Thu, 4 May 2023 04:30:06 -0400 Received: from mail-pf1-x42c.google.com (mail-pf1-x42c.google.com [IPv6:2607:f8b0:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5AA866188 for ; Thu, 4 May 2023 01:27:15 -0700 (PDT) Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-643846c006fso306761b3a.0 for ; Thu, 04 May 2023 01:27:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683188835; x=1685780835; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mmaLfLchQ4rAHy5t1YFYbHdQn/tu5s+YbDZEOcELexg=; b=O7IuTY7Xl9h8/AUCgL62GBsuZuAifKLapHZk0H3kSWhURmopInl7dQRbIUQFLLaGGT +upT51N7E6oc3pYoumUAmRx2jlrBlQSnbgfmsqLJM83Vmg/L7IJlbrR4E0WZg4VE4PcY d7QMdIOjxqCjuapOqfvNXiu4eq9MKyhPlrwhVCIfn8MxcGdVCrwF1XyoEJZp04QbFp6E xJ3sPrcn+oafKDbam5T1VEdVVcE6iajwK8nGZNrpR3TDieatgML4eMd7uzz8NMzDo/Ae UPsYdVb5nLKBgM4IH/i+wRibcO1PANAHmBE52xxe8qunM4jz0yvqOa75zDcG5pzzQTRR pGTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683188835; x=1685780835; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mmaLfLchQ4rAHy5t1YFYbHdQn/tu5s+YbDZEOcELexg=; b=lZcZUTy5e3qia8Ljr4mYTsxay/dyvlwfz9fyAivZLIXn2P6Beq/odMxgBv8JHhLYcp 7Qqqq5KjLutG2thaOwzHt+EsBZ6lc6mtXUqqIUnQDm52ZXMLIwPcXLgYBLMq8oodDuK/ jbMcUrQX1seFxX/Sje1ldtRJHc09pZolfKFaSJ3jlnjSw7UvcgpisdM0gGnT9uWCt8ig pbM674wTjHOJdAFfOIS6hxjuPORF0gpBMlIaKgv4WJ2wC0y1v4CYCUdEwuZNtfZ3paXY X/5WPUmfc2OTigqrKmDdG5HGMZVbd7VJOvdHJHOm3cetRg9eQu1vAbPxqL+MpMNq3GPh 92QQ== X-Gm-Message-State: AC+VfDz3Km831q3noIEj5FHBE7FN+fgQuhVf1Qhe7JmUroKaI+V8mD0o 9jZPY/NMnIrvS8yOhhqToMfqOQ== X-Google-Smtp-Source: ACHHUZ435F//tL0eS3YIpLg+RkgxRAGF5zZHKtthn+XkXKTItns7c2uRorHCLxqq+IpPQBJjnslLxA== X-Received: by 2002:a05:6a00:88b:b0:63d:3a18:49ed with SMTP id q11-20020a056a00088b00b0063d3a1849edmr1603633pfj.15.1683188834701; Thu, 04 May 2023 01:27:14 -0700 (PDT) Received: from localhost.localdomain ([223.233.65.180]) by smtp.gmail.com with ESMTPSA id s1-20020a056a00178100b00625d84a0194sm24913973pfg.107.2023.05.04.01.27.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 01:27:14 -0700 (PDT) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Cc: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com, bhupesh.sharma@linaro.org, robh+dt@kernel.org, linux-usb@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, krzysztof.kozlowski@linaro.org Subject: [PATCH v3 1/5] usb: misc: eud: Fix eud sysfs path (use 'qcom_eud') Date: Thu, 4 May 2023 13:56:40 +0530 Message-Id: <20230504082644.1461582-2-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230504082644.1461582-1-bhupesh.sharma@linaro.org> References: <20230504082644.1461582-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The eud sysfs enablement path is currently mentioned in the Documentation as: /sys/bus/platform/drivers/eud/.../enable Instead it should be: /sys/bus/platform/drivers/qcom_eud/.../enable Fix the same. Signed-off-by: Bhupesh Sharma Reviewed-by: Konrad Dybcio --- Documentation/ABI/testing/sysfs-driver-eud | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/ABI/testing/sysfs-driver-eud b/Documentation/ABI= /testing/sysfs-driver-eud index 83f3872182a4..2bab0db2d2f0 100644 --- a/Documentation/ABI/testing/sysfs-driver-eud +++ b/Documentation/ABI/testing/sysfs-driver-eud @@ -1,4 +1,4 @@ -What: /sys/bus/platform/drivers/eud/.../enable +What: /sys/bus/platform/drivers/qcom_eud/.../enable Date: February 2022 Contact: Souradeep Chowdhury Description: --=20 2.38.1 From nobody Mon Feb 9 02:20:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F20F0C7EE23 for ; Thu, 4 May 2023 08:30:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230033AbjEDIai (ORCPT ); Thu, 4 May 2023 04:30:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38396 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230001AbjEDIaK (ORCPT ); Thu, 4 May 2023 04:30:10 -0400 Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 861BB5FD1 for ; Thu, 4 May 2023 01:27:19 -0700 (PDT) Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-63b5465fc13so200593b3a.3 for ; Thu, 04 May 2023 01:27:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683188839; x=1685780839; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tpKnP1YDIVbRZiADGr23D8oPufyg/cq5r9T3i6z6bvI=; b=SqxCUtKDUckciWmrviJ3XhnAkxxA1WC+AmYMmH0dT+ADSNmyojxdmp2LSd/3s7CzZG 9D8GZERaj+o65tILZzOpY8F6UiueQ/rFMgRi/dAaejXt9BtCqEG54BjOO4ClcZdX36PN hcX/BppDb1EXnPq3/EUKvJyrPBDpQmKr7fCc5J+pf3VKTPb6r150uBQzInr1LEDbcI8n zryM1VuBSmSfmk3ea31151Uo/Fsc72TPQub9AsAfBpMDYvEy1NsNV8qED5OxVM6j76Pi E2gisu2Zz9TpvDqwoNkGnpO7uZA9cx1sh1PqQWXnjB9Nyls7qYZwbXzw7dLiF2T+GZl5 2l1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683188839; x=1685780839; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tpKnP1YDIVbRZiADGr23D8oPufyg/cq5r9T3i6z6bvI=; b=A4NrHLG9zaJRGSodeAG7+QN8hGTVceBQs5VuqzU43R/y+QAyHYrdLz14XqA1qWs1cO CHM30WxxQ6J75jpnVpbHFtDl8OyqE3Kw1DmLKskBf35HhBn54Rolrjg07eLN44Y+hEfb /5t8dRQWUKgp4/wC15V9qf0pcn/t3GxlvXzI8OZAR4H/eWv3AQd96d7HkN6LTTxFtAMV c24Mk9xEuD87MPVt2zn2s6O+gW6sXN6R2lJlmofK5PAYnNTmbzotvgyzVtBOsxMshYVZ l5a+F/c9b/NceKCruhqPZRA7VZsLjlMQ5/GgOOiI1lyHSAs/e3RIk+wgbQuQjCAmtuPn HDMQ== X-Gm-Message-State: AC+VfDxp8rbuj/bKoJ5y/fOX6ns5udvQpZlAUPbmHCHKXsjtfAilo5sg CfK7efANjSDnMChHPHFH4O+PLg== X-Google-Smtp-Source: ACHHUZ7UOqdcHAwQljJYRINyc92mh0tnSr55X6WqOMbku03xQt2V3sl+JoexUlJNe14g7jl5gWeVcw== X-Received: by 2002:aa7:888d:0:b0:63b:859f:f094 with SMTP id z13-20020aa7888d000000b0063b859ff094mr1782227pfe.20.1683188838921; Thu, 04 May 2023 01:27:18 -0700 (PDT) Received: from localhost.localdomain ([223.233.65.180]) by smtp.gmail.com with ESMTPSA id s1-20020a056a00178100b00625d84a0194sm24913973pfg.107.2023.05.04.01.27.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 01:27:18 -0700 (PDT) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Cc: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com, bhupesh.sharma@linaro.org, robh+dt@kernel.org, linux-usb@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, krzysztof.kozlowski@linaro.org Subject: [PATCH v3 2/5] dt-bindings: soc: qcom: eud: Add SM6115 / SM4250 support Date: Thu, 4 May 2023 13:56:41 +0530 Message-Id: <20230504082644.1461582-3-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230504082644.1461582-1-bhupesh.sharma@linaro.org> References: <20230504082644.1461582-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add dt-bindings for EUD found on Qualcomm SM6115 / SM4250 SoC. On this SoC (and derivatives) the enable bit inside 'tcsr_check_reg' needs to be set first to 'enable' the eud module. So, update the dt-bindings to accommodate the third register property (TCSR Base) required by the driver on these SoCs. Also for these SoCs, introduce a new bool property 'qcom,secure-mode-enable', which indicates that the mode manager needs to be accessed only via the secure world. Signed-off-by: Bhupesh Sharma --- .../devicetree/bindings/soc/qcom/qcom,eud.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml b/Doc= umentation/devicetree/bindings/soc/qcom/qcom,eud.yaml index f2c5ec7e6437..3b92cdf4e306 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml @@ -18,17 +18,33 @@ properties: items: - enum: - qcom,sc7280-eud + - qcom,sm6115-eud - const: qcom,eud =20 reg: + minItems: 2 items: - description: EUD Base Register Region - description: EUD Mode Manager Register + - description: TCSR Base Register Region + + reg-names: + minItems: 2 + items: + - const: eud-base + - const: eud-mode-mgr + - const: tcsr-base =20 interrupts: description: EUD interrupt maxItems: 1 =20 + qcom,secure-mode-enable: + type: boolean + description: + Indicates that the mode manager needs to be accessed only via the se= cure + world (through 'scm' calls). + ports: $ref: /schemas/graph.yaml#/properties/ports description: --=20 2.38.1 From nobody Mon Feb 9 02:20:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46F03C77B7C for ; Thu, 4 May 2023 08:30:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230310AbjEDIam (ORCPT ); Thu, 4 May 2023 04:30:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39584 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230266AbjEDIaQ (ORCPT ); Thu, 4 May 2023 04:30:16 -0400 Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 086A86E9B for ; Thu, 4 May 2023 01:27:24 -0700 (PDT) Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-64115eef620so10641744b3a.1 for ; Thu, 04 May 2023 01:27:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683188843; x=1685780843; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rC05tB6gG1w1yHT13tBk32ihblOOEZ5SfiKYI/IbjjQ=; b=IMfqygJFmeRRkLOeYT3j4HwKWtg+uVHGhi0RkKgfN0VDrkSrXNjAiMzxyNuxT7lRk3 omG09lUyaFV8SHmUiIOjrpQOAQMFNeNinaLTneF5Tw4YAaORj6y18i8k2jOuAErzPNWX dRaBdX1Eu/gfwFymXJAFiruM3QVXLjslziE7B+8LTJ3dBMdxPAs43RuPWsuJDAy6Heb2 Y9Nf639F72TqM2HzgLuzGoSWCmug7LLNzjCc6DwH+gi/OxM7KP3+JVLBfMSsjpGGAKnK iZb8kEGNRY6oTRF6e0UVq1LfJO+BXk3t+JWcJ5Q7GMtWmQmqAyFBYEZv3Hv/rxlMCB5V 2UuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683188843; x=1685780843; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rC05tB6gG1w1yHT13tBk32ihblOOEZ5SfiKYI/IbjjQ=; b=RfpZW1hnt+9ZkY+W8vEZtQHA5WfZUi8UfYo8XF75x6PQAk3KMdl6oMKmnDtI++OPsl jEHBbdx7S5H9t/fDaGn/AuzlOjh0eSlTW6k1DDVTIgpzSoGQh4C84fsDGvm0Wi3G2ZY9 3lvYLtLCQ9yNNQmpQtkE1PMg1GUr3+DGyXUGnioWAeh3fSEmxWu5tA0HXPw5zHVZi+Lj kp66xMRQBPfjhGaffDiywhzZoYh31ZNDonA51xv/TMtVnelBiU3Drb99ZiW/uVouFw7b GkMiiHy7VMrCdBdaPzyi3Ka9EOeqDFqvu86PRYf/HeJDO0+Q7Q8mmQ2FowrAg7y+ih/6 Jy6w== X-Gm-Message-State: AC+VfDyiGSDqXE3X1wfps7tNui0aKR7VTWN3IH5ENePXIUvUThNq5opo Yct3X/FiWP3GnrIAIk2LXFwCtg== X-Google-Smtp-Source: ACHHUZ4F+kqfr1zKvpCEgCXJESza+wXfDvl+Yo+sRVO2JxmTYIPLQXY41NZICDe7b7xHg+kFk7aAAg== X-Received: by 2002:a05:6a00:4186:b0:62d:bf69:e9e0 with SMTP id ca6-20020a056a00418600b0062dbf69e9e0mr1406319pfb.17.1683188843143; Thu, 04 May 2023 01:27:23 -0700 (PDT) Received: from localhost.localdomain ([223.233.65.180]) by smtp.gmail.com with ESMTPSA id s1-20020a056a00178100b00625d84a0194sm24913973pfg.107.2023.05.04.01.27.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 01:27:22 -0700 (PDT) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Cc: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com, bhupesh.sharma@linaro.org, robh+dt@kernel.org, linux-usb@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, krzysztof.kozlowski@linaro.org Subject: [PATCH v3 3/5] usb: misc: eud: Add driver support for SM6115 / SM4250 Date: Thu, 4 May 2023 13:56:42 +0530 Message-Id: <20230504082644.1461582-4-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230504082644.1461582-1-bhupesh.sharma@linaro.org> References: <20230504082644.1461582-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add SM6115 / SM4250 SoC EUD support in qcom_eud driver. On some SoCs (like the SM6115 / SM4250 SoC), the mode manager needs to be accessed only via the secure world (through 'scm' calls). Also, the enable bit inside 'tcsr_check_reg' needs to be set first to set the eud in 'enable' mode on these SoCs. Since this difference comes from how the firmware is configured, so the driver now relies on the presence of an extra boolean DT property to identify if secure access is needed. Signed-off-by: Bhupesh Sharma --- drivers/usb/misc/Kconfig | 1 + drivers/usb/misc/qcom_eud.c | 66 ++++++++++++++++++++++++++++++++++--- 2 files changed, 62 insertions(+), 5 deletions(-) diff --git a/drivers/usb/misc/Kconfig b/drivers/usb/misc/Kconfig index 99b15b77dfd5..fe1b5fec1dfc 100644 --- a/drivers/usb/misc/Kconfig +++ b/drivers/usb/misc/Kconfig @@ -147,6 +147,7 @@ config USB_APPLEDISPLAY config USB_QCOM_EUD tristate "QCOM Embedded USB Debugger(EUD) Driver" depends on ARCH_QCOM || COMPILE_TEST + select QCOM_SCM select USB_ROLE_SWITCH help This module enables support for Qualcomm Technologies, Inc. diff --git a/drivers/usb/misc/qcom_eud.c b/drivers/usb/misc/qcom_eud.c index b7f13df00764..b4736edcc64c 100644 --- a/drivers/usb/misc/qcom_eud.c +++ b/drivers/usb/misc/qcom_eud.c @@ -5,12 +5,14 @@ =20 #include #include +#include #include #include #include #include #include #include +#include #include #include #include @@ -30,15 +32,22 @@ #define EUD_INT_SAFE_MODE BIT(4) #define EUD_INT_ALL (EUD_INT_VBUS | EUD_INT_SAFE_MODE) =20 +struct eud_soc_cfg { + u32 tcsr_check_offset; +}; + struct eud_chip { struct device *dev; struct usb_role_switch *role_sw; + const struct eud_soc_cfg *eud_cfg; void __iomem *base; void __iomem *mode_mgr; unsigned int int_status; int irq; bool enabled; bool usb_attached; + bool secure_mode_enable; + phys_addr_t secure_mode_mgr; }; =20 static int enable_eud(struct eud_chip *priv) @@ -46,7 +55,11 @@ static int enable_eud(struct eud_chip *priv) writel(EUD_ENABLE, priv->base + EUD_REG_CSR_EUD_EN); writel(EUD_INT_VBUS | EUD_INT_SAFE_MODE, priv->base + EUD_REG_INT1_EN_MASK); - writel(1, priv->mode_mgr + EUD_REG_EUD_EN2); + + if (priv->secure_mode_mgr) + qcom_scm_io_writel(priv->secure_mode_mgr + EUD_REG_EUD_EN2, BIT(0)); + else + writel(1, priv->mode_mgr + EUD_REG_EUD_EN2); =20 return usb_role_switch_set_role(priv->role_sw, USB_ROLE_DEVICE); } @@ -54,7 +67,11 @@ static int enable_eud(struct eud_chip *priv) static void disable_eud(struct eud_chip *priv) { writel(0, priv->base + EUD_REG_CSR_EUD_EN); - writel(0, priv->mode_mgr + EUD_REG_EUD_EN2); + + if (priv->secure_mode_mgr) + qcom_scm_io_writel(priv->secure_mode_mgr + EUD_REG_EUD_EN2, 0); + else + writel(0, priv->mode_mgr + EUD_REG_EUD_EN2); } =20 static ssize_t enable_show(struct device *dev, @@ -178,12 +195,15 @@ static void eud_role_switch_release(void *data) static int eud_probe(struct platform_device *pdev) { struct eud_chip *chip; + struct resource *res; + phys_addr_t tcsr_base, tcsr_check; int ret; =20 chip =3D devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); if (!chip) return -ENOMEM; =20 + chip->dev =3D &pdev->dev; =20 chip->role_sw =3D usb_role_switch_get(&pdev->dev); @@ -200,9 +220,40 @@ static int eud_probe(struct platform_device *pdev) if (IS_ERR(chip->base)) return PTR_ERR(chip->base); =20 - chip->mode_mgr =3D devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(chip->mode_mgr)) - return PTR_ERR(chip->mode_mgr); + chip->secure_mode_enable =3D of_property_read_bool(chip->dev->of_node, + "qcom,secure-mode-enable"); + /* + * EUD block on a few Qualcomm SoCs need secure register access. + * Check for the same. + */ + if (chip->secure_mode_enable) { + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res) + return dev_err_probe(chip->dev, -ENODEV, + "failed to get secure_mode_mgr reg base\n"); + + chip->secure_mode_mgr =3D res->start; + } else { + chip->mode_mgr =3D devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(chip->mode_mgr)) + return PTR_ERR(chip->mode_mgr); + } + + /* Check for any SoC specific config data */ + chip->eud_cfg =3D of_device_get_match_data(&pdev->dev); + if (chip->eud_cfg) { + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 2); + if (!res) + return dev_err_probe(chip->dev, -ENODEV, + "failed to get tcsr reg base\n"); + + tcsr_base =3D res->start; + tcsr_check =3D tcsr_base + chip->eud_cfg->tcsr_check_offset; + + ret =3D qcom_scm_io_writel(tcsr_check, BIT(0)); + if (ret) + return dev_err_probe(chip->dev, ret, "failed to write tcsr check reg\n"= ); + } =20 chip->irq =3D platform_get_irq(pdev, 0); ret =3D devm_request_threaded_irq(&pdev->dev, chip->irq, handle_eud_irq, @@ -230,8 +281,13 @@ static int eud_remove(struct platform_device *pdev) return 0; } =20 +static const struct eud_soc_cfg sm6115_eud_cfg =3D { + .tcsr_check_offset =3D 0x25018, +}; + static const struct of_device_id eud_dt_match[] =3D { { .compatible =3D "qcom,sc7280-eud" }, + { .compatible =3D "qcom,sm6115-eud", .data =3D &sm6115_eud_cfg }, { } }; MODULE_DEVICE_TABLE(of, eud_dt_match); --=20 2.38.1 From nobody Mon Feb 9 02:20:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7620CC7EE21 for ; Thu, 4 May 2023 08:30:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230367AbjEDIaq (ORCPT ); Thu, 4 May 2023 04:30:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38628 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229733AbjEDIaT (ORCPT ); Thu, 4 May 2023 04:30:19 -0400 Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 97A7C127 for ; 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Thu, 04 May 2023 01:27:27 -0700 (PDT) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Cc: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com, bhupesh.sharma@linaro.org, robh+dt@kernel.org, linux-usb@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, krzysztof.kozlowski@linaro.org Subject: [PATCH v3 4/5] arm64: dts: qcom: sm6115: Add EUD dt node and dwc3 connector Date: Thu, 4 May 2023 13:56:43 +0530 Message-Id: <20230504082644.1461582-5-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230504082644.1461582-1-bhupesh.sharma@linaro.org> References: <20230504082644.1461582-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the Embedded USB Debugger(EUD) device tree node for SM6115 / SM4250 SoC. The node contains EUD base register region, EUD mode manager register region and TCSR Base register region along with the interrupt entry. Also add the typec connector node for EUD which is attached to EUD node via port. EUD is also attached to DWC3 node via port. To enable the role switch, we need to set dr_mode =3D "otg" property for 'usb_dwc3' sub-node in the board dts file. Also the EUD device can be enabled on a board once linux is boot'ed by setting: $ echo 1 > /sys/bus/platform/drivers/qcom_eud/../enable Signed-off-by: Bhupesh Sharma --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 48 ++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qco= m/sm6115.dtsi index f67863561f3f..6865342fc42f 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -180,6 +180,18 @@ core3 { }; }; =20 + eud_typec: connector { + compatible =3D "usb-c-connector"; + + ports { + port@0 { + con_eud: endpoint { + remote-endpoint =3D <&eud_con>; + }; + }; + }; + }; + firmware { scm: scm { compatible =3D "qcom,scm-sm6115", "qcom,scm"; @@ -647,6 +659,35 @@ gcc: clock-controller@1400000 { #power-domain-cells =3D <1>; }; =20 + eud: eud@1610000 { + compatible =3D "qcom,sm6115-eud", "qcom,eud"; + reg =3D <0x0 0x01610000 0x0 0x2000>, + <0x0 0x01612000 0x0 0x1000>, + <0x0 0x003c0000 0x0 0x40000>; + interrupts =3D ; + qcom,secure-mode-enable; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + eud_ep: endpoint { + remote-endpoint =3D <&usb2_role_switch>; + }; + }; + + port@1 { + reg =3D <1>; + eud_con: endpoint { + remote-endpoint =3D <&con_eud>; + }; + }; + }; + }; + usb_hsphy: phy@1613000 { compatible =3D "qcom,sm6115-qusb2-phy"; reg =3D <0x0 0x01613000 0x0 0x180>; @@ -1144,6 +1185,13 @@ usb_dwc3: usb@4e00000 { snps,has-lpm-erratum; snps,hird-threshold =3D /bits/ 8 <0x10>; snps,usb3_lpm_capable; + usb-role-switch; + + port { + usb2_role_switch: endpoint { + remote-endpoint =3D <&eud_ep>; + }; + }; }; }; =20 --=20 2.38.1 From nobody Mon Feb 9 02:20:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3440C7EE22 for ; Thu, 4 May 2023 08:31:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230110AbjEDIbA (ORCPT ); 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Thu, 04 May 2023 01:27:31 -0700 (PDT) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Cc: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-kernel@vger.kernel.org, bhupesh.linux@gmail.com, bhupesh.sharma@linaro.org, robh+dt@kernel.org, linux-usb@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, krzysztof.kozlowski@linaro.org Subject: [PATCH v3 5/5] arm64: dts: qcom: qrb4210-rb2: Enable EUD debug peripheral Date: Thu, 4 May 2023 13:56:44 +0530 Message-Id: <20230504082644.1461582-6-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230504082644.1461582-1-bhupesh.sharma@linaro.org> References: <20230504082644.1461582-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since the USB-C type port on the Qualcomm QRB4210-RB2 board can be set primarily in a 'device' configuration (with the default DIP switch settings), it makes sense to enable the EUD debug peripheral on the board by default by setting the USB 'dr_mode' property as 'otg'. Now, the EUD debug peripheral can be enabled by executing: $ echo 1 > /sys/bus/platform/drivers/qcom_eud/1610000.eud/enable Signed-off-by: Bhupesh Sharma --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 27 +++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts= /qcom/qrb4210-rb2.dts index 1a0776a0cfd0..0ce72f1ebc10 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -30,6 +30,10 @@ vph_pwr: vph-pwr-regulator { }; }; =20 +&eud { + status =3D "okay"; +}; + &qupv3_id_0 { status =3D "okay"; }; @@ -253,7 +257,28 @@ &usb { =20 &usb_dwc3 { maximum-speed =3D "super-speed"; - dr_mode =3D "peripheral"; + + /* + * There is only one USB DWC3 controller on QRB4210 board and it is conne= cted + * via a DIP Switch: + * - to either an USB - C type connector or an USB - A type connector + * (via a GL3590-S hub), and + * - to either an USB - A type connector (via a GL3590-S hub) or a connec= tor + * for further connection with a mezzanine board. + * + * All of the above hardware muxes would allow us to hook things up in + * different ways to some potential benefit for static configurations (fo= r e.g. + * on one hand we can have two USB - A type connectors and a USB - Ethern= et + * connection available and on the other we can use the USB - C type in + * peripheral mode). + * + * Note that since the USB - C type can be used only in peripehral mode, + * so hardcoding the mode to 'peripheral' here makes sense. + * + * However since we want to use the EUD debug device, we set the mode as + * 'otg' here. + */ + dr_mode =3D "otg"; }; =20 &usb_hsphy { --=20 2.38.1