From nobody Wed Feb 11 20:58:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54F16C7EE23 for ; Wed, 3 May 2023 13:02:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230057AbjECNCE (ORCPT ); Wed, 3 May 2023 09:02:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60410 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229601AbjECNCB (ORCPT ); Wed, 3 May 2023 09:02:01 -0400 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C3611A5; Wed, 3 May 2023 06:01:58 -0700 (PDT) Received: by mail-ej1-x62d.google.com with SMTP id a640c23a62f3a-959a3e2dc72so1010251766b.2; Wed, 03 May 2023 06:01:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683118917; x=1685710917; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JhiOdhDEfb+iWh2Mv/2vV0thu45ELxEEl7Ux8olY3M8=; b=GDgWhCa7cTPRM91qlWVp/Nbs6yAAzQTxkEm9m3fVLU05H+ocy+NgohNDdjESCghGYH pqeZbQHx/QVpX+CWCp9T/QRqvV3Vnl4e6jhqqtAHTxMeNTLLl8KDEl6dF1aDfH46bXuM 0RaDonz5kNkl4RUHwaKFsXP0PS9NSwIVO7JqfS4xb/rSqPAD6u8QcQ109WAC++fWH5si wt2eEFU5qXN7HhHQ5P08n85ETKpzJIxQRnJhRMVHbfyICPnxiqwP0N1IKeZUcs8Y+Rw8 2ifiKzBy0i4GzGz8dSpo+2UjlKo4bMNkAlqqBNhjCzaezSEVgEbuNBVo7wWyFsGCIQ8H SYMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683118917; x=1685710917; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JhiOdhDEfb+iWh2Mv/2vV0thu45ELxEEl7Ux8olY3M8=; b=EaPgHR1HGz+gkq0PbQBN+q5ibIyUWbTaEq/hb66Z2DmgxSYJ/09bOO/6BEnR8Jc31F kmPk3wyFFX2oTLPNweqHUErcG/OwBEmZIEs1J6euAPyN4AnZOvT1NR3POzSMAgyzxeIc Fxj25nXJYGUm2M8TIPfSP1cLmt56HbEy910ayOXwxG8V7x4CuoPN636AQT8FFdAJFZ6B L7e4+0Pkr2vMUb+XqaxlvyQ+p3cDiwmtfmC9twNvHEOUf9f7E6nc3iWWnWoeEc8l/ryb fYtO4JfMXdMfak/N/k5zyD8S8b0L4tq6M4LoHWL4YuiCzTeXLnhwUJQu5ZFWFKrB8p7x zsWA== X-Gm-Message-State: AC+VfDz0qEF32QF+cDxqEWESfTkCNSPwmP3YDKxzhfjEpWFgemKQnqqO 6hwHGwpT8joReuG7UQKkG1o= X-Google-Smtp-Source: ACHHUZ5VBCxtl59/JZsu9Fjmhg//S8oBIMkURJC7sUdEzQiKrgokJkDMu0wHpflO+8wKkVT9t+9ZWw== X-Received: by 2002:a17:906:ef0a:b0:958:5c21:3fa7 with SMTP id f10-20020a170906ef0a00b009585c213fa7mr3490600ejs.25.1683118916731; Wed, 03 May 2023 06:01:56 -0700 (PDT) Received: from localhost.localdomain ([95.183.227.33]) by smtp.gmail.com with ESMTPSA id my17-20020a1709065a5100b0095728081944sm16105578ejc.146.2023.05.03.06.01.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 May 2023 06:01:56 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Dmitry Baryshkov Cc: Yassine Oudjana , Yassine Oudjana , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH RESEND 1/3] dt-bindings: clock: qcom,msm8996-cbf: Add compatible for MSM8996 Pro Date: Wed, 3 May 2023 16:00:50 +0300 Message-Id: <20230503130051.144708-2-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230503130051.144708-1-y.oudjana@protonmail.com> References: <20230503130051.144708-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yassine Oudjana The CBF clock on MSM8996 Pro has a different divisor compared to MSM8996 and is therefore not fully compatible with it. Add a new compatible string to differentiate between them. Signed-off-by: Yassine Oudjana Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/clock/qcom,msm8996-cbf.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,msm8996-cbf.yaml = b/Documentation/devicetree/bindings/clock/qcom,msm8996-cbf.yaml index 3ffe69d8cdd5..0dfbd8c4d465 100644 --- a/Documentation/devicetree/bindings/clock/qcom,msm8996-cbf.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,msm8996-cbf.yaml @@ -15,7 +15,9 @@ description: > =20 properties: compatible: - const: qcom,msm8996-cbf + enum: + - qcom,msm8996-cbf + - qcom,msm8996pro-cbf =20 reg: maxItems: 1 --=20 2.40.0 From nobody Wed Feb 11 20:58:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40BC6C77B78 for ; Wed, 3 May 2023 13:02:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230095AbjECNCL (ORCPT ); Wed, 3 May 2023 09:02:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60466 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230045AbjECNCF (ORCPT ); Wed, 3 May 2023 09:02:05 -0400 Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 559C01A5; Wed, 3 May 2023 06:02:03 -0700 (PDT) Received: by mail-ed1-x535.google.com with SMTP id 4fb4d7f45d1cf-50bd875398dso2394850a12.1; Wed, 03 May 2023 06:02:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683118922; x=1685710922; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1V3rgI/5A2MTfAJo/8hueKDPxSOGXJm1mCHXT4uBpmY=; b=PNvCtK6WJsAPCggpeyY2cAVR6Tw4iRNJDt+Wq2Xeu3nq2io/Y1JUbNeXlZEE4wesab z3J1oYx42qC39l1cBaiWN64oPhEHpu70NsFwri2nc3O4bNZ47kmSBXUaybcue1LjVPBk 0qFMy06cY5sCuOqEnwQQIZJ7bLOmBuIqdah8SlcA2whIoBZNXlz9hSBwx+HQxlzwX0Wi fQQqZy/A6Ap8w1uzDPQ0UhYtyLE1ImWQtkZj8ICrDaUQllA39ApBfRJoIcjrgWyAF/Nv KfjBChTB3vsdT7/3MoF53TUFcpFcZtXZVZr5PmDGnb3Vj6X4ZBg6CStbHrxoJhIqJP/M b+AA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683118922; x=1685710922; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1V3rgI/5A2MTfAJo/8hueKDPxSOGXJm1mCHXT4uBpmY=; b=IlQ+gawut03x9BjMbDSj8n2OsjnZMEC/D7IpZfBLLI5HxTVwTRGMbHYDjzUrDD0rTN /RyBYZa1hPlnMQCcwMIPV84PYNwLxxrKIGPUlcENtbD0xxJ3UNAOfzAh7cu7NxpKcUXx Ao77my8wSJLCih8cW1iqtRsPeeM3H1Y5xBMf/PuaOYh3A7gpKAcu43ZcZw1N/R759ffu WPNgbuyK3+LjWyNVpQduU8v7tYpcaoP9giAitSr81U/OM90EtZSkpnxADomJRHcPMOdf tAH2r1kBkovx4LZ3pqe1mRMtAKRO0dozCLRzpKBAqWfy8f84h9bMB/Z+Z0XNaPZ6XK0+ v9lA== X-Gm-Message-State: AC+VfDxw5bLQipJbGcK2HBh+jtFOlysm6Y5QCTT5xmIqnQNYnLlPQtVS XhPwtEwv3t6BgPUGqdSOXpk= X-Google-Smtp-Source: ACHHUZ53NeMl5qShVSaUR8CZtdJjEBycHu9DNGpIdzfyfh2sdXRAla7ZglQhrS7q9beetAPw0gXyQA== X-Received: by 2002:a17:906:794c:b0:94f:1c90:cb71 with SMTP id l12-20020a170906794c00b0094f1c90cb71mr4116095ejo.65.1683118921466; Wed, 03 May 2023 06:02:01 -0700 (PDT) Received: from localhost.localdomain ([95.183.227.33]) by smtp.gmail.com with ESMTPSA id my17-20020a1709065a5100b0095728081944sm16105578ejc.146.2023.05.03.06.01.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 May 2023 06:02:01 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Dmitry Baryshkov Cc: Yassine Oudjana , Yassine Oudjana , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH RESEND 2/3] arm64: dts: qcom: msm8996pro: Add CBF scaling support Date: Wed, 3 May 2023 16:00:51 +0300 Message-Id: <20230503130051.144708-3-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230503130051.144708-1-y.oudjana@protonmail.com> References: <20230503130051.144708-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yassine Oudjana Add opp-peak-kBps to CPU OPPs to allow for CBF scaling, and change the CBF compatible to reflect the difference between it and the one on MSM8996. Signed-off-by: Yassine Oudjana Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/msm8996pro.dtsi | 51 ++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996pro.dtsi b/arch/arm64/boot/dts= /qcom/msm8996pro.dtsi index a679a9c0cf99..b74cff06f300 100644 --- a/arch/arm64/boot/dts/qcom/msm8996pro.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996pro.dtsi @@ -24,101 +24,121 @@ opp-307200000 { opp-hz =3D /bits/ 64 <307200000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <192000>; }; opp-384000000 { opp-hz =3D /bits/ 64 <384000000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <192000>; }; opp-460800000 { opp-hz =3D /bits/ 64 <460800000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <192000>; }; opp-537600000 { opp-hz =3D /bits/ 64 <537600000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <192000>; }; opp-614400000 { opp-hz =3D /bits/ 64 <614400000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <192000>; }; opp-691200000 { opp-hz =3D /bits/ 64 <691200000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <307200>; }; opp-768000000 { opp-hz =3D /bits/ 64 <768000000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <307200>; }; opp-844800000 { opp-hz =3D /bits/ 64 <844800000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <384000>; }; opp-902400000 { opp-hz =3D /bits/ 64 <902400000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <441600>; }; opp-979200000 { opp-hz =3D /bits/ 64 <979200000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <537600>; }; opp-1056000000 { opp-hz =3D /bits/ 64 <1056000000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <614400>; }; opp-1132800000 { opp-hz =3D /bits/ 64 <1132800000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <691200>; }; opp-1209600000 { opp-hz =3D /bits/ 64 <1209600000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <768000>; }; opp-1286400000 { opp-hz =3D /bits/ 64 <1286400000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <844800>; }; opp-1363200000 { opp-hz =3D /bits/ 64 <1363200000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <902400>; }; opp-1440000000 { opp-hz =3D /bits/ 64 <1440000000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <979200>; }; opp-1516800000 { opp-hz =3D /bits/ 64 <1516800000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <1132800>; }; opp-1593600000 { opp-hz =3D /bits/ 64 <1593600000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <1190400>; }; opp-1996800000 { opp-hz =3D /bits/ 64 <1996800000>; opp-supported-hw =3D <0x20>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <1516800>; }; opp-2188800000 { opp-hz =3D /bits/ 64 <2188800000>; opp-supported-hw =3D <0x10>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <1593600>; }; }; =20 @@ -131,136 +151,163 @@ opp-307200000 { opp-hz =3D /bits/ 64 <307200000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <192000>; }; opp-384000000 { opp-hz =3D /bits/ 64 <384000000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <192000>; }; opp-460800000 { opp-hz =3D /bits/ 64 <460800000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <192000>; }; opp-537600000 { opp-hz =3D /bits/ 64 <537600000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <192000>; }; opp-614400000 { opp-hz =3D /bits/ 64 <614400000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <192000>; }; opp-691200000 { opp-hz =3D /bits/ 64 <691200000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <307200>; }; opp-748800000 { opp-hz =3D /bits/ 64 <748800000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <307200>; }; opp-825600000 { opp-hz =3D /bits/ 64 <825600000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <384000>; }; opp-902400000 { opp-hz =3D /bits/ 64 <902400000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <441600>; }; opp-979200000 { opp-hz =3D /bits/ 64 <979200000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <441600>; }; opp-1056000000 { opp-hz =3D /bits/ 64 <1056000000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <537600>; }; opp-1132800000 { opp-hz =3D /bits/ 64 <1132800000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <614400>; }; opp-1209600000 { opp-hz =3D /bits/ 64 <1209600000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <691200>; }; opp-1286400000 { opp-hz =3D /bits/ 64 <1286400000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <768000>; }; opp-1363200000 { opp-hz =3D /bits/ 64 <1363200000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <844800>; }; opp-1440000000 { opp-hz =3D /bits/ 64 <1440000000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <902400>; }; opp-1516800000 { opp-hz =3D /bits/ 64 <1516800000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <979200>; }; opp-1593600000 { opp-hz =3D /bits/ 64 <1593600000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <1056000>; }; opp-1670400000 { opp-hz =3D /bits/ 64 <1670400000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <1132800>; }; opp-1747200000 { opp-hz =3D /bits/ 64 <1747200000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <1190400>; }; opp-1824000000 { opp-hz =3D /bits/ 64 <1824000000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <1286400>; }; opp-1900800000 { opp-hz =3D /bits/ 64 <1900800000>; opp-supported-hw =3D <0x70>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <1363200>; }; opp-1977600000 { opp-hz =3D /bits/ 64 <1977600000>; opp-supported-hw =3D <0x30>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <1440000>; }; opp-2054400000 { opp-hz =3D /bits/ 64 <2054400000>; opp-supported-hw =3D <0x30>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <1516800>; }; opp-2150400000 { opp-hz =3D /bits/ 64 <2150400000>; opp-supported-hw =3D <0x30>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <1593600>; }; opp-2246400000 { opp-hz =3D /bits/ 64 <2246400000>; opp-supported-hw =3D <0x10>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <1593600>; }; opp-2342400000 { opp-hz =3D /bits/ 64 <2342400000>; opp-supported-hw =3D <0x10>; clock-latency-ns =3D <200000>; + opp-peak-kBps =3D <1593600>; }; }; }; @@ -289,3 +336,7 @@ opp-560000000 { }; /* The rest is inherited from msm8996 */ }; + +&cbf { + compatible =3D "qcom,msm8996pro-cbf"; +}; --=20 2.40.0 From nobody Wed Feb 11 20:58:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31687C77B78 for ; Wed, 3 May 2023 13:02:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230119AbjECNCR (ORCPT ); Wed, 3 May 2023 09:02:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229914AbjECNCI (ORCPT ); Wed, 3 May 2023 09:02:08 -0400 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F3615598; Wed, 3 May 2023 06:02:06 -0700 (PDT) Received: by mail-ed1-x530.google.com with SMTP id 4fb4d7f45d1cf-50b8d2eed3dso7032850a12.0; Wed, 03 May 2023 06:02:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683118925; x=1685710925; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5l3X/5LryvYFHFoYM7ZoZSis1FJRQH3TBUtUCR1RoIw=; b=C9oigbNw++3UxAZ996YgdeW6OPwWtTmRLof1HURqz2YTaDfs768reIjTMvEVEuYABp DzOeyVzF2mR1EKeUllpy5Y9CCI4n6j8UkXyTm8R1DoEv5ATqA2BUOAlYZDQk0U28scKr ZBFxrjEXn3LYEqfjlvgBajWbW4Uol5ZeljavfZ3NqzB+yv1fL6BG14hjUBk03KE87tHc mkXJaY4wLo583EtTQiZABV0IsDaCV8WEnGPBekdiPDVu13il8yVEVJ8X9n9sCc3VGiMu 0paIOzDY5HVguqSQnlS5pxws/5UIwnQHFsd28mvyNKR04nrFX7AeEVmJQmyZjiwuu4uW mJjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683118925; x=1685710925; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5l3X/5LryvYFHFoYM7ZoZSis1FJRQH3TBUtUCR1RoIw=; b=IfXeC4eMjS5dJ9j824SevH8NiYiKEly+t8broq3tp8dbnokFllmrnXoBU3vWLB3PnB ah+1wBmeE9ie5mlEgMyhjaqGkGPqmgEWkvTmAiVsWVoGzEfceJDEuODFmyLaG8DphsuS He/GX2pcZ8f0VypZ1UURIrbuwNbiNXozjX4cWYafj7lGV0PaNUBc3cjTmgtG0TV5jjeI xJFZ2+h22yI8R3O1HwyGkP+5JOOrF9q008ZxPLbzXe2q8EfpPXZoIlMkVqhzi+tIZbRO wjfJU/NT7e2yjpxyzuSq7SWWgkWlspJISrT7Yw0tkt49g1MYdh7ytc4kDSfJvo+r63Gw Iv0g== X-Gm-Message-State: AC+VfDzogz31UYXj8/loUwPG8P2h/2kzwWgsF6M3E5EovgLRwBmYT4GD VOToGLtwZQk0INTSmA38LFk= X-Google-Smtp-Source: ACHHUZ5OknE5OTyBTGKZb1lzAdQhiKHdxWR+M+MMc0367wgX2TEJ0mRMXUnVrb4obGf41yxGiwmbMw== X-Received: by 2002:a17:907:2687:b0:94f:49a2:619a with SMTP id bn7-20020a170907268700b0094f49a2619amr2637597ejc.11.1683118924571; Wed, 03 May 2023 06:02:04 -0700 (PDT) Received: from localhost.localdomain ([95.183.227.33]) by smtp.gmail.com with ESMTPSA id my17-20020a1709065a5100b0095728081944sm16105578ejc.146.2023.05.03.06.02.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 May 2023 06:02:04 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Dmitry Baryshkov Cc: Yassine Oudjana , Yassine Oudjana , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH RESEND 3/3] clk: qcom: cbf-msm8996: Add support for MSM8996 Pro Date: Wed, 3 May 2023 16:00:52 +0300 Message-Id: <20230503130051.144708-4-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230503130051.144708-1-y.oudjana@protonmail.com> References: <20230503130051.144708-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yassine Oudjana The CBF PLL on MSM8996 Pro has a /4 post divisor instead of /2. Handle the difference accordingly. Signed-off-by: Yassine Oudjana --- drivers/clk/qcom/clk-cbf-8996.c | 121 ++++++++++++++++++++++++++++---- 1 file changed, 106 insertions(+), 15 deletions(-) diff --git a/drivers/clk/qcom/clk-cbf-8996.c b/drivers/clk/qcom/clk-cbf-899= 6.c index 1bb2cd956d68..a3e96578ddd9 100644 --- a/drivers/clk/qcom/clk-cbf-8996.c +++ b/drivers/clk/qcom/clk-cbf-8996.c @@ -65,6 +65,19 @@ static const struct alpha_pll_config cbfpll_config =3D { .early_output_mask =3D BIT(3), }; =20 +static const struct alpha_pll_config cbfpll_pro_config =3D { + .l =3D 72, + .config_ctl_val =3D 0x200d4828, + .config_ctl_hi_val =3D 0x006, + .test_ctl_val =3D 0x1c000000, + .test_ctl_hi_val =3D 0x00004000, + .pre_div_mask =3D BIT(12), + .post_div_mask =3D 0x3 << 8, + .post_div_val =3D 0x3 << 8, + .main_output_mask =3D BIT(0), + .early_output_mask =3D BIT(3), +}; + static struct clk_alpha_pll cbf_pll =3D { .offset =3D CBF_PLL_OFFSET, .regs =3D cbf_pll_regs, @@ -93,6 +106,20 @@ static struct clk_fixed_factor cbf_pll_postdiv =3D { }, }; =20 +static struct clk_fixed_factor cbf_pro_pll_postdiv =3D { + .mult =3D 1, + .div =3D 4, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cbf_pll_postdiv", + .parent_hws =3D (const struct clk_hw*[]){ + &cbf_pll.clkr.hw + }, + .num_parents =3D 1, + .ops =3D &clk_fixed_factor_ops, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + static const struct clk_parent_data cbf_mux_parent_data[] =3D { { .index =3D DT_XO }, { .hw =3D &cbf_pll.clkr.hw }, @@ -100,6 +127,13 @@ static const struct clk_parent_data cbf_mux_parent_dat= a[] =3D { { .index =3D DT_APCS_AUX }, }; =20 +static const struct clk_parent_data cbf_pro_mux_parent_data[] =3D { + { .index =3D DT_XO }, + { .hw =3D &cbf_pll.clkr.hw }, + { .hw =3D &cbf_pro_pll_postdiv.hw }, + { .index =3D DT_APCS_AUX }, +}; + struct clk_cbf_8996_mux { u32 reg; struct notifier_block nb; @@ -140,12 +174,14 @@ static int clk_cbf_8996_mux_determine_rate(struct clk= _hw *hw, struct clk_rate_request *req) { struct clk_hw *parent; + struct clk_hw *post_div_hw =3D clk_hw_get_parent_by_index(hw, CBF_DIV_IND= EX); + struct clk_fixed_factor *post_div =3D to_clk_fixed_factor(post_div_hw); =20 - if (req->rate < (DIV_THRESHOLD / 2)) + if (req->rate < (DIV_THRESHOLD / post_div->div)) return -EINVAL; =20 if (req->rate < DIV_THRESHOLD) - parent =3D clk_hw_get_parent_by_index(hw, CBF_DIV_INDEX); + parent =3D post_div_hw; else parent =3D clk_hw_get_parent_by_index(hw, CBF_PLL_INDEX); =20 @@ -177,10 +213,24 @@ static struct clk_cbf_8996_mux cbf_mux =3D { }, }; =20 +static struct clk_cbf_8996_mux cbf_pro_mux =3D { + .reg =3D CBF_MUX_OFFSET, + .nb.notifier_call =3D cbf_clk_notifier_cb, + .clkr.hw.init =3D &(struct clk_init_data) { + .name =3D "cbf_mux", + .parent_data =3D cbf_pro_mux_parent_data, + .num_parents =3D ARRAY_SIZE(cbf_pro_mux_parent_data), + .ops =3D &clk_cbf_8996_mux_ops, + /* CPU clock is critical and should never be gated */ + .flags =3D CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + }, +}; + static int cbf_clk_notifier_cb(struct notifier_block *nb, unsigned long ev= ent, void *data) { struct clk_notifier_data *cnd =3D data; + struct clk_hw *hw =3D __clk_get_hw(cnd->clk); =20 switch (event) { case PRE_RATE_CHANGE: @@ -188,19 +238,19 @@ static int cbf_clk_notifier_cb(struct notifier_block = *nb, unsigned long event, * Avoid overvolting. clk_core_set_rate_nolock() walks from top * to bottom, so it will change the rate of the PLL before * chaging the parent of PMUX. This can result in pmux getting - * clocked twice the expected rate. + * clocked twice (or 4 times) the expected rate. * - * Manually switch to PLL/2 here. + * Manually switch to PLL/DIV here. */ if (cnd->old_rate > DIV_THRESHOLD && cnd->new_rate < DIV_THRESHOLD) - clk_cbf_8996_mux_set_parent(&cbf_mux.clkr.hw, CBF_DIV_INDEX); + clk_cbf_8996_mux_set_parent(hw, CBF_DIV_INDEX); break; case ABORT_RATE_CHANGE: /* Revert manual change */ if (cnd->new_rate < DIV_THRESHOLD && cnd->old_rate > DIV_THRESHOLD) - clk_cbf_8996_mux_set_parent(&cbf_mux.clkr.hw, CBF_PLL_INDEX); + clk_cbf_8996_mux_set_parent(hw, CBF_PLL_INDEX); break; default: break; @@ -213,11 +263,50 @@ static struct clk_hw *cbf_msm8996_hw_clks[] =3D { &cbf_pll_postdiv.hw, }; =20 +static struct clk_hw *cbf_msm8996pro_hw_clks[] =3D { + &cbf_pro_pll_postdiv.hw, +}; + static struct clk_regmap *cbf_msm8996_clks[] =3D { &cbf_pll.clkr, &cbf_mux.clkr, }; =20 +static struct clk_regmap *cbf_msm8996pro_clks[] =3D { + &cbf_pll.clkr, + &cbf_pro_mux.clkr, +}; + +struct cbf_match_data { + const struct alpha_pll_config *config; + struct clk_fixed_factor *cbf_pll_postdiv; + struct clk_cbf_8996_mux *cbf_mux; + struct clk_hw **hw_clks; + size_t nr_hw_clks; + struct clk_regmap **clks; + size_t nr_clks; +}; + +static const struct cbf_match_data cbf_msm8996_match_data =3D { + .config =3D &cbfpll_config, + .cbf_pll_postdiv =3D &cbf_pll_postdiv, + .cbf_mux =3D &cbf_mux, + .hw_clks =3D cbf_msm8996_hw_clks, + .nr_hw_clks =3D ARRAY_SIZE(cbf_msm8996_hw_clks), + .clks =3D cbf_msm8996_clks, + .nr_clks =3D ARRAY_SIZE(cbf_msm8996_clks) +}; + +static const struct cbf_match_data cbf_msm8996pro_match_data =3D { + .config =3D &cbfpll_pro_config, + .cbf_pll_postdiv =3D &cbf_pro_pll_postdiv, + .cbf_mux =3D &cbf_pro_mux, + .hw_clks =3D cbf_msm8996pro_hw_clks, + .nr_hw_clks =3D ARRAY_SIZE(cbf_msm8996pro_hw_clks), + .clks =3D cbf_msm8996pro_clks, + .nr_clks =3D ARRAY_SIZE(cbf_msm8996pro_clks) +}; + static const struct regmap_config cbf_msm8996_regmap_config =3D { .reg_bits =3D 32, .reg_stride =3D 4, @@ -274,6 +363,7 @@ static int qcom_msm8996_cbf_probe(struct platform_devic= e *pdev) void __iomem *base; struct regmap *regmap; struct device *dev =3D &pdev->dev; + const struct cbf_match_data *data =3D of_device_get_match_data(dev); int i, ret; =20 base =3D devm_platform_ioremap_resource(pdev, 0); @@ -295,7 +385,7 @@ static int qcom_msm8996_cbf_probe(struct platform_devic= e *pdev) CBF_MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK, CBF_MUX_AUTO_CLK_SEL_ALWAYS_ON_GPLL0_SEL); =20 - clk_alpha_pll_configure(&cbf_pll, regmap, &cbfpll_config); + clk_alpha_pll_configure(&cbf_pll, regmap, data->config); =20 /* Wait for PLL(s) to lock */ udelay(50); @@ -311,27 +401,27 @@ static int qcom_msm8996_cbf_probe(struct platform_dev= ice *pdev) /* Switch CBF to use the primary PLL */ regmap_update_bits(regmap, CBF_MUX_OFFSET, CBF_MUX_PARENT_MASK, 0x1); =20 - for (i =3D 0; i < ARRAY_SIZE(cbf_msm8996_hw_clks); i++) { - ret =3D devm_clk_hw_register(dev, cbf_msm8996_hw_clks[i]); + for (i =3D 0; i < data->nr_hw_clks; i++) { + ret =3D devm_clk_hw_register(dev, data->hw_clks[i]); if (ret) return ret; } =20 - for (i =3D 0; i < ARRAY_SIZE(cbf_msm8996_clks); i++) { - ret =3D devm_clk_register_regmap(dev, cbf_msm8996_clks[i]); + for (i =3D 0; i < data->nr_clks; i++) { + ret =3D devm_clk_register_regmap(dev, data->clks[i]); if (ret) return ret; } =20 - ret =3D devm_clk_notifier_register(dev, cbf_mux.clkr.hw.clk, &cbf_mux.nb); + ret =3D devm_clk_notifier_register(dev, data->cbf_mux->clkr.hw.clk, &data= ->cbf_mux->nb); if (ret) return ret; =20 - ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &cbf_mux.c= lkr.hw); + ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &data->cbf= _mux->clkr.hw); if (ret) return ret; =20 - return qcom_msm8996_cbf_icc_register(pdev, &cbf_mux.clkr.hw); + return qcom_msm8996_cbf_icc_register(pdev, &data->cbf_mux->clkr.hw); } =20 static int qcom_msm8996_cbf_remove(struct platform_device *pdev) @@ -340,7 +430,8 @@ static int qcom_msm8996_cbf_remove(struct platform_devi= ce *pdev) } =20 static const struct of_device_id qcom_msm8996_cbf_match_table[] =3D { - { .compatible =3D "qcom,msm8996-cbf" }, + { .compatible =3D "qcom,msm8996-cbf", .data =3D &cbf_msm8996_match_data }, + { .compatible =3D "qcom,msm8996pro-cbf", .data =3D &cbf_msm8996pro_match_= data }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, qcom_msm8996_cbf_match_table); --=20 2.40.0