From nobody Thu Dec 18 22:29:59 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05EACC19F20 for ; Tue, 2 May 2023 22:43:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230093AbjEBWnB (ORCPT ); Tue, 2 May 2023 18:43:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59244 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230193AbjEBWmi (ORCPT ); Tue, 2 May 2023 18:42:38 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B48123A94 for ; Tue, 2 May 2023 15:42:06 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-b9a7e76b32bso5497231276.1 for ; Tue, 02 May 2023 15:42:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067322; x=1685659322; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=06KK258ohGmPy18JQ9TrkKPYNxfE1W3HUyTXp1S5eNw=; b=Eegnm+Ud+T3KzRhrDomrI/LmuJqDU6lDnIFlVaApkKJiUonjsaga4DSnbLzD0nikyb vJ77E/ZvHl8IXk4251xnejdH0r+ba8suAfsNyCOVcjTerjTw2VaCDi5zwSYOQKUoBqgG iXcNWF1SljSCcsiE7yXB+beM0LGwABWQELwd7ILjppjdDwz3hVfTv4DJH2QzXZCQXrH5 QkdYr58Cp0jQtfZezoctXyb5yQS6rl5/JEmqGZvsqXzUnZx1hFy2uTDPQO16NnFlG5Eo M4RBgWIzM1hf0XHzhkOcfVOj5tn92mskKjidxJNNyb1HQPtJNn/eGae4f56lPEKdTjIS pwbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067322; x=1685659322; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=06KK258ohGmPy18JQ9TrkKPYNxfE1W3HUyTXp1S5eNw=; b=W9jnq4kVSpRr7+zqfQFwpAe4CDXNYW53Z6rqHhHnRuoHmhoCm0T00SZ6CkcPcAN87z CTLsQqvnCLv/j3YGIqg7H6+iyyPT5IrXVuo0OIbb2Q0MB180uqp3RKwVh4uu1a8/QhCP mkcGebBhIA6iyk6LqbBH9JKXVy6gGMjrmx4l5s51kLuYefknUUNEe7RdIsMwbOBMQPLX IiMGJlpYX1tMvMF/yNjIGFzBWINGDzbkcnq8Ban9J+4JJNezxMnPPzi08OPCEy4RdQMJ MzlTbEmLhgZPW69kB+dUMLnm4AO182tS2jsw3Pte1Ppe+jVD1W6ierjEsN+QKqL6vpB0 GaNg== X-Gm-Message-State: AC+VfDyXvZk6gRqAzAF9z4v6x8Rl9tRL2t8D+uC6A5ppRk8tfiqJxgx3 JAcH/F5HDA5YNKmH68LbvdYg0LH41YUL X-Google-Smtp-Source: ACHHUZ5d2g0A2W2z8Cq0XUOkQDUDIkOeFEZnBj+oEpo2d8DNoeRTAeNgglNP5ds2O8WnL9cPvXe5W4SzclDY X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a05:6902:1003:b0:b8f:54f5:89ff with SMTP id w3-20020a056902100300b00b8f54f589ffmr12028554ybt.11.1683067322093; Tue, 02 May 2023 15:42:02 -0700 (PDT) Date: Tue, 2 May 2023 15:38:30 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-24-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 23/44] perf parse-events: Support PMUs for legacy cache events From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allow a legacy cache event to be both, for example, "L1-dcache-load-miss" and "cpu/L1-dcache-load-miss/" by introducing a new legacy cache term type. The term type is processed in config_term_pmu, setting both the type in perf_event_attr and the config. The code to determine the config is factored out of parse_events_add_cache and shared. If the PMU doesn't support legacy events, currently just core/hybrid PMUs do, then the term is treated like a PE_NAME term - as before. If only terms are being parsed, such as for perf_pmu__new_alias, then the PE_LEGACY_CACHE token is always parsed as PE_NAME. Signed-off-by: Ian Rogers --- tools/perf/tests/parse-events.c | 18 +++++++++ tools/perf/util/parse-events.c | 70 ++++++++++++++++++++++----------- tools/perf/util/parse-events.h | 3 ++ tools/perf/util/parse-events.l | 9 ++++- tools/perf/util/parse-events.y | 14 ++++++- tools/perf/util/pmu.c | 5 +++ tools/perf/util/pmu.h | 1 + 7 files changed, 96 insertions(+), 24 deletions(-) diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index 43c0778983e5..c3afd0b129bb 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -1875,6 +1875,24 @@ static const struct evlist_test test__events_pmu[] = =3D { .check =3D test__checkevent_raw_pmu, /* 5 */ }, + { + .name =3D "cpu/L1-dcache-load-miss/", + .valid =3D test__pmu_cpu_valid, + .check =3D test__checkevent_genhw, + /* 6 */ + }, + { + .name =3D "cpu/L1-dcache-load-miss/kp", + .valid =3D test__pmu_cpu_valid, + .check =3D test__checkevent_genhw_modifier, + /* 7 */ + }, + { + .name =3D "cpu/L1-dcache-misses,name=3Dcachepmu/", + .valid =3D test__pmu_cpu_valid, + .check =3D test__checkevent_config_cache, + /* 8 */ + }, }; =20 struct terms_test { diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index b5d95fce520c..f692dd953593 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -404,33 +404,27 @@ static int config_attr(struct perf_event_attr *attr, struct parse_events_error *err, config_term_func_t config_term); =20 -int parse_events_add_cache(struct list_head *list, int *idx, const char *n= ame, - struct parse_events_error *err, - struct list_head *head_config, - struct parse_events_state *parse_state) +/** + * parse_events__decode_legacy_cache - Search name for the legacy cache ev= ent + * name composed of 1, 2 or 3 hyphen + * separated sections. The first secti= on is + * the cache type while the others are= the + * optional op and optional result. To= make + * life hard the names in the table al= so + * contain hyphens and the longest name + * should always be selected. + */ +static int parse_events__decode_legacy_cache(const char *name, int pmu_typ= e, __u64 *config) { - struct perf_event_attr attr; - LIST_HEAD(config_terms); - const char *config_name, *metric_id; - int cache_type =3D -1, cache_op =3D -1, cache_result =3D -1; - int ret, len; + int len, cache_type =3D -1, cache_op =3D -1, cache_result =3D -1; const char *name_end =3D &name[strlen(name) + 1]; - bool hybrid; const char *str =3D name; =20 - /* - * Search str for the legacy cache event name composed of 1, 2 or 3 - * hyphen separated sections. The first section is the cache type while - * the others are the optional op and optional result. To make life hard - * the names in the table also contain hyphens and the longest name - * should always be selected. - */ cache_type =3D parse_aliases(str, evsel__hw_cache, PERF_COUNT_HW_CACHE_MA= X, &len); if (cache_type =3D=3D -1) return -EINVAL; str +=3D len + 1; =20 - config_name =3D get_config_name(head_config); if (str < name_end) { cache_op =3D parse_aliases(str, evsel__hw_cache_op, PERF_COUNT_HW_CACHE_OP_MAX, &len); @@ -471,9 +465,28 @@ int parse_events_add_cache(struct list_head *list, int= *idx, const char *name, if (cache_result =3D=3D -1) cache_result =3D PERF_COUNT_HW_CACHE_RESULT_ACCESS; =20 + *config =3D ((__u64)pmu_type << PERF_PMU_TYPE_SHIFT) | + cache_type | (cache_op << 8) | (cache_result << 16); + return 0; +} + +int parse_events_add_cache(struct list_head *list, int *idx, const char *n= ame, + struct parse_events_error *err, + struct list_head *head_config, + struct parse_events_state *parse_state) +{ + struct perf_event_attr attr; + LIST_HEAD(config_terms); + const char *config_name, *metric_id; + int ret; + bool hybrid; + + memset(&attr, 0, sizeof(attr)); - attr.config =3D cache_type | (cache_op << 8) | (cache_result << 16); attr.type =3D PERF_TYPE_HW_CACHE; + ret =3D parse_events__decode_legacy_cache(name, /*pmu_type=3D*/0, &attr.c= onfig); + if (ret) + return ret; =20 if (head_config) { if (config_attr(&attr, head_config, err, @@ -484,6 +497,7 @@ int parse_events_add_cache(struct list_head *list, int = *idx, const char *name, return -ENOMEM; } =20 + config_name =3D get_config_name(head_config); metric_id =3D get_config_metric_id(head_config); ret =3D parse_events__add_cache_hybrid(list, idx, &attr, config_name ? : name, @@ -1022,6 +1036,7 @@ static const char *config_term_names[__PARSE_EVENTS__= TERM_TYPE_NR] =3D { [PARSE_EVENTS__TERM_TYPE_AUX_SAMPLE_SIZE] =3D "aux-sample-size", [PARSE_EVENTS__TERM_TYPE_METRIC_ID] =3D "metric-id", [PARSE_EVENTS__TERM_TYPE_RAW] =3D "raw", + [PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE] =3D "legacy-cache", }; =20 static bool config_term_shrinked; @@ -1199,15 +1214,25 @@ static int config_term_pmu(struct perf_event_attr *= attr, struct parse_events_term *term, struct parse_events_error *err) { + if (term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE) { + const struct perf_pmu *pmu =3D perf_pmu__find_by_type(attr->type); + + if (perf_pmu__supports_legacy_cache(pmu)) { + attr->type =3D PERF_TYPE_HW_CACHE; + return parse_events__decode_legacy_cache(term->config, pmu->type, + &attr->config); + } else + term->type_term =3D PARSE_EVENTS__TERM_TYPE_USER; + } if (term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_USER || - term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_DRV_CFG) + term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_DRV_CFG) { /* * Always succeed for sysfs terms, as we dont know * at this point what type they need to have. */ return 0; - else - return config_term_common(attr, term, err); + } + return config_term_common(attr, term, err); } =20 #ifdef HAVE_LIBTRACEEVENT @@ -2147,6 +2172,7 @@ int __parse_events(struct evlist *evlist, const char = *str, .evlist =3D evlist, .stoken =3D PE_START_EVENTS, .fake_pmu =3D fake_pmu, + .match_legacy_cache_terms =3D true, }; int ret; =20 diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index f638542c8638..5acb62c2e00a 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -71,6 +71,7 @@ enum { PARSE_EVENTS__TERM_TYPE_AUX_SAMPLE_SIZE, PARSE_EVENTS__TERM_TYPE_METRIC_ID, PARSE_EVENTS__TERM_TYPE_RAW, + PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE, __PARSE_EVENTS__TERM_TYPE_NR, }; =20 @@ -122,6 +123,8 @@ struct parse_events_state { int stoken; struct perf_pmu *fake_pmu; char *hybrid_pmu_name; + /* Should PE_LEGACY_NAME tokens be generated for config terms? */ + bool match_legacy_cache_terms; bool wild_card_pmus; }; =20 diff --git a/tools/perf/util/parse-events.l b/tools/perf/util/parse-events.l index 4b35c099189a..abe0ce681d29 100644 --- a/tools/perf/util/parse-events.l +++ b/tools/perf/util/parse-events.l @@ -63,6 +63,11 @@ static int str(yyscan_t scanner, int token) return token; } =20 +static int lc_str(yyscan_t scanner, const struct parse_events_state *state) +{ + return str(scanner, state->match_legacy_cache_terms ? PE_LEGACY_CACHE : P= E_NAME); +} + static bool isbpf_suffix(char *text) { int len =3D strlen(text); @@ -185,7 +190,6 @@ lc_op_result (load|loads|read|store|stores|write|prefet= ch|prefetches|speculative =20 %{ struct parse_events_state *_parse_state =3D parse_events_get_extra(yyscan= ner); - { int start_token =3D _parse_state->stoken; =20 @@ -269,6 +273,9 @@ r{num_raw_hex} { return str(yyscanner, PE_RAW); } r0x{num_raw_hex} { return str(yyscanner, PE_RAW); } , { return ','; } "/" { BEGIN(INITIAL); return '/'; } +{lc_type} { return lc_str(yyscanner, _parse_state); } +{lc_type}-{lc_op_result} { return lc_str(yyscanner, _parse_state); } +{lc_type}-{lc_op_result}-{lc_op_result} { return lc_str(yyscanner, _parse_= state); } {name_minus} { return str(yyscanner, PE_NAME); } \[all\] { return PE_ARRAY_ALL; } "[" { BEGIN(array); return '['; } diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y index e7072b5601c5..f84fa1b132b3 100644 --- a/tools/perf/util/parse-events.y +++ b/tools/perf/util/parse-events.y @@ -723,7 +723,7 @@ event_term $$ =3D head; } =20 -name_or_raw: PE_RAW | PE_NAME +name_or_raw: PE_RAW | PE_NAME | PE_LEGACY_CACHE =20 event_term: PE_RAW @@ -775,6 +775,18 @@ name_or_raw '=3D' PE_VALUE_SYM_HW $$ =3D term; } | +PE_LEGACY_CACHE +{ + struct parse_events_term *term; + + if (parse_events_term__num(&term, PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE, + $1, 1, true, &@1, NULL)) { + free($1); + YYABORT; + } + $$ =3D term; +} +| PE_NAME { struct parse_events_term *term; diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index cb33d869f1ed..63071d876190 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -1650,6 +1650,11 @@ bool is_pmu_core(const char *name) return !strcmp(name, "cpu") || is_arm_pmu_core(name); } =20 +bool perf_pmu__supports_legacy_cache(const struct perf_pmu *pmu) +{ + return is_pmu_core(pmu->name) || perf_pmu__is_hybrid(pmu->name); +} + static bool pmu_alias_is_duplicate(struct sevent *alias_a, struct sevent *alias_b) { diff --git a/tools/perf/util/pmu.h b/tools/perf/util/pmu.h index b9a02dedd473..05702bc4bcf8 100644 --- a/tools/perf/util/pmu.h +++ b/tools/perf/util/pmu.h @@ -220,6 +220,7 @@ void perf_pmu__del_formats(struct list_head *formats); struct perf_pmu *perf_pmu__scan(struct perf_pmu *pmu); =20 bool is_pmu_core(const char *name); +bool perf_pmu__supports_legacy_cache(const struct perf_pmu *pmu); void print_pmu_events(const struct print_callbacks *print_cb, void *print_= state); bool pmu_have_event(const char *pname, const char *name); =20 --=20 2.40.1.495.gc816e09b53d-goog