From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B576C77B75 for ; Tue, 2 May 2023 22:39:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229915AbjEBWjT (ORCPT ); Tue, 2 May 2023 18:39:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55326 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229911AbjEBWjQ (ORCPT ); Tue, 2 May 2023 18:39:16 -0400 Received: from mail-pl1-x649.google.com (mail-pl1-x649.google.com [IPv6:2607:f8b0:4864:20::649]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A27F12D74 for ; Tue, 2 May 2023 15:39:14 -0700 (PDT) Received: by mail-pl1-x649.google.com with SMTP id d9443c01a7336-1ab07423559so9575915ad.3 for ; Tue, 02 May 2023 15:39:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067154; x=1685659154; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=h10TGNBRB+swYQLldhqIixkznDBQsILm/HEqOr0YFfQ=; b=yYeNw6rrDXtRTtstKxgcQ/8z/3UzTNAFcKVoOAyBjspBXMBO0280ONt3OEZQqCcqjn Uwz14ZbYkRZ8poP7bXJm/CQtUujNMn0OQ3hQS4OPRhGIVV0kKDMNTF2IybxRnraKTv4N i/VWPPJaKm8JaWLKANQMq3foxEYe11qfksY81IxJrTwSXT/FN6JZffVFUa+Acwg95bva VQpdyjMTNTkRCowm1pbWH2ay14pPe974KC0ZNstH45sYtJjLIBZoDIOh0A4hnPtZzmlL lREJuzVfQQt6j0+JJn9/5P3WH/TbbWwUTcYK54VpD9pNbXJTAQFwo293BzYxwMF7kscE MBeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067154; x=1685659154; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=h10TGNBRB+swYQLldhqIixkznDBQsILm/HEqOr0YFfQ=; b=VZ3FVkJ9HojUIUclHVr808Z7JEJ3NKg13oCPDzJxp/NokMqXg4qO8DEBLlk7w6wUE3 xNZSkUJWPKur5Y22gDfZ5gnhoiCRsGq9DRn0yXZklH7GlDh1jN5OWE4x7ii8/BUnRMMX v+xJPE5mMDPmsWB1S4FXkoYOfQH0zEil6Nrmb68fdO2+oUOpCTs5+D/4VR56/yosj2om awMrUliswnhWhCDPK1UMncpJbQqGacrNbOmlzNplf/DtRx6j6NNkmCLoRarLicUNgoaS QC5SYkiUQMbbDceH1fZCtoj9TYqDtEQIRH+g3i0E7deLr7xt8yCaN44PJ2pgQNPYobAV pqPg== X-Gm-Message-State: AC+VfDyuxSfDBuNE5LIsSzgo8+P0BUMEyw6daHM1kowluTrfvBBASYhe uTh1XyOXxmY7KnKF+8JUa8G0XjlwDgpe X-Google-Smtp-Source: ACHHUZ47hifw5kvjgdhe0rDUe3579g8BZgsdKW6Wmz2s+UmPoufmfiO1wLZGgHZDvdlaI0qZZVy319SeCR1h X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a17:903:492:b0:1a2:8940:6db0 with SMTP id jj18-20020a170903049200b001a289406db0mr11798plb.13.1683067154077; Tue, 02 May 2023 15:39:14 -0700 (PDT) Date: Tue, 2 May 2023 15:38:08 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-2-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 01/44] perf metric: Change divide by zero and !support events behavior From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Division by zero causes expression parsing to fail and no metric to be generated. This can mean for short running benchmarks metrics are not shown. Change the behavior to make the value nan, which gets shown like: ''' $ perf stat -M TopdownL2 true Performance counter stats for 'true': 1,031,492 INST_RETIRED.ANY # nan % tma_= fetch_bandwidth # nan % tma_heavy_o= perations # nan % tma_light_o= perations 29,304 CPU_CLK_UNHALTED.REF_XCLK # nan % tma_= fetch_latency # nan % tma_branch_= mispredicts # nan % tma_machine= _clears # nan % tma_core_bo= und # nan % tma_memory_= bound 2,658,319 IDQ_UOPS_NOT_DELIVERED.CORE 11,167 EXE_ACTIVITY.BOUND_ON_STORES 262,058 EXE_ACTIVITY.1_PORTS_UTIL BR_MISP_RETIRED.ALL_BRANCHES = (0.00%) INT_MISC.RECOVERY_CYCLES_ANY = (0.00%) CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE = (0.00%) CPU_CLK_UNHALTED.THREAD = (0.00%) UOPS_RETIRED.RETIRE_SLOTS = (0.00%) CYCLE_ACTIVITY.STALLS_MEM_ANY = (0.00%) UOPS_RETIRED.MACRO_FUSED = (0.00%) IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE = (0.00%) EXE_ACTIVITY.2_PORTS_UTIL = (0.00%) CYCLE_ACTIVITY.STALLS_TOTAL = (0.00%) MACHINE_CLEARS.COUNT = (0.00%) UOPS_ISSUED.ANY = (0.00%) 0.002864879 seconds time elapsed 0.003012000 seconds user 0.000000000 seconds sys ''' When events aren't supported a count of 0 can be confusing and make metrics look meaningful. Change these to be nan also which, with the next change, gets shown like: ''' $ perf stat true Performance counter stats for 'true': 1.25 msec task-clock:u # 0.387 CPUs ut= ilized 0 context-switches:u # 0.000 /sec 0 cpu-migrations:u # 0.000 /sec 46 page-faults:u # 36.702 K/sec 255,942 cycles:u # 0.204 GHz = (88.66%) 123,046 instructions:u # 0.48 insn pe= r cycle 28,301 branches:u # 22.580 M/sec 2,489 branch-misses:u # 8.79% of all = branches 4,719 CPU_CLK_UNHALTED.REF_XCLK:u # 3.765 M/sec # nan % tma_fronten= d_bound # nan % tma_retiring # nan % tma_backend= _bound # nan % tma_bad_spe= culation 344,855 IDQ_UOPS_NOT_DELIVERED.CORE:u # 275.147 M/sec INT_MISC.RECOVERY_CYCLES_ANY:u CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE:u = (0.00%) CPU_CLK_UNHALTED.THREAD:u = (0.00%) UOPS_RETIRED.RETIRE_SLOTS:u = (0.00%) UOPS_ISSUED.ANY:u = (0.00%) 0.003238142 seconds time elapsed 0.000000000 seconds user 0.003434000 seconds sys ''' Ensure that nan metric values are quoted as nan isn't a valid number in json. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/tests/expr.c | 3 ++- tools/perf/tests/parse-metric.c | 1 + tools/perf/util/expr.y | 6 +++++- tools/perf/util/stat-display.c | 2 +- tools/perf/util/stat-shadow.c | 25 +++++++++++++++++++------ 5 files changed, 28 insertions(+), 9 deletions(-) diff --git a/tools/perf/tests/expr.c b/tools/perf/tests/expr.c index cbf0e0c74906..733ead151c63 100644 --- a/tools/perf/tests/expr.c +++ b/tools/perf/tests/expr.c @@ -120,7 +120,8 @@ static int test__expr(struct test_suite *t __maybe_unus= ed, int subtest __maybe_u =20 p =3D "FOO/0"; ret =3D expr__parse(&val, ctx, p); - TEST_ASSERT_VAL("division by zero", ret =3D=3D -1); + TEST_ASSERT_VAL("division by zero", ret =3D=3D 0); + TEST_ASSERT_VAL("division by zero", isnan(val)); =20 p =3D "BAR/"; ret =3D expr__parse(&val, ctx, p); diff --git a/tools/perf/tests/parse-metric.c b/tools/perf/tests/parse-metri= c.c index 1185b79e6274..c05148ea400c 100644 --- a/tools/perf/tests/parse-metric.c +++ b/tools/perf/tests/parse-metric.c @@ -38,6 +38,7 @@ static void load_runtime_stat(struct evlist *evlist, stru= ct value *vals) evlist__alloc_aggr_stats(evlist, 1); evlist__for_each_entry(evlist, evsel) { count =3D find_value(evsel->name, vals); + evsel->supported =3D true; evsel->stats->aggr->counts.val =3D count; if (evsel__name_is(evsel, "duration_time")) update_stats(&walltime_nsecs_stats, count); diff --git a/tools/perf/util/expr.y b/tools/perf/util/expr.y index 250e444bf032..4ce931cccb63 100644 --- a/tools/perf/util/expr.y +++ b/tools/perf/util/expr.y @@ -225,7 +225,11 @@ expr: NUMBER { if (fpclassify($3.val) =3D=3D FP_ZERO) { pr_debug("division by zero\n"); - YYABORT; + assert($3.ids =3D=3D NULL); + if (compute_ids) + ids__free($1.ids); + $$.val =3D NAN; + $$.ids =3D NULL; } else if (!compute_ids || (is_const($1.val) && is_const($3.val))) { assert($1.ids =3D=3D NULL); assert($3.ids =3D=3D NULL); diff --git a/tools/perf/util/stat-display.c b/tools/perf/util/stat-display.c index 73b2ff2ddf29..bf5a6c14dfcd 100644 --- a/tools/perf/util/stat-display.c +++ b/tools/perf/util/stat-display.c @@ -431,7 +431,7 @@ static void print_metric_json(struct perf_stat_config *= config __maybe_unused, struct outstate *os =3D ctx; FILE *out =3D os->fh; =20 - fprintf(out, "\"metric-value\" : %f, ", val); + fprintf(out, "\"metric-value\" : \"%f\", ", val); fprintf(out, "\"metric-unit\" : \"%s\"", unit); if (!config->metric_only) fprintf(out, "}"); diff --git a/tools/perf/util/stat-shadow.c b/tools/perf/util/stat-shadow.c index eeccab6751d7..1566a206ba42 100644 --- a/tools/perf/util/stat-shadow.c +++ b/tools/perf/util/stat-shadow.c @@ -403,12 +403,25 @@ static int prepare_metric(struct evsel **metric_event= s, if (!aggr) break; =20 - /* - * If an event was scaled during stat gathering, reverse - * the scale before computing the metric. - */ - val =3D aggr->counts.val * (1.0 / metric_events[i]->scale); - source_count =3D evsel__source_count(metric_events[i]); + if (!metric_events[i]->supported) { + /* + * Not supported events will have a count of 0, + * which can be confusing in a + * metric. Explicitly set the value to NAN. Not + * counted events (enable time of 0) are read as + * 0. + */ + val =3D NAN; + source_count =3D 0; + } else { + /* + * If an event was scaled during stat gathering, + * reverse the scale before computing the + * metric. + */ + val =3D aggr->counts.val * (1.0 / metric_events[i]->scale); + source_count =3D evsel__source_count(metric_events[i]); + } } n =3D strdup(evsel__metric_id(metric_events[i])); if (!n) --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48111C77B75 for ; Tue, 2 May 2023 22:39:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229911AbjEBWjc (ORCPT ); Tue, 2 May 2023 18:39:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55676 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229914AbjEBWj3 (ORCPT ); Tue, 2 May 2023 18:39:29 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9672330EF for ; Tue, 2 May 2023 15:39:23 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-b9a6f15287eso552930276.1 for ; Tue, 02 May 2023 15:39:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067162; x=1685659162; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=3DVy621GYiHB+6fU/268WLthwNlggN6c1xnlL0X7vU8=; b=F6p59By143t7B3onb48y5PrfMz0WvsnIWHgCmD9MSxEWtEoyWMZBByqL8R6C+3OA+6 GYmETQATKFApIE3MqIC3PpZSbayv4fLLr5HSedHZKt+vl49KkesehX9831R2t7hBR12M p3PLLquC+0/l7r56IqqF/iE8M13faTyrWpUrOLh4XFHIIHjkJV1eW5L2JewOM8VBAOca n8pGb4GlejDAL/Um+ht/lPCtrgM/fCHSkkRXcBkvGO6b+Lq/CBKPHUn7t57NYpFHtvJ6 O0rA+gv5ki5084ux2LkRMoyYOJl7zmsri5HMJETxlsbcSUojA3Z8R0tJkVi6x9IUmi8l 69Cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067162; x=1685659162; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=3DVy621GYiHB+6fU/268WLthwNlggN6c1xnlL0X7vU8=; b=Y2Kh1TH7RCoClkubfYBmC3ACgu70WD/aPEkxwod/b1x7syKQhhvniYRmULy63RGYZf DGYCc3aj6yEOs9+Kg1Q3RFw4gi63+cKdrv3tlKhOESaqIuCDzd/wH5fQegS+jHBqs1LU NukzijplC/Fm5AOZ0yX52KHLdioMgfDUYnZfm7jPEFs/mdVu3DX4UZQRfqlx1oynpS/B sQ+fflW4XVGls71+GXsFlSyB09Kd7DOVjw0pxrK9Xd+o+jZIOQ9map6XRPGsxLfMaK3t zN2tsZa4FHtKhwKjvDleWoXyF//yP6waiyOK6UGxkXhOmBy29VKnXQuQMsMfhyDuSGrR wrgQ== X-Gm-Message-State: AC+VfDz2uahH7mj+Pm0gQQkaaDtqBhn+4srlXix+Di1h4MmpEQCEhRML f+5jCeMwlAzpbKtjPE4rRcQ8omWr08g+ X-Google-Smtp-Source: ACHHUZ6cVYw3nZo5XIGdjainuFtVO48FoXiCiFFHyRkiYuxelQ7ivnKAP1bI1zNMiXDo9Hr9UN9E3qkTu8gh X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a05:690c:2887:b0:544:bbd2:74be with SMTP id ee7-20020a05690c288700b00544bbd274bemr84312ywb.4.1683067162600; Tue, 02 May 2023 15:39:22 -0700 (PDT) Date: Tue, 2 May 2023 15:38:09 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-3-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 02/44] perf stat: Introduce skippable evsels From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Perf stat with no arguments will use default events and metrics. These events may fail to open even with kernel and hypervisor disabled. When these fail then the permissions error appears even though they were implicitly selected. This is particularly a problem with the automatic selection of the TopdownL1 metric group on certain architectures like Skylake: ''' $ perf stat true Error: Access to performance monitoring and observability operations is limited. Consider adjusting /proc/sys/kernel/perf_event_paranoid setting to open access to performance monitoring and observability operations for processes without CAP_PERFMON, CAP_SYS_PTRACE or CAP_SYS_ADMIN Linux capability. More information can be found at 'Perf events and tool security' document: https://www.kernel.org/doc/html/latest/admin-guide/perf-security.html perf_event_paranoid setting is 2: -1: Allow use of (almost) all events by all users Ignore mlock limit after perf_event_mlock_kb without CAP_IPC_LOCK >=3D 0: Disallow raw and ftrace function tracepoint access >=3D 1: Disallow CPU event access >=3D 2: Disallow kernel profiling To make the adjusted perf_event_paranoid setting permanent preserve it in /etc/sysctl.conf (e.g. kernel.perf_event_paranoid =3D ) ''' This patch adds skippable evsels that when they fail to open won't cause termination and will appear as "" in output. The TopdownL1 events, from the metric group, are marked as skippable. This turns the failure above to: ''' $ perf stat perf bench internals synthesize Computing performance of single threaded perf event synthesis by synthesizing events on the perf process itself: Average synthesis took: 49.287 usec (+- 0.083 usec) Average num. events: 3.000 (+- 0.000) Average time per event 16.429 usec Average data synthesis took: 49.641 usec (+- 0.085 usec) Average num. events: 11.000 (+- 0.000) Average time per event 4.513 usec Performance counter stats for 'perf bench internals synthesize': 1,222.38 msec task-clock:u # 0.993 CPUs ut= ilized 0 context-switches:u # 0.000 /sec 0 cpu-migrations:u # 0.000 /sec 162 page-faults:u # 132.529 /sec 774,445,184 cycles:u # 0.634 GHz = (49.61%) 1,640,969,811 instructions:u # 2.12 insn pe= r cycle (59.67%) 302,052,148 branches:u # 247.102 M/sec = (59.69%) 1,807,718 branch-misses:u # 0.60% of all = branches (59.68%) 5,218,927 CPU_CLK_UNHALTED.REF_XCLK:u # 4.269 M/sec # 17.3 % tma_fronten= d_bound # 56.4 % tma_retiring # nan % tma_backend= _bound # nan % tma_bad_spe= culation (60.01%) 536,580,469 IDQ_UOPS_NOT_DELIVERED.CORE:u # 438.965 M/sec = (60.33%) INT_MISC.RECOVERY_CYCLES_ANY:u 5,223,936 CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE:u # 4.274 M/s= ec (40.31%) 774,127,250 CPU_CLK_UNHALTED.THREAD:u # 633.297 M/sec = (50.34%) 1,746,579,518 UOPS_RETIRED.RETIRE_SLOTS:u # 1.429 G/sec = (50.12%) 1,940,625,702 UOPS_ISSUED.ANY:u # 1.588 G/sec = (49.70%) 1.231055525 seconds time elapsed 0.258327000 seconds user 0.965749000 seconds sys ''' The event INT_MISC.RECOVERY_CYCLES_ANY:u is skipped as it can't be opened with paranoia 2 on Skylake. With a lower paranoia, or as root, all events/metrics are computed. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/builtin-stat.c | 38 +++++++++++++++++++++++++++++--------- tools/perf/util/evsel.c | 15 +++++++++++++-- tools/perf/util/evsel.h | 1 + 3 files changed, 43 insertions(+), 11 deletions(-) diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index be9677aa642f..ffb47b166098 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -667,6 +667,13 @@ static enum counter_recovery stat_handle_error(struct = evsel *counter) evsel_list->core.threads->err_thread =3D -1; return COUNTER_RETRY; } + } else if (counter->skippable) { + if (verbose > 0) + ui__warning("skipping event %s that kernel failed to open .\n", + evsel__name(counter)); + counter->supported =3D false; + counter->errored =3D true; + return COUNTER_SKIP; } =20 evsel__open_strerror(counter, &target, errno, msg, sizeof(msg)); @@ -1890,15 +1897,28 @@ static int add_default_attributes(void) * caused by exposing latent bugs. This is fixed properly in: * https://lore.kernel.org/lkml/bff481ba-e60a-763f-0aa0-3ee53302c480@lin= ux.intel.com/ */ - if (metricgroup__has_metric("TopdownL1") && !perf_pmu__has_hybrid() && - metricgroup__parse_groups(evsel_list, "TopdownL1", - /*metric_no_group=3D*/false, - /*metric_no_merge=3D*/false, - /*metric_no_threshold=3D*/true, - stat_config.user_requested_cpu_list, - stat_config.system_wide, - &stat_config.metric_events) < 0) - return -1; + if (metricgroup__has_metric("TopdownL1") && !perf_pmu__has_hybrid()) { + struct evlist *metric_evlist =3D evlist__new(); + struct evsel *metric_evsel; + + if (!metric_evlist) + return -1; + + if (metricgroup__parse_groups(metric_evlist, "TopdownL1", + /*metric_no_group=3D*/false, + /*metric_no_merge=3D*/false, + /*metric_no_threshold=3D*/true, + stat_config.user_requested_cpu_list, + stat_config.system_wide, + &stat_config.metric_events) < 0) + return -1; + + evlist__for_each_entry(metric_evlist, metric_evsel) { + metric_evsel->skippable =3D true; + } + evlist__splice_list_tail(evsel_list, &metric_evlist->core.entries); + evlist__delete(metric_evlist); + } =20 /* Platform specific attrs */ if (evlist__add_default_attrs(evsel_list, default_null_attrs) < 0) diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c index 356c07f03be6..1cd04b5998d2 100644 --- a/tools/perf/util/evsel.c +++ b/tools/perf/util/evsel.c @@ -290,6 +290,7 @@ void evsel__init(struct evsel *evsel, evsel->per_pkg_mask =3D NULL; evsel->collect_stat =3D false; evsel->pmu_name =3D NULL; + evsel->skippable =3D false; } =20 struct evsel *evsel__new_idx(struct perf_event_attr *attr, int idx) @@ -1725,9 +1726,13 @@ static int get_group_fd(struct evsel *evsel, int cpu= _map_idx, int thread) return -1; =20 fd =3D FD(leader, cpu_map_idx, thread); - BUG_ON(fd =3D=3D -1); + BUG_ON(fd =3D=3D -1 && !leader->skippable); =20 - return fd; + /* + * When the leader has been skipped, return -2 to distinguish from no + * group leader case. + */ + return fd =3D=3D -1 ? -2 : fd; } =20 static void evsel__remove_fd(struct evsel *pos, int nr_cpus, int nr_thread= s, int thread_idx) @@ -2109,6 +2114,12 @@ static int evsel__open_cpu(struct evsel *evsel, stru= ct perf_cpu_map *cpus, =20 group_fd =3D get_group_fd(evsel, idx, thread); =20 + if (group_fd =3D=3D -2) { + pr_debug("broken group leader for %s\n", evsel->name); + err =3D -EINVAL; + goto out_close; + } + test_attr__ready(); =20 /* Debug message used by test scripts */ diff --git a/tools/perf/util/evsel.h b/tools/perf/util/evsel.h index 35805dcdb1b9..bf8f01af1c0b 100644 --- a/tools/perf/util/evsel.h +++ b/tools/perf/util/evsel.h @@ -95,6 +95,7 @@ struct evsel { bool weak_group; bool bpf_counter; bool use_config_name; + bool skippable; int bpf_fd; struct bpf_object *bpf_obj; struct list_head config_terms; --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6411FC19F20 for ; Tue, 2 May 2023 22:39:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229973AbjEBWjw (ORCPT ); Tue, 2 May 2023 18:39:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56096 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229941AbjEBWjt (ORCPT ); Tue, 2 May 2023 18:39:49 -0400 Received: from mail-pf1-x449.google.com (mail-pf1-x449.google.com [IPv6:2607:f8b0:4864:20::449]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5EC0B30C0 for ; Tue, 2 May 2023 15:39:30 -0700 (PDT) Received: by mail-pf1-x449.google.com with SMTP id d2e1a72fcca58-64115e69e1eso453546b3a.0 for ; Tue, 02 May 2023 15:39:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067170; x=1685659170; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:from:to:cc:subject:date :message-id:reply-to; bh=d8stMu3pEgwI+YgPkaK5pHnIUWo7htcW/4QFR//BHJg=; b=kMTsttbLT/BKwv5kYtDXGEYUra61ts3tmmz5D3U2O1OftnPHWhCPHJ9KSc5B0TikvD mQHvingvAP6KEHikJD8plk0jSKfrVMpyqxNPN9Mc+ZmUvgYt+aToof+8kSmpPo/DCF64 a3d2UTL44QW15lwD1Pid/LjDqYPPlXmEMKx3VhWMw4lEld+lm5epzeND07CDf3hJurYp q9ct89cvDz5LNVWnyC/Yh29QK2xcp80FNznhuwdbmUl+8Vn/++VGmFVwDl9Uk+gxe/km okQMN+1Z8BkHV/Zhfc5JiOhdwAhrtmAkbQg/u4uU6ZQgZPXrN56uFOy8C19rwvZ57YTt OPQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067170; x=1685659170; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=d8stMu3pEgwI+YgPkaK5pHnIUWo7htcW/4QFR//BHJg=; b=W5l844No84NkFmGw3UD8w+e0iedJp8vfh+VbDhisiCpm8WRKgGJ9nLq750KsKBBU6C D1F9VMgjIbkC4FcFTdfnF3tAoo8aVWjiL9bs6l4oKWWTA8SUno1TOVBi9Fouph8ow88Y ujyx3qKJHUxGnt4GK3qnPtWK8prWwA1MrFrrhSciCl/XAa9Cbu/JmIB2jqClPFpu4o/6 omcUHoRGjGa2sNLf03NyhWpgUj2AJ6e3f9czG4ysA2+IgE0y0QxgbtVlgy3yDOPmyMAP CJzhLbzcdpVTA2Wg0oTkQaCqTDCrdYVedCPJFvgJKYz4Dzbk6YGrblvRXZ4v6ZHqEM0C gCAw== X-Gm-Message-State: AC+VfDxvr8eNuZAVpdX31XunHfi9AVnnM69CFhO7IfxMU141rUjm9lcv hVCQ+s4gKjWnT163Ag7VA42U4s2OtfdE X-Google-Smtp-Source: ACHHUZ7bK7SYPa3fDOlBOxBLfVLYSB65velTVuN3//4zaNvEbqGBv/h3YUd32XCfrnIgVQv4jSaeFt4tFhUC X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a05:6a00:2409:b0:63d:24ea:4172 with SMTP id z9-20020a056a00240900b0063d24ea4172mr69779pfh.1.1683067169889; Tue, 02 May 2023 15:39:29 -0700 (PDT) Date: Tue, 2 May 2023 15:38:10 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-4-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 03/44] perf metric: Json flag to not group events if gathering a metric group From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some metric groups have metrics that don't have fully overlapping events, meaning that the group's events become unique event groups that may need to multiplex with each other. This can be particularly unfortunate when the groups wouldn't need to multiplex because there are sufficient hardware counters. Add a flag so that if recording a metric group then the metrics within the group needn't use groups for their events. The flag is added to Intel TopdownL1 and TopdownL2 metrics. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- .../arch/x86/alderlake/adl-metrics.json | 26 +++++++++++++++++++ .../arch/x86/alderlaken/adln-metrics.json | 14 ++++++++++ .../arch/x86/broadwell/bdw-metrics.json | 12 +++++++++ .../arch/x86/broadwellde/bdwde-metrics.json | 12 +++++++++ .../arch/x86/broadwellx/bdx-metrics.json | 12 +++++++++ .../arch/x86/cascadelakex/clx-metrics.json | 12 +++++++++ .../arch/x86/haswell/hsw-metrics.json | 12 +++++++++ .../arch/x86/haswellx/hsx-metrics.json | 12 +++++++++ .../arch/x86/icelake/icl-metrics.json | 12 +++++++++ .../arch/x86/icelakex/icx-metrics.json | 12 +++++++++ .../arch/x86/ivybridge/ivb-metrics.json | 12 +++++++++ .../arch/x86/ivytown/ivt-metrics.json | 12 +++++++++ .../arch/x86/jaketown/jkt-metrics.json | 12 +++++++++ .../arch/x86/sandybridge/snb-metrics.json | 12 +++++++++ .../arch/x86/sapphirerapids/spr-metrics.json | 12 +++++++++ .../arch/x86/skylake/skl-metrics.json | 12 +++++++++ .../arch/x86/skylakex/skx-metrics.json | 12 +++++++++ .../arch/x86/tigerlake/tgl-metrics.json | 12 +++++++++ tools/perf/pmu-events/jevents.py | 4 ++- tools/perf/pmu-events/pmu-events.h | 1 + tools/perf/util/metricgroup.c | 8 +++--- 21 files changed, 240 insertions(+), 5 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json b/to= ols/perf/pmu-events/arch/x86/alderlake/adl-metrics.json index 75d80e70e5cd..1f9047553942 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json @@ -133,6 +133,7 @@ "MetricGroup": "TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "Counts the total number of issue slots that= were not consumed by the backend due to backend stalls. Note that uops mu= st be available for consumption in order for this event to count. If a uop= is not available (IQ is empty), this event will not count. The rest of t= hese subevents count backend stalls, in cycles, due to an outstanding reque= st which is memory bound vs core bound. The subevents are not slot based = events and therefore can not be precisely added or subtracted from the Back= end_Bound_Aux subevents which are slot based.", "ScaleUnit": "100%", "Unit": "cpu_atom" @@ -143,6 +144,7 @@ "MetricGroup": "TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound_aux", "MetricThreshold": "tma_backend_bound_aux > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "Counts the total number of issue slots that= were not consumed by the backend due to backend stalls. Note that UOPS mu= st be available for consumption in order for this event to count. If a uop= is not available (IQ is empty), this event will not count. All of these s= ubevents count backend stalls, in slots, due to a resource limitation. Th= ese are not cycle based events and therefore can not be precisely added or = subtracted from the Backend_Bound subevents which are cycle based. These s= ubevents are supplementary to Backend_Bound and can be used to analyze resu= lts from a resource perspective at allocation.", "ScaleUnit": "100%", "Unit": "cpu_atom" @@ -153,6 +155,7 @@ "MetricGroup": "TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "Counts the total number of issue slots that = were not consumed by the backend because allocation is stalled due to a mis= predicted jump or a machine clear. Only issue slots wasted due to fast nuke= s such as memory ordering nukes are counted. Other nukes are not accounted = for. Counts all issue slots blocked during this recovery window including r= elevant microcode flows and while uops are not yet available in the instruc= tion queue (IQ). Also includes the issue slots that were consumed by the ba= ckend but were thrown away because they were younger than the mispredict or= machine clear.", "ScaleUnit": "100%", "Unit": "cpu_atom" @@ -163,6 +166,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", "MetricName": "tma_base", "MetricThreshold": "tma_base > 0.6", + "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%", "Unit": "cpu_atom" }, @@ -182,6 +186,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.05", + "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%", "Unit": "cpu_atom" }, @@ -209,6 +214,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1", + "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%", "Unit": "cpu_atom" }, @@ -255,6 +261,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1", + "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%", "Unit": "cpu_atom" }, @@ -264,6 +271,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.15", + "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%", "Unit": "cpu_atom" }, @@ -291,6 +299,7 @@ "MetricGroup": "TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "ScaleUnit": "100%", "Unit": "cpu_atom" }, @@ -593,6 +602,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.05", + "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%", "Unit": "cpu_atom" }, @@ -611,6 +621,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2", + "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%", "Unit": "cpu_atom" }, @@ -629,6 +640,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", "MetricName": "tma_ms_uops", "MetricThreshold": "tma_ms_uops > 0.05", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "Counts the number of uops that are from the = complex flows issued by the micro-sequencer (MS). This includes uops from = flows due to complex instructions, faults, assists, and inserted flows.", "ScaleUnit": "100%", "Unit": "cpu_atom" @@ -729,6 +741,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_aux_group= ", "MetricName": "tma_resource_bound", "MetricThreshold": "tma_resource_bound > 0.2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "Counts the total number of issue slots that= were not consumed by the backend due to backend stalls. Note that uops mu= st be available for consumption in order for this event to count. If a uop= is not available (IQ is empty), this event will not count.", "ScaleUnit": "100%", "Unit": "cpu_atom" @@ -739,6 +752,7 @@ "MetricGroup": "TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.75", + "MetricgroupNoGroup": "TopdownL1", "ScaleUnit": "100%", "Unit": "cpu_atom" }, @@ -848,6 +862,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", "ScaleUnit": "100%", "Unit": "cpu_core" @@ -858,6 +873,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%", "Unit": "cpu_core" @@ -868,6 +884,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS. Related metrics: = tma_info_branch_misprediction_cost, tma_info_mispredictions, tma_mispredict= s_resteers", "ScaleUnit": "100%", "Unit": "cpu_core" @@ -919,6 +936,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%", "Unit": "cpu_core" @@ -1031,6 +1049,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 6 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", "ScaleUnit": "100%", "Unit": "cpu_core" @@ -1041,6 +1060,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_= 16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", "ScaleUnit": "100%", "Unit": "cpu_core" @@ -1121,6 +1141,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound. Sample with: FRONTE= ND_RETIRED.LATENCY_GE_4_PS", "ScaleUnit": "100%", "Unit": "cpu_core" @@ -1141,6 +1162,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences. Sample with: UOPS_RETIRED.HEA= VY", "ScaleUnit": "100%", "Unit": "cpu_core" @@ -2023,6 +2045,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%", "Unit": "cpu_core" @@ -2082,6 +2105,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sh= aring, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_c= ache", "ScaleUnit": "100%", "Unit": "cpu_core" @@ -2112,6 +2136,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%", "Unit": "cpu_core" @@ -2310,6 +2335,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .SLOTS", "ScaleUnit": "100%", "Unit": "cpu_core" diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json b/= tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json index 1a85d935c733..0402adbf7d92 100644 --- a/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json +++ b/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json @@ -98,6 +98,7 @@ "MetricGroup": "TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "Counts the total number of issue slots that= were not consumed by the backend due to backend stalls. Note that uops mu= st be available for consumption in order for this event to count. If a uop= is not available (IQ is empty), this event will not count. The rest of t= hese subevents count backend stalls, in cycles, due to an outstanding reque= st which is memory bound vs core bound. The subevents are not slot based = events and therefore can not be precisely added or subtracted from the Back= end_Bound_Aux subevents which are slot based.", "ScaleUnit": "100%" }, @@ -107,6 +108,7 @@ "MetricGroup": "TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound_aux", "MetricThreshold": "tma_backend_bound_aux > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "Counts the total number of issue slots that= were not consumed by the backend due to backend stalls. Note that UOPS mu= st be available for consumption in order for this event to count. If a uop= is not available (IQ is empty), this event will not count. All of these s= ubevents count backend stalls, in slots, due to a resource limitation. Th= ese are not cycle based events and therefore can not be precisely added or = subtracted from the Backend_Bound subevents which are cycle based. These s= ubevents are supplementary to Backend_Bound and can be used to analyze resu= lts from a resource perspective at allocation.", "ScaleUnit": "100%" }, @@ -116,6 +118,7 @@ "MetricGroup": "TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "Counts the total number of issue slots that = were not consumed by the backend because allocation is stalled due to a mis= predicted jump or a machine clear. Only issue slots wasted due to fast nuke= s such as memory ordering nukes are counted. Other nukes are not accounted = for. Counts all issue slots blocked during this recovery window including r= elevant microcode flows and while uops are not yet available in the instruc= tion queue (IQ). Also includes the issue slots that were consumed by the ba= ckend but were thrown away because they were younger than the mispredict or= machine clear.", "ScaleUnit": "100%" }, @@ -125,6 +128,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", "MetricName": "tma_base", "MetricThreshold": "tma_base > 0.6", + "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%" }, { @@ -142,6 +146,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.05", + "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%" }, { @@ -166,6 +171,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1", + "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%" }, { @@ -207,6 +213,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1", + "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%" }, { @@ -215,6 +222,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.15", + "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%" }, { @@ -239,6 +247,7 @@ "MetricGroup": "TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "ScaleUnit": "100%" }, { @@ -499,6 +508,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.05", + "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%" }, { @@ -515,6 +525,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2", + "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%" }, { @@ -531,6 +542,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", "MetricName": "tma_ms_uops", "MetricThreshold": "tma_ms_uops > 0.05", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "Counts the number of uops that are from the = complex flows issued by the micro-sequencer (MS). This includes uops from = flows due to complex instructions, faults, assists, and inserted flows.", "ScaleUnit": "100%" }, @@ -620,6 +632,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_aux_group= ", "MetricName": "tma_resource_bound", "MetricThreshold": "tma_resource_bound > 0.2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "Counts the total number of issue slots that= were not consumed by the backend due to backend stalls. Note that uops mu= st be available for consumption in order for this event to count. If a uop= is not available (IQ is empty), this event will not count.", "ScaleUnit": "100%" }, @@ -629,6 +642,7 @@ "MetricGroup": "TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.75", + "MetricgroupNoGroup": "TopdownL1", "ScaleUnit": "100%" }, { diff --git a/tools/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json b/to= ols/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json index 51cf8560a8d3..f9e2316601e1 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json @@ -103,6 +103,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound.", "ScaleUnit": "100%" }, @@ -112,6 +113,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%" }, @@ -122,6 +124,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics:= tma_info_branch_misprediction_cost, tma_mispredicts_resteers", "ScaleUnit": "100%" }, @@ -170,6 +173,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%" }, @@ -263,6 +267,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 4 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Rel= ated metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_iptb, tma_l= cp", "ScaleUnit": "100%" }, @@ -272,6 +277,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", "ScaleUnit": "100%" }, @@ -326,6 +332,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound.", "ScaleUnit": "100%" }, @@ -335,6 +342,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences.", "ScaleUnit": "100%" }, @@ -828,6 +836,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, @@ -858,6 +867,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sh= aring, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_c= ache", "ScaleUnit": "100%" }, @@ -886,6 +896,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%" }, @@ -1048,6 +1059,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .RETIRE_SLOTS", "ScaleUnit": "100%" }, diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json = b/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json index fb57c7382408..e9c46d336a8e 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json @@ -97,6 +97,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", "ScaleUnit": "100%" }, @@ -106,6 +107,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%" }, @@ -116,6 +118,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS. Related metrics: = tma_info_branch_misprediction_cost, tma_mispredicts_resteers", "ScaleUnit": "100%" }, @@ -164,6 +167,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%" }, @@ -248,6 +252,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 4 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_dsb_coverage, tma_info_iptb, tma_lcp", "ScaleUnit": "100%" }, @@ -257,6 +262,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_= 16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", "ScaleUnit": "100%" }, @@ -311,6 +317,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound. Sample with: FRONTE= ND_RETIRED.LATENCY_GE_4_PS", "ScaleUnit": "100%" }, @@ -320,6 +327,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences.", "ScaleUnit": "100%" }, @@ -795,6 +803,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, @@ -825,6 +834,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sh= aring, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_c= ache", "ScaleUnit": "100%" }, @@ -853,6 +863,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%" }, @@ -1013,6 +1024,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .SLOTS", "ScaleUnit": "100%" }, diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json b/t= ools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json index 65ec0c9e55d1..437b9867acb9 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json @@ -103,6 +103,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound.", "ScaleUnit": "100%" }, @@ -112,6 +113,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%" }, @@ -122,6 +124,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics:= tma_info_branch_misprediction_cost, tma_mispredicts_resteers", "ScaleUnit": "100%" }, @@ -170,6 +173,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%" }, @@ -263,6 +267,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 4 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Rel= ated metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_iptb, tma_l= cp", "ScaleUnit": "100%" }, @@ -272,6 +277,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", "ScaleUnit": "100%" }, @@ -326,6 +332,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound.", "ScaleUnit": "100%" }, @@ -335,6 +342,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences.", "ScaleUnit": "100%" }, @@ -829,6 +837,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, @@ -869,6 +878,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sh= aring, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_c= ache", "ScaleUnit": "100%" }, @@ -897,6 +907,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%" }, @@ -1079,6 +1090,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .RETIRE_SLOTS", "ScaleUnit": "100%" }, diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json b= /tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json index 8f7dc72accd0..875c766222e3 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json @@ -101,6 +101,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound.", "ScaleUnit": "100%" }, @@ -110,6 +111,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%" }, @@ -120,6 +122,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics:= tma_info_branch_misprediction_cost, tma_info_mispredictions, tma_mispredic= ts_resteers", "ScaleUnit": "100%" }, @@ -167,6 +170,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%" }, @@ -271,6 +275,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 4 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", "ScaleUnit": "100%" }, @@ -280,6 +285,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_= 16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", "ScaleUnit": "100%" }, @@ -354,6 +360,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound. Sample with: FRONTE= ND_RETIRED.LATENCY_GE_4_PS", "ScaleUnit": "100%" }, @@ -372,6 +379,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences.", "ScaleUnit": "100%" }, @@ -1142,6 +1150,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, @@ -1196,6 +1205,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sh= aring, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_c= ache", "ScaleUnit": "100%" }, @@ -1224,6 +1234,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%" }, @@ -1458,6 +1469,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .RETIRE_SLOTS", "ScaleUnit": "100%" }, diff --git a/tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json b/tool= s/perf/pmu-events/arch/x86/haswell/hsw-metrics.json index 2528418200bb..9570a88d6d1c 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json +++ b/tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json @@ -103,6 +103,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound.", "ScaleUnit": "100%" }, @@ -112,6 +113,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%" }, @@ -122,6 +124,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics:= tma_info_branch_misprediction_cost, tma_mispredicts_resteers", "ScaleUnit": "100%" }, @@ -161,6 +164,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%" }, @@ -254,6 +258,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 4 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Rel= ated metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_iptb, tma_l= cp", "ScaleUnit": "100%" }, @@ -263,6 +268,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", "ScaleUnit": "100%" }, @@ -272,6 +278,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound.", "ScaleUnit": "100%" }, @@ -281,6 +288,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences.", "ScaleUnit": "100%" }, @@ -663,6 +671,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, @@ -693,6 +702,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sh= aring, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_c= ache", "ScaleUnit": "100%" }, @@ -721,6 +731,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%" }, @@ -874,6 +885,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .RETIRE_SLOTS", "ScaleUnit": "100%" }, diff --git a/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json b/too= ls/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json index 11f152c346eb..a522202cf684 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json @@ -103,6 +103,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound.", "ScaleUnit": "100%" }, @@ -112,6 +113,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%" }, @@ -122,6 +124,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics:= tma_info_branch_misprediction_cost, tma_mispredicts_resteers", "ScaleUnit": "100%" }, @@ -161,6 +164,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%" }, @@ -254,6 +258,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 4 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Rel= ated metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_iptb, tma_l= cp", "ScaleUnit": "100%" }, @@ -263,6 +268,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", "ScaleUnit": "100%" }, @@ -272,6 +278,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound.", "ScaleUnit": "100%" }, @@ -281,6 +288,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences.", "ScaleUnit": "100%" }, @@ -664,6 +672,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, @@ -704,6 +713,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sh= aring, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_c= ache", "ScaleUnit": "100%" }, @@ -732,6 +742,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%" }, @@ -905,6 +916,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .RETIRE_SLOTS", "ScaleUnit": "100%" }, diff --git a/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json b/tool= s/perf/pmu-events/arch/x86/icelake/icl-metrics.json index f45ae3483df4..1a2154f28b7b 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json @@ -115,6 +115,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", "ScaleUnit": "100%" }, @@ -124,6 +125,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%" }, @@ -141,6 +143,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics:= tma_info_branch_misprediction_cost, tma_info_mispredictions, tma_mispredic= ts_resteers", "ScaleUnit": "100%" }, @@ -187,6 +190,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%" }, @@ -288,6 +292,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 5 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", "ScaleUnit": "100%" }, @@ -297,6 +302,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_= 16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", "ScaleUnit": "100%" }, @@ -369,6 +375,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound. Sample with: FRONTE= ND_RETIRED.LATENCY_GE_4_PS", "ScaleUnit": "100%" }, @@ -378,6 +385,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences.", "ScaleUnit": "100%" }, @@ -1111,6 +1119,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, @@ -1164,6 +1173,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sh= aring, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_c= ache", "ScaleUnit": "100%" }, @@ -1191,6 +1201,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%" }, @@ -1360,6 +1371,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .SLOTS", "ScaleUnit": "100%" }, diff --git a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json b/too= ls/perf/pmu-events/arch/x86/icelakex/icx-metrics.json index 0f9b174dfc22..1ef772b40e04 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json @@ -80,6 +80,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", "ScaleUnit": "100%" }, @@ -89,6 +90,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%" }, @@ -106,6 +108,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics:= tma_info_branch_misprediction_cost, tma_info_mispredictions, tma_mispredic= ts_resteers", "ScaleUnit": "100%" }, @@ -152,6 +155,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%" }, @@ -253,6 +257,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 5 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", "ScaleUnit": "100%" }, @@ -262,6 +267,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_= 16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", "ScaleUnit": "100%" }, @@ -334,6 +340,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound. Sample with: FRONTE= ND_RETIRED.LATENCY_GE_4_PS", "ScaleUnit": "100%" }, @@ -343,6 +350,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences.", "ScaleUnit": "100%" }, @@ -1134,6 +1142,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, @@ -1187,6 +1196,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sh= aring, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_c= ache", "ScaleUnit": "100%" }, @@ -1214,6 +1224,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%" }, @@ -1410,6 +1421,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .SLOTS", "ScaleUnit": "100%" }, diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json b/to= ols/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json index 5247f69c13b6..11080ccffd51 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json @@ -103,6 +103,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound.", "ScaleUnit": "100%" }, @@ -112,6 +113,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%" }, @@ -122,6 +124,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics:= tma_info_branch_misprediction_cost, tma_mispredicts_resteers", "ScaleUnit": "100%" }, @@ -161,6 +164,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%" }, @@ -254,6 +258,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 4 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Rel= ated metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_iptb, tma_l= cp", "ScaleUnit": "100%" }, @@ -263,6 +268,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", "ScaleUnit": "100%" }, @@ -299,6 +305,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound.", "ScaleUnit": "100%" }, @@ -308,6 +315,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences.", "ScaleUnit": "100%" }, @@ -724,6 +732,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, @@ -754,6 +763,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sh= aring, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_c= ache", "ScaleUnit": "100%" }, @@ -782,6 +792,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%" }, @@ -917,6 +928,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .RETIRE_SLOTS", "ScaleUnit": "100%" }, diff --git a/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json b/tool= s/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json index 89469b10fa30..65a46d659c0a 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json @@ -103,6 +103,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound.", "ScaleUnit": "100%" }, @@ -112,6 +113,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%" }, @@ -122,6 +124,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics:= tma_info_branch_misprediction_cost, tma_mispredicts_resteers", "ScaleUnit": "100%" }, @@ -161,6 +164,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%" }, @@ -254,6 +258,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 4 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Rel= ated metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_iptb, tma_l= cp", "ScaleUnit": "100%" }, @@ -263,6 +268,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", "ScaleUnit": "100%" }, @@ -299,6 +305,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound.", "ScaleUnit": "100%" }, @@ -308,6 +315,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences.", "ScaleUnit": "100%" }, @@ -725,6 +733,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, @@ -765,6 +774,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sh= aring, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_c= ache", "ScaleUnit": "100%" }, @@ -793,6 +803,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%" }, @@ -948,6 +959,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .RETIRE_SLOTS", "ScaleUnit": "100%" }, diff --git a/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json b/too= ls/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json index e8f4e5c01c9f..66a6f657bd6f 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json @@ -76,6 +76,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound.", "ScaleUnit": "100%" }, @@ -85,6 +86,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%" }, @@ -95,6 +97,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics:= tma_info_branch_misprediction_cost, tma_mispredicts_resteers", "ScaleUnit": "100%" }, @@ -114,6 +117,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%" }, @@ -160,6 +164,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 4 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Rel= ated metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_lcp", "ScaleUnit": "100%" }, @@ -169,6 +174,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", "ScaleUnit": "100%" }, @@ -205,6 +211,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound.", "ScaleUnit": "100%" }, @@ -214,6 +221,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences.", "ScaleUnit": "100%" }, @@ -412,6 +420,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, @@ -422,6 +431,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches= , tma_remote_cache", "ScaleUnit": "100%" }, @@ -450,6 +460,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%" }, @@ -487,6 +498,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .RETIRE_SLOTS", "ScaleUnit": "100%" }, diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json b/= tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json index 4a99fe515f4b..4b8bc19392a4 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json @@ -76,6 +76,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound.", "ScaleUnit": "100%" }, @@ -85,6 +86,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%" }, @@ -95,6 +97,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics:= tma_info_branch_misprediction_cost, tma_mispredicts_resteers", "ScaleUnit": "100%" }, @@ -114,6 +117,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%" }, @@ -160,6 +164,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 4 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Rel= ated metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_lcp", "ScaleUnit": "100%" }, @@ -169,6 +174,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", "ScaleUnit": "100%" }, @@ -205,6 +211,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound.", "ScaleUnit": "100%" }, @@ -214,6 +221,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences.", "ScaleUnit": "100%" }, @@ -411,6 +419,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, @@ -421,6 +430,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches= , tma_remote_cache", "ScaleUnit": "100%" }, @@ -449,6 +459,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%" }, @@ -486,6 +497,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .RETIRE_SLOTS", "ScaleUnit": "100%" }, diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json= b/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json index 126300b7ae77..620fc5bd2217 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json @@ -87,6 +87,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", "ScaleUnit": "100%" }, @@ -96,6 +97,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%" }, @@ -105,6 +107,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS. Related metrics: = tma_info_branch_misprediction_cost, tma_info_mispredictions, tma_mispredict= s_resteers", "ScaleUnit": "100%" }, @@ -151,6 +154,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%" }, @@ -252,6 +256,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 6 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", "ScaleUnit": "100%" }, @@ -261,6 +266,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_= 16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", "ScaleUnit": "100%" }, @@ -351,6 +357,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound. Sample with: FRONTE= ND_RETIRED.LATENCY_GE_4_PS", "ScaleUnit": "100%" }, @@ -369,6 +376,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences. Sample with: UOPS_RETIRED.HEA= VY", "ScaleUnit": "100%" }, @@ -1216,6 +1224,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, @@ -1269,6 +1278,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sh= aring, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_c= ache", "ScaleUnit": "100%" }, @@ -1304,6 +1314,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%" }, @@ -1509,6 +1520,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .SLOTS", "ScaleUnit": "100%" }, diff --git a/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json b/tool= s/perf/pmu-events/arch/x86/skylake/skl-metrics.json index a6d212b349f5..21ef6c9be816 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json @@ -101,6 +101,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound.", "ScaleUnit": "100%" }, @@ -110,6 +111,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%" }, @@ -120,6 +122,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics:= tma_info_branch_misprediction_cost, tma_info_mispredictions, tma_mispredic= ts_resteers", "ScaleUnit": "100%" }, @@ -167,6 +170,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%" }, @@ -271,6 +275,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 4 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", "ScaleUnit": "100%" }, @@ -280,6 +285,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_= 16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", "ScaleUnit": "100%" }, @@ -345,6 +351,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound. Sample with: FRONTE= ND_RETIRED.LATENCY_GE_4_PS", "ScaleUnit": "100%" }, @@ -363,6 +370,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences.", "ScaleUnit": "100%" }, @@ -1065,6 +1073,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, @@ -1110,6 +1119,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sh= aring, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_c= ache", "ScaleUnit": "100%" }, @@ -1138,6 +1148,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%" }, @@ -1343,6 +1354,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .RETIRE_SLOTS", "ScaleUnit": "100%" }, diff --git a/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json b/too= ls/perf/pmu-events/arch/x86/skylakex/skx-metrics.json index fa2f7f126a30..eb6f12c0343d 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json @@ -101,6 +101,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound.", "ScaleUnit": "100%" }, @@ -110,6 +111,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%" }, @@ -120,6 +122,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics:= tma_info_branch_misprediction_cost, tma_info_mispredictions, tma_mispredic= ts_resteers", "ScaleUnit": "100%" }, @@ -167,6 +170,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%" }, @@ -271,6 +275,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 4 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", "ScaleUnit": "100%" }, @@ -280,6 +285,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_= 16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", "ScaleUnit": "100%" }, @@ -354,6 +360,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound. Sample with: FRONTE= ND_RETIRED.LATENCY_GE_4_PS", "ScaleUnit": "100%" }, @@ -372,6 +379,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences.", "ScaleUnit": "100%" }, @@ -1123,6 +1131,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, @@ -1177,6 +1186,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sh= aring, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_c= ache", "ScaleUnit": "100%" }, @@ -1205,6 +1215,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%" }, @@ -1429,6 +1440,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .RETIRE_SLOTS", "ScaleUnit": "100%" }, diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json b/to= ols/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json index 4c80d6be6cf1..b442ed4acfbb 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json @@ -109,6 +109,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", "ScaleUnit": "100%" }, @@ -118,6 +119,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%" }, @@ -135,6 +137,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics:= tma_info_branch_misprediction_cost, tma_info_mispredictions, tma_mispredic= ts_resteers", "ScaleUnit": "100%" }, @@ -181,6 +184,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%" }, @@ -282,6 +286,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 5 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", "ScaleUnit": "100%" }, @@ -291,6 +296,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_= 16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", "ScaleUnit": "100%" }, @@ -363,6 +369,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound. Sample with: FRONTE= ND_RETIRED.LATENCY_GE_4_PS", "ScaleUnit": "100%" }, @@ -372,6 +379,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences.", "ScaleUnit": "100%" }, @@ -1125,6 +1133,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, @@ -1178,6 +1187,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sh= aring, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_c= ache", "ScaleUnit": "100%" }, @@ -1205,6 +1215,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%" }, @@ -1374,6 +1385,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .SLOTS", "ScaleUnit": "100%" }, diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jeven= ts.py index ca99b9cfe4ad..f57a8f274025 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -52,7 +52,8 @@ _json_event_attributes =3D [ # Attributes that are in pmu_metric rather than pmu_event. _json_metric_attributes =3D [ 'metric_name', 'metric_group', 'metric_expr', 'metric_threshold', 'des= c', - 'long_desc', 'unit', 'compat', 'aggr_mode', 'event_grouping' + 'long_desc', 'unit', 'compat', 'metricgroup_no_group', 'aggr_mode', + 'event_grouping' ] # Attributes that are bools or enum int values, encoded as '0', '1',... _json_enum_attributes =3D ['aggr_mode', 'deprecated', 'event_grouping', 'p= erpkg'] @@ -303,6 +304,7 @@ class JsonEvent: self.deprecated =3D jd.get('Deprecated') self.metric_name =3D jd.get('MetricName') self.metric_group =3D jd.get('MetricGroup') + self.metricgroup_no_group =3D jd.get('MetricgroupNoGroup') self.event_grouping =3D convert_metric_constraint(jd.get('MetricConstr= aint')) self.metric_expr =3D None if 'MetricExpr' in jd: diff --git a/tools/perf/pmu-events/pmu-events.h b/tools/perf/pmu-events/pmu= -events.h index b7dff8f1021f..80349685cf4d 100644 --- a/tools/perf/pmu-events/pmu-events.h +++ b/tools/perf/pmu-events/pmu-events.h @@ -59,6 +59,7 @@ struct pmu_metric { const char *compat; const char *desc; const char *long_desc; + const char *metricgroup_no_group; enum aggr_mode_class aggr_mode; enum metric_event_groups event_grouping; }; diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index 4b9a16291b96..e1acb0d23b95 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -1144,12 +1144,12 @@ static int metricgroup__add_metric_callback(const s= truct pmu_metric *pm, struct metricgroup__add_metric_data *data =3D vdata; int ret =3D 0; =20 - if (pm->metric_expr && - (match_metric(pm->metric_group, data->metric_name) || - match_metric(pm->metric_name, data->metric_name))) { + if (pm->metric_expr && match_pm_metric(pm, data->metric_name)) { + bool metric_no_group =3D data->metric_no_group || + match_metric(data->metric_name, pm->metricgroup_no_group); =20 data->has_match =3D true; - ret =3D add_metric(data->list, pm, data->modifier, data->metric_no_group, + ret =3D add_metric(data->list, pm, data->modifier, metric_no_group, data->metric_no_threshold, data->user_requested_cpu_list, data->system_wide, /*root_metric=3D*/NULL, /*visited_metrics=3D*/NULL, table); --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27608C19F20 for ; Tue, 2 May 2023 22:40:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229949AbjEBWkJ (ORCPT ); Tue, 2 May 2023 18:40:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56368 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229995AbjEBWkD (ORCPT ); Tue, 2 May 2023 18:40:03 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33CD435A8 for ; Tue, 2 May 2023 15:39:38 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-b9a7d92d0f7so7689022276.1 for ; Tue, 02 May 2023 15:39:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067177; x=1685659177; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=dIl1kUAo9IYD/UhzcgxFmKKCjB+AQPORsd+rIG9tHuw=; b=vlmuRJR29pht0Gp3pNW+5EH0OUu/iLD4+LrJjhclGh+ZyS7JovyFHhS4SNpxGnSS1N x892EOk8Wi/p6/5ZpEQEmLXWRhDiM0F2E+3W95Dg4DMllizoLNxZvxxFltLWct8Q8jls ezVuzXoF46wy31d5zCVf8OGKlqQaGVFSCfr5xTFyx4I8VSqqAOlw1mcjZhEs9q+CD2Kk gpeGdlWr2A6MXpDa4h5iSK54Dpua0MVOnlwKzHIULOnuQsy2xmLnS3zRNATvW9iNn3H0 nu7FYfNvLyf4IqU+uYkUAhtEzlyizYHtAhHw8DEuHVAVGWpEwa+/3jU7QCpfL0NYySo8 hBUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067177; x=1685659177; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=dIl1kUAo9IYD/UhzcgxFmKKCjB+AQPORsd+rIG9tHuw=; b=cIdQeW9llknmtIiif9WXZj23Xokwo7Y/lq7q5+1qw0o/mab+GKWrobENi/L7N8gCHB s9wicwBFzPvyFUYNOra6p/T5fra1PUhxQEhp9uFod7wPlPtvMqELwU9WVVUcLkPIJTSx h3MAcQFvSPfe2t8vw/WKLVPLXEbIHiXIlUkaeKeM4/q7KkXau2Y0hMz2JTgp1np5YuF0 BP/biTUxIkjIcba2wv6Jp9vD129Kpc4821xoEnS4GkbsFbJDeJ6lrzxqHiPTKam2hMkC yOG3YoUJYil4d1vFGIcxgauTNdxjZ9LDO0UUey5wXuaOyW0WJ9z8/cAJ7yGO5jqpsmKx gRsA== X-Gm-Message-State: AC+VfDyfI/Pghk5La2XFdiS9QdCPRx9veqkvS6noFa8wrYnP0rPuNMxY FW7Lv09oGmZcYnmKdXrb+ZUwp1IbDqdB X-Google-Smtp-Source: ACHHUZ658OJAc3DqZHBjuqUr7dv/cjG8MEsPVkZxQ9G6ZD7qckXXN4VR4ZUDntaQKmJ1CB1SF4RKb3ZyaXI+ X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a25:ea53:0:b0:b99:3b72:39a with SMTP id o19-20020a25ea53000000b00b993b72039amr6857243ybe.7.1683067177345; Tue, 02 May 2023 15:39:37 -0700 (PDT) Date: Tue, 2 May 2023 15:38:11 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-5-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 04/44] perf parse-events: Don't reorder ungrouped events by pmu From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The pmu_group_name by default returns "cpu" which on non-hybrid/ARM means that ungrouped software, and hardware events are all going to sort by the original insertion index. However, on hybrid and ARM wildcard expansion may mean the PMU name is set and events will be unnecessarily reordered - triggering the reordering warning. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/util/parse-events.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index d71019dcd614..34ba840ae19a 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -2140,25 +2140,32 @@ static int evlist__cmp(void *state, const struct li= st_head *l, const struct list int *leader_idx =3D state; int lhs_leader_idx =3D *leader_idx, rhs_leader_idx =3D *leader_idx, ret; const char *lhs_pmu_name, *rhs_pmu_name; + bool lhs_has_group =3D false, rhs_has_group =3D false; =20 /* * First sort by grouping/leader. Read the leader idx only if the evsel * is part of a group, as -1 indicates no group. */ - if (lhs_core->leader !=3D lhs_core || lhs_core->nr_members > 1) + if (lhs_core->leader !=3D lhs_core || lhs_core->nr_members > 1) { + lhs_has_group =3D true; lhs_leader_idx =3D lhs_core->leader->idx; - if (rhs_core->leader !=3D rhs_core || rhs_core->nr_members > 1) + } + if (rhs_core->leader !=3D rhs_core || rhs_core->nr_members > 1) { + rhs_has_group =3D true; rhs_leader_idx =3D rhs_core->leader->idx; + } =20 if (lhs_leader_idx !=3D rhs_leader_idx) return lhs_leader_idx - rhs_leader_idx; =20 - /* Group by PMU. Groups can't span PMUs. */ - lhs_pmu_name =3D evsel__group_pmu_name(lhs); - rhs_pmu_name =3D evsel__group_pmu_name(rhs); - ret =3D strcmp(lhs_pmu_name, rhs_pmu_name); - if (ret) - return ret; + /* Group by PMU if there is a group. Groups can't span PMUs. */ + if (lhs_has_group && rhs_has_group) { + lhs_pmu_name =3D evsel__group_pmu_name(lhs); + rhs_pmu_name =3D evsel__group_pmu_name(rhs); + ret =3D strcmp(lhs_pmu_name, rhs_pmu_name); + if (ret) + return ret; + } =20 /* Architecture specific sorting. */ return arch_evlist__cmp(lhs, rhs); --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D195C7EE21 for ; Tue, 2 May 2023 22:40:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229976AbjEBWkW (ORCPT ); Tue, 2 May 2023 18:40:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56588 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229982AbjEBWkP (ORCPT ); Tue, 2 May 2023 18:40:15 -0400 Received: from mail-pf1-x44a.google.com (mail-pf1-x44a.google.com [IPv6:2607:f8b0:4864:20::44a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E35712D74 for ; Tue, 2 May 2023 15:39:45 -0700 (PDT) Received: by mail-pf1-x44a.google.com with SMTP id d2e1a72fcca58-64115ef7234so385176b3a.1 for ; Tue, 02 May 2023 15:39:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067184; x=1685659184; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:from:to:cc:subject:date :message-id:reply-to; bh=pu+qnvO2EIt8egj2Q0XgeZXFcabh0X5taGysX92E8Pc=; b=AwrJ6bejoHe/AsvrsyhaYCJ1H1NTT01fnGyrPnuHhGk17gU4URYa3ji1i9bWrPkgqO WlbmdJqxKfk7prOvFs+FXMa9IzxGJvCKayP8jn9wGlRq3PXmLJZLfolFMoyYdmWwY+1v bYydBJNO+WT8cG/67hMcDeh8EO9x7ocKaSIZg5loemArLf7/EK96aLIolASU2xLlg6Bk 5lEHFMo7n5vPg9lfaFpitWoXtK6VMbJ4L7ZkXBxb9VkmfODUICjAz5jSeB9Bf/aTTWIx OZYaFsLFd4BT4nkYOUPyU6H0QC8pz81qs/DXfv/ZYGII7JP6ruhoPfUAHp4OL6BIS6ub v/bQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067184; x=1685659184; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=pu+qnvO2EIt8egj2Q0XgeZXFcabh0X5taGysX92E8Pc=; b=Y5AE7pIY3B7MotZb0KTKuiZzQO5LgYkk0Ac8PfirmgrhCnDmoA5SeMnZd3XbNRs+je cg5NVx9Je+hdmS2a60Nesy5o6J0m4mzpblW1yEa5jHiMlXwOk7LDg/Jomk4a4ZylYdO5 HRbI0VE/A6fV//Nee5uMkKSKtb0ALwYsCKblqZBUy9CjjdH37Vmt9vGlz4LhOerlHzJA 79CgG/3N4+a0NJU6JRqAK0Vx87p7ZBKutmaoxVrwNMCEtikcUY7KCCav0+sPHUAPEgpj t+HkWeVCfX30UYTG9qEMgrtnrQhzXv6Fz7cqUmPA9KmfEs1ziinRET192x5WNxjqVyTz yvKw== X-Gm-Message-State: AC+VfDy8pSeW68EtwoJx2VWpYS/eefy4U31c39RKMzXdhJR9qv9Y+mzy 4MjmCwXk++ip0cNxMojjhpEHxXFWdb9B X-Google-Smtp-Source: ACHHUZ5XCMyqagreOZJU6o4EH1oiMhM+uLdV8LECquLyJt5ME29kO2V80AVtw5H80VEYXMcMHVYNBF62h25Y X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a05:6a00:26db:b0:63d:38db:60e9 with SMTP id p27-20020a056a0026db00b0063d38db60e9mr43868pfw.2.1683067183940; Tue, 02 May 2023 15:39:43 -0700 (PDT) Date: Tue, 2 May 2023 15:38:12 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-6-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 05/44] perf vendor events intel: Add alderlake metric constraints From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Previously these constraints were disabled as they contained topdown events. Since: https://lore.kernel.org/all/20230312021543.3060328-9-irogers@google.com/ the topdown events are correctly grouped even if no group exists. This change was created by PR: https://github.com/intel/perfmon/pull/71 Signed-off-by: Ian Rogers Tested-by: Kan Liang --- .../pmu-events/arch/x86/alderlake/adl-metrics.json | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json b/to= ols/perf/pmu-events/arch/x86/alderlake/adl-metrics.json index 1f9047553942..4c2a14ea5a1c 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json @@ -1077,6 +1077,7 @@ }, { "BriefDescription": "This metric represents overall arithmetic flo= ating-point (FP) operations fraction the CPU has executed (retired)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_gr= oup", "MetricName": "tma_fp_arith", @@ -1203,6 +1204,7 @@ }, { "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_m= ispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_= misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * tma_info_slots / B= R_MISP_RETIRED.ALL_BRANCHES", "MetricGroup": "Bad;BrMispredicts;tma_issueBM", "MetricName": "tma_info_branch_misprediction_cost", @@ -1255,6 +1257,7 @@ }, { "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization = if tma_core_bound < tma_ports_utilization else 1) if tma_info_smt_2t_utiliz= ation > 0.5 else 0)", "MetricGroup": "Cor;SMT", "MetricName": "tma_info_core_bound_likely", @@ -1315,6 +1318,7 @@ }, { "BriefDescription": "Total pipeline cost of DSB (uop cache) misses= - subset of the Instruction_Fetch_BW Bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_= branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + = tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tm= a_lsd + tma_mite))", "MetricGroup": "DSBmiss;Fed;tma_issueFB", "MetricName": "tma_info_dsb_misses", @@ -1408,6 +1412,7 @@ }, { "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma= _mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icach= e_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_big_cod= e", "MetricGroup": "Fed;FetchBW;Frontend", "MetricName": "tma_info_instruction_fetch_bw", @@ -1827,6 +1832,7 @@ }, { "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_me= mory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + t= ma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_dtlb_load + tma_fb= _full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_stor= e_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tm= a_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tm= a_split_stores + tma_store_latency + tma_streaming_stores)))", "MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB", "MetricName": "tma_info_memory_data_tlbs", @@ -1836,6 +1842,7 @@ }, { "BriefDescription": "Total pipeline cost of Memory Latency related= bottlenecks (external memory and off-core caches)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dra= m_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (= tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (= tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bou= nd) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tm= a_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_= bound + tma_l2_bound + tma_l3_bound + tma_store_bound))", "MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat", "MetricName": "tma_info_memory_latency", @@ -1845,6 +1852,7 @@ }, { "BriefDescription": "Total pipeline cost of Branch Misprediction r= elated bottlenecks", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency *= tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_i= cache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", "MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM", "MetricName": "tma_info_mispredictions", @@ -1877,6 +1885,7 @@ }, { "BriefDescription": "Average number of Uops retired in cycles wher= e at least one uop has retired.", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_retiring * tma_info_slots / cpu_core@UOPS_RETIR= ED.SLOTS\\,cmask\\=3D1@", "MetricGroup": "Pipeline;Ret", "MetricName": "tma_info_retire", @@ -2152,6 +2161,7 @@ }, { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring memory operations -- uops for memory load or store a= ccesses.", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_light_operations * MEM_UOP_RETIRED.ANY / (tma_r= etiring * tma_info_slots)", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", "MetricName": "tma_memory_operations", @@ -2231,6 +2241,7 @@ }, { "BriefDescription": "This metric represents the remaining light uo= ps fraction the CPU has executed - remaining means not covered by other sib= ling nodes", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_i= nt_operations + tma_memory_operations + tma_fused_instructions + tma_non_fu= sed_branches + tma_nop_instructions))", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", "MetricName": "tma_other_light_ops", --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D16FC7EE21 for ; Tue, 2 May 2023 22:40:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230002AbjEBWk2 (ORCPT ); Tue, 2 May 2023 18:40:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56568 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229970AbjEBWkV (ORCPT ); Tue, 2 May 2023 18:40:21 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9741B273A for ; Tue, 2 May 2023 15:39:52 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-b9a77926afbso8665261276.3 for ; Tue, 02 May 2023 15:39:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067191; x=1685659191; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:from:to:cc:subject:date :message-id:reply-to; bh=kUqIzU74xlE5Kx3pMTtUAqqI2RU8Dst3dNg1w1BZSyA=; b=699XHwHFOrTyqrqqXUTthTiAjZ7RR07G4qFqKRtY3g9JDgyNi3xuKCnNkFkq7ROLX3 u1vK/JSl8d60HAl9wytToNq4DjObukhnvQhJxwyaU00d2gospNMsmBDvUNioK5MDVS4/ qMGCUkPh2Kf4iMbzhUI5PE4E61ZnUABZOxBrv9TTFrsot0giEqSEMb0K8cRS5DL3tLU/ UmPQW6cbkmqunbmO5V9B6blP2KDPssqxWbShbSYfKS+gWs/4BBMdBO5Brx/Knr2ZD95q eE9nSgsxqJTwy/XOyHd2Ya1rWOIwv/T1v/0sVBdhE72J/N78damNLfs4wgwszaZubzFN 1+aQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067191; x=1685659191; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=kUqIzU74xlE5Kx3pMTtUAqqI2RU8Dst3dNg1w1BZSyA=; b=OJh4B1yi51M9C2XU1JQQES/3zmV3/rEfnRY5yKUGu+wzTKwKHlGiborrO1gHkoLUWJ s7m7alYSIKH5GE/MdAEt2TVG5vq6Uzh02QerLUSEBj7c9C7DwNO6CGatIRRMUCwfzOqp 25nDCO0ZSMg0zNUO2GsALEmbfT+39PAyUocoxm4317XdacEDjhvSqaC53+UzfFQzefVV WQA0lHWlYTwQbc+QPo87eOchKn4H/iDYInhlVzjECyAH6MA2RDrwVi2Zk3BXbfqDsZ8+ nGglwHcibKP+IVSbpbSs/gmmxEGwatTRTIuSYZ9+s7JQn/0TzBKFjxkhe9z9jp3oUAsZ exLg== X-Gm-Message-State: AC+VfDwEizdfieQGtnFMq2PgcgcY4ji6QaeCgLagS3XgFcc6kxfr6F+a kjXI5KXHabvESCQ7MEa3/zzSFg9xUFQF X-Google-Smtp-Source: ACHHUZ7Qhs3u/9GYCotzoJXOHdwSFpTuCv6DFkueBX6gHHDWQ/FEsoQVc2ew48Bwh/7kiymxm1Yupx2TSVPv X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a05:6902:100e:b0:b8f:47c4:58ed with SMTP id w14-20020a056902100e00b00b8f47c458edmr11376660ybt.9.1683067190869; Tue, 02 May 2023 15:39:50 -0700 (PDT) Date: Tue, 2 May 2023 15:38:13 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-7-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 06/44] perf vendor events intel: Add icelake metric constraints From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Previously these constraints were disabled as they contained topdown events. Since: https://lore.kernel.org/all/20230312021543.3060328-9-irogers@google.com/ the topdown events are correctly grouped even if no group exists. This change was created by PR: https://github.com/intel/perfmon/pull/71 Signed-off-by: Ian Rogers Tested-by: Kan Liang --- .../perf/pmu-events/arch/x86/icelake/icl-metrics.json | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json b/tool= s/perf/pmu-events/arch/x86/icelake/icl-metrics.json index 1a2154f28b7b..ae8a96ec7fa5 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json @@ -317,6 +317,7 @@ }, { "BriefDescription": "This metric represents overall arithmetic flo= ating-point (FP) operations fraction the CPU has executed (retired)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_gr= oup", "MetricName": "tma_fp_arith", @@ -421,6 +422,7 @@ }, { "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_m= ispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_= misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * tma_info_slots / B= R_MISP_RETIRED.ALL_BRANCHES", "MetricGroup": "Bad;BrMispredicts;tma_issueBM", "MetricName": "tma_info_branch_misprediction_cost", @@ -466,6 +468,7 @@ }, { "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization = if tma_core_bound < tma_ports_utilization else 1) if tma_info_smt_2t_utiliz= ation > 0.5 else 0)", "MetricGroup": "Cor;SMT", "MetricName": "tma_info_core_bound_likely", @@ -518,6 +521,7 @@ }, { "BriefDescription": "Total pipeline cost of DSB (uop cache) misses= - subset of the Instruction_Fetch_BW Bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_= branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + = tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tm= a_lsd + tma_mite))", "MetricGroup": "DSBmiss;Fed;tma_issueFB", "MetricName": "tma_info_dsb_misses", @@ -599,6 +603,7 @@ }, { "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma= _mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icach= e_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_big_cod= e", "MetricGroup": "Fed;FetchBW;Frontend", "MetricName": "tma_info_instruction_fetch_bw", @@ -937,6 +942,7 @@ }, { "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_me= mory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + t= ma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_= dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fw= d_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound += tma_l3_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_= false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores= )))", "MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB", "MetricName": "tma_info_memory_data_tlbs", @@ -945,6 +951,7 @@ }, { "BriefDescription": "Total pipeline cost of Memory Latency related= bottlenecks (external memory and off-core caches)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dra= m_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (= tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (= tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bou= nd) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tm= a_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_= bound + tma_l2_bound + tma_l3_bound + tma_store_bound))", "MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat", "MetricName": "tma_info_memory_latency", @@ -953,6 +960,7 @@ }, { "BriefDescription": "Total pipeline cost of Branch Misprediction r= elated bottlenecks", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency *= tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_i= cache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", "MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM", "MetricName": "tma_info_mispredictions", @@ -1004,6 +1012,7 @@ }, { "BriefDescription": "Average number of Uops retired in cycles wher= e at least one uop has retired.", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_retiring * tma_info_slots / cpu@UOPS_RETIRED.SL= OTS\\,cmask\\=3D1@", "MetricGroup": "Pipeline;Ret", "MetricName": "tma_info_retire" @@ -1207,6 +1216,7 @@ }, { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring memory operations -- uops for memory load or store a= ccesses.", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_= RETIRED.ANY", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", "MetricName": "tma_memory_operations", @@ -1277,6 +1287,7 @@ }, { "BriefDescription": "This metric represents the remaining light uo= ps fraction the CPU has executed - remaining means not covered by other sib= ling nodes", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_m= emory_operations + tma_branch_instructions + tma_nop_instructions))", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", "MetricName": "tma_other_light_ops", --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39627C7EE21 for ; Tue, 2 May 2023 22:40:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230046AbjEBWkj (ORCPT ); Tue, 2 May 2023 18:40:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56778 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230036AbjEBWk0 (ORCPT ); Tue, 2 May 2023 18:40:26 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E77DB2D4E for ; Tue, 2 May 2023 15:40:01 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-b9a805e82a9so9884963276.3 for ; Tue, 02 May 2023 15:40:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067201; x=1685659201; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:from:to:cc:subject:date :message-id:reply-to; bh=ACILkomP7xAnicp1B5oS0CzcGm3M1w5NGLrNqaEc+zg=; b=tYjziJIxpgtzUb1ACwnwv3T65Z8EuGwcFRX5+OKiiIO3OnE/6PxghV1axLr1nQ65kr hgtHhSib5zckAcFOFQgmFSUTzNLvnrwMFQV+NsOPeQmJZezi1bIBOEsDyQJ0AVQcU12Z TuLSfpuJtsD0d/qNrcWlbUCRRI2FVZJO70r0F9RxOi2mJsjgYrvEt5ptbc9Xj6jCvxEs EiGK+iJwceYrMiixLuLLWdm5dpMIKcHl61TL5Yy2crj6fVWUxtO68b8ne6UyZ/21w+my 1qEoFOp0fq9a6N/pPWVUUq+iE6FSAuoPJgwp07kANVeDapZEYCi2SghAwNnJBWCVQoWY 8EhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067201; x=1685659201; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=ACILkomP7xAnicp1B5oS0CzcGm3M1w5NGLrNqaEc+zg=; b=N+GDBLYsFu8OALOghzhhE7XrtRZU88yVe0WB6OQjF9SkKM1gILDKbZOH2Gvr0Lc5ST J8plvwSpe6UVFUN0RKCMqMIqKTCPsAqqEdshSoeb+SaP40VcyzDzg2IiFRlsF13C2fgW oKvX94h3TqXfxB1mcjNZyaEjyZ6u5Coe+0RBDqoT0/fcxTL7/96lqq54OmGcZ6mCsJJh 7B998wwy8QT6OTe/bX0lQJYoWStcfFmbY17qqtA/nd9HllQVu0w2oN8VJSBwp3M09TYm /fKvC3yZnsZ3r8O6kDvIFj0Wwh79XdI8vdCf9VIogruyPIG/rF2L6ZBSh/V/gAcLAd55 Zy7Q== X-Gm-Message-State: AC+VfDxdb/is1jLX74XKykbyiuuyXh4nWlSkA9c39qagjcnMot5TJ97w 9AP6Y5Hs6ZIj143Xi0uaciPNyjCGWTLm X-Google-Smtp-Source: ACHHUZ7/kKX8MrTdGJZgJi2PzFaLkuoZ5T+GrHlfUID2mQhiBXg4pa6ojG+XPWavtVF0873za8Dof2556KLk X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a25:8250:0:b0:b9d:d623:1960 with SMTP id d16-20020a258250000000b00b9dd6231960mr3989197ybn.0.1683067201142; Tue, 02 May 2023 15:40:01 -0700 (PDT) Date: Tue, 2 May 2023 15:38:14 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-8-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 07/44] perf vendor events intel: Add icelakex metric constraints From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Previously these constraints were disabled as they contained topdown events. Since: https://lore.kernel.org/all/20230312021543.3060328-9-irogers@google.com/ the topdown events are correctly grouped even if no group exists. This change was created by PR: https://github.com/intel/perfmon/pull/71 Signed-off-by: Ian Rogers Tested-by: Kan Liang --- .../pmu-events/arch/x86/icelakex/icx-metrics.json | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json b/too= ls/perf/pmu-events/arch/x86/icelakex/icx-metrics.json index 1ef772b40e04..b736fec164d0 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json @@ -282,6 +282,7 @@ }, { "BriefDescription": "This metric represents overall arithmetic flo= ating-point (FP) operations fraction the CPU has executed (retired)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_gr= oup", "MetricName": "tma_fp_arith", @@ -386,6 +387,7 @@ }, { "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_m= ispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_= misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * tma_info_slots / B= R_MISP_RETIRED.ALL_BRANCHES", "MetricGroup": "Bad;BrMispredicts;tma_issueBM", "MetricName": "tma_info_branch_misprediction_cost", @@ -431,6 +433,7 @@ }, { "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization = if tma_core_bound < tma_ports_utilization else 1) if tma_info_smt_2t_utiliz= ation > 0.5 else 0)", "MetricGroup": "Cor;SMT", "MetricName": "tma_info_core_bound_likely", @@ -483,6 +486,7 @@ }, { "BriefDescription": "Total pipeline cost of DSB (uop cache) misses= - subset of the Instruction_Fetch_BW Bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_= branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + = tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tm= a_mite))", "MetricGroup": "DSBmiss;Fed;tma_issueFB", "MetricName": "tma_info_dsb_misses", @@ -564,6 +568,7 @@ }, { "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma= _mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icach= e_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_big_cod= e", "MetricGroup": "Fed;FetchBW;Frontend", "MetricName": "tma_info_instruction_fetch_bw", @@ -948,6 +953,7 @@ }, { "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_me= mory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + t= ma_pmm_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k= _aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_load= s + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound = + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtl= b_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_stor= e_latency + tma_streaming_stores)))", "MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB", "MetricName": "tma_info_memory_data_tlbs", @@ -956,6 +962,7 @@ }, { "BriefDescription": "Total pipeline cost of Memory Latency related= bottlenecks (external memory and off-core caches)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dra= m_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_= store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + = tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound= + tma_pmm_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_= accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_b= ound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_p= mm_bound + tma_store_bound))", "MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat", "MetricName": "tma_info_memory_latency", @@ -964,6 +971,7 @@ }, { "BriefDescription": "Total pipeline cost of Branch Misprediction r= elated bottlenecks", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency *= tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_i= cache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", "MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM", "MetricName": "tma_info_mispredictions", @@ -1027,6 +1035,7 @@ }, { "BriefDescription": "Average number of Uops retired in cycles wher= e at least one uop has retired.", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_retiring * tma_info_slots / cpu@UOPS_RETIRED.SL= OTS\\,cmask\\=3D1@", "MetricGroup": "Pipeline;Ret", "MetricName": "tma_info_retire" @@ -1230,6 +1239,7 @@ }, { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring memory operations -- uops for memory load or store a= ccesses.", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_= RETIRED.ANY", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", "MetricName": "tma_memory_operations", @@ -1300,6 +1310,7 @@ }, { "BriefDescription": "This metric represents the remaining light uo= ps fraction the CPU has executed - remaining means not covered by other sib= ling nodes", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_m= emory_operations + tma_branch_instructions + tma_nop_instructions))", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", "MetricName": "tma_other_light_ops", --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47EC8C19F20 for ; Tue, 2 May 2023 22:40:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230052AbjEBWkp (ORCPT ); Tue, 2 May 2023 18:40:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56756 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230015AbjEBWkh (ORCPT ); Tue, 2 May 2023 18:40:37 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77AC030E4 for ; Tue, 2 May 2023 15:40:08 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-b9a6eeea78cso650490276.0 for ; Tue, 02 May 2023 15:40:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067207; x=1685659207; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:from:to:cc:subject:date :message-id:reply-to; bh=7EN19QVchQR1O/U+7gWBQO9KjDeBdf2tyCzS7+tNUxk=; b=iZrCrPENQMdCXgnHpN5mPkQZGaqd5MgLiEEvm9qmtb/ju8foM54ZfYn69rpEVyD2aZ yaYhIHfJwUF6Ny3SmkL1lDor4Hulv7WI7xyKgI0UdOWAFXqgPGjhjCH2lsCZG4JCwGEw mUPwuzedn3x7+Z3z/cY6GX8SoyndLx0VQVnFCorEWLEBiul4jwo5PRAsY9oaDpNkmNbe 3goiBCue58pqe0swEE4gO/i0k3+RMsmZvC65g04QvQIRPX0+0MNQpq5sZmISGPavzR7R +vRNmr8L2GchukaV1BR7EzLA1vOh+WwCTZfOZ1APP08E04TtsyTYV+jXNvjpyriU9p9y nsgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067207; x=1685659207; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=7EN19QVchQR1O/U+7gWBQO9KjDeBdf2tyCzS7+tNUxk=; b=G03fosqwmz9UmNUA8A09gK5uuk3Nb7Qnn7+rcVKpVtntzekNAvAJG8aT7Df6YwHKrZ FFed98NjHdQ60BgwzITsbhFl0lAcjlGXnOCFwi+eExTYXwqHN3yabdeSomJO2sqC5WN0 3gB1P0KBLGJfThAO5XOCJZksNG5QsDp/fMWJvsWmaV7A57Jamm7FaJOatGduD0kl1Llb XJlo4HXMnE6oP7DinpIzLhWtB4M76+yWb8Pe6Ihcca1P9CT2apZDWWgOuu5BvD6V1ICR DSFKNhdq9gERFPneB28gCn47z5wbkMmqTQ8b04uKnXSBjfRfBU6feqnMfjqDAi+YIUIB xtaA== X-Gm-Message-State: AC+VfDzDVBKN3/zINJnVqBgqvZDR3RKKAmBa13YKvRGN4ISp2JjliQSl IYKXeJfSvrZ37y/kxQr5jOfQiBn8AM0D X-Google-Smtp-Source: ACHHUZ5Z5yycYCrJNEZxBBnMrV1lhIDqQQEkQtf85U00/hQOrj6abEdRgrljNjx5+5GK5LiKXKVYffluEhOt X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a25:8a88:0:b0:b96:3383:3585 with SMTP id h8-20020a258a88000000b00b9633833585mr91030ybl.4.1683067207493; Tue, 02 May 2023 15:40:07 -0700 (PDT) Date: Tue, 2 May 2023 15:38:15 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-9-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 08/44] perf vendor events intel: Add sapphirerapids metric constraints From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Previously these constraints were disabled as they contained topdown events. Since: https://lore.kernel.org/all/20230312021543.3060328-9-irogers@google.com/ the topdown events are correctly grouped even if no group exists. This change was created by PR: https://github.com/intel/perfmon/pull/71 Signed-off-by: Ian Rogers Tested-by: Kan Liang --- .../arch/x86/sapphirerapids/spr-metrics.json | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json= b/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json index 620fc5bd2217..4308e2483112 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json @@ -290,6 +290,7 @@ }, { "BriefDescription": "This metric represents overall arithmetic flo= ating-point (FP) operations fraction the CPU has executed (retired)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector + tma_f= p_amx", "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_gr= oup", "MetricName": "tma_fp_arith", @@ -412,6 +413,7 @@ }, { "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_m= ispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_= misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * tma_info_slots / B= R_MISP_RETIRED.ALL_BRANCHES", "MetricGroup": "Bad;BrMispredicts;tma_issueBM", "MetricName": "tma_info_branch_misprediction_cost", @@ -457,6 +459,7 @@ }, { "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization = if tma_core_bound < tma_ports_utilization else 1) if tma_info_smt_2t_utiliz= ation > 0.5 else 0)", "MetricGroup": "Cor;SMT", "MetricName": "tma_info_core_bound_likely", @@ -509,6 +512,7 @@ }, { "BriefDescription": "Total pipeline cost of DSB (uop cache) misses= - subset of the Instruction_Fetch_BW Bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_= branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + = tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tm= a_mite))", "MetricGroup": "DSBmiss;Fed;tma_issueFB", "MetricName": "tma_info_dsb_misses", @@ -590,6 +594,7 @@ }, { "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma= _mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icach= e_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_big_cod= e", "MetricGroup": "Fed;FetchBW;Frontend", "MetricName": "tma_info_instruction_fetch_bw", @@ -998,6 +1003,7 @@ }, { "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_me= mory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + t= ma_pmm_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_dt= lb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_= blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + t= ma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtl= b_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_st= reaming_stores)))", "MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB", "MetricName": "tma_info_memory_data_tlbs", @@ -1006,6 +1012,7 @@ }, { "BriefDescription": "Total pipeline cost of Memory Latency related= bottlenecks (external memory and off-core caches)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dra= m_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_= store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + = tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound= + tma_pmm_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_= accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_b= ound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_p= mm_bound + tma_store_bound))", "MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat", "MetricName": "tma_info_memory_latency", @@ -1014,6 +1021,7 @@ }, { "BriefDescription": "Total pipeline cost of Branch Misprediction r= elated bottlenecks", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency *= tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_i= cache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", "MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM", "MetricName": "tma_info_mispredictions", @@ -1054,6 +1062,7 @@ }, { "BriefDescription": "Average number of Uops retired in cycles wher= e at least one uop has retired.", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_retiring * tma_info_slots / cpu@UOPS_RETIRED.SL= OTS\\,cmask\\=3D1@", "MetricGroup": "Pipeline;Ret", "MetricName": "tma_info_retire" @@ -1328,6 +1337,7 @@ }, { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring memory operations -- uops for memory load or store a= ccesses.", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_light_operations * MEM_UOP_RETIRED.ANY / (tma_r= etiring * tma_info_slots)", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", "MetricName": "tma_memory_operations", @@ -1399,6 +1409,7 @@ }, { "BriefDescription": "This metric represents the remaining light uo= ps fraction the CPU has executed - remaining means not covered by other sib= ling nodes", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_i= nt_operations + tma_memory_operations + tma_fused_instructions + tma_non_fu= sed_branches + tma_nop_instructions))", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", "MetricName": "tma_other_light_ops", --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E1E5C7EE21 for ; Tue, 2 May 2023 22:40:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230084AbjEBWk6 (ORCPT ); Tue, 2 May 2023 18:40:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57300 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230078AbjEBWkz (ORCPT ); Tue, 2 May 2023 18:40:55 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB7E92D6D for ; Tue, 2 May 2023 15:40:21 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-b9a753ce33cso8824945276.2 for ; Tue, 02 May 2023 15:40:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067216; x=1685659216; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:from:to:cc:subject:date :message-id:reply-to; bh=JmL6hSbfwKLQ2Rkdau58A867nnjWXNzjuwqbLX3orRI=; b=p0HVrCzKK3SdQEGqL8DDu6W0gYIELMrqr04BWz5egZWLV0X7etg/TxW20lOjLKLLRb HMKfHEGUJnRjhyt1q/M4v8x3b/4vx/2McLkN6wBUHQubFl5FFxpgF8EMHI+FN0FbtRuR /xwN6SOCjeWlvV6tHa7upQC/gSKWegFhiIBoPDohinWnQzu6XxiVzSAdF141GNnY6Crz 57c7nbkGzo/DeZ1Fu4tzNYMXKoFo1Wi408rxY7xElLByFuEWSn0fFPIkbIRyxfk2+1Wc ZalNCJA4z1qiojZEITqhpzPKAlJ2t7Wjyo64BTLUxjK35tCqwk8SyHtGjaWm0dCNzDGA DQ8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067216; x=1685659216; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=JmL6hSbfwKLQ2Rkdau58A867nnjWXNzjuwqbLX3orRI=; b=O1kf/eV8U9oP8gxDrtxc1cNfwjdCLQbzb2LDPzOnUb96WjCwQ9QhqFqrZPQ7nxUDvl 0D2XzaXKxl0UayUY8HwFg9xT7k4l0v9Bqf/Z0wDpjUI+oYdIl4drvpG1SA9UYgbp+1O7 kcIictKU75OdzAjvn+a48+S2dZ/kInWnAyoOAAadhjb7ID9qirFQQSe1Q8QXIm0hTTQ7 FEEYGWaOUxetorYhyD8VZoqMck+cRLk/7azd4RC87LNkLE1SS9IcLkVBHBB+weEyiMoN L1hG9Ybm4Y5zObig9pSreZgFJtdQpKwxUv3ezcPRaYhB9i6itVsaHodQJd5qBZlvm6Bv rtLw== X-Gm-Message-State: AC+VfDyzRWslcQr/byJLogtD7zxFITrefALxJPQCpjn0vAGAsG7KlvrU xcqCbPYdiFR29TChGfCnVi31DW17gIns X-Google-Smtp-Source: ACHHUZ4x652Df5lZBpcACbhi+E28WNvkzFhzgZL6XDlnmSPTZdnUsW1rRkupP0Cq/2lAU2/wtqRP3IWafF32 X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a05:6902:18c3:b0:b95:6b30:9752 with SMTP id ck3-20020a05690218c300b00b956b309752mr11299856ybb.12.1683067215959; Tue, 02 May 2023 15:40:15 -0700 (PDT) Date: Tue, 2 May 2023 15:38:16 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-10-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 09/44] perf vendor events intel: Add tigerlake metric constraints From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Previously these constraints were disabled as they contained topdown events. Since: https://lore.kernel.org/all/20230312021543.3060328-9-irogers@google.com/ the topdown events are correctly grouped even if no group exists. This change was created by PR: https://github.com/intel/perfmon/pull/71 Signed-off-by: Ian Rogers Tested-by: Kan Liang --- .../pmu-events/arch/x86/tigerlake/tgl-metrics.json | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json b/to= ols/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json index b442ed4acfbb..ae62bacf9f5e 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json @@ -311,6 +311,7 @@ }, { "BriefDescription": "This metric represents overall arithmetic flo= ating-point (FP) operations fraction the CPU has executed (retired)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_gr= oup", "MetricName": "tma_fp_arith", @@ -415,6 +416,7 @@ }, { "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_m= ispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_= misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * tma_info_slots / B= R_MISP_RETIRED.ALL_BRANCHES", "MetricGroup": "Bad;BrMispredicts;tma_issueBM", "MetricName": "tma_info_branch_misprediction_cost", @@ -460,6 +462,7 @@ }, { "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization = if tma_core_bound < tma_ports_utilization else 1) if tma_info_smt_2t_utiliz= ation > 0.5 else 0)", "MetricGroup": "Cor;SMT", "MetricName": "tma_info_core_bound_likely", @@ -512,6 +515,7 @@ }, { "BriefDescription": "Total pipeline cost of DSB (uop cache) misses= - subset of the Instruction_Fetch_BW Bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_= branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + = tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tm= a_lsd + tma_mite))", "MetricGroup": "DSBmiss;Fed;tma_issueFB", "MetricName": "tma_info_dsb_misses", @@ -593,6 +597,7 @@ }, { "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma= _mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icach= e_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_big_cod= e", "MetricGroup": "Fed;FetchBW;Frontend", "MetricName": "tma_info_instruction_fetch_bw", @@ -957,6 +962,7 @@ }, { "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_me= mory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + t= ma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_= dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fw= d_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound += tma_l3_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_= false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores= )))", "MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB", "MetricName": "tma_info_memory_data_tlbs", @@ -965,6 +971,7 @@ }, { "BriefDescription": "Total pipeline cost of Memory Latency related= bottlenecks (external memory and off-core caches)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dra= m_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (= tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (= tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bou= nd) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tm= a_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_= bound + tma_l2_bound + tma_l3_bound + tma_store_bound))", "MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat", "MetricName": "tma_info_memory_latency", @@ -973,6 +980,7 @@ }, { "BriefDescription": "Total pipeline cost of Branch Misprediction r= elated bottlenecks", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency *= tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_i= cache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", "MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM", "MetricName": "tma_info_mispredictions", @@ -1024,6 +1032,7 @@ }, { "BriefDescription": "Average number of Uops retired in cycles wher= e at least one uop has retired.", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_retiring * tma_info_slots / cpu@UOPS_RETIRED.SL= OTS\\,cmask\\=3D1@", "MetricGroup": "Pipeline;Ret", "MetricName": "tma_info_retire" @@ -1221,6 +1230,7 @@ }, { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring memory operations -- uops for memory load or store a= ccesses.", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_= RETIRED.ANY", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", "MetricName": "tma_memory_operations", @@ -1291,6 +1301,7 @@ }, { "BriefDescription": "This metric represents the remaining light uo= ps fraction the CPU has executed - remaining means not covered by other sib= ling nodes", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_m= emory_operations + tma_branch_instructions + tma_nop_instructions))", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", "MetricName": "tma_other_light_ops", --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5B62C19F20 for ; Tue, 2 May 2023 22:41:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230074AbjEBWlB (ORCPT ); Tue, 2 May 2023 18:41:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57180 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230048AbjEBWk5 (ORCPT ); Tue, 2 May 2023 18:40:57 -0400 Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0E13E358E for ; Tue, 2 May 2023 15:40:25 -0700 (PDT) Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-552f2f940edso84337997b3.0 for ; Tue, 02 May 2023 15:40:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067222; x=1685659222; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=2hc6sYqaX/JTEzA/WD5PdQqzvPbvzN/Ao//5MFid2Dk=; b=cPM/XeaYqW8ATEh2et7lHdr0dAMzZNIm5WbuxFf8j8j45I0GkN69BbdrMqfbvtTjFz /rwgkYHSWC2gH7+pVPv4Tep2Zl1i4ofTcxJWGu21WQU5f2n+npUt3CnreJzRJfB0Vuuc DRLXb+f4x0X3cZe4SFAa3gfzN7lHKQU0gtpHFQOZ3H2Ald2QdjFk/xpj2qKEhrAn+EoH kt7DdfJLOuiwhz9l+SqgE85rpt5CJDQtCeQYyHkr7RX09hbO0RTSaiXsSo6u3mg3oXkJ bWUtBTofyZCuUyzSy8IIZZWqd6+PoU69fjDSZ/yuISJ9duzO3QAhqmVIFpUU3eFVgrp9 cOCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067222; x=1685659222; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=2hc6sYqaX/JTEzA/WD5PdQqzvPbvzN/Ao//5MFid2Dk=; b=XhsPtfRnYhVfaqAHWS/qiHv0DLxwC9HmA2RKJ1l6mwsKXY3fu+9Kllg9UkU3YUy2Mc Ixc5Y2cgZcFVXpsEQ2/Mke13NgGbugD3sY9t62A4F5Lg3xtLLHwSFo72pKvWrMpZ1XTo vGQcfAgqSErOEfka/Kuzl2n19tJ1qu/KDU34e6R0tpmrnYdNKe3vRO3mXznuhjDrjiTR /JPTEMac9K8e9ZJy7zPp7Tv9Dqx7+q9QmjvKroe8idmxSky6HwDVYLUmBGYsXNwzvMsj iREEKBrcWh6anE3i7NlAbYzw/X+IJDni3bP0Voh9/E2Vz8+Yv+tmyl6YniHFc6Z48auZ MlSA== X-Gm-Message-State: AC+VfDyCnWy/hxUEvATpSCeqo6wBxVB1VhY9JkYj064UdSNQJXD8Bc+r LHn+Zp7Mt0m6lk2pkKxKcblEPt976puR X-Google-Smtp-Source: ACHHUZ6aqJfkF1DqLqV5dk0PcZwobR7Cpms4xHZeUifk8XAn1c6w2Zms4SRaNZSJKKQ3uNmdCClNiXbd+SuL X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a81:a8c4:0:b0:556:edb1:1fb0 with SMTP id f187-20020a81a8c4000000b00556edb11fb0mr11609056ywh.10.1683067222531; Tue, 02 May 2023 15:40:22 -0700 (PDT) Date: Tue, 2 May 2023 15:38:17 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-11-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 10/44] perf test: Test more sysfs events From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Parse events for all PMUs, and not just cpu, in test "Parsing of all PMU events from sysfs". Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/tests/parse-events.c | 129 ++++++++++++++++++-------------- 1 file changed, 71 insertions(+), 58 deletions(-) diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index 8068cfd89b84..3721a2182f45 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -7,6 +7,7 @@ #include "debug.h" #include "pmu.h" #include "pmu-hybrid.h" +#include "pmus.h" #include #include #include "fncache.h" @@ -558,7 +559,8 @@ static int test__checkevent_pmu_events(struct evlist *e= vlist) struct evsel *evsel =3D evlist__first(evlist); =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type = || + strcmp(evsel->pmu_name, "cpu")); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", @@ -590,7 +592,8 @@ static int test__checkevent_pmu_events_mix(struct evlis= t *evlist) /* cpu/pmu-event/u*/ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type = || + strcmp(evsel->pmu_name, "cpu")); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", @@ -2225,74 +2228,84 @@ static int test_pmu(void) =20 static int test__pmu_events(struct test_suite *test __maybe_unused, int su= btest __maybe_unused) { - struct stat st; - char path[PATH_MAX]; - struct dirent *ent; - DIR *dir; - int ret; - - if (!test_pmu()) - return TEST_SKIP; + struct perf_pmu *pmu; + int ret =3D TEST_OK; =20 - snprintf(path, PATH_MAX, "%s/bus/event_source/devices/cpu/events/", - sysfs__mountpoint()); + if (list_empty(&pmus)) + perf_pmu__scan(NULL); =20 - ret =3D stat(path, &st); - if (ret) { - pr_debug("omitting PMU cpu events tests: %s\n", path); - return TEST_OK; - } + perf_pmus__for_each_pmu(pmu) { + struct stat st; + char path[PATH_MAX]; + struct dirent *ent; + DIR *dir; + int err; =20 - dir =3D opendir(path); - if (!dir) { - pr_debug("can't open pmu event dir: %s\n", path); - return TEST_FAIL; - } + snprintf(path, PATH_MAX, "%s/bus/event_source/devices/%s/events/", + sysfs__mountpoint(), pmu->name); =20 - ret =3D TEST_OK; - while ((ent =3D readdir(dir))) { - struct evlist_test e =3D { .name =3D NULL, }; - char name[2 * NAME_MAX + 1 + 12 + 3]; - int test_ret; + err =3D stat(path, &st); + if (err) { + pr_debug("skipping PMU %s events tests: %s\n", pmu->name, path); + continue; + } =20 - /* Names containing . are special and cannot be used directly */ - if (strchr(ent->d_name, '.')) + dir =3D opendir(path); + if (!dir) { + pr_debug("can't open pmu event dir: %s\n", path); + ret =3D combine_test_results(ret, TEST_SKIP); continue; + } =20 - snprintf(name, sizeof(name), "cpu/event=3D%s/u", ent->d_name); + while ((ent =3D readdir(dir))) { + struct evlist_test e =3D { .name =3D NULL, }; + char name[2 * NAME_MAX + 1 + 12 + 3]; + int test_ret; =20 - e.name =3D name; - e.check =3D test__checkevent_pmu_events; + /* Names containing . are special and cannot be used directly */ + if (strchr(ent->d_name, '.')) + continue; =20 - test_ret =3D test_event(&e); - if (test_ret !=3D TEST_OK) { - pr_debug("Test PMU event failed for '%s'", name); - ret =3D combine_test_results(ret, test_ret); - } - /* - * Names containing '-' are recognized as prefixes and suffixes - * due to '-' being a legacy PMU separator. This fails when the - * prefix or suffix collides with an existing legacy token. For - * example, branch-brs has a prefix (branch) that collides with - * a PE_NAME_CACHE_TYPE token causing a parse error as a suffix - * isn't expected after this. As event names in the config - * slashes are allowed a '-' in the name we check this works - * above. - */ - if (strchr(ent->d_name, '-')) - continue; + snprintf(name, sizeof(name), "%s/event=3D%s/u", pmu->name, ent->d_name); =20 - snprintf(name, sizeof(name), "%s:u,cpu/event=3D%s/u", ent->d_name, ent->= d_name); - e.name =3D name; - e.check =3D test__checkevent_pmu_events_mix; - test_ret =3D test_event(&e); - if (test_ret !=3D TEST_OK) { - pr_debug("Test PMU event failed for '%s'", name); - ret =3D combine_test_results(ret, test_ret); + e.name =3D name; + e.check =3D test__checkevent_pmu_events; + + test_ret =3D test_event(&e); + if (test_ret !=3D TEST_OK) { + pr_debug("Test PMU event failed for '%s'", name); + ret =3D combine_test_results(ret, test_ret); + } + + if (!is_pmu_core(pmu->name)) + continue; + + /* + * Names containing '-' are recognized as prefixes and suffixes + * due to '-' being a legacy PMU separator. This fails when the + * prefix or suffix collides with an existing legacy token. For + * example, branch-brs has a prefix (branch) that collides with + * a PE_NAME_CACHE_TYPE token causing a parse error as a suffix + * isn't expected after this. As event names in the config + * slashes are allowed a '-' in the name we check this works + * above. + */ + if (strchr(ent->d_name, '-')) + continue; + + snprintf(name, sizeof(name), "%s:u,%s/event=3D%s/u", + ent->d_name, pmu->name, ent->d_name); + e.name =3D name; + e.check =3D test__checkevent_pmu_events_mix; + test_ret =3D test_event(&e); + if (test_ret !=3D TEST_OK) { + pr_debug("Test PMU event failed for '%s'", name); + ret =3D combine_test_results(ret, test_ret); + } } - } =20 - closedir(dir); + closedir(dir); + } return ret; } =20 --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 991B7C19F20 for ; Tue, 2 May 2023 22:41:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230082AbjEBWlO (ORCPT ); Tue, 2 May 2023 18:41:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230015AbjEBWlM (ORCPT ); Tue, 2 May 2023 18:41:12 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B1A93A9A for ; Tue, 2 May 2023 15:40:32 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-b9a7c45b8e1so7730734276.3 for ; Tue, 02 May 2023 15:40:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067229; x=1685659229; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=DOnZ2OKjlCq2CMx90UX2ZPWCEDMEl/hBSCdauBOSwyg=; b=IoTJMyEobSDIJv1QyUDMmxGGV9wHG4+zMd6uosrqg//eIBbse9xgINyme8g2w9CntC DFPbZ3X8+n3aJsIiNC2/Ul7Bdojx6o5tVgszEn9B/qpRuVxKNt9Ow8hw1pKeqZLeYcd1 IbJoq6P1NIS4QZEyvKfTKTSOANbl+4Bnau+JSClba+FF2atLEFMO2sAVnVw+Or5aZVRI 2EfixSZzj+Q8A3CR0a47urNbRvtSK/ELNieLxZd5ikydlCWCZTF5VXkCR7GH503SqaoI 8rESINzQAlxOqwcyWsxz/xdToKiviJMW16wIHCHkAJTqjmQrVWrfe+L0Z4A6iSbV3UTh JldQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067229; x=1685659229; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=DOnZ2OKjlCq2CMx90UX2ZPWCEDMEl/hBSCdauBOSwyg=; b=a2V59TNnp5oSj80nGqKsjeYikIG1LUyLVQ0qSLQlcECxwT076XktV73Zy4GxcRuHdH dlNWpsVjvZ7KL8DA8BbMVB00wFhR/nk8PenHQcLQoWH5jaOBeS4JFuHaPp4djcupaCKc uZMc4xvo5BpBxSB3vT4pF8N0S/T3G44YVvyGLTt4UcErb26SL/hjyNzquLzu6mZvhS2R 61bNSPQ7dRPT+kgegE52ly402U0iQgHdNcR3o66aNIVqBh2EWVmytlpMQ40q6zdAcMMH wP31AWGMR8dzUC7s1wilkYeu/4W0WZGY5JkGsncUZdTk5vNLs90K6iBwSx0+YvSHaHyF +sew== X-Gm-Message-State: AC+VfDzJZTbWSCNLpv/vT8L0KDDdm6gMMfAVZ5xKWTKMKobSExouRICM AYBKe6N9pB1m88X5hE4AceGTMEi1owVn X-Google-Smtp-Source: ACHHUZ7bkS+Y09SwE9jvgupciznHDby6NANZZhdZ47txsHbvKXbziwG5oshPrZcmZcSd7aM/aAZ/WxBv1xJX X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a25:d250:0:b0:b9e:2f92:52b with SMTP id j77-20020a25d250000000b00b9e2f92052bmr2684908ybg.2.1683067229666; Tue, 02 May 2023 15:40:29 -0700 (PDT) Date: Tue, 2 May 2023 15:38:18 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-12-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 11/44] perf test: Use valid for PMU tests From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rather than skip all tests in test__events_pmu if PMU cpu isn't present, use the per-test valid test. This allows the running of software PMU tests on hybrid and arm systems. Reviewed-by: Kan Liang Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/tests/parse-events.c | 27 +++++++++------------------ 1 file changed, 9 insertions(+), 18 deletions(-) diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index 3721a2182f45..c06fa7653ac2 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -1432,6 +1432,11 @@ static int test__checkevent_config_cache(struct evli= st *evlist) return TEST_OK; } =20 +static bool test__pmu_cpu_valid(void) +{ + return !!perf_pmu__find("cpu"); +} + static bool test__intel_pt_valid(void) { return !!perf_pmu__find("intel_pt"); @@ -1981,21 +1986,25 @@ static const struct evlist_test test__events[] =3D { static const struct evlist_test test__events_pmu[] =3D { { .name =3D "cpu/config=3D10,config1,config2=3D3,period=3D1000/u", + .valid =3D test__pmu_cpu_valid, .check =3D test__checkevent_pmu, /* 0 */ }, { .name =3D "cpu/config=3D1,name=3Dkrava/u,cpu/config=3D2/u", + .valid =3D test__pmu_cpu_valid, .check =3D test__checkevent_pmu_name, /* 1 */ }, { .name =3D "cpu/config=3D1,call-graph=3Dfp,time,period=3D100000/,cpu/con= fig=3D2,call-graph=3Dno,time=3D0,period=3D2000/", + .valid =3D test__pmu_cpu_valid, .check =3D test__checkevent_pmu_partial_time_callgraph, /* 2 */ }, { .name =3D "cpu/name=3D'COMPLEX_CYCLES_NAME:orig=3Dcycles,desc=3Dchip-cl= ock-ticks',period=3D0x1,event=3D0x2/ukp", + .valid =3D test__pmu_cpu_valid, .check =3D test__checkevent_complex_name, /* 3 */ }, @@ -2211,21 +2220,6 @@ static int test__terms2(struct test_suite *test __ma= ybe_unused, int subtest __ma return test_terms(test__terms, ARRAY_SIZE(test__terms)); } =20 -static int test_pmu(void) -{ - struct stat st; - char path[PATH_MAX]; - int ret; - - snprintf(path, PATH_MAX, "%s/bus/event_source/devices/cpu/format/", - sysfs__mountpoint()); - - ret =3D stat(path, &st); - if (ret) - pr_debug("omitting PMU cpu tests\n"); - return !ret; -} - static int test__pmu_events(struct test_suite *test __maybe_unused, int su= btest __maybe_unused) { struct perf_pmu *pmu; @@ -2311,9 +2305,6 @@ static int test__pmu_events(struct test_suite *test _= _maybe_unused, int subtest =20 static int test__pmu_events2(struct test_suite *test __maybe_unused, int s= ubtest __maybe_unused) { - if (!test_pmu()) - return TEST_SKIP; - return test_events(test__events_pmu, ARRAY_SIZE(test__events_pmu)); } =20 --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50657C77B75 for ; Tue, 2 May 2023 22:41:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230094AbjEBWla (ORCPT ); Tue, 2 May 2023 18:41:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57726 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230086AbjEBWlV (ORCPT ); Tue, 2 May 2023 18:41:21 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 63C483ABA for ; Tue, 2 May 2023 15:40:40 -0700 (PDT) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-55a40d32a6bso32953517b3.2 for ; Tue, 02 May 2023 15:40:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067238; x=1685659238; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=dK5S8mU9rwbMcBHhA51JwhTrLHY8Q2AOOjtiR8G9v4Y=; b=k05Rs1L+/P+dL52ExnC3GepqHz5YxI4hF8D3xtemOGb+/3E0XruDnFShQx/AkzK9Le 8ffrEsZLMpIRYOWT0QUXydNhMaw7xtXQeCoVbVTNEbNl/pdOeepRLfB8JABv2hymulxt 2f44sdHQkD/X43MPJrLpEBBRKrfvQMV/1uEKAfriCn+dt+4mxSm1gSmo8ljm6wNgFY7y a4nMjuyqsfHX+VJ/9vRzWEHTFHcyCkLDFI5ODrhJ7wskv1lONwQeywUZSSkPzwycKsu3 QnUYTAqBnwBTltxGT+3fmIxV3+1zyjEvMhMYAQ0ULNKTRN86gt1cPOj/lIpAGYiIJkUO FqNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067238; x=1685659238; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=dK5S8mU9rwbMcBHhA51JwhTrLHY8Q2AOOjtiR8G9v4Y=; b=SInIrX/fUYgl8uyNwUrO4HGbPFg8EWSM1tb2G0UUxFUkaYDjHRCEjFL3MYiH9zlMs0 84RaeEE/TuAAQglmNX5BXAawfs9Ygg7O+hnAxY6N33peErsaypfYnXWgpWANz6K3/h4Y DQbc/dY7HXZ4BbnYIxGp+KjO69UbOvt5n1evhXLgf0KDAB0RUOVow+yNfAhkzsN2QTHV 9vxQ1+5HGFYua7AOpM7gLJh0hR0u0pSMOuGmIZ1Gw/TMb2HBYfIAgkSkXNcP0IVepeZp KUkd6Ghv739iQc/QkDQ6shyVCh+GkY5x+HC/knLx8Hh66Tjouhy+XQnreTXTNDeyfXf7 +2gQ== X-Gm-Message-State: AC+VfDxnM8ka4ciycGv2QDpvJTp5IGRDPkSX4syKs70gCIZOioBI4pIA OWRJrlDjg9KeYfjsm0xdpJ9+/lDSTdg2 X-Google-Smtp-Source: ACHHUZ7W2ieYrIqlSQXSrqb47BfmN5rhcvBoq+5vjU8fiJ+oO7Sh4qNeygmVcPn47CbYft/b96bPpqx+rRm7 X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a81:ef04:0:b0:543:bbdb:8c2b with SMTP id o4-20020a81ef04000000b00543bbdb8c2bmr11404682ywm.10.1683067238293; Tue, 02 May 2023 15:40:38 -0700 (PDT) Date: Tue, 2 May 2023 15:38:19 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-13-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 12/44] perf test: Mask configs with extended types then test From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add helper to test the config of an evsel. Dependent on the type of the evsel, mask the config so that high-bits containing the extended PMU type are ignored. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/tests/parse-events.c | 197 ++++++++++++++------------------ 1 file changed, 88 insertions(+), 109 deletions(-) diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index c06fa7653ac2..4b00cb4aa73a 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -21,6 +21,21 @@ #define PERF_TP_SAMPLE_TYPE (PERF_SAMPLE_RAW | PERF_SAMPLE_TIME | \ PERF_SAMPLE_CPU | PERF_SAMPLE_PERIOD) =20 +static bool test_config(const struct evsel *evsel, __u64 expected_config) +{ + __u32 type =3D evsel->core.attr.type; + __u64 config =3D evsel->core.attr.config; + + if (type =3D=3D PERF_TYPE_HARDWARE || type =3D=3D PERF_TYPE_HW_CACHE) { + /* + * HARDWARE and HW_CACHE events encode the PMU's extended type + * in the top 32-bits. Mask in order to ignore. + */ + config &=3D PERF_HW_EVENT_MASK; + } + return config =3D=3D expected_config; +} + #ifdef HAVE_LIBTRACEEVENT =20 #if defined(__s390x__) @@ -87,7 +102,7 @@ static int test__checkevent_raw(struct evlist *evlist) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 0x1a =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); return TEST_OK; } =20 @@ -97,7 +112,7 @@ static int test__checkevent_numeric(struct evlist *evlis= t) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", 1 =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 1 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 1)); return TEST_OK; } =20 @@ -107,8 +122,7 @@ static int test__checkevent_symbolic_name(struct evlist= *evlist) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_INSTRUCTIONS =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_INSTRUCT= IONS)); return TEST_OK; } =20 @@ -118,8 +132,7 @@ static int test__checkevent_symbolic_name_config(struct= evlist *evlist) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CPU_CYCLES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); /* * The period value gets configured within evlist__config, * while this test executes only parse events method. @@ -139,8 +152,7 @@ static int test__checkevent_symbolic_alias(struct evlis= t *evlist) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_SOFTWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_SW_PAGE_FAULTS =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_SW_PAGE_FAU= LTS)); return TEST_OK; } =20 @@ -150,7 +162,7 @@ static int test__checkevent_genhw(struct evlist *evlist) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HW_CACHE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", (1 << 16) =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 1 << 16)); return TEST_OK; } =20 @@ -160,7 +172,7 @@ static int test__checkevent_breakpoint(struct evlist *e= vlist) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_BREAKPOINT =3D=3D evsel->core.att= r.type); - TEST_ASSERT_VAL("wrong config", 0 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0)); TEST_ASSERT_VAL("wrong bp_type", (HW_BREAKPOINT_R | HW_BREAKPOINT_W) =3D= =3D evsel->core.attr.bp_type); TEST_ASSERT_VAL("wrong bp_len", HW_BREAKPOINT_LEN_4 =3D=3D @@ -174,7 +186,7 @@ static int test__checkevent_breakpoint_x(struct evlist = *evlist) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_BREAKPOINT =3D=3D evsel->core.att= r.type); - TEST_ASSERT_VAL("wrong config", 0 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0)); TEST_ASSERT_VAL("wrong bp_type", HW_BREAKPOINT_X =3D=3D evsel->core.attr.bp_type); TEST_ASSERT_VAL("wrong bp_len", sizeof(long) =3D=3D evsel->core.attr.bp_l= en); @@ -188,7 +200,7 @@ static int test__checkevent_breakpoint_r(struct evlist = *evlist) TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_BREAKPOINT =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 0 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0)); TEST_ASSERT_VAL("wrong bp_type", HW_BREAKPOINT_R =3D=3D evsel->core.attr.bp_type); TEST_ASSERT_VAL("wrong bp_len", @@ -203,7 +215,7 @@ static int test__checkevent_breakpoint_w(struct evlist = *evlist) TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_BREAKPOINT =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 0 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0)); TEST_ASSERT_VAL("wrong bp_type", HW_BREAKPOINT_W =3D=3D evsel->core.attr.bp_type); TEST_ASSERT_VAL("wrong bp_len", @@ -218,7 +230,7 @@ static int test__checkevent_breakpoint_rw(struct evlist= *evlist) TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_BREAKPOINT =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 0 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0)); TEST_ASSERT_VAL("wrong bp_type", (HW_BREAKPOINT_R|HW_BREAKPOINT_W) =3D=3D evsel->core.attr.bp_type); TEST_ASSERT_VAL("wrong bp_len", @@ -447,7 +459,7 @@ static int test__checkevent_pmu(struct evlist *evlist) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 10 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 10)); TEST_ASSERT_VAL("wrong config1", 1 =3D=3D evsel->core.attr.config1); TEST_ASSERT_VAL("wrong config2", 3 =3D=3D evsel->core.attr.config2); TEST_ASSERT_VAL("wrong config3", 0 =3D=3D evsel->core.attr.config3); @@ -469,7 +481,7 @@ static int test__checkevent_list(struct evlist *evlist) =20 /* r1 */ TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 1 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 1)); TEST_ASSERT_VAL("wrong config1", 0 =3D=3D evsel->core.attr.config1); TEST_ASSERT_VAL("wrong config2", 0 =3D=3D evsel->core.attr.config2); TEST_ASSERT_VAL("wrong config3", 0 =3D=3D evsel->core.attr.config3); @@ -492,7 +504,7 @@ static int test__checkevent_list(struct evlist *evlist) /* 1:1:hp */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", 1 =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 1 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 1)); TEST_ASSERT_VAL("wrong exclude_user", evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -509,14 +521,14 @@ static int test__checkevent_pmu_name(struct evlist *e= vlist) /* cpu/config=3D1,name=3Dkrava/u */ TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 1 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 1)); TEST_ASSERT_VAL("wrong name", !strcmp(evsel__name(evsel), "krava")); =20 /* cpu/config=3D2/u" */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 2 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 2)); TEST_ASSERT_VAL("wrong name", !strcmp(evsel__name(evsel), "cpu/config=3D2/u")); =20 @@ -530,7 +542,7 @@ static int test__checkevent_pmu_partial_time_callgraph(= struct evlist *evlist) /* cpu/config=3D1,call-graph=3Dfp,time,period=3D100000/ */ TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 1 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 1)); /* * The period, time and callgraph value gets configured within evlist__co= nfig, * while this test executes only parse events method. @@ -542,7 +554,7 @@ static int test__checkevent_pmu_partial_time_callgraph(= struct evlist *evlist) /* cpu/config=3D2,call-graph=3Dno,time=3D0,period=3D2000/ */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 2 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 2)); /* * The period, time and callgraph value gets configured within evlist__co= nfig, * while this test executes only parse events method. @@ -696,8 +708,7 @@ static int test__group1(struct evlist *evlist) /* instructions:k */ evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_INSTRUCTIONS =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_INSTRUCT= IONS)); TEST_ASSERT_VAL("wrong exclude_user", evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -712,8 +723,7 @@ static int test__group1(struct evlist *evlist) /* cycles:upp */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CPU_CYCLES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -738,8 +748,7 @@ static int test__group2(struct evlist *evlist) /* faults + :ku modifier */ evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong type", PERF_TYPE_SOFTWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_SW_PAGE_FAULTS =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_SW_PAGE_FAU= LTS)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -754,8 +763,7 @@ static int test__group2(struct evlist *evlist) /* cache-references + :u modifier */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CACHE_REFERENCES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CACHE_RE= FERENCES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -769,8 +777,7 @@ static int test__group2(struct evlist *evlist) /* cycles:k */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CPU_CYCLES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong exclude_user", evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -813,8 +820,7 @@ static int test__group3(struct evlist *evlist __maybe_u= nused) /* group1 cycles:kppp */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CPU_CYCLES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong exclude_user", evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -830,8 +836,7 @@ static int test__group3(struct evlist *evlist __maybe_u= nused) /* group2 cycles + G modifier */ evsel =3D leader =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CPU_CYCLES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -848,7 +853,7 @@ static int test__group3(struct evlist *evlist __maybe_u= nused) /* group2 1:3 + G modifier */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", 1 =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 3 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 3)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -862,8 +867,7 @@ static int test__group3(struct evlist *evlist __maybe_u= nused) /* instructions:u */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_INSTRUCTIONS =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_INSTRUCT= IONS)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -887,8 +891,7 @@ static int test__group4(struct evlist *evlist __maybe_u= nused) /* cycles:u + p */ evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CPU_CYCLES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -905,8 +908,7 @@ static int test__group4(struct evlist *evlist __maybe_u= nused) /* instructions:kp + p */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_INSTRUCTIONS =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_INSTRUCT= IONS)); TEST_ASSERT_VAL("wrong exclude_user", evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -931,8 +933,7 @@ static int test__group5(struct evlist *evlist __maybe_u= nused) /* cycles + G */ evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CPU_CYCLES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -948,8 +949,7 @@ static int test__group5(struct evlist *evlist __maybe_u= nused) /* instructions + G */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_INSTRUCTIONS =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_INSTRUCT= IONS)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -963,8 +963,7 @@ static int test__group5(struct evlist *evlist __maybe_u= nused) /* cycles:G */ evsel =3D leader =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CPU_CYCLES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -980,8 +979,7 @@ static int test__group5(struct evlist *evlist __maybe_u= nused) /* instructions:G */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_INSTRUCTIONS =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_INSTRUCT= IONS)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -994,8 +992,7 @@ static int test__group5(struct evlist *evlist __maybe_u= nused) /* cycles */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CPU_CYCLES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -1017,8 +1014,7 @@ static int test__group_gh1(struct evlist *evlist) /* cycles + :H group modifier */ evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CPU_CYCLES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -1033,8 +1029,7 @@ static int test__group_gh1(struct evlist *evlist) /* cache-misses:G + :H group modifier */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CACHE_MISSES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CACHE_MI= SSES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -1057,8 +1052,7 @@ static int test__group_gh2(struct evlist *evlist) /* cycles + :G group modifier */ evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CPU_CYCLES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -1073,8 +1067,7 @@ static int test__group_gh2(struct evlist *evlist) /* cache-misses:H + :G group modifier */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CACHE_MISSES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CACHE_MI= SSES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -1097,8 +1090,7 @@ static int test__group_gh3(struct evlist *evlist) /* cycles:G + :u group modifier */ evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CPU_CYCLES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -1113,8 +1105,7 @@ static int test__group_gh3(struct evlist *evlist) /* cache-misses:H + :u group modifier */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CACHE_MISSES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CACHE_MI= SSES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -1137,8 +1128,7 @@ static int test__group_gh4(struct evlist *evlist) /* cycles:G + :uG group modifier */ evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CPU_CYCLES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -1153,8 +1143,7 @@ static int test__group_gh4(struct evlist *evlist) /* cache-misses:H + :uG group modifier */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CACHE_MISSES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CACHE_MI= SSES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -1176,8 +1165,7 @@ static int test__leader_sample1(struct evlist *evlist) /* cycles - sampling group leader */ evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CPU_CYCLES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -1191,8 +1179,7 @@ static int test__leader_sample1(struct evlist *evlist) /* cache-misses - not sampling */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CACHE_MISSES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CACHE_MI= SSES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -1205,8 +1192,7 @@ static int test__leader_sample1(struct evlist *evlist) /* branch-misses - not sampling */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_BRANCH_MISSES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_BRANCH_M= ISSES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -1229,8 +1215,7 @@ static int test__leader_sample2(struct evlist *evlist= __maybe_unused) /* instructions - sampling group leader */ evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_INSTRUCTIONS =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_INSTRUCT= IONS)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -1244,8 +1229,7 @@ static int test__leader_sample2(struct evlist *evlist= __maybe_unused) /* branch-misses - not sampling */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_BRANCH_MISSES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_BRANCH_M= ISSES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -1281,8 +1265,7 @@ static int test__pinned_group(struct evlist *evlist) /* cycles - group leader */ evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CPU_CYCLES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong group name", !evsel->group_name); TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); TEST_ASSERT_VAL("wrong pinned", evsel->core.attr.pinned); @@ -1290,14 +1273,12 @@ static int test__pinned_group(struct evlist *evlist) /* cache-misses - can not be pinned, but will go on with the leader */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CACHE_MISSES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CACHE_MI= SSES)); TEST_ASSERT_VAL("wrong pinned", !evsel->core.attr.pinned); =20 /* branch-misses - ditto */ evsel =3D evsel__next(evsel); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_BRANCH_MISSES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_BRANCH_M= ISSES)); TEST_ASSERT_VAL("wrong pinned", !evsel->core.attr.pinned); =20 return TEST_OK; @@ -1325,8 +1306,7 @@ static int test__exclusive_group(struct evlist *evlis= t) /* cycles - group leader */ evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CPU_CYCLES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong group name", !evsel->group_name); TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); TEST_ASSERT_VAL("wrong exclusive", evsel->core.attr.exclusive); @@ -1334,14 +1314,12 @@ static int test__exclusive_group(struct evlist *evl= ist) /* cache-misses - can not be pinned, but will go on with the leader */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CACHE_MISSES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CACHE_MI= SSES)); TEST_ASSERT_VAL("wrong exclusive", !evsel->core.attr.exclusive); =20 /* branch-misses - ditto */ evsel =3D evsel__next(evsel); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_BRANCH_MISSES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_BRANCH_M= ISSES)); TEST_ASSERT_VAL("wrong exclusive", !evsel->core.attr.exclusive); =20 return TEST_OK; @@ -1352,7 +1330,7 @@ static int test__checkevent_breakpoint_len(struct evl= ist *evlist) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_BREAKPOINT =3D=3D evsel->core.att= r.type); - TEST_ASSERT_VAL("wrong config", 0 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0)); TEST_ASSERT_VAL("wrong bp_type", (HW_BREAKPOINT_R | HW_BREAKPOINT_W) =3D= =3D evsel->core.attr.bp_type); TEST_ASSERT_VAL("wrong bp_len", HW_BREAKPOINT_LEN_1 =3D=3D @@ -1367,7 +1345,7 @@ static int test__checkevent_breakpoint_len_w(struct e= vlist *evlist) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_BREAKPOINT =3D=3D evsel->core.att= r.type); - TEST_ASSERT_VAL("wrong config", 0 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0)); TEST_ASSERT_VAL("wrong bp_type", HW_BREAKPOINT_W =3D=3D evsel->core.attr.bp_type); TEST_ASSERT_VAL("wrong bp_len", HW_BREAKPOINT_LEN_2 =3D=3D @@ -1395,8 +1373,7 @@ static int test__checkevent_precise_max_modifier(stru= ct evlist *evlist) =20 TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_SOFTWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_SW_TASK_CLOCK =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_SW_TASK_CLO= CK)); return TEST_OK; } =20 @@ -1454,7 +1431,9 @@ static int test__checkevent_complex_name(struct evlis= t *evlist) { struct evsel *evsel =3D evlist__first(evlist); =20 - TEST_ASSERT_VAL("wrong complex name parsing", evsel__name_is(evsel, "COMP= LEX_CYCLES_NAME:orig=3Dcycles,desc=3Dchip-clock-ticks")); + TEST_ASSERT_VAL("wrong complex name parsing", + evsel__name_is(evsel, + "COMPLEX_CYCLES_NAME:orig=3Dcycles,desc=3Dchip-clock-ticks")); return TEST_OK; } =20 @@ -1464,7 +1443,7 @@ static int test__checkevent_raw_pmu(struct evlist *ev= list) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_SOFTWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", 0x1a =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); return TEST_OK; } =20 @@ -1473,7 +1452,7 @@ static int test__sym_event_slash(struct evlist *evlis= t) struct evsel *evsel =3D evlist__first(evlist); =20 TEST_ASSERT_VAL("wrong type", evsel->core.attr.type =3D=3D PERF_TYPE_HARD= WARE); - TEST_ASSERT_VAL("wrong config", evsel->core.attr.config =3D=3D PERF_COUNT= _HW_CPU_CYCLES); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); return TEST_OK; } @@ -1483,7 +1462,7 @@ static int test__sym_event_dc(struct evlist *evlist) struct evsel *evsel =3D evlist__first(evlist); =20 TEST_ASSERT_VAL("wrong type", evsel->core.attr.type =3D=3D PERF_TYPE_HARD= WARE); - TEST_ASSERT_VAL("wrong config", evsel->core.attr.config =3D=3D PERF_COUNT= _HW_CPU_CYCLES); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong exclude_user", evsel->core.attr.exclude_user); return TEST_OK; } @@ -1550,7 +1529,7 @@ static int test__hybrid_hw_event_with_pmu(struct evli= st *evlist) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 0x3c =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); return TEST_OK; } =20 @@ -1561,12 +1540,12 @@ static int test__hybrid_hw_group_event(struct evlis= t *evlist) evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 0x3c =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); =20 evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 0xc0 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0xc0)); TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); return TEST_OK; } @@ -1582,7 +1561,7 @@ static int test__hybrid_sw_hw_group_event(struct evli= st *evlist) =20 evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 0x3c =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); return TEST_OK; } @@ -1594,7 +1573,7 @@ static int test__hybrid_hw_sw_group_event(struct evli= st *evlist) evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 0x3c =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); =20 evsel =3D evsel__next(evsel); @@ -1610,14 +1589,14 @@ static int test__hybrid_group_modifier1(struct evli= st *evlist) evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 0x3c =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); TEST_ASSERT_VAL("wrong exclude_user", evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); =20 evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 0xc0 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0xc0)); TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); @@ -1631,17 +1610,17 @@ static int test__hybrid_raw1(struct evlist *evlist) if (!perf_pmu__hybrid_mounted("cpu_atom")) { TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entr= ies); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type= ); - TEST_ASSERT_VAL("wrong config", 0x1a =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); return TEST_OK; } =20 TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 0x1a =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); =20 /* The type of second event is randome value */ evsel =3D evsel__next(evsel); - TEST_ASSERT_VAL("wrong config", 0x1a =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); return TEST_OK; } =20 @@ -1651,7 +1630,7 @@ static int test__hybrid_raw2(struct evlist *evlist) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 0x1a =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); return TEST_OK; } =20 --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63C1CC7EE24 for ; Tue, 2 May 2023 22:41:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230105AbjEBWlZ (ORCPT ); Tue, 2 May 2023 18:41:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57700 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230094AbjEBWlU (ORCPT ); Tue, 2 May 2023 18:41:20 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36E212722 for ; Tue, 2 May 2023 15:40:45 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-b9a6f15287eso558758276.1 for ; Tue, 02 May 2023 15:40:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067245; x=1685659245; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=L8nwm9FM63+8LyKX6JPZhyGr0V07Z0tZiVV7cZTfwEo=; b=RryHY3yjpE1k1gRrW1Qmm8/Sj/Tj3bA431RHAOaLshSWLtZOI1IDrfok8oOxQGq+1L srO6LFsU/XHwpHXl1oyzwE/alpKo4htNBqi81q29JUojWWEXr7vCe8JtJ7RIzgEeowue /bIrBh1O0Xt98CGXPJYn8ROD7zZazVf8wqfp9/BF+xQyVaFXMORAaL4hsigZADL8Je9Q mKni2h14dI+1+eNuV22ZdPVB/j6mTGhXRJpEl0jX/Hiy4dqm4qAMXd+ljd4+r92Dr1K+ oamliAIaOSlXc8kjQ+qE6tZMjCfBoaojoaUiV43sM/g7nAJsoNOtJSEVbfOvpvUhvz5X 4tZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067245; x=1685659245; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=L8nwm9FM63+8LyKX6JPZhyGr0V07Z0tZiVV7cZTfwEo=; b=g+lXcdzjKOBhdJax3Wp+aDumACfaEZN/NYUnhjJgPko9UnVO2g5Ls7FQz3hUVEf1eJ ifWGVEImEJiCaFmGx6X/zedvbA2zgUvxNnJr7NvxE0kFmgh97rBCzgEXC3HWt5Vk+YbR ESHTMq/FYvxG6nu611nNLqUowjW8YFM3q5ETuLb7DTbxlSvObX/bYOWL0lIzshkBwWko XTQae6L+i+QQ7cMpSQ/d873OmumOMMXA35kQHc+EuojXCoNJLCD7IXWp/yO8RZH/3VqE bbZrvtK2+6JZ12PUUyzmEENtLh43mZaTKWPvGBfGOXxW7Y0JNkrmoPv9X+U8Gryltlfw pE6g== X-Gm-Message-State: AC+VfDzwqowCmwe5FYSUgLf+md+NEgMse2EktvNnP9YIHOU0tSx9Ot37 zo2AQcP3S5T1m75WUO6eUWNNIFeypeB3 X-Google-Smtp-Source: ACHHUZ5aYfqJ48wRkPJWZd0xz/8ZyNgjy30vQ9zOnan16SX0b/DjkBZhUlkn7Fy4Mvk0BCydktLkxNwuFYp2 X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a81:7e4d:0:b0:559:d859:d749 with SMTP id p13-20020a817e4d000000b00559d859d749mr85943ywn.5.1683067244808; Tue, 02 May 2023 15:40:44 -0700 (PDT) Date: Tue, 2 May 2023 15:38:20 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-14-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 13/44] perf test: Test more with config_cache From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" test__checkevent_config_cache checks the parsing of "L1-dcache-misses/name=3Dcachepmu/". Don't just check that the name is set correctly, also validate the rest of the perf_event_attr for L1-dcache-misses. Reviewed-by: Kan Liang Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/tests/parse-events.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index 4b00cb4aa73a..3f75f0315db8 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -1406,7 +1406,7 @@ static int test__checkevent_config_cache(struct evlis= t *evlist) struct evsel *evsel =3D evlist__first(evlist); =20 TEST_ASSERT_VAL("wrong name setting", evsel__name_is(evsel, "cachepmu")); - return TEST_OK; + return test__checkevent_genhw(evlist); } =20 static bool test__pmu_cpu_valid(void) --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DC95C19F20 for ; Tue, 2 May 2023 22:41:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230140AbjEBWli (ORCPT ); Tue, 2 May 2023 18:41:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57844 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230101AbjEBWl1 (ORCPT ); Tue, 2 May 2023 18:41:27 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 99186272B for ; Tue, 2 May 2023 15:40:55 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-b8f6bef3d4aso9045066276.0 for ; Tue, 02 May 2023 15:40:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067253; x=1685659253; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=BX+wo12NQqjkG8fkdhxrtw5rHRURfV8DWGPIMVVXPZo=; b=jY1k2M0HBIeDTiWg0fv95l2HIE9v6FnHmXzEqYWxpVONa8HrzcblzBmmv5G+VH5lGc 6IyNnPFzIjrt8KiDSKO1vSXlOCZosH+xespOL9kSxzyKBgItosPRAG6TnTWnK31//CZu wTjKGlvln6ZSMOQsEg03/dH1YIZwqR2mBhRGEbCc3FihZbv+DRTlqAj3zZzoUGQ8L98b 1MGnSVPgASF8CxcDPme6XRlFdB7VIVhmsYVeairqma5D+1hMBDEgKG6S/yQzAAn1Mc/U eULo6Q7xK19ULL1yJkXNFh6S6m5nSsWPJKr/4X/cCIxfoQ7QIOh3rGooefcbQTqEtDjM rojw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067253; x=1685659253; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=BX+wo12NQqjkG8fkdhxrtw5rHRURfV8DWGPIMVVXPZo=; b=YmiCiNP2kO0kniziqq7T3m8rlNlt0oea614T58VTDDW+qXM6Cr1ga881zln0jFb2Jq /JeNiUjvX6WXOHx+TsTuuNoXtuStn9kOgLnDx2siokD33nuA9BXjIj65vww0v0IoQpwE l6kpDU00YAgZs1Whm1g2bkc9z3xhxaXpn8jgns4ku1jirxSvLmnINXwiDiDystDQLXjn OqgDi7d1OlVIRo9B6Li0PhcLliVBCWj6ejAsx/sWkD353gV1Z8+c7q3/g1Qxvuw0L5qE qieOv31Syzsnj3JXywWOYjeI6qbjY7m0xHfsZ71pkdcmUKSrb9Mc+491x8iGVOlRQQeE iWdA== X-Gm-Message-State: AC+VfDwUtQgGg8zgtQWVTMqXFAuOaro1xHKhVWqzMaQHJf2T91obEvRR egNWWqXyhxNgvHA5/sLlkexyboILp3oT X-Google-Smtp-Source: ACHHUZ70i3gpaxdmSUa18mV3yojjR/gFy4NlVLSd9oaXrd39WKJMtXfkJvPt9KwbDIjBe6rQHnqBXuXKEwSH X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a05:6902:1081:b0:b9d:d5dc:5971 with SMTP id v1-20020a056902108100b00b9dd5dc5971mr6038137ybu.2.1683067253491; Tue, 02 May 2023 15:40:53 -0700 (PDT) Date: Tue, 2 May 2023 15:38:21 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-15-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 14/44] perf test: Roundtrip name, don't assume 1 event per name From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Opening hardware names and a legacy cache event on a hybrid PMU opens it on each PMU. Parsing and checking indexes fails, as the parsed index is double the expected. Avoid checking the index by just comparing the names immediately after the parse. This change removes hard coded hybrid logic and removes assumptions about the expansion of an event. On hybrid the PMUs may or may not support an event and so using a distance isn't a consistent solution. Reviewed-by: Kan Liang Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/tests/evsel-roundtrip-name.c | 119 ++++++++++-------------- 1 file changed, 49 insertions(+), 70 deletions(-) diff --git a/tools/perf/tests/evsel-roundtrip-name.c b/tools/perf/tests/evs= el-roundtrip-name.c index e94fed901992..15ff86f9da0b 100644 --- a/tools/perf/tests/evsel-roundtrip-name.c +++ b/tools/perf/tests/evsel-roundtrip-name.c @@ -4,114 +4,93 @@ #include "parse-events.h" #include "tests.h" #include "debug.h" -#include "pmu.h" -#include "pmu-hybrid.h" -#include #include =20 static int perf_evsel__roundtrip_cache_name_test(void) { - char name[128]; - int type, op, err =3D 0, ret =3D 0, i, idx; - struct evsel *evsel; - struct evlist *evlist =3D evlist__new(); + int ret =3D TEST_OK; =20 - if (evlist =3D=3D NULL) - return -ENOMEM; - - for (type =3D 0; type < PERF_COUNT_HW_CACHE_MAX; type++) { - for (op =3D 0; op < PERF_COUNT_HW_CACHE_OP_MAX; op++) { + for (int type =3D 0; type < PERF_COUNT_HW_CACHE_MAX; type++) { + for (int op =3D 0; op < PERF_COUNT_HW_CACHE_OP_MAX; op++) { /* skip invalid cache type */ if (!evsel__is_cache_op_valid(type, op)) continue; =20 - for (i =3D 0; i < PERF_COUNT_HW_CACHE_RESULT_MAX; i++) { - __evsel__hw_cache_type_op_res_name(type, op, i, name, sizeof(name)); - err =3D parse_event(evlist, name); - if (err) - ret =3D err; - } - } - } - - idx =3D 0; - evsel =3D evlist__first(evlist); + for (int res =3D 0; res < PERF_COUNT_HW_CACHE_RESULT_MAX; res++) { + char name[128]; + struct evlist *evlist =3D evlist__new(); + struct evsel *evsel; + int err; =20 - for (type =3D 0; type < PERF_COUNT_HW_CACHE_MAX; type++) { - for (op =3D 0; op < PERF_COUNT_HW_CACHE_OP_MAX; op++) { - /* skip invalid cache type */ - if (!evsel__is_cache_op_valid(type, op)) - continue; + if (evlist =3D=3D NULL) { + pr_debug("Failed to alloc evlist"); + return TEST_FAIL; + } + __evsel__hw_cache_type_op_res_name(type, op, res, + name, sizeof(name)); =20 - for (i =3D 0; i < PERF_COUNT_HW_CACHE_RESULT_MAX; i++) { - __evsel__hw_cache_type_op_res_name(type, op, i, name, sizeof(name)); - if (evsel->core.idx !=3D idx) + err =3D parse_event(evlist, name); + if (err) { + pr_debug("Failure to parse cache event '%s' possibly as PMUs don't su= pport it", + name); + evlist__delete(evlist); continue; - - ++idx; - - if (strcmp(evsel__name(evsel), name)) { - pr_debug("%s !=3D %s\n", evsel__name(evsel), name); - ret =3D -1; } - - evsel =3D evsel__next(evsel); + evlist__for_each_entry(evlist, evsel) { + if (strcmp(evsel__name(evsel), name)) { + pr_debug("%s !=3D %s\n", evsel__name(evsel), name); + ret =3D TEST_FAIL; + } + } + evlist__delete(evlist); } } } - - evlist__delete(evlist); return ret; } =20 -static int __perf_evsel__name_array_test(const char *const names[], int nr= _names, - int distance) +static int perf_evsel__name_array_test(const char *const names[], int nr_n= ames) { - int i, err; - struct evsel *evsel; - struct evlist *evlist =3D evlist__new(); + int ret =3D TEST_OK; =20 - if (evlist =3D=3D NULL) - return -ENOMEM; + for (int i =3D 0; i < nr_names; ++i) { + struct evlist *evlist =3D evlist__new(); + struct evsel *evsel; + int err; =20 - for (i =3D 0; i < nr_names; ++i) { + if (evlist =3D=3D NULL) { + pr_debug("Failed to alloc evlist"); + return TEST_FAIL; + } err =3D parse_event(evlist, names[i]); if (err) { pr_debug("failed to parse event '%s', err %d\n", names[i], err); - goto out_delete_evlist; + evlist__delete(evlist); + ret =3D TEST_FAIL; + continue; } - } - - err =3D 0; - evlist__for_each_entry(evlist, evsel) { - if (strcmp(evsel__name(evsel), names[evsel->core.idx / distance])) { - --err; - pr_debug("%s !=3D %s\n", evsel__name(evsel), names[evsel->core.idx / di= stance]); + evlist__for_each_entry(evlist, evsel) { + if (strcmp(evsel__name(evsel), names[i])) { + pr_debug("%s !=3D %s\n", evsel__name(evsel), names[i]); + ret =3D TEST_FAIL; + } } + evlist__delete(evlist); } - -out_delete_evlist: - evlist__delete(evlist); - return err; + return ret; } =20 -#define perf_evsel__name_array_test(names, distance) \ - __perf_evsel__name_array_test(names, ARRAY_SIZE(names), distance) - static int test__perf_evsel__roundtrip_name_test(struct test_suite *test _= _maybe_unused, int subtest __maybe_unused) { - int err =3D 0, ret =3D 0; - - if (perf_pmu__has_hybrid() && perf_pmu__hybrid_mounted("cpu_atom")) - return perf_evsel__name_array_test(evsel__hw_names, 2); + int err =3D 0, ret =3D TEST_OK; =20 - err =3D perf_evsel__name_array_test(evsel__hw_names, 1); + err =3D perf_evsel__name_array_test(evsel__hw_names, PERF_COUNT_HW_MAX); if (err) ret =3D err; =20 - err =3D __perf_evsel__name_array_test(evsel__sw_names, PERF_COUNT_SW_DUMM= Y + 1, 1); + err =3D perf_evsel__name_array_test(evsel__sw_names, PERF_COUNT_SW_DUMMY = + 1); if (err) ret =3D err; =20 --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4066DC19F20 for ; Tue, 2 May 2023 22:42:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230154AbjEBWmA (ORCPT ); Tue, 2 May 2023 18:42:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58062 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230130AbjEBWld (ORCPT ); Tue, 2 May 2023 18:41:33 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 40E5735AF for ; Tue, 2 May 2023 15:41:03 -0700 (PDT) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-55a37bf6fd0so57612457b3.2 for ; Tue, 02 May 2023 15:41:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067261; x=1685659261; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=qB7CrIho8sUs4uqST1FvQg7dTPewP8sCTz3Jefkl1h4=; b=lxncKhMnNm9yFOauI/N4W5skagugkDlwjtW8YKG0Z7fL9go5oid+Ip5dfz0RBDrtm8 Cn5OSc0aAfkha9Xfr9K0s5vhlCOkIRVaS25FJ9Fa22A2dmjDgmlGJQInogoCBWMKWCqV it/njqtjFK133gTeKWhtiIuK7AeabaX5sLljn1DEuUUeomRHq0xjAqbDD5NqFhwEypq9 ObR3KQ+GF7IuKSSu8cF2J4O3Ds4KWcGFWSiRipPo0nz1/+Z5kO6O5Br8g2pjm2RBImMn vj1E4YBYtdpgltVEO/jh/Vbeo/n7TkkB8V7qO2mko1XDTW++v7TiggWVXcoFNVBxQ7U3 eTjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067261; x=1685659261; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=qB7CrIho8sUs4uqST1FvQg7dTPewP8sCTz3Jefkl1h4=; b=lHgonR7/CdYGp58DKI8/oZPZSWp7qEHo6xxHzPhvDWz8TrMn4BCnaW7LXiYnpaQ6hQ AsSNRduuRV+ffb7fwq/f4qZwzjMqp/YP+VZkdYsLGvq/Q2Ax+tzL83Cy5/NUjiziF81C ZWkTYavqxZh+X56xbITSOCqI92pWsB0U6Swskf4ic+TlGs17VKyd2aObzBN2QWvOH9oX RnITUbJykbab/plXxrPBu5L5FqQUfkwwRS3fVBmmeY6vzEj1kTQ2Uxm+qtOfk8lAen4i Ep8NaNmGwlYagpvqZC5442OGwpF9cGjhX3k0trJQt0omue5WhWcGntuU+Vtiol0sKnPj YT2A== X-Gm-Message-State: AC+VfDxSatEX1J2Ov1KZ6EF6eDxBlDSYakkfTyn1AbCEHGk3wy12s/s3 DY5R39bwCWbD7ZF5AFJcLU8ONoeXJ1RZ X-Google-Smtp-Source: ACHHUZ4BXwblVCTqfQe8rNR9zxb8oNAJOcUiEgLwFKM9aond1w34GGfJmV324wZvZhCPjFMEgtlsVPuViT2Z X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a81:a8c4:0:b0:54d:3afc:d503 with SMTP id f187-20020a81a8c4000000b0054d3afcd503mr11162592ywh.8.1683067261442; Tue, 02 May 2023 15:41:01 -0700 (PDT) Date: Tue, 2 May 2023 15:38:22 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-16-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 15/44] perf parse-events: Set attr.type to PMU type early From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Set attr.type to PMU type early so that later terms can override the value. Setting the value in perf_pmu__config means that earlier steps, like config_term_pmu, can override the value. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/util/parse-events.c | 2 +- tools/perf/util/pmu.c | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index 34ba840ae19a..707c53f1be09 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -1492,9 +1492,9 @@ int parse_events_add_pmu(struct parse_events_state *p= arse_state, } else { memset(&attr, 0, sizeof(attr)); } + attr.type =3D pmu->type; =20 if (!head_config) { - attr.type =3D pmu->type; evsel =3D __add_event(list, &parse_state->idx, &attr, /*init_attr=3D*/true, /*name=3D*/NULL, /*metric_id=3D*/NULL, pmu, diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index ad209c88a124..cb33d869f1ed 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -1398,7 +1398,6 @@ int perf_pmu__config(struct perf_pmu *pmu, struct per= f_event_attr *attr, { bool zero =3D !!pmu->default_config; =20 - attr->type =3D pmu->type; return perf_pmu__config_terms(pmu->name, &pmu->format, attr, head_terms, zero, err); } --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89463C77B75 for ; Tue, 2 May 2023 22:42:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230128AbjEBWmD (ORCPT ); Tue, 2 May 2023 18:42:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58442 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230162AbjEBWlw (ORCPT ); Tue, 2 May 2023 18:41:52 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B46BC3A98 for ; Tue, 2 May 2023 15:41:19 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-b9a7e76b32bso5496584276.1 for ; Tue, 02 May 2023 15:41:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067275; x=1685659275; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=Qf6Qd+fJp/raw+o0EdprpNNrlfsXq40MPV/2YI8RBqA=; b=3VydHCm3HgLmx6zItjD+1wFhHOgcny1QSRaN3JIELmw2g1+8kUo1PNF2GtCA4vzcB7 XZ4D97vkLvkwLYfW99cCITs05raM8q4aKas0B6aBoFngrecoVIdqsQm3OxyxbEM4avbo 95oI8DfQkLA89kdERL9rh3AzfWNVbsPTAO78TAt5Qw2W4FmqRDJNmUWGRuaZ1GQ8FhLL D2pvTp5E1oLMLMEL83qdXu33mzrJ0uG/UlHRH6kPBDHpMH/4TytLwno+eKUGUJm/l0Iw PsW6Y9UhDutNVlGl9HcghLFy53aFt4qUb8Ey0yMuPBohy93WaJJw/Wmo2+wS1dGLA6dF 6Y5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067275; x=1685659275; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Qf6Qd+fJp/raw+o0EdprpNNrlfsXq40MPV/2YI8RBqA=; b=hX25eiwIsb0D3bsXvlzbJ13iKlrCbpOzwzzejdYG7HkS0MZN2uobHiUDW2INbxi4EJ vqM6EJAyfB0jhr4B7Aqc+MxQ3CTOy058lr6K/MIvWnqvfl7YsRuuXjzYO0DzYg3c1K2b qP59JtzIsV/1cm2COL2LTL+VknSQbA86QoaSnROyyCMvYbCNs5P9zlPjWADwtCeViaUD sR9nBmUkgIbOCeJP2IsZeEIhTsOSZejD2Q0Pt4NCU2eyU7KT0seuLSwbPzJSCN9hov0L 31d0sQlii3svsRHQxN9eua1YJ+VdqF3SsFPK2FZVQBxqd7Fl8jZ+gP+FHAdGj5zUWzVP hiEA== X-Gm-Message-State: AC+VfDzz2Ylqh5Pzt/hUrlSThBP/vK6Y/4zPCFDmcdnuV/i2DLVbP0lV ry06ytKgRmg6XpPQFxByQzxjB23m4pAz X-Google-Smtp-Source: ACHHUZ6/hhd6yEUy1giaHBhk/Dt9KBSzPepqdFaaTHsd+AwHkMOfSYDqQVzXja176m6G5LOonb3Z4bUJc/fF X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a25:584:0:b0:b9e:5d82:f542 with SMTP id 126-20020a250584000000b00b9e5d82f542mr2875249ybf.5.1683067275451; Tue, 02 May 2023 15:41:15 -0700 (PDT) Date: Tue, 2 May 2023 15:38:23 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-17-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 16/44] perf parse-events: Set pmu_name whenever a pmu is given From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Change add_event to always set pmu_name when possible as not all code checks both pmu->name and evsel->pmu_name, for example, uniquify_counter in stat-display.c. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/util/parse-events.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index 707c53f1be09..9cb5f040a74c 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -269,6 +269,7 @@ __add_event(struct list_head *list, int *idx, evsel->core.requires_cpu =3D pmu ? pmu->is_uncore : false; evsel->auto_merge_stats =3D auto_merge_stats; evsel->pmu =3D pmu; + evsel->pmu_name =3D pmu && pmu->name ? strdup(pmu->name) : NULL; =20 if (name) evsel->name =3D strdup(name); @@ -1500,12 +1501,7 @@ int parse_events_add_pmu(struct parse_events_state *= parse_state, /*metric_id=3D*/NULL, pmu, /*config_terms=3D*/NULL, auto_merge_stats, /*cpu_list=3D*/NULL); - if (evsel) { - evsel->pmu_name =3D name ? strdup(name) : NULL; - return 0; - } else { - return -ENOMEM; - } + return evsel ? 0 : -ENOMEM; } =20 if (!parse_state->fake_pmu && perf_pmu__check_alias(pmu, head_config, &in= fo)) @@ -1561,7 +1557,6 @@ int parse_events_add_pmu(struct parse_events_state *p= arse_state, if (evsel->name) evsel->use_config_name =3D true; =20 - evsel->pmu_name =3D name ? strdup(name) : NULL; evsel->percore =3D config_term_percore(&evsel->config_terms); =20 if (parse_state->fake_pmu) --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4DCEC19F20 for ; Tue, 2 May 2023 22:42:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230186AbjEBWmO (ORCPT ); Tue, 2 May 2023 18:42:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58404 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230188AbjEBWl4 (ORCPT ); Tue, 2 May 2023 18:41:56 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B4473A85 for ; Tue, 2 May 2023 15:41:28 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-b9a7d92d0f7so7691262276.1 for ; Tue, 02 May 2023 15:41:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067282; x=1685659282; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=iSuig3L8R5UEDXeqP0djSS5EgyFufZhQb0rbIBIx5wU=; b=tDLYa0DQagvJ/QEPb9MjF/kNyIbrftWOqww62OA+GLPcY0iPlzA9ULd7zv3ROY9sar WqJIcorOzUgc626O10s3jw3jAjVb1lhnelGHisy/AzS9YiQbhGWMILCDsNslA7qu/XE+ B3f9unZkl+ue2Q5QZSr/nNdXW2Tx0mwZeBKtc2NjkDCz1vQVctEpZSRnQykEZnJHmVAq kDdug1BZcy8lT5cOtr2dGNG1+MixqjPC36LVFwhnWLzOgMc739di1qwHBtxtOoc1s8uG edlsXphPdjdnMdCQIY2LUJWLvwQ9xlXP3JQcelH0gfLNcg6Dq8H83iG9gwDRfVQjapaL cSjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067282; x=1685659282; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=iSuig3L8R5UEDXeqP0djSS5EgyFufZhQb0rbIBIx5wU=; b=j2rXOHZggmX5vt/Ofk4yzOOB/c6yOjvtYiT+8HccPVFIh48w5P8088azA8y/equ2GV DYU3mF2mRBRYDGYjysSM9gMObJJynqN7G+3EEasQM+pNnC2RsPGWSw8Q+eTJalgdr0j4 om5Y68jUXPJ6DPRCwcDQVDDo0Kv8iTxUpjez2PQSfI6CGLN+SRR4TIoccdFwTka2CQhq 96CeMRNlrOlfrvLbLBDCRfshtpFMo61xtEYRaMdMueUjuh7mqwwIZSCOEZiYArue3iRD JJnGAQhCvBblq7q5UT+mDjJDCKKwEY2Pg+q1hUAPqOhxOa/Ks5IoVCJR2UvAODKvqwBS xuWg== X-Gm-Message-State: AC+VfDxNMPiSd0m1gvVftsFTrGPOVp6oMjplko577euNq6vWdMtM5w7J OsNN5SCj+tdXQzvo7QVtmKcMfwElgWXj X-Google-Smtp-Source: ACHHUZ4Sq05iGbzmiRWZnqfkmEkdK/S23O3fX4bTPuRLUM7P1GSv/HY6a7FCp6laKk36EZyzo5FJl5vK7p6I X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a25:4245:0:b0:b97:8207:443b with SMTP id p66-20020a254245000000b00b978207443bmr6892574yba.5.1683067282203; Tue, 02 May 2023 15:41:22 -0700 (PDT) Date: Tue, 2 May 2023 15:38:24 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-18-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 17/44] perf print-events: Avoid unnecessary strlist From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The strlist in print_hwcache_events holds the event names as they are generated, and then it is iterated and printed. This is unnecessary and each event can just be printed as it is processed. Rename the variable i to res, to be more intention revealing and consistent with other code. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/util/print-events.c | 60 ++++++++++++++++++---------------- 1 file changed, 31 insertions(+), 29 deletions(-) diff --git a/tools/perf/util/print-events.c b/tools/perf/util/print-events.c index ee145cec42c0..89ac34a922c9 100644 --- a/tools/perf/util/print-events.c +++ b/tools/perf/util/print-events.c @@ -230,58 +230,60 @@ void print_sdt_events(const struct print_callbacks *p= rint_cb, void *print_state) =20 int print_hwcache_events(const struct print_callbacks *print_cb, void *pri= nt_state) { - struct strlist *evt_name_list =3D strlist__new(NULL, NULL); - struct str_node *nd; + const char *event_type_descriptor =3D event_type_descriptors[PERF_TYPE_HW= _CACHE]; =20 - if (!evt_name_list) { - pr_debug("Failed to allocate new strlist for hwcache events\n"); - return -ENOMEM; - } for (int type =3D 0; type < PERF_COUNT_HW_CACHE_MAX; type++) { for (int op =3D 0; op < PERF_COUNT_HW_CACHE_OP_MAX; op++) { /* skip invalid cache type */ if (!evsel__is_cache_op_valid(type, op)) continue; =20 - for (int i =3D 0; i < PERF_COUNT_HW_CACHE_RESULT_MAX; i++) { + for (int res =3D 0; res < PERF_COUNT_HW_CACHE_RESULT_MAX; res++) { struct perf_pmu *pmu =3D NULL; char name[64]; =20 - __evsel__hw_cache_type_op_res_name(type, op, i, name, sizeof(name)); + __evsel__hw_cache_type_op_res_name(type, op, res, + name, sizeof(name)); if (!perf_pmu__has_hybrid()) { if (is_event_supported(PERF_TYPE_HW_CACHE, - type | (op << 8) | (i << 16))) - strlist__add(evt_name_list, name); + type | (op << 8) | (res << 16))) { + print_cb->print_event(print_state, + "cache", + /*pmu_name=3D*/NULL, + name, + /*event_alias=3D*/NULL, + /*scale_unit=3D*/NULL, + /*deprecated=3D*/false, + event_type_descriptor, + /*desc=3D*/NULL, + /*long_desc=3D*/NULL, + /*encoding_desc=3D*/NULL); + } continue; } perf_pmu__for_each_hybrid_pmu(pmu) { if (is_event_supported(PERF_TYPE_HW_CACHE, - type | (op << 8) | (i << 16) | + type | (op << 8) | (res << 16) | ((__u64)pmu->type << PERF_PMU_TYPE_SHIFT))) { char new_name[128]; - snprintf(new_name, sizeof(new_name), - "%s/%s/", pmu->name, name); - strlist__add(evt_name_list, new_name); + snprintf(new_name, sizeof(new_name), + "%s/%s/", pmu->name, name); + print_cb->print_event(print_state, + "cache", + pmu->name, + name, + new_name, + /*scale_unit=3D*/NULL, + /*deprecated=3D*/false, + event_type_descriptor, + /*desc=3D*/NULL, + /*long_desc=3D*/NULL, + /*encoding_desc=3D*/NULL); } } } } } - - strlist__for_each_entry(nd, evt_name_list) { - print_cb->print_event(print_state, - "cache", - /*pmu_name=3D*/NULL, - nd->s, - /*event_alias=3D*/NULL, - /*scale_unit=3D*/NULL, - /*deprecated=3D*/false, - event_type_descriptors[PERF_TYPE_HW_CACHE], - /*desc=3D*/NULL, - /*long_desc=3D*/NULL, - /*encoding_desc=3D*/NULL); - } - strlist__delete(evt_name_list); return 0; } =20 --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5BCBC77B75 for ; Tue, 2 May 2023 22:42:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230119AbjEBWmV (ORCPT ); Tue, 2 May 2023 18:42:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58420 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230149AbjEBWl6 (ORCPT ); Tue, 2 May 2023 18:41:58 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B4A093C0D for ; Tue, 2 May 2023 15:41:32 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-b9a7ddd9aceso8968540276.3 for ; Tue, 02 May 2023 15:41:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067288; x=1685659288; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=cja6thLl6nGgxgvMZ1vgG5tUv8T6qrolEUvsoj4LuYk=; b=YqB9H0gzFZswsHtyGL3u85nomhbu/MirqYi1a+p8B9bisg/IIliYYGXtZ75FXNnVy7 dMs4VCsG7cf+lyH1kWzffHUoZwz6hef8o62ezl1nWQi73Voh2kBUZGcmTZAk2dYGNG8Y CwZjURUHwWj8zzcJ5KLmrgcpCDCFn4RaMxGCcxvOZndxElVnqxRzi2rfGIKBvDleeqM2 mkHTj3TErDka5OOxnYVdBNFKLpYGqwjZ01uplka16Jafl8SpTBEOSDBvzUxiEYwn2sFm GkhokN2khJ8fQUG3foZB6fZrQ6qV4vJu1z6hdZ9XJf5S4eWlJDLkVtjhB2aIzRobtbZ2 PVAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067288; x=1685659288; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=cja6thLl6nGgxgvMZ1vgG5tUv8T6qrolEUvsoj4LuYk=; b=SL/yUSVe3fj0hnCGd4rm6GeERzHTaYxG5BXz0lsprv57O3EPoy4AfM5xWN8Uqg13tU MlAUltufL2Wh245KG5ZBoVSVInn+YareN7w7p0C5LDBUzxCEtsiOhxgv74m96oojoCM6 sCEOWUCi9FKLIOpg2lHtqK0coo94ouyITjU0KNCllByX5TA0EhgtzFMK5Rul3ADHvMXj t9mVXsdaMBMAwO57SB6xgN7wPloybieulRfyMS0d0mlMenXClrV4Y+VzouWaO1TLiNrz qzvKJ3FcCAlwb1JXNdElo9Egec31xWW5cc96e5Wbtq3jAv0Gl/RMWfN73m0aNct1Lg3h nTaQ== X-Gm-Message-State: AC+VfDzrvwYNfmN1gNCjKqP8P1hKzQqbwv3kcaI5RqtK0+VvSDHPBe3q vjsWq2JlY6Y4PseFXwjnQkww6sqoI1pS X-Google-Smtp-Source: ACHHUZ5UwHHJKHMCu97gdaG0UvGSV//r/6HyK0945mEyFLmyueG5Q/EO+SGnmzzjTSUVZMJk+pQZ3nV6NmaS X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a25:d18e:0:b0:b9e:5008:1770 with SMTP id i136-20020a25d18e000000b00b9e50081770mr3182439ybg.8.1683067288781; Tue, 02 May 2023 15:41:28 -0700 (PDT) Date: Tue, 2 May 2023 15:38:25 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-19-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 18/44] perf parse-events: Avoid scanning PMUs before parsing From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The event parser needs to handle two special cases: 1) legacy events like L1-dcache-load-miss. These event names don't appear in json or sysfs, and lookup tables are used for the config value. 2) raw events where 'r0xead' is the same as 'read' unless the PMU has an event called 'read' in which case the event has priority. The previous parser to handle these cases would scan all PMUs for components of event names. These components would then be used to classify in the lexer whether the token should be part of a legacy event, a raw event or an event. The grammar would handle legacy event tokens or recombining the tokens back into a regular event name. The code wasn't PMU specific and had issues around events like AMD's branch-brs that would fail to parse as it expects brs to be a suffix on a legacy event style name: $ perf stat -e branch-brs true event syntax error: 'branch-brs' \___ parser error This change removes processing all PMUs by using the lexer in the form of a regular expression matcher. The lexer will return the token for the longest matched sequence of characters, and in the event of a tie the first. The legacy events are a fixed number of regular expressions, and by matching these before a name token its possible to generate an accurate legacy event token with everything else matching as a name. Because of the lexer change the handling of hyphens in the grammar can be removed as hyphens just become a part of the name. To handle raw events and terms the parser is changed to defer trying to evaluate whether something is a raw event until the PMU is known in the grammar. Once the PMU is known, the events of the PMU can be scanned for the 'read' style problem. A new term type is added for these raw terms, used to enable deferring the evaluation. While this change is large, it has stats of: 170 insertions(+), 436 deletions(-) the bulk of the change is deleting the old approach. It isn't possible to break apart the code added due to the dependencies on how the parts of the parsing work. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/tests/parse-events.c | 24 +-- tools/perf/tests/pmu-events.c | 9 - tools/perf/util/parse-events.c | 329 ++++++++++---------------------- tools/perf/util/parse-events.h | 16 +- tools/perf/util/parse-events.l | 85 +-------- tools/perf/util/parse-events.y | 143 +++++--------- 6 files changed, 170 insertions(+), 436 deletions(-) diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index 3f75f0315db8..5ba90b32c524 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -676,11 +676,11 @@ static int test__checkterms_simple(struct list_head *= terms) */ term =3D list_entry(term->list.next, struct parse_events_term, list); TEST_ASSERT_VAL("wrong type term", - term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_USER); + term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_RAW); TEST_ASSERT_VAL("wrong type val", - term->type_val =3D=3D PARSE_EVENTS__TERM_TYPE_NUM); - TEST_ASSERT_VAL("wrong val", term->val.num =3D=3D 1); - TEST_ASSERT_VAL("wrong config", !strcmp(term->config, "read")); + term->type_val =3D=3D PARSE_EVENTS__TERM_TYPE_STR); + TEST_ASSERT_VAL("wrong val", !strcmp(term->val.str, "read")); + TEST_ASSERT_VAL("wrong config", !strcmp(term->config, "raw")); =20 /* * r0xead @@ -690,11 +690,11 @@ static int test__checkterms_simple(struct list_head *= terms) */ term =3D list_entry(term->list.next, struct parse_events_term, list); TEST_ASSERT_VAL("wrong type term", - term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_CONFIG); + term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_RAW); TEST_ASSERT_VAL("wrong type val", - term->type_val =3D=3D PARSE_EVENTS__TERM_TYPE_NUM); - TEST_ASSERT_VAL("wrong val", term->val.num =3D=3D 0xead); - TEST_ASSERT_VAL("wrong config", !strcmp(term->config, "config")); + term->type_val =3D=3D PARSE_EVENTS__TERM_TYPE_STR); + TEST_ASSERT_VAL("wrong val", !strcmp(term->val.str, "r0xead")); + TEST_ASSERT_VAL("wrong config", !strcmp(term->config, "raw")); return TEST_OK; } =20 @@ -2104,7 +2104,6 @@ static int test_event_fake_pmu(const char *str) return -ENOMEM; =20 parse_events_error__init(&err); - perf_pmu__test_parse_init(); ret =3D __parse_events(evlist, str, &err, &perf_pmu__fake, /*warn_if_reor= dered=3D*/true); if (ret) { pr_debug("failed to parse event '%s', err %d, str '%s'\n", @@ -2158,13 +2157,6 @@ static int test_term(const struct terms_test *t) =20 INIT_LIST_HEAD(&terms); =20 - /* - * The perf_pmu__test_parse_init prepares perf_pmu_events_list - * which gets freed in parse_events_terms. - */ - if (perf_pmu__test_parse_init()) - return -1; - ret =3D parse_events_terms(&terms, t->str); if (ret) { pr_debug("failed to parse terms '%s', err %d\n", diff --git a/tools/perf/tests/pmu-events.c b/tools/perf/tests/pmu-events.c index 1dff863b9711..a2cde61b1c77 100644 --- a/tools/perf/tests/pmu-events.c +++ b/tools/perf/tests/pmu-events.c @@ -776,15 +776,6 @@ static int check_parse_id(const char *id, struct parse= _events_error *error, for (cur =3D strchr(dup, '@') ; cur; cur =3D strchr(++cur, '@')) *cur =3D '/'; =20 - if (fake_pmu) { - /* - * Every call to __parse_events will try to initialize the PMU - * state from sysfs and then clean it up at the end. Reset the - * PMU events to the test state so that we don't pick up - * erroneous prefixes and suffixes. - */ - perf_pmu__test_parse_init(); - } ret =3D __parse_events(evlist, dup, error, fake_pmu, /*warn_if_reordered= =3D*/true); free(dup); =20 diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index 9cb5f040a74c..b5d95fce520c 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -34,11 +34,6 @@ =20 #define MAX_NAME_LEN 100 =20 -struct perf_pmu_event_symbol { - char *symbol; - enum perf_pmu_event_symbol_type type; -}; - #ifdef PARSER_DEBUG extern int parse_events_debug; #endif @@ -49,15 +44,6 @@ static int parse_events__with_hybrid_pmu(struct parse_ev= ents_state *parse_state, const char *str, char *pmu_name, struct list_head *list); =20 -static struct perf_pmu_event_symbol *perf_pmu_events_list; -/* - * The variable indicates the number of supported pmu event symbols. - * 0 means not initialized and ready to init - * -1 means failed to init, don't try anymore - * >0 is the number of supported pmu event symbols - */ -static int perf_pmu_events_list_num; - struct event_symbol event_symbols_hw[PERF_COUNT_HW_MAX] =3D { [PERF_COUNT_HW_CPU_CYCLES] =3D { .symbol =3D "cpu-cycles", @@ -236,6 +222,57 @@ static char *get_config_name(struct list_head *head_te= rms) return get_config_str(head_terms, PARSE_EVENTS__TERM_TYPE_NAME); } =20 +/** + * fix_raw - For each raw term see if there is an event (aka alias) in pmu= that + * matches the raw's string value. If the string value matches an + * event then change the term to be an event, if not then change= it to + * be a config term. For example, "read" may be an event of the = PMU or + * a raw hex encoding of 0xead. The fix-up is done late so the P= MU of + * the event can be determined and we don't need to scan all PMUs + * ahead-of-time. + * @config_terms: the list of terms that may contain a raw term. + * @pmu: the PMU to scan for events from. + */ +static void fix_raw(struct list_head *config_terms, struct perf_pmu *pmu) +{ + struct parse_events_term *term; + + list_for_each_entry(term, config_terms, list) { + struct perf_pmu_alias *alias; + bool matched =3D false; + + if (term->type_term !=3D PARSE_EVENTS__TERM_TYPE_RAW) + continue; + + list_for_each_entry(alias, &pmu->aliases, list) { + if (!strcmp(alias->name, term->val.str)) { + free(term->config); + term->config =3D term->val.str; + term->type_val =3D PARSE_EVENTS__TERM_TYPE_NUM; + term->type_term =3D PARSE_EVENTS__TERM_TYPE_USER; + term->val.num =3D 1; + term->no_value =3D true; + matched =3D true; + break; + } + } + if (!matched) { + u64 num; + + free(term->config); + term->config =3D strdup("config"); + errno =3D 0; + num =3D strtoull(term->val.str + 1, NULL, 16); + assert(errno =3D=3D 0); + free(term->val.str); + term->type_val =3D PARSE_EVENTS__TERM_TYPE_NUM; + term->type_term =3D PARSE_EVENTS__TERM_TYPE_CONFIG; + term->val.num =3D num; + term->no_value =3D false; + } + } +} + static struct evsel * __add_event(struct list_head *list, int *idx, struct perf_event_attr *attr, @@ -329,18 +366,27 @@ static int add_event_tool(struct list_head *list, int= *idx, return 0; } =20 -static int parse_aliases(char *str, const char *const names[][EVSEL__MAX_A= LIASES], int size) +/** + * parse_aliases - search names for entries beginning or equalling str ign= oring + * case. If mutliple entries in names match str then the l= ongest + * is chosen. + * @str: The needle to look for. + * @names: The haystack to search. + * @size: The size of the haystack. + * @longest: Out argument giving the length of the matching entry. + */ +static int parse_aliases(const char *str, const char *const names[][EVSEL_= _MAX_ALIASES], int size, + int *longest) { - int i, j; - int n, longest =3D -1; + *longest =3D -1; + for (int i =3D 0; i < size; i++) { + for (int j =3D 0; j < EVSEL__MAX_ALIASES && names[i][j]; j++) { + int n =3D strlen(names[i][j]); =20 - for (i =3D 0; i < size; i++) { - for (j =3D 0; j < EVSEL__MAX_ALIASES && names[i][j]; j++) { - n =3D strlen(names[i][j]); - if (n > longest && !strncasecmp(str, names[i][j], n)) - longest =3D n; + if (n > *longest && !strncasecmp(str, names[i][j], n)) + *longest =3D n; } - if (longest > 0) + if (*longest > 0) return i; } =20 @@ -358,52 +404,58 @@ static int config_attr(struct perf_event_attr *attr, struct parse_events_error *err, config_term_func_t config_term); =20 -int parse_events_add_cache(struct list_head *list, int *idx, - char *type, char *op_result1, char *op_result2, +int parse_events_add_cache(struct list_head *list, int *idx, const char *n= ame, struct parse_events_error *err, struct list_head *head_config, struct parse_events_state *parse_state) { struct perf_event_attr attr; LIST_HEAD(config_terms); - char name[MAX_NAME_LEN]; const char *config_name, *metric_id; int cache_type =3D -1, cache_op =3D -1, cache_result =3D -1; - char *op_result[2] =3D { op_result1, op_result2 }; - int i, n, ret; + int ret, len; + const char *name_end =3D &name[strlen(name) + 1]; bool hybrid; + const char *str =3D name; =20 /* - * No fallback - if we cannot get a clear cache type - * then bail out: + * Search str for the legacy cache event name composed of 1, 2 or 3 + * hyphen separated sections. The first section is the cache type while + * the others are the optional op and optional result. To make life hard + * the names in the table also contain hyphens and the longest name + * should always be selected. */ - cache_type =3D parse_aliases(type, evsel__hw_cache, PERF_COUNT_HW_CACHE_M= AX); + cache_type =3D parse_aliases(str, evsel__hw_cache, PERF_COUNT_HW_CACHE_MA= X, &len); if (cache_type =3D=3D -1) return -EINVAL; + str +=3D len + 1; =20 config_name =3D get_config_name(head_config); - n =3D snprintf(name, MAX_NAME_LEN, "%s", type); - - for (i =3D 0; (i < 2) && (op_result[i]); i++) { - char *str =3D op_result[i]; - - n +=3D snprintf(name + n, MAX_NAME_LEN - n, "-%s", str); - - if (cache_op =3D=3D -1) { + if (str < name_end) { + cache_op =3D parse_aliases(str, evsel__hw_cache_op, + PERF_COUNT_HW_CACHE_OP_MAX, &len); + if (cache_op >=3D 0) { + if (!evsel__is_cache_op_valid(cache_type, cache_op)) + return -EINVAL; + str +=3D len + 1; + } else { + cache_result =3D parse_aliases(str, evsel__hw_cache_result, + PERF_COUNT_HW_CACHE_RESULT_MAX, &len); + if (cache_result >=3D 0) + str +=3D len + 1; + } + } + if (str < name_end) { + if (cache_op < 0) { cache_op =3D parse_aliases(str, evsel__hw_cache_op, - PERF_COUNT_HW_CACHE_OP_MAX); + PERF_COUNT_HW_CACHE_OP_MAX, &len); if (cache_op >=3D 0) { if (!evsel__is_cache_op_valid(cache_type, cache_op)) return -EINVAL; - continue; } - } - - if (cache_result =3D=3D -1) { + } else if (cache_result < 0) { cache_result =3D parse_aliases(str, evsel__hw_cache_result, - PERF_COUNT_HW_CACHE_RESULT_MAX); - if (cache_result >=3D 0) - continue; + PERF_COUNT_HW_CACHE_RESULT_MAX, &len); } } =20 @@ -969,6 +1021,7 @@ static const char *config_term_names[__PARSE_EVENTS__T= ERM_TYPE_NR] =3D { [PARSE_EVENTS__TERM_TYPE_AUX_OUTPUT] =3D "aux-output", [PARSE_EVENTS__TERM_TYPE_AUX_SAMPLE_SIZE] =3D "aux-sample-size", [PARSE_EVENTS__TERM_TYPE_METRIC_ID] =3D "metric-id", + [PARSE_EVENTS__TERM_TYPE_RAW] =3D "raw", }; =20 static bool config_term_shrinked; @@ -1090,6 +1143,9 @@ do { \ case PARSE_EVENTS__TERM_TYPE_METRIC_ID: CHECK_TYPE_VAL(STR); break; + case PARSE_EVENTS__TERM_TYPE_RAW: + CHECK_TYPE_VAL(STR); + break; case PARSE_EVENTS__TERM_TYPE_MAX_STACK: CHECK_TYPE_VAL(NUM); break; @@ -1486,6 +1542,8 @@ int parse_events_add_pmu(struct parse_events_state *p= arse_state, parse_events_error__handle(err, 0, err_str, NULL); return -EINVAL; } + if (head_config) + fix_raw(head_config, pmu); =20 if (pmu->default_config) { memcpy(&attr, pmu->default_config, @@ -1870,180 +1928,6 @@ int parse_events_name(struct list_head *list, const= char *name) return 0; } =20 -static int -comp_pmu(const void *p1, const void *p2) -{ - struct perf_pmu_event_symbol *pmu1 =3D (struct perf_pmu_event_symbol *) p= 1; - struct perf_pmu_event_symbol *pmu2 =3D (struct perf_pmu_event_symbol *) p= 2; - - return strcasecmp(pmu1->symbol, pmu2->symbol); -} - -static void perf_pmu__parse_cleanup(void) -{ - if (perf_pmu_events_list_num > 0) { - struct perf_pmu_event_symbol *p; - int i; - - for (i =3D 0; i < perf_pmu_events_list_num; i++) { - p =3D perf_pmu_events_list + i; - zfree(&p->symbol); - } - zfree(&perf_pmu_events_list); - perf_pmu_events_list_num =3D 0; - } -} - -#define SET_SYMBOL(str, stype) \ -do { \ - p->symbol =3D str; \ - if (!p->symbol) \ - goto err; \ - p->type =3D stype; \ -} while (0) - -/* - * Read the pmu events list from sysfs - * Save it into perf_pmu_events_list - */ -static void perf_pmu__parse_init(void) -{ - - struct perf_pmu *pmu =3D NULL; - struct perf_pmu_alias *alias; - int len =3D 0; - - pmu =3D NULL; - while ((pmu =3D perf_pmu__scan(pmu)) !=3D NULL) { - list_for_each_entry(alias, &pmu->aliases, list) { - char *tmp =3D strchr(alias->name, '-'); - - if (tmp) { - char *tmp2 =3D NULL; - - tmp2 =3D strchr(tmp + 1, '-'); - len++; - if (tmp2) - len++; - } - - len++; - } - } - - if (len =3D=3D 0) { - perf_pmu_events_list_num =3D -1; - return; - } - perf_pmu_events_list =3D malloc(sizeof(struct perf_pmu_event_symbol) * le= n); - if (!perf_pmu_events_list) - return; - perf_pmu_events_list_num =3D len; - - len =3D 0; - pmu =3D NULL; - while ((pmu =3D perf_pmu__scan(pmu)) !=3D NULL) { - list_for_each_entry(alias, &pmu->aliases, list) { - struct perf_pmu_event_symbol *p =3D perf_pmu_events_list + len; - char *tmp =3D strchr(alias->name, '-'); - char *tmp2 =3D NULL; - - if (tmp) - tmp2 =3D strchr(tmp + 1, '-'); - if (tmp2) { - SET_SYMBOL(strndup(alias->name, tmp - alias->name), - PMU_EVENT_SYMBOL_PREFIX); - p++; - tmp++; - SET_SYMBOL(strndup(tmp, tmp2 - tmp), PMU_EVENT_SYMBOL_SUFFIX); - p++; - SET_SYMBOL(strdup(++tmp2), PMU_EVENT_SYMBOL_SUFFIX2); - len +=3D 3; - } else if (tmp) { - SET_SYMBOL(strndup(alias->name, tmp - alias->name), - PMU_EVENT_SYMBOL_PREFIX); - p++; - SET_SYMBOL(strdup(++tmp), PMU_EVENT_SYMBOL_SUFFIX); - len +=3D 2; - } else { - SET_SYMBOL(strdup(alias->name), PMU_EVENT_SYMBOL); - len++; - } - } - } - qsort(perf_pmu_events_list, len, - sizeof(struct perf_pmu_event_symbol), comp_pmu); - - return; -err: - perf_pmu__parse_cleanup(); -} - -/* - * This function injects special term in - * perf_pmu_events_list so the test code - * can check on this functionality. - */ -int perf_pmu__test_parse_init(void) -{ - struct perf_pmu_event_symbol *list, *tmp, symbols[] =3D { - {(char *)"read", PMU_EVENT_SYMBOL}, - {(char *)"event", PMU_EVENT_SYMBOL_PREFIX}, - {(char *)"two", PMU_EVENT_SYMBOL_SUFFIX}, - {(char *)"hyphen", PMU_EVENT_SYMBOL_SUFFIX}, - {(char *)"hyph", PMU_EVENT_SYMBOL_SUFFIX2}, - }; - unsigned long i, j; - - tmp =3D list =3D malloc(sizeof(*list) * ARRAY_SIZE(symbols)); - if (!list) - return -ENOMEM; - - for (i =3D 0; i < ARRAY_SIZE(symbols); i++, tmp++) { - tmp->type =3D symbols[i].type; - tmp->symbol =3D strdup(symbols[i].symbol); - if (!tmp->symbol) - goto err_free; - } - - perf_pmu_events_list =3D list; - perf_pmu_events_list_num =3D ARRAY_SIZE(symbols); - - qsort(perf_pmu_events_list, ARRAY_SIZE(symbols), - sizeof(struct perf_pmu_event_symbol), comp_pmu); - return 0; - -err_free: - for (j =3D 0, tmp =3D list; j < i; j++, tmp++) - zfree(&tmp->symbol); - free(list); - return -ENOMEM; -} - -enum perf_pmu_event_symbol_type -perf_pmu__parse_check(const char *name) -{ - struct perf_pmu_event_symbol p, *r; - - /* scan kernel pmu events from sysfs if needed */ - if (perf_pmu_events_list_num =3D=3D 0) - perf_pmu__parse_init(); - /* - * name "cpu" could be prefix of cpu-cycles or cpu// events. - * cpu-cycles has been handled by hardcode. - * So it must be cpu// events, not kernel pmu event. - */ - if ((perf_pmu_events_list_num <=3D 0) || !strcmp(name, "cpu")) - return PMU_EVENT_SYMBOL_ERR; - - p.symbol =3D strdup(name); - r =3D bsearch(&p, perf_pmu_events_list, - (size_t) perf_pmu_events_list_num, - sizeof(struct perf_pmu_event_symbol), comp_pmu); - zfree(&p.symbol); - return r ? r->type : PMU_EVENT_SYMBOL_ERR; -} - static int parse_events__scanner(const char *str, struct parse_events_state *parse_state) { @@ -2081,7 +1965,6 @@ int parse_events_terms(struct list_head *terms, const= char *str) int ret; =20 ret =3D parse_events__scanner(str, &parse_state); - perf_pmu__parse_cleanup(); =20 if (!ret) { list_splice(parse_state.terms, terms); @@ -2106,7 +1989,6 @@ static int parse_events__with_hybrid_pmu(struct parse= _events_state *parse_state, int ret; =20 ret =3D parse_events__scanner(str, &ps); - perf_pmu__parse_cleanup(); =20 if (!ret) { if (!list_empty(&ps.list)) { @@ -2269,7 +2151,6 @@ int __parse_events(struct evlist *evlist, const char = *str, int ret; =20 ret =3D parse_events__scanner(str, &parse_state); - perf_pmu__parse_cleanup(); =20 if (!ret && list_empty(&parse_state.list)) { WARN_ONCE(true, "WARNING: event parser found nothing\n"); diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index 86ad4438a2aa..f638542c8638 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -41,14 +41,6 @@ int parse_events_terms(struct list_head *terms, const ch= ar *str); int parse_filter(const struct option *opt, const char *str, int unset); int exclude_perf(const struct option *opt, const char *arg, int unset); =20 -enum perf_pmu_event_symbol_type { - PMU_EVENT_SYMBOL_ERR, /* not a PMU EVENT */ - PMU_EVENT_SYMBOL, /* normal style PMU event */ - PMU_EVENT_SYMBOL_PREFIX, /* prefix of pre-suf style event */ - PMU_EVENT_SYMBOL_SUFFIX, /* suffix of pre-suf style event */ - PMU_EVENT_SYMBOL_SUFFIX2, /* suffix of pre-suf2 style event */ -}; - enum { PARSE_EVENTS__TERM_TYPE_NUM, PARSE_EVENTS__TERM_TYPE_STR, @@ -78,6 +70,7 @@ enum { PARSE_EVENTS__TERM_TYPE_AUX_OUTPUT, PARSE_EVENTS__TERM_TYPE_AUX_SAMPLE_SIZE, PARSE_EVENTS__TERM_TYPE_METRIC_ID, + PARSE_EVENTS__TERM_TYPE_RAW, __PARSE_EVENTS__TERM_TYPE_NR, }; =20 @@ -174,8 +167,7 @@ int parse_events_add_numeric(struct parse_events_state = *parse_state, int parse_events_add_tool(struct parse_events_state *parse_state, struct list_head *list, int tool_event); -int parse_events_add_cache(struct list_head *list, int *idx, - char *type, char *op_result1, char *op_result2, +int parse_events_add_cache(struct list_head *list, int *idx, const char *n= ame, struct parse_events_error *error, struct list_head *head_config, struct parse_events_state *parse_state); @@ -198,8 +190,6 @@ int parse_events_multi_pmu_add(struct parse_events_stat= e *parse_state, int parse_events_copy_term_list(struct list_head *old, struct list_head **new); =20 -enum perf_pmu_event_symbol_type -perf_pmu__parse_check(const char *name); void parse_events__set_leader(char *name, struct list_head *list); void parse_events_update_lists(struct list_head *list_event, struct list_head *list_all); @@ -241,8 +231,6 @@ static inline bool is_sdt_event(char *str __maybe_unuse= d) } #endif /* HAVE_LIBELF_SUPPORT */ =20 -int perf_pmu__test_parse_init(void); - struct evsel *parse_events__add_event_hybrid(struct list_head *list, int *= idx, struct perf_event_attr *attr, const char *name, diff --git a/tools/perf/util/parse-events.l b/tools/perf/util/parse-events.l index 51fe0a9fb3de..4b35c099189a 100644 --- a/tools/perf/util/parse-events.l +++ b/tools/perf/util/parse-events.l @@ -63,17 +63,6 @@ static int str(yyscan_t scanner, int token) return token; } =20 -static int raw(yyscan_t scanner) -{ - YYSTYPE *yylval =3D parse_events_get_lval(scanner); - char *text =3D parse_events_get_text(scanner); - - if (perf_pmu__parse_check(text) =3D=3D PMU_EVENT_SYMBOL) - return str(scanner, PE_NAME); - - return __value(yylval, text + 1, 16, PE_RAW); -} - static bool isbpf_suffix(char *text) { int len =3D strlen(text); @@ -131,35 +120,6 @@ do { \ yyless(0); \ } while (0) =20 -static int pmu_str_check(yyscan_t scanner, struct parse_events_state *pars= e_state) -{ - YYSTYPE *yylval =3D parse_events_get_lval(scanner); - char *text =3D parse_events_get_text(scanner); - - yylval->str =3D strdup(text); - - /* - * If we're not testing then parse check determines the PMU event type - * which if it isn't a PMU returns PE_NAME. When testing the result of - * parse check can't be trusted so we return PE_PMU_EVENT_FAKE unless - * an '!' is present in which case the text can't be a PMU name. - */ - switch (perf_pmu__parse_check(text)) { - case PMU_EVENT_SYMBOL_PREFIX: - return PE_PMU_EVENT_PRE; - case PMU_EVENT_SYMBOL_SUFFIX: - return PE_PMU_EVENT_SUF; - case PMU_EVENT_SYMBOL_SUFFIX2: - return PE_PMU_EVENT_SUF2; - case PMU_EVENT_SYMBOL: - return parse_state->fake_pmu - ? PE_PMU_EVENT_FAKE : PE_KERNEL_PMU_EVENT; - default: - return parse_state->fake_pmu && !strchr(text,'!') - ? PE_PMU_EVENT_FAKE : PE_NAME; - } -} - static int sym(yyscan_t scanner, int type, int config) { YYSTYPE *yylval =3D parse_events_get_lval(scanner); @@ -211,13 +171,15 @@ bpf_source [^,{}]+\.c[a-zA-Z0-9._]* num_dec [0-9]+ num_hex 0x[a-fA-F0-9]+ num_raw_hex [a-fA-F0-9]+ -name [a-zA-Z_*?\[\]][a-zA-Z0-9_*?.\[\]!]* +name [a-zA-Z_*?\[\]][a-zA-Z0-9_*?.\[\]!\-]* name_tag [\'][a-zA-Z_*?\[\]][a-zA-Z0-9_*?\-,\.\[\]:=3D]*[\'] name_minus [a-zA-Z_*?][a-zA-Z0-9\-_*?.:]* drv_cfg_term [a-zA-Z0-9_\.]+(=3D[a-zA-Z0-9_*?\.:]+)? /* If you add a modifier you need to update check_modifier() */ modifier_event [ukhpPGHSDIWeb]+ modifier_bp [rwx]{1,3} +lc_type (L1-dcache|l1-d|l1d|L1-data|L1-icache|l1-i|l1i|L1-instruction|LLC= |L2|dTLB|d-tlb|Data-TLB|iTLB|i-tlb|Instruction-TLB|branch|branches|bpu|btb|= bpc|node) +lc_op_result (load|loads|read|store|stores|write|prefetch|prefetches|specu= lative-read|speculative-load|refs|Reference|ops|access|misses|miss) =20 %% =20 @@ -303,8 +265,8 @@ percore { return term(yyscanner, PARSE_EVENTS__TERM_T= YPE_PERCORE); } aux-output { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_AUX_OUTPUT); } aux-sample-size { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_AUX_SAMP= LE_SIZE); } metric-id { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_METRIC_ID); } -r{num_raw_hex} { return raw(yyscanner); } -r0x{num_raw_hex} { return raw(yyscanner); } +r{num_raw_hex} { return str(yyscanner, PE_RAW); } +r0x{num_raw_hex} { return str(yyscanner, PE_RAW); } , { return ','; } "/" { BEGIN(INITIAL); return '/'; } {name_minus} { return str(yyscanner, PE_NAME); } @@ -359,47 +321,20 @@ system_time { return tool(yyscanner, PERF_TOOL_S= YSTEM_TIME); } bpf-output { return sym(yyscanner, PERF_TYPE_SOFTWARE, PERF_COUNT_SW_B= PF_OUTPUT); } cgroup-switches { return sym(yyscanner, PERF_TYPE_SOFTWARE, PERF_COUNT= _SW_CGROUP_SWITCHES); } =20 - /* - * We have to handle the kernel PMU event cycles-ct/cycles-t/mem-loads/me= m-stores separately. - * Because the prefix cycles is mixed up with cpu-cycles. - * loads and stores are mixed up with cache event - */ -cycles-ct | -cycles-t | -mem-loads | -mem-loads-aux | -mem-stores | -topdown-[a-z-]+ | -tx-capacity-[a-z-]+ | -el-capacity-[a-z-]+ { return str(yyscanner, PE_KERNEL_PMU_EVENT); } - -L1-dcache|l1-d|l1d|L1-data | -L1-icache|l1-i|l1i|L1-instruction | -LLC|L2 | -dTLB|d-tlb|Data-TLB | -iTLB|i-tlb|Instruction-TLB | -branch|branches|bpu|btb|bpc | -node { return str(yyscanner, PE_NAME_CACHE_TYPE); } - -load|loads|read | -store|stores|write | -prefetch|prefetches | -speculative-read|speculative-load | -refs|Reference|ops|access | -misses|miss { return str(yyscanner, PE_NAME_CACHE_OP_RESULT); } - +{lc_type} { return str(yyscanner, PE_LEGACY_CACHE); } +{lc_type}-{lc_op_result} { return str(yyscanner, PE_LEGACY_CACHE); } +{lc_type}-{lc_op_result}-{lc_op_result} { return str(yyscanner, PE_LEGACY_= CACHE); } mem: { BEGIN(mem); return PE_PREFIX_MEM; } -r{num_raw_hex} { return raw(yyscanner); } +r{num_raw_hex} { return str(yyscanner, PE_RAW); } {num_dec} { return value(yyscanner, 10); } {num_hex} { return value(yyscanner, 16); } =20 {modifier_event} { return str(yyscanner, PE_MODIFIER_EVENT); } {bpf_object} { if (!isbpf(yyscanner)) { USER_REJECT }; return str(yyscann= er, PE_BPF_OBJECT); } {bpf_source} { if (!isbpf(yyscanner)) { USER_REJECT }; return str(yyscann= er, PE_BPF_SOURCE); } -{name} { return pmu_str_check(yyscanner, _parse_state); } +{name} { return str(yyscanner, PE_NAME); } {name_tag} { return str(yyscanner, PE_NAME); } "/" { BEGIN(config); return '/'; } -- { return '-'; } , { BEGIN(event); return ','; } : { return ':'; } "{" { BEGIN(event); return '{'; } diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y index 4488443e506e..e7072b5601c5 100644 --- a/tools/perf/util/parse-events.y +++ b/tools/perf/util/parse-events.y @@ -8,6 +8,7 @@ =20 #define YYDEBUG 1 =20 +#include #include #include #include @@ -52,36 +53,35 @@ static void free_list_evsel(struct list_head* list_evse= l) %} =20 %token PE_START_EVENTS PE_START_TERMS -%token PE_VALUE PE_VALUE_SYM_HW PE_VALUE_SYM_SW PE_RAW PE_TERM +%token PE_VALUE PE_VALUE_SYM_HW PE_VALUE_SYM_SW PE_TERM %token PE_VALUE_SYM_TOOL %token PE_EVENT_NAME -%token PE_NAME +%token PE_RAW PE_NAME %token PE_BPF_OBJECT PE_BPF_SOURCE %token PE_MODIFIER_EVENT PE_MODIFIER_BP -%token PE_NAME_CACHE_TYPE PE_NAME_CACHE_OP_RESULT +%token PE_LEGACY_CACHE %token PE_PREFIX_MEM PE_PREFIX_RAW PE_PREFIX_GROUP %token PE_ERROR -%token PE_PMU_EVENT_PRE PE_PMU_EVENT_SUF PE_PMU_EVENT_SUF2 PE_KERNEL_PMU_E= VENT PE_PMU_EVENT_FAKE +%token PE_KERNEL_PMU_EVENT PE_PMU_EVENT_FAKE %token PE_ARRAY_ALL PE_ARRAY_RANGE %token PE_DRV_CFG_TERM %type PE_VALUE %type PE_VALUE_SYM_HW %type PE_VALUE_SYM_SW %type PE_VALUE_SYM_TOOL -%type PE_RAW %type PE_TERM %type value_sym +%type PE_RAW %type PE_NAME %type PE_BPF_OBJECT %type PE_BPF_SOURCE -%type PE_NAME_CACHE_TYPE -%type PE_NAME_CACHE_OP_RESULT +%type PE_LEGACY_CACHE %type PE_MODIFIER_EVENT %type PE_MODIFIER_BP %type PE_EVENT_NAME -%type PE_PMU_EVENT_PRE PE_PMU_EVENT_SUF PE_PMU_EVENT_SUF2 PE_KERNEL_= PMU_EVENT PE_PMU_EVENT_FAKE +%type PE_KERNEL_PMU_EVENT PE_PMU_EVENT_FAKE %type PE_DRV_CFG_TERM -%type event_pmu_name +%type name_or_raw %destructor { free ($$); } %type event_term %destructor { parse_events_term__delete ($$); } @@ -273,11 +273,8 @@ event_def: event_pmu | event_legacy_raw sep_dc | event_bpf_file =20 -event_pmu_name: -PE_NAME | PE_PMU_EVENT_PRE - event_pmu: -event_pmu_name opt_pmu_config +PE_NAME opt_pmu_config { struct parse_events_state *parse_state =3D _parse_state; struct parse_events_error *error =3D parse_state->error; @@ -303,10 +300,12 @@ event_pmu_name opt_pmu_config list =3D alloc_list(); if (!list) CLEANUP_YYABORT; + /* Attempt to add to list assuming $1 is a PMU name. */ if (parse_events_add_pmu(_parse_state, list, $1, $2, /*auto_merge_stats= =3D*/false)) { struct perf_pmu *pmu =3D NULL; int ok =3D 0; =20 + /* Failure to add, try wildcard expansion of $1 as a PMU name. */ if (asprintf(&pattern, "%s*", $1) < 0) CLEANUP_YYABORT; =20 @@ -329,6 +328,12 @@ event_pmu_name opt_pmu_config } } =20 + if (!ok) { + /* Failure to add, assume $1 is an event name. */ + zfree(&list); + ok =3D !parse_events_multi_pmu_add(_parse_state, $1, $2, &list); + $2 =3D NULL; + } if (!ok) CLEANUP_YYABORT; } @@ -352,41 +357,27 @@ PE_KERNEL_PMU_EVENT sep_dc $$ =3D list; } | -PE_KERNEL_PMU_EVENT opt_pmu_config +PE_NAME sep_dc { struct list_head *list; int err; =20 - /* frees $2 */ - err =3D parse_events_multi_pmu_add(_parse_state, $1, $2, &list); + err =3D parse_events_multi_pmu_add(_parse_state, $1, NULL, &list); free($1); if (err < 0) YYABORT; $$ =3D list; } | -PE_PMU_EVENT_PRE '-' PE_PMU_EVENT_SUF '-' PE_PMU_EVENT_SUF2 sep_dc -{ - struct list_head *list; - char pmu_name[128]; - snprintf(pmu_name, sizeof(pmu_name), "%s-%s-%s", $1, $3, $5); - free($1); - free($3); - free($5); - if (parse_events_multi_pmu_add(_parse_state, pmu_name, NULL, &list) < 0) - YYABORT; - $$ =3D list; -} -| -PE_PMU_EVENT_PRE '-' PE_PMU_EVENT_SUF sep_dc +PE_KERNEL_PMU_EVENT opt_pmu_config { struct list_head *list; - char pmu_name[128]; + int err; =20 - snprintf(pmu_name, sizeof(pmu_name), "%s-%s", $1, $3); + /* frees $2 */ + err =3D parse_events_multi_pmu_add(_parse_state, $1, $2, &list); free($1); - free($3); - if (parse_events_multi_pmu_add(_parse_state, pmu_name, NULL, &list) < 0) + if (err < 0) YYABORT; $$ =3D list; } @@ -476,7 +467,7 @@ PE_VALUE_SYM_TOOL sep_slash_slash_dc } =20 event_legacy_cache: -PE_NAME_CACHE_TYPE '-' PE_NAME_CACHE_OP_RESULT '-' PE_NAME_CACHE_OP_RESULT= opt_event_config +PE_LEGACY_CACHE opt_event_config { struct parse_events_state *parse_state =3D _parse_state; struct parse_events_error *error =3D parse_state->error; @@ -485,51 +476,8 @@ PE_NAME_CACHE_TYPE '-' PE_NAME_CACHE_OP_RESULT '-' PE_= NAME_CACHE_OP_RESULT opt_e =20 list =3D alloc_list(); ABORT_ON(!list); - err =3D parse_events_add_cache(list, &parse_state->idx, $1, $3, $5, error= , $6, - parse_state); - parse_events_terms__delete($6); - free($1); - free($3); - free($5); - if (err) { - free_list_evsel(list); - YYABORT; - } - $$ =3D list; -} -| -PE_NAME_CACHE_TYPE '-' PE_NAME_CACHE_OP_RESULT opt_event_config -{ - struct parse_events_state *parse_state =3D _parse_state; - struct parse_events_error *error =3D parse_state->error; - struct list_head *list; - int err; + err =3D parse_events_add_cache(list, &parse_state->idx, $1, error, $2, pa= rse_state); =20 - list =3D alloc_list(); - ABORT_ON(!list); - err =3D parse_events_add_cache(list, &parse_state->idx, $1, $3, NULL, err= or, $4, - parse_state); - parse_events_terms__delete($4); - free($1); - free($3); - if (err) { - free_list_evsel(list); - YYABORT; - } - $$ =3D list; -} -| -PE_NAME_CACHE_TYPE opt_event_config -{ - struct parse_events_state *parse_state =3D _parse_state; - struct parse_events_error *error =3D parse_state->error; - struct list_head *list; - int err; - - list =3D alloc_list(); - ABORT_ON(!list); - err =3D parse_events_add_cache(list, &parse_state->idx, $1, NULL, NULL, e= rror, $2, - parse_state); parse_events_terms__delete($2); free($1); if (err) { @@ -633,17 +581,6 @@ tracepoint_name opt_event_config } =20 tracepoint_name: -PE_NAME '-' PE_NAME ':' PE_NAME -{ - struct tracepoint_name tracepoint; - - ABORT_ON(asprintf(&tracepoint.sys, "%s-%s", $1, $3) < 0); - tracepoint.event =3D $5; - free($1); - free($3); - $$ =3D tracepoint; -} -| PE_NAME ':' PE_NAME { struct tracepoint_name tracepoint =3D {$1, $3}; @@ -673,10 +610,15 @@ PE_RAW opt_event_config { struct list_head *list; int err; + u64 num; =20 list =3D alloc_list(); ABORT_ON(!list); - err =3D parse_events_add_numeric(_parse_state, list, PERF_TYPE_RAW, $1, $= 2); + errno =3D 0; + num =3D strtoull($1 + 1, NULL, 16); + ABORT_ON(errno); + free($1); + err =3D parse_events_add_numeric(_parse_state, list, PERF_TYPE_RAW, num, = $2); parse_events_terms__delete($2); if (err) { free(list); @@ -781,17 +723,22 @@ event_term $$ =3D head; } =20 +name_or_raw: PE_RAW | PE_NAME + event_term: PE_RAW { struct parse_events_term *term; =20 - ABORT_ON(parse_events_term__num(&term, PARSE_EVENTS__TERM_TYPE_CONFIG, - NULL, $1, false, &@1, NULL)); + if (parse_events_term__str(&term, PARSE_EVENTS__TERM_TYPE_RAW, + strdup("raw"), $1, &@1, &@1)) { + free($1); + YYABORT; + } $$ =3D term; } | -PE_NAME '=3D' PE_NAME +name_or_raw '=3D' PE_NAME { struct parse_events_term *term; =20 @@ -804,7 +751,7 @@ PE_NAME '=3D' PE_NAME $$ =3D term; } | -PE_NAME '=3D' PE_VALUE +name_or_raw '=3D' PE_VALUE { struct parse_events_term *term; =20 @@ -816,7 +763,7 @@ PE_NAME '=3D' PE_VALUE $$ =3D term; } | -PE_NAME '=3D' PE_VALUE_SYM_HW +name_or_raw '=3D' PE_VALUE_SYM_HW { struct parse_events_term *term; int config =3D $3 & 255; @@ -876,7 +823,7 @@ PE_TERM $$ =3D term; } | -PE_NAME array '=3D' PE_NAME +name_or_raw array '=3D' PE_NAME { struct parse_events_term *term; =20 @@ -891,7 +838,7 @@ PE_NAME array '=3D' PE_NAME $$ =3D term; } | -PE_NAME array '=3D' PE_VALUE +name_or_raw array '=3D' PE_VALUE { struct parse_events_term *term; =20 --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F01EC19F20 for ; Tue, 2 May 2023 22:42:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230215AbjEBWmd (ORCPT ); Tue, 2 May 2023 18:42:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58716 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230172AbjEBWmG (ORCPT ); Tue, 2 May 2023 18:42:06 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D26033C3D for ; Tue, 2 May 2023 15:41:43 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-b9a805e82a9so9887843276.3 for ; Tue, 02 May 2023 15:41:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067295; x=1685659295; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=Y7D6E0hATCK7e1RhJ0eODuZwXaDaxrE5gp17wu1kd6s=; b=D/bkUj+CvVAC7aYfNgnj4KG5nYd3eTAqh9e6DM0gZZCoQjFlJnRsvX7S3ZBoM9MfVM KovVZNSKZIy2UKW3qeC63Thp8iWn9rHXFjDF1VBowQR1A9soWiwMrXhk3BKdOYLbxIHi iy2ENXEPlZWq6HdDGDMhx6Fp+UZyezvplvUvthMQ3yN0+8U1X0zMaAvbBHvjg2hEzSGA 8RC+TbU+v1BSw9c8YFFtAevtcRnNXp+uQh7oL0j0PWWa7H+9zbM0fQaAiO6xVNMKOSC9 E/0k/1HdFn9HJrPvmmkZgc7CzWtGHCF3DM03VK8bXN+3zyxaRJG7karDc8BdJ147CuHc aKOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067295; x=1685659295; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Y7D6E0hATCK7e1RhJ0eODuZwXaDaxrE5gp17wu1kd6s=; b=gFadxnz/10jB0Hw3e7HaO18C9Hj9++5xsmstIBLXiYZzDVC3kvIrPjnlZqmvYwk3jU mekoVZ6CWWToUz5N1r8sr5klsNKNU2o5D8+6L00IXK4ygixo1SjTTHCmnii14ywIVpHa 75IDsYcaJ9pyHpQ3dRRr0rjDbaAgRa3WPOGNae975zCGbwMxkc5Xul0xVmNA5wGGr3n1 z1kbViqGnoutbL6uL3jJYggIrqTxZq4C5Z8pUNIn22IaXbhVrhZKrO3SBUpy1xXXk8pp XQ03fzEX0+frIKL2KS8G1Bd4H8/OQj9ITwLSAeXRxLzTXZFolNsOD+WPB+Z+2HTDLIpN K7xA== X-Gm-Message-State: AC+VfDxgWyfTjpev3NgSyexvNhJeRFqHyGU7R4yG+migCOtGKZ/cVnz5 5aWP+9wUdiwYXL15JY36AIYXzRa37gk6 X-Google-Smtp-Source: ACHHUZ7LYH229NyKNMZkZWsQienaXd755Yu/epnis0xg39gsfR3yA6p0IrF5aj4wIWeZaeopiMz6DL1RqYce X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a25:d08a:0:b0:b99:34c:ab15 with SMTP id h132-20020a25d08a000000b00b99034cab15mr7544350ybg.1.1683067295712; Tue, 02 May 2023 15:41:35 -0700 (PDT) Date: Tue, 2 May 2023 15:38:26 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-20-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 19/44] perf evsel: Modify group pmu name for software events From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If we have a group of {cycles,faults} then we need the faults software event to appear to be on the same PMU as cycles so that we don't split the group in parse_events__sort_events_and_fix_groups. This case is relatively easy as cycles is the leader and will have a PMU name. In the reverse case, {faults,cycles} we still need faults to appear to have the PMU name of cycles but the old behavior is just to return "cpu". For hybrid this fails as cycles will be on "cpu_core" or "cpu_atom", causing faults to be split into a different group. Change the behavior for software events so that the whole group is searched for the named PMU. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/util/evsel.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c index 1cd04b5998d2..63522322e118 100644 --- a/tools/perf/util/evsel.c +++ b/tools/perf/util/evsel.c @@ -829,23 +829,26 @@ bool evsel__name_is(struct evsel *evsel, const char *= name) =20 const char *evsel__group_pmu_name(const struct evsel *evsel) { - const struct evsel *leader; + struct evsel *leader, *pos; =20 /* If the pmu_name is set use it. pmu_name isn't set for CPU and software= events. */ if (evsel->pmu_name) return evsel->pmu_name; /* * Software events may be in a group with other uncore PMU events. Use - * the pmu_name of the group leader to avoid breaking the software event - * out of the group. + * the pmu_name of the first non-software event to avoid breaking the + * software event out of the group. * * Aux event leaders, like intel_pt, expect a group with events from * other PMUs, so substitute the AUX event's PMU in this case. */ leader =3D evsel__leader(evsel); - if ((evsel->core.attr.type =3D=3D PERF_TYPE_SOFTWARE || evsel__is_aux_eve= nt(leader)) && - leader->pmu_name) { - return leader->pmu_name; + if (evsel->core.attr.type =3D=3D PERF_TYPE_SOFTWARE || evsel__is_aux_even= t(leader)) { + /* Starting with the leader, find the first event with a named PMU. */ + for_each_group_evsel(pos, leader) { + if (pos->pmu_name) + return pos->pmu_name; + } } =20 return "cpu"; --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF930C7EE21 for ; Tue, 2 May 2023 22:42:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230183AbjEBWmf (ORCPT ); Tue, 2 May 2023 18:42:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58484 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230219AbjEBWmL (ORCPT ); Tue, 2 May 2023 18:42:11 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 591743C26 for ; Tue, 2 May 2023 15:41:47 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-b9a7550dca3so7676902276.0 for ; Tue, 02 May 2023 15:41:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067302; x=1685659302; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=MasqsEhlUSuvLba++EoDj6GYVx6X1KX0unKy9hZk1ks=; b=rVkLn6aEcVeeFSrct+Jm+8oOhoVBizCX7Jym54F4zw4G1axEh8qD5QtfudACQoobpf 0GYRbz1dVy3ehZ6iv1K+JFSHnVb0wgPGcmqLEqDjLog2s+n55HoJ9ImwNFnYak5/bgTB YhpKRHeV/R5DA7PA4uUgpynfthsKThvue2P2HBWp5c2UjNMP3wVDEsPRtPIJP4+SvgPs ijarWgrpTZEokLS/yOfbBqVr7Fj32Fv4ldGnY1XctezL/+35PFFRYgSAtCb7mnTZCul+ yIU9FE4t4pJZvHneSKm2LAhYiDnNfhf14AQxgQJZ93JL+FaFMs/qG3BLP8Il/zzcz0GC s4yg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067302; x=1685659302; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=MasqsEhlUSuvLba++EoDj6GYVx6X1KX0unKy9hZk1ks=; b=RLzD9t0dqUO/8Q1snF7H7XXP32DNAvOdq8EkHzj3j3iHYHRhtje3zdO9XhFfLjEB0K N4HQvWRCUgJTBaYF8CVmtzVxooHLREPKrtAs6TpSwF6n79o8/GVZ8d/33+eNCPwJX6xU k3h+uMWsD/I6csOSJp6TWt9wi+1VGZiP1lGdIMCNiOMbRqShfdqMeqo+2gObvMbRuQKg eGGFJ9Xm0Zv+fU/RYE0i46fNgT5nXb3IDj+XnyGus9smNw5kcovgpjqid/jRQJBX58di z4MkCOpG9PGv/dlt5ygsHR+4P2JERsSW/gwYQVazMvE7aCauYOIu8xcim4xhXkg6q3dH olqA== X-Gm-Message-State: AC+VfDzpjEDlNppOWNjPSLLWk59q+fofmfrDBNft5tlCVWRvYWMW40v6 AFwQ0XmceD+BfQ7YAxY43KHZMayw1Ah4 X-Google-Smtp-Source: ACHHUZ7FQVLSJIXJ7OLU8DhkwRoeHji3vXD/7AI2INlXOCeas5pCRkQdkcpaF1WDYGlIfzPGt5e0568fhjfO X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a25:1a55:0:b0:ba0:8a8e:528e with SMTP id a82-20020a251a55000000b00ba08a8e528emr15507yba.0.1683067302233; Tue, 02 May 2023 15:41:42 -0700 (PDT) Date: Tue, 2 May 2023 15:38:27 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-21-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 20/44] perf test: Move x86 hybrid tests to arch/x86 From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The tests use x86 hybrid specific PMUs. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/arch/x86/include/arch-tests.h | 1 + tools/perf/arch/x86/tests/Build | 1 + tools/perf/arch/x86/tests/arch-tests.c | 10 + tools/perf/arch/x86/tests/hybrid.c | 277 +++++++++++++++++++++++ tools/perf/tests/parse-events.c | 181 --------------- 5 files changed, 289 insertions(+), 181 deletions(-) create mode 100644 tools/perf/arch/x86/tests/hybrid.c diff --git a/tools/perf/arch/x86/include/arch-tests.h b/tools/perf/arch/x86= /include/arch-tests.h index 902e9ea9b99e..33d39c1d3e64 100644 --- a/tools/perf/arch/x86/include/arch-tests.h +++ b/tools/perf/arch/x86/include/arch-tests.h @@ -11,6 +11,7 @@ int test__intel_pt_pkt_decoder(struct test_suite *test, i= nt subtest); int test__intel_pt_hybrid_compat(struct test_suite *test, int subtest); int test__bp_modify(struct test_suite *test, int subtest); int test__x86_sample_parsing(struct test_suite *test, int subtest); +int test__hybrid(struct test_suite *test, int subtest); =20 extern struct test_suite *arch_tests[]; =20 diff --git a/tools/perf/arch/x86/tests/Build b/tools/perf/arch/x86/tests/Bu= ild index 6f4e8636c3bf..08cc8b9c931e 100644 --- a/tools/perf/arch/x86/tests/Build +++ b/tools/perf/arch/x86/tests/Build @@ -3,5 +3,6 @@ perf-$(CONFIG_DWARF_UNWIND) +=3D dwarf-unwind.o =20 perf-y +=3D arch-tests.o perf-y +=3D sample-parsing.o +perf-y +=3D hybrid.o perf-$(CONFIG_AUXTRACE) +=3D insn-x86.o intel-pt-test.o perf-$(CONFIG_X86_64) +=3D bp-modify.o diff --git a/tools/perf/arch/x86/tests/arch-tests.c b/tools/perf/arch/x86/t= ests/arch-tests.c index aae6ea0fe52b..147ad0638bbb 100644 --- a/tools/perf/arch/x86/tests/arch-tests.c +++ b/tools/perf/arch/x86/tests/arch-tests.c @@ -22,6 +22,15 @@ struct test_suite suite__intel_pt =3D { DEFINE_SUITE("x86 bp modify", bp_modify); #endif DEFINE_SUITE("x86 Sample parsing", x86_sample_parsing); +static struct test_case hybrid_tests[] =3D { + TEST_CASE_REASON("x86 hybrid event parsing", hybrid, "not hybrid"), + { .name =3D NULL, } +}; + +struct test_suite suite__hybrid =3D { + .desc =3D "x86 hybrid", + .test_cases =3D hybrid_tests, +}; =20 struct test_suite *arch_tests[] =3D { #ifdef HAVE_DWARF_UNWIND_SUPPORT @@ -35,5 +44,6 @@ struct test_suite *arch_tests[] =3D { &suite__bp_modify, #endif &suite__x86_sample_parsing, + &suite__hybrid, NULL, }; diff --git a/tools/perf/arch/x86/tests/hybrid.c b/tools/perf/arch/x86/tests= /hybrid.c new file mode 100644 index 000000000000..0f99cfd116ee --- /dev/null +++ b/tools/perf/arch/x86/tests/hybrid.c @@ -0,0 +1,277 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "arch-tests.h" +#include "debug.h" +#include "evlist.h" +#include "evsel.h" +#include "pmu-hybrid.h" +#include "tests/tests.h" + +static bool test_config(const struct evsel *evsel, __u64 expected_config) +{ + return (evsel->core.attr.config & PERF_HW_EVENT_MASK) =3D=3D expected_con= fig; +} + +static int test__hybrid_hw_event_with_pmu(struct evlist *evlist) +{ + struct evsel *evsel =3D evlist__first(evlist); + + TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); + return TEST_OK; +} + +static int test__hybrid_hw_group_event(struct evlist *evlist) +{ + struct evsel *evsel, *leader; + + evsel =3D leader =3D evlist__first(evlist); + TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); + TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); + + evsel =3D evsel__next(evsel); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0xc0)); + TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); + return TEST_OK; +} + +static int test__hybrid_sw_hw_group_event(struct evlist *evlist) +{ + struct evsel *evsel, *leader; + + evsel =3D leader =3D evlist__first(evlist); + TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_SOFTWARE =3D=3D evsel->core.attr.= type); + TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); + + evsel =3D evsel__next(evsel); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); + TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); + return TEST_OK; +} + +static int test__hybrid_hw_sw_group_event(struct evlist *evlist) +{ + struct evsel *evsel, *leader; + + evsel =3D leader =3D evlist__first(evlist); + TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); + TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); + + evsel =3D evsel__next(evsel); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_SOFTWARE =3D=3D evsel->core.attr.= type); + TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); + return TEST_OK; +} + +static int test__hybrid_group_modifier1(struct evlist *evlist) +{ + struct evsel *evsel, *leader; + + evsel =3D leader =3D evlist__first(evlist); + TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); + TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); + TEST_ASSERT_VAL("wrong exclude_user", evsel->core.attr.exclude_user); + TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); + + evsel =3D evsel__next(evsel); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0xc0)); + TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); + TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); + TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); + return TEST_OK; +} + +static int test__hybrid_raw1(struct evlist *evlist) +{ + struct evsel *evsel =3D evlist__first(evlist); + + if (!perf_pmu__hybrid_mounted("cpu_atom")) { + TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entr= ies); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type= ); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); + return TEST_OK; + } + + TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); + + /* The type of second event is randome value */ + evsel =3D evsel__next(evsel); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); + return TEST_OK; +} + +static int test__hybrid_raw2(struct evlist *evlist) +{ + struct evsel *evsel =3D evlist__first(evlist); + + TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); + return TEST_OK; +} + +static int test__hybrid_cache_event(struct evlist *evlist) +{ + struct evsel *evsel =3D evlist__first(evlist); + + TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_HW_CACHE =3D=3D evsel->core.attr.= type); + TEST_ASSERT_VAL("wrong config", 0x2 =3D=3D (evsel->core.attr.config & 0xf= fffffff)); + return TEST_OK; +} + +static int test__checkevent_pmu(struct evlist *evlist) +{ + + struct evsel *evsel =3D evlist__first(evlist); + + TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); + TEST_ASSERT_VAL("wrong config", 10 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config1", 1 =3D=3D evsel->core.attr.config1); + TEST_ASSERT_VAL("wrong config2", 3 =3D=3D evsel->core.attr.config2); + TEST_ASSERT_VAL("wrong config3", 0 =3D=3D evsel->core.attr.config3); + /* + * The period value gets configured within evlist__config, + * while this test executes only parse events method. + */ + TEST_ASSERT_VAL("wrong period", 0 =3D=3D evsel->core.attr.sample_peri= od); + + return TEST_OK; +} + +struct evlist_test { + const char *name; + bool (*valid)(void); + int (*check)(struct evlist *evlist); +}; + +static const struct evlist_test test__hybrid_events[] =3D { + { + .name =3D "cpu_core/cpu-cycles/", + .check =3D test__hybrid_hw_event_with_pmu, + /* 0 */ + }, + { + .name =3D "{cpu_core/cpu-cycles/,cpu_core/instructions/}", + .check =3D test__hybrid_hw_group_event, + /* 1 */ + }, + { + .name =3D "{cpu-clock,cpu_core/cpu-cycles/}", + .check =3D test__hybrid_sw_hw_group_event, + /* 2 */ + }, + { + .name =3D "{cpu_core/cpu-cycles/,cpu-clock}", + .check =3D test__hybrid_hw_sw_group_event, + /* 3 */ + }, + { + .name =3D "{cpu_core/cpu-cycles/k,cpu_core/instructions/u}", + .check =3D test__hybrid_group_modifier1, + /* 4 */ + }, + { + .name =3D "r1a", + .check =3D test__hybrid_raw1, + /* 5 */ + }, + { + .name =3D "cpu_core/r1a/", + .check =3D test__hybrid_raw2, + /* 6 */ + }, + { + .name =3D "cpu_core/config=3D10,config1,config2=3D3,period=3D1000/u", + .check =3D test__checkevent_pmu, + /* 7 */ + }, + { + .name =3D "cpu_core/LLC-loads/", + .check =3D test__hybrid_cache_event, + /* 8 */ + }, +}; + +static int test_event(const struct evlist_test *e) +{ + struct parse_events_error err; + struct evlist *evlist; + int ret; + + if (e->valid && !e->valid()) { + pr_debug("... SKIP\n"); + return TEST_OK; + } + + evlist =3D evlist__new(); + if (evlist =3D=3D NULL) { + pr_err("Failed allocation"); + return TEST_FAIL; + } + parse_events_error__init(&err); + ret =3D parse_events(evlist, e->name, &err); + if (ret) { + pr_debug("failed to parse event '%s', err %d, str '%s'\n", + e->name, ret, err.str); + parse_events_error__print(&err, e->name); + ret =3D TEST_FAIL; + if (strstr(err.str, "can't access trace events")) + ret =3D TEST_SKIP; + } else { + ret =3D e->check(evlist); + } + parse_events_error__exit(&err); + evlist__delete(evlist); + + return ret; +} + +static int combine_test_results(int existing, int latest) +{ + if (existing =3D=3D TEST_FAIL) + return TEST_FAIL; + if (existing =3D=3D TEST_SKIP) + return latest =3D=3D TEST_OK ? TEST_SKIP : latest; + return latest; +} + +static int test_events(const struct evlist_test *events, int cnt) +{ + int ret =3D TEST_OK; + + for (int i =3D 0; i < cnt; i++) { + const struct evlist_test *e =3D &events[i]; + int test_ret; + + pr_debug("running test %d '%s'\n", i, e->name); + test_ret =3D test_event(e); + if (test_ret !=3D TEST_OK) { + pr_debug("Event test failure: test %d '%s'", i, e->name); + ret =3D combine_test_results(ret, test_ret); + } + } + + return ret; +} + +int test__hybrid(struct test_suite *test __maybe_unused, int subtest __may= be_unused) +{ + if (!perf_pmu__has_hybrid()) + return TEST_SKIP; + + return test_events(test__hybrid_events, ARRAY_SIZE(test__hybrid_events)); +} diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index 5ba90b32c524..43c0778983e5 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -6,7 +6,6 @@ #include "tests.h" #include "debug.h" #include "pmu.h" -#include "pmu-hybrid.h" #include "pmus.h" #include #include @@ -1523,127 +1522,6 @@ static int test__all_tracepoints(struct evlist *evl= ist) } #endif /* HAVE_LIBTRACEVENT */ =20 -static int test__hybrid_hw_event_with_pmu(struct evlist *evlist) -{ - struct evsel *evsel =3D evlist__first(evlist); - - TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); - return TEST_OK; -} - -static int test__hybrid_hw_group_event(struct evlist *evlist) -{ - struct evsel *evsel, *leader; - - evsel =3D leader =3D evlist__first(evlist); - TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); - TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); - - evsel =3D evsel__next(evsel); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0xc0)); - TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); - return TEST_OK; -} - -static int test__hybrid_sw_hw_group_event(struct evlist *evlist) -{ - struct evsel *evsel, *leader; - - evsel =3D leader =3D evlist__first(evlist); - TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_SOFTWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); - - evsel =3D evsel__next(evsel); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); - TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); - return TEST_OK; -} - -static int test__hybrid_hw_sw_group_event(struct evlist *evlist) -{ - struct evsel *evsel, *leader; - - evsel =3D leader =3D evlist__first(evlist); - TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); - TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); - - evsel =3D evsel__next(evsel); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_SOFTWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); - return TEST_OK; -} - -static int test__hybrid_group_modifier1(struct evlist *evlist) -{ - struct evsel *evsel, *leader; - - evsel =3D leader =3D evlist__first(evlist); - TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); - TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); - TEST_ASSERT_VAL("wrong exclude_user", evsel->core.attr.exclude_user); - TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); - - evsel =3D evsel__next(evsel); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0xc0)); - TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); - TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); - TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); - return TEST_OK; -} - -static int test__hybrid_raw1(struct evlist *evlist) -{ - struct evsel *evsel =3D evlist__first(evlist); - - if (!perf_pmu__hybrid_mounted("cpu_atom")) { - TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entr= ies); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type= ); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); - return TEST_OK; - } - - TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); - - /* The type of second event is randome value */ - evsel =3D evsel__next(evsel); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); - return TEST_OK; -} - -static int test__hybrid_raw2(struct evlist *evlist) -{ - struct evsel *evsel =3D evlist__first(evlist); - - TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); - return TEST_OK; -} - -static int test__hybrid_cache_event(struct evlist *evlist) -{ - struct evsel *evsel =3D evlist__first(evlist); - - TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_HW_CACHE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", 0x2 =3D=3D (evsel->core.attr.config & 0xf= fffffff)); - return TEST_OK; -} - struct evlist_test { const char *name; bool (*valid)(void); @@ -2011,54 +1889,6 @@ static const struct terms_test test__terms[] =3D { }, }; =20 -static const struct evlist_test test__hybrid_events[] =3D { - { - .name =3D "cpu_core/cpu-cycles/", - .check =3D test__hybrid_hw_event_with_pmu, - /* 0 */ - }, - { - .name =3D "{cpu_core/cpu-cycles/,cpu_core/instructions/}", - .check =3D test__hybrid_hw_group_event, - /* 1 */ - }, - { - .name =3D "{cpu-clock,cpu_core/cpu-cycles/}", - .check =3D test__hybrid_sw_hw_group_event, - /* 2 */ - }, - { - .name =3D "{cpu_core/cpu-cycles/,cpu-clock}", - .check =3D test__hybrid_hw_sw_group_event, - /* 3 */ - }, - { - .name =3D "{cpu_core/cpu-cycles/k,cpu_core/instructions/u}", - .check =3D test__hybrid_group_modifier1, - /* 4 */ - }, - { - .name =3D "r1a", - .check =3D test__hybrid_raw1, - /* 5 */ - }, - { - .name =3D "cpu_core/r1a/", - .check =3D test__hybrid_raw2, - /* 6 */ - }, - { - .name =3D "cpu_core/config=3D10,config1,config2=3D3,period=3D1000/u", - .check =3D test__checkevent_pmu, - /* 7 */ - }, - { - .name =3D "cpu_core/LLC-loads/", - .check =3D test__hybrid_cache_event, - /* 8 */ - }, -}; - static int test_event(const struct evlist_test *e) { struct parse_events_error err; @@ -2337,14 +2167,6 @@ static bool test_alias(char **event, char **alias) return false; } =20 -static int test__hybrid(struct test_suite *test __maybe_unused, int subtes= t __maybe_unused) -{ - if (!perf_pmu__has_hybrid()) - return TEST_SKIP; - - return test_events(test__hybrid_events, ARRAY_SIZE(test__hybrid_events)); -} - static int test__checkevent_pmu_events_alias(struct evlist *evlist) { struct evsel *evsel1 =3D evlist__first(evlist); @@ -2408,9 +2230,6 @@ static struct test_case tests__parse_events[] =3D { TEST_CASE_REASON("Test event parsing", events2, "permissions"), - TEST_CASE_REASON("Test parsing of \"hybrid\" CPU events", - hybrid, - "not hybrid"), TEST_CASE_REASON("Parsing of all PMU events from sysfs", pmu_events, "permissions"), --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69273C7EE24 for ; Tue, 2 May 2023 22:42:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230222AbjEBWms (ORCPT ); Tue, 2 May 2023 18:42:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57842 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230149AbjEBWmV (ORCPT ); Tue, 2 May 2023 18:42:21 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 12207359F for ; Tue, 2 May 2023 15:41:58 -0700 (PDT) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-552f2f940edso84358317b3.0 for ; Tue, 02 May 2023 15:41:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067308; x=1685659308; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=ub3nsWvIc7LdAE08OZJfmvPZS6krUrWnEa75g5zW2eY=; b=AOK1HC/vf5yI5ql5xcP5VyEU2FXfzZB2Kmq1GuA4h4OL/07Yh4rwN64HQkYCe5v1Bn uiJx9+PL/bleEnQvS+kPi2bu9wb6NnOUz+zaGla9geQwfPGv2mqCuN4pmSQignFH8i0k Dkt74qsBq2zwe3IR2gfljagbPd7k4p44KYhVJ0CgalJJQm+V2b2+T5/PoWqDu86RxDXJ 3vc42n7qnd99938EmEO8L2p3w5yLbSKtUudkwPl3vtANbsh94aCW4i6lGpdJyQsdfmUq yDGe1dmN7j3yLTJOIIV93fDRMNKkF4srjV7tgxWv32gTOkhC+6AZ+BF3FWw2KQUhCN5O e7Nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067308; x=1685659308; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=ub3nsWvIc7LdAE08OZJfmvPZS6krUrWnEa75g5zW2eY=; b=Ko+XQK1pKWibBwW80gTHPNAsz+IcS6jrVEDX9D9hJqcGtCntoG8vqCrElc6G23ZiBN VMamUXng37ctp/cgnfe7MfVuDJGKZYrQMiU3d2ZbpZbWtDt3bDxfoKUyZUbA8vX2B7xw E3RYLVL/Z3D7+IOC5ATgBWmx01m9LOFc31oYyFCT1r2c2QXDWXMsJyEOnFEgo1HcGmMd aLPGkyKx637iFJzKzDJcH4rNHlvxw9xmZWkIJ6V2ieHMiHGIxh6sT6y9BVCOgJlbXM9l wjtQzo/dmosX7wbD27m0/DHzLILxQGT3hjKusOOAh/bh9x0iwXG1++EJ0mi1i4NpuN2h VOcA== X-Gm-Message-State: AC+VfDwzoP+YhAsJWW8tsA93OfCwnbDp3UGCMldnyC0OkzLjElAoXCs1 /EwjGhAKJq/+xyIVrs86e/TPn79AdDWR X-Google-Smtp-Source: ACHHUZ5O5QDTGQhFxpgi0A658hMse1rEsdLbBsf0gMGIcJSpwIugw8qyRTL5V1lyZ7qI72XFYeTyIpcCCKbr X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a81:7e41:0:b0:556:9897:e2c7 with SMTP id p1-20020a817e41000000b005569897e2c7mr11611032ywn.3.1683067308397; Tue, 02 May 2023 15:41:48 -0700 (PDT) Date: Tue, 2 May 2023 15:38:28 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-22-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 21/44] perf test x86 hybrid: Update test expectations From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Don't assume evlist order. Switch to a loop rather than depend on evlist order for raw events test. Update hybrid event expectations. Previous values were based on parsing legacy hardware events from sysfs, update to the correct PMU specific legacy values. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/arch/x86/tests/hybrid.c | 54 ++++++++++++++---------------- 1 file changed, 26 insertions(+), 28 deletions(-) diff --git a/tools/perf/arch/x86/tests/hybrid.c b/tools/perf/arch/x86/tests= /hybrid.c index 0f99cfd116ee..d2a173ba3db9 100644 --- a/tools/perf/arch/x86/tests/hybrid.c +++ b/tools/perf/arch/x86/tests/hybrid.c @@ -11,13 +11,18 @@ static bool test_config(const struct evsel *evsel, __u6= 4 expected_config) return (evsel->core.attr.config & PERF_HW_EVENT_MASK) =3D=3D expected_con= fig; } =20 +static bool test_perf_config(const struct perf_evsel *evsel, __u64 expecte= d_config) +{ + return (evsel->attr.config & PERF_HW_EVENT_MASK) =3D=3D expected_config; +} + static int test__hybrid_hw_event_with_pmu(struct evlist *evlist) { struct evsel *evsel =3D evlist__first(evlist); =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); return TEST_OK; } =20 @@ -27,13 +32,13 @@ static int test__hybrid_hw_group_event(struct evlist *e= vlist) =20 evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); =20 evsel =3D evsel__next(evsel); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0xc0)); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_INSTRUCT= IONS)); TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); return TEST_OK; } @@ -48,8 +53,8 @@ static int test__hybrid_sw_hw_group_event(struct evlist *= evlist) TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); =20 evsel =3D evsel__next(evsel); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); return TEST_OK; } @@ -60,8 +65,8 @@ static int test__hybrid_hw_sw_group_event(struct evlist *= evlist) =20 evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); =20 evsel =3D evsel__next(evsel); @@ -76,15 +81,15 @@ static int test__hybrid_group_modifier1(struct evlist *= evlist) =20 evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); TEST_ASSERT_VAL("wrong exclude_user", evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); =20 evsel =3D evsel__next(evsel); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0xc0)); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_INSTRUCT= IONS)); TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); @@ -93,22 +98,15 @@ static int test__hybrid_group_modifier1(struct evlist *= evlist) =20 static int test__hybrid_raw1(struct evlist *evlist) { - struct evsel *evsel =3D evlist__first(evlist); + struct perf_evsel *evsel; =20 - if (!perf_pmu__hybrid_mounted("cpu_atom")) { - TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entr= ies); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type= ); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); - return TEST_OK; - } - - TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); + perf_evlist__for_each_evsel(&evlist->core, evsel) { + struct perf_pmu *pmu =3D perf_pmu__find_by_type(evsel->attr.type); =20 - /* The type of second event is randome value */ - evsel =3D evsel__next(evsel); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); + TEST_ASSERT_VAL("missing pmu", pmu); + TEST_ASSERT_VAL("unexpected pmu", !strncmp(pmu->name, "cpu_", 4)); + TEST_ASSERT_VAL("wrong config", test_perf_config(evsel, 0x1a)); + } return TEST_OK; } =20 --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A212FC77B75 for ; Tue, 2 May 2023 22:42:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230224AbjEBWmv (ORCPT ); Tue, 2 May 2023 18:42:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58442 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230015AbjEBWmW (ORCPT ); Tue, 2 May 2023 18:42:22 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 762973586 for ; Tue, 2 May 2023 15:41:59 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-b9a7df507c5so8702934276.1 for ; Tue, 02 May 2023 15:41:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067315; x=1685659315; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=l4ljR53ZCaGFcHXQHUCt//riNKiVKOYfs1jr6/UH5IU=; b=GGjX+DbnIxT8t1a0kgOdx316hYjFIfzSSU1v/mga+roisnqY6RM/7DW3aIPt4BysKa EgR3MC88At6I9W19h+J4PLTaLaw0VLQbj2w+JM9yuFU3rZ6ND4m97q2j/zEkQMgmcqIB TqhfrrNrZYQBmwxU6fcVgeITVGHMwThcvEiZWe8n/pceTy1gRucFNZwsHyl+k8VFYpyD M3vflpYu/ebqASzpGIT+dw3iTI0hm9Za5c6gyyRtdfv4Ks7iibdRtSt0bpgegqc84tRn pjZ0MSi3exhs5Y4t0Jr9eYCMMvL/vXChsyjWJ4gpQ64hKawd58R8QUa3khK9m3m+rTiL RKMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067315; x=1685659315; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=l4ljR53ZCaGFcHXQHUCt//riNKiVKOYfs1jr6/UH5IU=; b=i5F0u47mocC1kINRQ7oNveK2Oc4avLNplFDW2Gyj79DudIOCmKKnVqx2KeAutPq+ZZ 0Q7rkWYTDHjMkz8mCXuin1CVNBTEJOVKnrK+IlcLqUgbMLABu6WBRjfxwXFajAzj7aAk DejEbNlvV7mdBxw6GP/vFsViDH6cJZSJZlkdXyOa83Ga5N1r28gaBvPi8DwlMJz+yQUS adhpApBsQ6kon3xBK1EHTn3oU3fqTkQQGcffqPHK10HQMIigQO5lRln14hscZ2XBBH3A OS+jWRB6gy/6I/fyUFyjrSHKCWBT7UPWj1lN4OHngsssSJQXXOMzJEUa04Dc6w8ePWjE mtpA== X-Gm-Message-State: AC+VfDypUFUbAsHYjSRZn7GzLDqMm513AVHg6VvC9sUNHf2JCXF8iCwE 7d3D32odONYtkZXJP8bRcQMDkmufj9Ly X-Google-Smtp-Source: ACHHUZ7FZwP1StSYgkqnayDzhLFCagX3C5YCZQYe9UMPBXhVAb9W2kaum8VNomZQymzs2BQ4ccahbOU2ovQi X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a05:6902:100e:b0:b8f:47c4:58ed with SMTP id w14-20020a056902100e00b00b8f47c458edmr11379278ybt.9.1683067315352; Tue, 02 May 2023 15:41:55 -0700 (PDT) Date: Tue, 2 May 2023 15:38:29 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-23-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 22/44] perf test x86 hybrid: Add hybrid extended type checks From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Assert hybrid extended types are as expected. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/arch/x86/tests/hybrid.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/tools/perf/arch/x86/tests/hybrid.c b/tools/perf/arch/x86/tests= /hybrid.c index d2a173ba3db9..941a9edfed4e 100644 --- a/tools/perf/arch/x86/tests/hybrid.c +++ b/tools/perf/arch/x86/tests/hybrid.c @@ -16,12 +16,18 @@ static bool test_perf_config(const struct perf_evsel *e= vsel, __u64 expected_conf return (evsel->attr.config & PERF_HW_EVENT_MASK) =3D=3D expected_config; } =20 +static bool test_hybrid_type(const struct evsel *evsel, __u64 expected_con= fig) +{ + return (evsel->core.attr.config >> PERF_PMU_TYPE_SHIFT) =3D=3D expected_c= onfig; +} + static int test__hybrid_hw_event_with_pmu(struct evlist *evlist) { struct evsel *evsel =3D evlist__first(evlist); =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); + TEST_ASSERT_VAL("wrong hybrid type", test_hybrid_type(evsel, PERF_TYPE_RA= W)); TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); return TEST_OK; } @@ -33,11 +39,13 @@ static int test__hybrid_hw_group_event(struct evlist *e= vlist) evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); + TEST_ASSERT_VAL("wrong hybrid type", test_hybrid_type(evsel, PERF_TYPE_RA= W)); TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); =20 evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); + TEST_ASSERT_VAL("wrong hybrid type", test_hybrid_type(evsel, PERF_TYPE_RA= W)); TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_INSTRUCT= IONS)); TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); return TEST_OK; @@ -54,6 +62,7 @@ static int test__hybrid_sw_hw_group_event(struct evlist *= evlist) =20 evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); + TEST_ASSERT_VAL("wrong hybrid type", test_hybrid_type(evsel, PERF_TYPE_RA= W)); TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); return TEST_OK; @@ -66,6 +75,7 @@ static int test__hybrid_hw_sw_group_event(struct evlist *= evlist) evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); + TEST_ASSERT_VAL("wrong hybrid type", test_hybrid_type(evsel, PERF_TYPE_RA= W)); TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); =20 @@ -82,6 +92,7 @@ static int test__hybrid_group_modifier1(struct evlist *ev= list) evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); + TEST_ASSERT_VAL("wrong hybrid type", test_hybrid_type(evsel, PERF_TYPE_RA= W)); TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); TEST_ASSERT_VAL("wrong exclude_user", evsel->core.attr.exclude_user); @@ -89,6 +100,7 @@ static int test__hybrid_group_modifier1(struct evlist *e= vlist) =20 evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); + TEST_ASSERT_VAL("wrong hybrid type", test_hybrid_type(evsel, PERF_TYPE_RA= W)); TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_INSTRUCT= IONS)); TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05EACC19F20 for ; Tue, 2 May 2023 22:43:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230093AbjEBWnB (ORCPT ); Tue, 2 May 2023 18:43:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59244 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230193AbjEBWmi (ORCPT ); Tue, 2 May 2023 18:42:38 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B48123A94 for ; Tue, 2 May 2023 15:42:06 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-b9a7e76b32bso5497231276.1 for ; Tue, 02 May 2023 15:42:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067322; x=1685659322; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=06KK258ohGmPy18JQ9TrkKPYNxfE1W3HUyTXp1S5eNw=; b=Eegnm+Ud+T3KzRhrDomrI/LmuJqDU6lDnIFlVaApkKJiUonjsaga4DSnbLzD0nikyb vJ77E/ZvHl8IXk4251xnejdH0r+ba8suAfsNyCOVcjTerjTw2VaCDi5zwSYOQKUoBqgG iXcNWF1SljSCcsiE7yXB+beM0LGwABWQELwd7ILjppjdDwz3hVfTv4DJH2QzXZCQXrH5 QkdYr58Cp0jQtfZezoctXyb5yQS6rl5/JEmqGZvsqXzUnZx1hFy2uTDPQO16NnFlG5Eo M4RBgWIzM1hf0XHzhkOcfVOj5tn92mskKjidxJNNyb1HQPtJNn/eGae4f56lPEKdTjIS pwbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067322; x=1685659322; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=06KK258ohGmPy18JQ9TrkKPYNxfE1W3HUyTXp1S5eNw=; b=W9jnq4kVSpRr7+zqfQFwpAe4CDXNYW53Z6rqHhHnRuoHmhoCm0T00SZ6CkcPcAN87z CTLsQqvnCLv/j3YGIqg7H6+iyyPT5IrXVuo0OIbb2Q0MB180uqp3RKwVh4uu1a8/QhCP mkcGebBhIA6iyk6LqbBH9JKXVy6gGMjrmx4l5s51kLuYefknUUNEe7RdIsMwbOBMQPLX IiMGJlpYX1tMvMF/yNjIGFzBWINGDzbkcnq8Ban9J+4JJNezxMnPPzi08OPCEy4RdQMJ MzlTbEmLhgZPW69kB+dUMLnm4AO182tS2jsw3Pte1Ppe+jVD1W6ierjEsN+QKqL6vpB0 GaNg== X-Gm-Message-State: AC+VfDyXvZk6gRqAzAF9z4v6x8Rl9tRL2t8D+uC6A5ppRk8tfiqJxgx3 JAcH/F5HDA5YNKmH68LbvdYg0LH41YUL X-Google-Smtp-Source: ACHHUZ5d2g0A2W2z8Cq0XUOkQDUDIkOeFEZnBj+oEpo2d8DNoeRTAeNgglNP5ds2O8WnL9cPvXe5W4SzclDY X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a05:6902:1003:b0:b8f:54f5:89ff with SMTP id w3-20020a056902100300b00b8f54f589ffmr12028554ybt.11.1683067322093; Tue, 02 May 2023 15:42:02 -0700 (PDT) Date: Tue, 2 May 2023 15:38:30 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-24-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 23/44] perf parse-events: Support PMUs for legacy cache events From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allow a legacy cache event to be both, for example, "L1-dcache-load-miss" and "cpu/L1-dcache-load-miss/" by introducing a new legacy cache term type. The term type is processed in config_term_pmu, setting both the type in perf_event_attr and the config. The code to determine the config is factored out of parse_events_add_cache and shared. If the PMU doesn't support legacy events, currently just core/hybrid PMUs do, then the term is treated like a PE_NAME term - as before. If only terms are being parsed, such as for perf_pmu__new_alias, then the PE_LEGACY_CACHE token is always parsed as PE_NAME. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/tests/parse-events.c | 18 +++++++++ tools/perf/util/parse-events.c | 70 ++++++++++++++++++++++----------- tools/perf/util/parse-events.h | 3 ++ tools/perf/util/parse-events.l | 9 ++++- tools/perf/util/parse-events.y | 14 ++++++- tools/perf/util/pmu.c | 5 +++ tools/perf/util/pmu.h | 1 + 7 files changed, 96 insertions(+), 24 deletions(-) diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index 43c0778983e5..c3afd0b129bb 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -1875,6 +1875,24 @@ static const struct evlist_test test__events_pmu[] = =3D { .check =3D test__checkevent_raw_pmu, /* 5 */ }, + { + .name =3D "cpu/L1-dcache-load-miss/", + .valid =3D test__pmu_cpu_valid, + .check =3D test__checkevent_genhw, + /* 6 */ + }, + { + .name =3D "cpu/L1-dcache-load-miss/kp", + .valid =3D test__pmu_cpu_valid, + .check =3D test__checkevent_genhw_modifier, + /* 7 */ + }, + { + .name =3D "cpu/L1-dcache-misses,name=3Dcachepmu/", + .valid =3D test__pmu_cpu_valid, + .check =3D test__checkevent_config_cache, + /* 8 */ + }, }; =20 struct terms_test { diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index b5d95fce520c..f692dd953593 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -404,33 +404,27 @@ static int config_attr(struct perf_event_attr *attr, struct parse_events_error *err, config_term_func_t config_term); =20 -int parse_events_add_cache(struct list_head *list, int *idx, const char *n= ame, - struct parse_events_error *err, - struct list_head *head_config, - struct parse_events_state *parse_state) +/** + * parse_events__decode_legacy_cache - Search name for the legacy cache ev= ent + * name composed of 1, 2 or 3 hyphen + * separated sections. The first secti= on is + * the cache type while the others are= the + * optional op and optional result. To= make + * life hard the names in the table al= so + * contain hyphens and the longest name + * should always be selected. + */ +static int parse_events__decode_legacy_cache(const char *name, int pmu_typ= e, __u64 *config) { - struct perf_event_attr attr; - LIST_HEAD(config_terms); - const char *config_name, *metric_id; - int cache_type =3D -1, cache_op =3D -1, cache_result =3D -1; - int ret, len; + int len, cache_type =3D -1, cache_op =3D -1, cache_result =3D -1; const char *name_end =3D &name[strlen(name) + 1]; - bool hybrid; const char *str =3D name; =20 - /* - * Search str for the legacy cache event name composed of 1, 2 or 3 - * hyphen separated sections. The first section is the cache type while - * the others are the optional op and optional result. To make life hard - * the names in the table also contain hyphens and the longest name - * should always be selected. - */ cache_type =3D parse_aliases(str, evsel__hw_cache, PERF_COUNT_HW_CACHE_MA= X, &len); if (cache_type =3D=3D -1) return -EINVAL; str +=3D len + 1; =20 - config_name =3D get_config_name(head_config); if (str < name_end) { cache_op =3D parse_aliases(str, evsel__hw_cache_op, PERF_COUNT_HW_CACHE_OP_MAX, &len); @@ -471,9 +465,28 @@ int parse_events_add_cache(struct list_head *list, int= *idx, const char *name, if (cache_result =3D=3D -1) cache_result =3D PERF_COUNT_HW_CACHE_RESULT_ACCESS; =20 + *config =3D ((__u64)pmu_type << PERF_PMU_TYPE_SHIFT) | + cache_type | (cache_op << 8) | (cache_result << 16); + return 0; +} + +int parse_events_add_cache(struct list_head *list, int *idx, const char *n= ame, + struct parse_events_error *err, + struct list_head *head_config, + struct parse_events_state *parse_state) +{ + struct perf_event_attr attr; + LIST_HEAD(config_terms); + const char *config_name, *metric_id; + int ret; + bool hybrid; + + memset(&attr, 0, sizeof(attr)); - attr.config =3D cache_type | (cache_op << 8) | (cache_result << 16); attr.type =3D PERF_TYPE_HW_CACHE; + ret =3D parse_events__decode_legacy_cache(name, /*pmu_type=3D*/0, &attr.c= onfig); + if (ret) + return ret; =20 if (head_config) { if (config_attr(&attr, head_config, err, @@ -484,6 +497,7 @@ int parse_events_add_cache(struct list_head *list, int = *idx, const char *name, return -ENOMEM; } =20 + config_name =3D get_config_name(head_config); metric_id =3D get_config_metric_id(head_config); ret =3D parse_events__add_cache_hybrid(list, idx, &attr, config_name ? : name, @@ -1022,6 +1036,7 @@ static const char *config_term_names[__PARSE_EVENTS__= TERM_TYPE_NR] =3D { [PARSE_EVENTS__TERM_TYPE_AUX_SAMPLE_SIZE] =3D "aux-sample-size", [PARSE_EVENTS__TERM_TYPE_METRIC_ID] =3D "metric-id", [PARSE_EVENTS__TERM_TYPE_RAW] =3D "raw", + [PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE] =3D "legacy-cache", }; =20 static bool config_term_shrinked; @@ -1199,15 +1214,25 @@ static int config_term_pmu(struct perf_event_attr *= attr, struct parse_events_term *term, struct parse_events_error *err) { + if (term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE) { + const struct perf_pmu *pmu =3D perf_pmu__find_by_type(attr->type); + + if (perf_pmu__supports_legacy_cache(pmu)) { + attr->type =3D PERF_TYPE_HW_CACHE; + return parse_events__decode_legacy_cache(term->config, pmu->type, + &attr->config); + } else + term->type_term =3D PARSE_EVENTS__TERM_TYPE_USER; + } if (term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_USER || - term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_DRV_CFG) + term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_DRV_CFG) { /* * Always succeed for sysfs terms, as we dont know * at this point what type they need to have. */ return 0; - else - return config_term_common(attr, term, err); + } + return config_term_common(attr, term, err); } =20 #ifdef HAVE_LIBTRACEEVENT @@ -2147,6 +2172,7 @@ int __parse_events(struct evlist *evlist, const char = *str, .evlist =3D evlist, .stoken =3D PE_START_EVENTS, .fake_pmu =3D fake_pmu, + .match_legacy_cache_terms =3D true, }; int ret; =20 diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index f638542c8638..5acb62c2e00a 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -71,6 +71,7 @@ enum { PARSE_EVENTS__TERM_TYPE_AUX_SAMPLE_SIZE, PARSE_EVENTS__TERM_TYPE_METRIC_ID, PARSE_EVENTS__TERM_TYPE_RAW, + PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE, __PARSE_EVENTS__TERM_TYPE_NR, }; =20 @@ -122,6 +123,8 @@ struct parse_events_state { int stoken; struct perf_pmu *fake_pmu; char *hybrid_pmu_name; + /* Should PE_LEGACY_NAME tokens be generated for config terms? */ + bool match_legacy_cache_terms; bool wild_card_pmus; }; =20 diff --git a/tools/perf/util/parse-events.l b/tools/perf/util/parse-events.l index 4b35c099189a..abe0ce681d29 100644 --- a/tools/perf/util/parse-events.l +++ b/tools/perf/util/parse-events.l @@ -63,6 +63,11 @@ static int str(yyscan_t scanner, int token) return token; } =20 +static int lc_str(yyscan_t scanner, const struct parse_events_state *state) +{ + return str(scanner, state->match_legacy_cache_terms ? PE_LEGACY_CACHE : P= E_NAME); +} + static bool isbpf_suffix(char *text) { int len =3D strlen(text); @@ -185,7 +190,6 @@ lc_op_result (load|loads|read|store|stores|write|prefet= ch|prefetches|speculative =20 %{ struct parse_events_state *_parse_state =3D parse_events_get_extra(yyscan= ner); - { int start_token =3D _parse_state->stoken; =20 @@ -269,6 +273,9 @@ r{num_raw_hex} { return str(yyscanner, PE_RAW); } r0x{num_raw_hex} { return str(yyscanner, PE_RAW); } , { return ','; } "/" { BEGIN(INITIAL); return '/'; } +{lc_type} { return lc_str(yyscanner, _parse_state); } +{lc_type}-{lc_op_result} { return lc_str(yyscanner, _parse_state); } +{lc_type}-{lc_op_result}-{lc_op_result} { return lc_str(yyscanner, _parse_= state); } {name_minus} { return str(yyscanner, PE_NAME); } \[all\] { return PE_ARRAY_ALL; } "[" { BEGIN(array); return '['; } diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y index e7072b5601c5..f84fa1b132b3 100644 --- a/tools/perf/util/parse-events.y +++ b/tools/perf/util/parse-events.y @@ -723,7 +723,7 @@ event_term $$ =3D head; } =20 -name_or_raw: PE_RAW | PE_NAME +name_or_raw: PE_RAW | PE_NAME | PE_LEGACY_CACHE =20 event_term: PE_RAW @@ -775,6 +775,18 @@ name_or_raw '=3D' PE_VALUE_SYM_HW $$ =3D term; } | +PE_LEGACY_CACHE +{ + struct parse_events_term *term; + + if (parse_events_term__num(&term, PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE, + $1, 1, true, &@1, NULL)) { + free($1); + YYABORT; + } + $$ =3D term; +} +| PE_NAME { struct parse_events_term *term; diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index cb33d869f1ed..63071d876190 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -1650,6 +1650,11 @@ bool is_pmu_core(const char *name) return !strcmp(name, "cpu") || is_arm_pmu_core(name); } =20 +bool perf_pmu__supports_legacy_cache(const struct perf_pmu *pmu) +{ + return is_pmu_core(pmu->name) || perf_pmu__is_hybrid(pmu->name); +} + static bool pmu_alias_is_duplicate(struct sevent *alias_a, struct sevent *alias_b) { diff --git a/tools/perf/util/pmu.h b/tools/perf/util/pmu.h index b9a02dedd473..05702bc4bcf8 100644 --- a/tools/perf/util/pmu.h +++ b/tools/perf/util/pmu.h @@ -220,6 +220,7 @@ void perf_pmu__del_formats(struct list_head *formats); struct perf_pmu *perf_pmu__scan(struct perf_pmu *pmu); =20 bool is_pmu_core(const char *name); +bool perf_pmu__supports_legacy_cache(const struct perf_pmu *pmu); void print_pmu_events(const struct print_callbacks *print_cb, void *print_= state); bool pmu_have_event(const char *pname, const char *name); =20 --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7735FC7EE21 for ; Tue, 2 May 2023 22:43:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230254AbjEBWnN (ORCPT ); Tue, 2 May 2023 18:43:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59588 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230236AbjEBWmy (ORCPT ); Tue, 2 May 2023 18:42:54 -0400 Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 531243C0D for ; Tue, 2 May 2023 15:42:19 -0700 (PDT) Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-55a2648c164so55536867b3.2 for ; Tue, 02 May 2023 15:42:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067329; x=1685659329; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=OKlYtbEHxsaZvta2/vy5tQOz2M7WlkKnPlSTO/BorIw=; b=34n61pw0lhsMxf3JzyGX8OVhO88pWi2hZXwZtGvgf+H3i8F4qY28qLk5GvE+cgf2nw 8hBWiOu5XbmQrhXYB4E4bYQQ5GYdw5ht1a83yLfaq3U13CaSRgM25Kkckv4VH2JjZ5XP LkCrDJaKj5ZOVlaRAUMutxFVf/uP1rhVFo7DSYFT4a1PAn1r/rjD/uTiUsEd/edc/3xw WaPgph9I7WojFtUxzE8UMw7JtIobFXP4GWQf/N3WVWMUoDpp0M/3hiYLMaDb99aNHKQ4 w+HWqbWzhmz/KYb4QCA0tOK+hB7z0BiMSzTtS4h9+ePA1JAGUj141JpmvFqoG7uhGoCr s/UQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067329; x=1685659329; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=OKlYtbEHxsaZvta2/vy5tQOz2M7WlkKnPlSTO/BorIw=; b=gK4p5hoTjSxWGBvM38DmotlJ7JOCa4gNTuC3xqmEKaeLIVeTr0M4tPsRyKygIVJx/H U2YW4v6hl8zAOM3V7WNb1qtxRtkh2iAQNyD1/ADXj3Ds8aSRXhS/MMLnjrBlVdu5uMwj ouaM7ZLirrR1cqKUoyGJ4did5IK/Tq6ARHj0mdo4yScx2yIw8ccLOnTAQ3QR4u+sCjwO 1aL22zxVCB62ct1kDlxnRNLVzDh8rj0Y2ic4yH+zyNE4WnZB3naDfWwpAMEX1lpBkPow 2s6j9aHjgKkV503/Y3PFpVBQZVBEa/QZyXIyBcZ+4b5z0NcgwpzYbNewgXyXE+g05yfE +mhA== X-Gm-Message-State: AC+VfDwWnIemXaoy/rl6JoHzvRzbDAGg2tT01JkRsIQl/cgq3lLGqT2t 7SEssyJhM0P0268z4Wgbw3IdC0sBddk+ X-Google-Smtp-Source: ACHHUZ7Hoo6fiNSGYnn9agkl3IfR8ZwOvYLMP9XCtsXlo+2oIJNSNDj2GKmJMIQIPXgdYlVMwUCcp5HVvLro X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a81:ca07:0:b0:556:2da0:fb8 with SMTP id p7-20020a81ca07000000b005562da00fb8mr11025635ywi.7.1683067328807; Tue, 02 May 2023 15:42:08 -0700 (PDT) Date: Tue, 2 May 2023 15:38:31 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-25-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 24/44] perf parse-events: Wildcard legacy cache events From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" It is inconsistent that "perf stat -e instructions-retired" wildcard opens on all PMUs while legacy cache events like "perf stat -e L1-dcache-load-miss" do not. A behavior introduced by hybrid is that a legacy cache event like L1-dcache-load-miss should wildcard open on all hybrid PMUs. Previously hybrid would call to is_event_supported for each PMU, a failure of which results in the event not being added. This isn't done in this case as the parser should just create perf_event_attr and the later open should fail, or the counter give "". If this wants to be avoided then the PMU can be named with the event. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/util/parse-events-hybrid.c | 33 ------------- tools/perf/util/parse-events-hybrid.h | 7 --- tools/perf/util/parse-events.c | 68 ++++++++++++++------------- tools/perf/util/parse-events.h | 3 +- tools/perf/util/parse-events.y | 2 +- 5 files changed, 37 insertions(+), 76 deletions(-) diff --git a/tools/perf/util/parse-events-hybrid.c b/tools/perf/util/parse-= events-hybrid.c index 7c9f9150bad5..d2c0be051d46 100644 --- a/tools/perf/util/parse-events-hybrid.c +++ b/tools/perf/util/parse-events-hybrid.c @@ -179,36 +179,3 @@ int parse_events__add_numeric_hybrid(struct parse_even= ts_state *parse_state, return add_raw_hybrid(parse_state, list, attr, name, metric_id, config_terms); } - -int parse_events__add_cache_hybrid(struct list_head *list, int *idx, - struct perf_event_attr *attr, - const char *name, - const char *metric_id, - struct list_head *config_terms, - bool *hybrid, - struct parse_events_state *parse_state) -{ - struct perf_pmu *pmu; - int ret; - - *hybrid =3D false; - if (!perf_pmu__has_hybrid()) - return 0; - - *hybrid =3D true; - perf_pmu__for_each_hybrid_pmu(pmu) { - LIST_HEAD(terms); - - if (pmu_cmp(parse_state, pmu)) - continue; - - copy_config_terms(&terms, config_terms); - ret =3D create_event_hybrid(PERF_TYPE_HW_CACHE, idx, list, - attr, name, metric_id, &terms, pmu); - free_config_terms(&terms); - if (ret) - return ret; - } - - return 0; -} diff --git a/tools/perf/util/parse-events-hybrid.h b/tools/perf/util/parse-= events-hybrid.h index cbc05fec02a2..bc2966e73897 100644 --- a/tools/perf/util/parse-events-hybrid.h +++ b/tools/perf/util/parse-events-hybrid.h @@ -15,11 +15,4 @@ int parse_events__add_numeric_hybrid(struct parse_events= _state *parse_state, struct list_head *config_terms, bool *hybrid); =20 -int parse_events__add_cache_hybrid(struct list_head *list, int *idx, - struct perf_event_attr *attr, - const char *name, const char *metric_id, - struct list_head *config_terms, - bool *hybrid, - struct parse_events_state *parse_state); - #endif /* __PERF_PARSE_EVENTS_HYBRID_H */ diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index f692dd953593..9f2bbf8f3a81 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -472,46 +472,48 @@ static int parse_events__decode_legacy_cache(const ch= ar *name, int pmu_type, __u =20 int parse_events_add_cache(struct list_head *list, int *idx, const char *n= ame, struct parse_events_error *err, - struct list_head *head_config, - struct parse_events_state *parse_state) + struct list_head *head_config) { - struct perf_event_attr attr; - LIST_HEAD(config_terms); - const char *config_name, *metric_id; - int ret; - bool hybrid; + struct perf_pmu *pmu =3D NULL; + bool found_supported =3D false; + const char *config_name =3D get_config_name(head_config); + const char *metric_id =3D get_config_metric_id(head_config); =20 + while ((pmu =3D perf_pmu__scan(pmu)) !=3D NULL) { + LIST_HEAD(config_terms); + struct perf_event_attr attr; + int ret; =20 - memset(&attr, 0, sizeof(attr)); - attr.type =3D PERF_TYPE_HW_CACHE; - ret =3D parse_events__decode_legacy_cache(name, /*pmu_type=3D*/0, &attr.c= onfig); - if (ret) - return ret; + /* Skip unsupported PMUs. */ + if (!perf_pmu__supports_legacy_cache(pmu)) + continue; =20 - if (head_config) { - if (config_attr(&attr, head_config, err, - config_term_common)) - return -EINVAL; + memset(&attr, 0, sizeof(attr)); + attr.type =3D PERF_TYPE_HW_CACHE; =20 - if (get_config_terms(head_config, &config_terms)) - return -ENOMEM; - } + ret =3D parse_events__decode_legacy_cache(name, pmu->type, &attr.config); + if (ret) + return ret; =20 - config_name =3D get_config_name(head_config); - metric_id =3D get_config_metric_id(head_config); - ret =3D parse_events__add_cache_hybrid(list, idx, &attr, - config_name ? : name, - metric_id, - &config_terms, - &hybrid, parse_state); - if (hybrid) - goto out_free_terms; + found_supported =3D true; =20 - ret =3D add_event(list, idx, &attr, config_name ? : name, metric_id, - &config_terms); -out_free_terms: - free_config_terms(&config_terms); - return ret; + if (head_config) { + if (config_attr(&attr, head_config, err, + config_term_common)) + return -EINVAL; + + if (get_config_terms(head_config, &config_terms)) + return -ENOMEM; + } + + if (__add_event(list, idx, &attr, /*init_attr*/true, config_name ?: name, + metric_id, pmu, &config_terms, /*auto_merge_stats=3D*/false, + /*cpu_list=3D*/NULL) =3D=3D NULL) + return -ENOMEM; + + free_config_terms(&config_terms); + } + return found_supported ? 0 : -EINVAL; } =20 #ifdef HAVE_LIBTRACEEVENT diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index 5acb62c2e00a..0c26303f7f63 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -172,8 +172,7 @@ int parse_events_add_tool(struct parse_events_state *pa= rse_state, int tool_event); int parse_events_add_cache(struct list_head *list, int *idx, const char *n= ame, struct parse_events_error *error, - struct list_head *head_config, - struct parse_events_state *parse_state); + struct list_head *head_config); int parse_events_add_breakpoint(struct list_head *list, int *idx, u64 addr, char *type, u64 len); int parse_events_add_pmu(struct parse_events_state *parse_state, diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y index f84fa1b132b3..cc7528558845 100644 --- a/tools/perf/util/parse-events.y +++ b/tools/perf/util/parse-events.y @@ -476,7 +476,7 @@ PE_LEGACY_CACHE opt_event_config =20 list =3D alloc_list(); ABORT_ON(!list); - err =3D parse_events_add_cache(list, &parse_state->idx, $1, error, $2, pa= rse_state); + err =3D parse_events_add_cache(list, &parse_state->idx, $1, error, $2); =20 parse_events_terms__delete($2); free($1); --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5EBE0C7EE21 for ; Tue, 2 May 2023 22:43:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230325AbjEBWnZ (ORCPT ); Tue, 2 May 2023 18:43:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59234 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230217AbjEBWm6 (ORCPT ); Tue, 2 May 2023 18:42:58 -0400 Received: from mail-pl1-x64a.google.com (mail-pl1-x64a.google.com [IPv6:2607:f8b0:4864:20::64a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F73E3C1E for ; Tue, 2 May 2023 15:42:26 -0700 (PDT) Received: by mail-pl1-x64a.google.com with SMTP id d9443c01a7336-1ab07423559so9586215ad.3 for ; Tue, 02 May 2023 15:42:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067335; x=1685659335; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=9zs/j9Cazyz7I8CxMfSVvkdUGrebs57+5ZgPQMD0JXU=; b=c3qhuLI3C5wJcCInc8e3ii7vGHS4U5A/gMAoYDzop02Gqm/MYAHVzyCMGy97NaJ+AZ ZqlumZbWFatPTSNjGHU6jazEH1t5zGd12YeLgaVzL5zoHkuMOB+spsw0u1L8kJ4ysANj FHPa85K476G5kUy7N2+9cvzUtTQKg5PCLK54YpvOyJ+BYmnq/7nMJeumM2Du1H5GCMAL DAIlBfK5SYKakEducet4PV/nAxtnksLNK725rsis/H3rKbtZf0j0wAF61UzHUtWuUv5M dhhna3cNSKrQpDPUBHsVk3rozI3B6WF3HD+utw8/+ASRCGmuQxtUWuECM2aROhfTmdLs zIVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067335; x=1685659335; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=9zs/j9Cazyz7I8CxMfSVvkdUGrebs57+5ZgPQMD0JXU=; b=hhTGtIg4zW2xJStNdd+GYOFR4pc8i19SZ/1B67xK0eBIM17ZSQUWYQIh2B/uS9F8ty ru65+HpTo1KTfcPCtMNyHOgLgb88GXaNh5StaWdO9Uu5g3Op9SPCbfdLqTB5asqyVZd4 pvimXfU47omSjRpYgEYwUq7Qkvq9nyMJ+LWYYhV9TihXVas8OQ4J6fhLO9cUdOqzXgHh OdoN3u8/88+wONgFY9muSbRw4WEa9AEkwdKdGHUZ2q7Qlwu44fKcPIiOyt+MTLEtEWOU qOxO57YGIFfSamO4aISiMHacjT6g/Q0HN71NfbunNQScZSOh5054ViBTnfUN/I05Q5sa pKEA== X-Gm-Message-State: AC+VfDx1/J4YGHzTOJj0zs2XWLPwvrdOxDUsrjRoK5v5H2w7mXWe9KBa Awk80Kxxqx1qkAY7pgF82xUKWkgobF4i X-Google-Smtp-Source: ACHHUZ4X2QtC+Q2k97Tu5cCKHb++i6yGYeaArn4k1LSnE+8cf1yTDkvG/otnB1zy1LcYgjbfbmjoanhpFTCB X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a17:902:d4d1:b0:1a6:4ce8:3ed5 with SMTP id o17-20020a170902d4d100b001a64ce83ed5mr36043plg.4.1683067335300; Tue, 02 May 2023 15:42:15 -0700 (PDT) Date: Tue, 2 May 2023 15:38:32 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-26-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 25/44] perf print-events: Print legacy cache events for each PMU From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Mirroring parse_events_add_cache, list the legacy name alongside its alias with the PMU. Remove the now unnecessary hybrid logic. Note, the alias output removes the event type descriptor, so: L1-dcache-loads [Hardware cache event] becomes: L1-dcache-loads OR cpu/L1-dcache-loads/ Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/util/parse-events.c | 2 +- tools/perf/util/parse-events.h | 1 + tools/perf/util/print-events.c | 88 ++++++++++++++++------------------ 3 files changed, 43 insertions(+), 48 deletions(-) diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index 9f2bbf8f3a81..ec72f11fb37f 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -414,7 +414,7 @@ static int config_attr(struct perf_event_attr *attr, * contain hyphens and the longest name * should always be selected. */ -static int parse_events__decode_legacy_cache(const char *name, int pmu_typ= e, __u64 *config) +int parse_events__decode_legacy_cache(const char *name, int pmu_type, __u6= 4 *config) { int len, cache_type =3D -1, cache_op =3D -1, cache_result =3D -1; const char *name_end =3D &name[strlen(name) + 1]; diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index 0c26303f7f63..4e49be290209 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -173,6 +173,7 @@ int parse_events_add_tool(struct parse_events_state *pa= rse_state, int parse_events_add_cache(struct list_head *list, int *idx, const char *n= ame, struct parse_events_error *error, struct list_head *head_config); +int parse_events__decode_legacy_cache(const char *name, int pmu_type, __u6= 4 *config); int parse_events_add_breakpoint(struct list_head *list, int *idx, u64 addr, char *type, u64 len); int parse_events_add_pmu(struct parse_events_state *parse_state, diff --git a/tools/perf/util/print-events.c b/tools/perf/util/print-events.c index 89ac34a922c9..d148842b205a 100644 --- a/tools/perf/util/print-events.c +++ b/tools/perf/util/print-events.c @@ -230,56 +230,50 @@ void print_sdt_events(const struct print_callbacks *p= rint_cb, void *print_state) =20 int print_hwcache_events(const struct print_callbacks *print_cb, void *pri= nt_state) { + struct perf_pmu *pmu =3D NULL; const char *event_type_descriptor =3D event_type_descriptors[PERF_TYPE_HW= _CACHE]; =20 - for (int type =3D 0; type < PERF_COUNT_HW_CACHE_MAX; type++) { - for (int op =3D 0; op < PERF_COUNT_HW_CACHE_OP_MAX; op++) { - /* skip invalid cache type */ - if (!evsel__is_cache_op_valid(type, op)) - continue; - - for (int res =3D 0; res < PERF_COUNT_HW_CACHE_RESULT_MAX; res++) { - struct perf_pmu *pmu =3D NULL; - char name[64]; - - __evsel__hw_cache_type_op_res_name(type, op, res, - name, sizeof(name)); - if (!perf_pmu__has_hybrid()) { - if (is_event_supported(PERF_TYPE_HW_CACHE, - type | (op << 8) | (res << 16))) { - print_cb->print_event(print_state, - "cache", - /*pmu_name=3D*/NULL, - name, - /*event_alias=3D*/NULL, - /*scale_unit=3D*/NULL, - /*deprecated=3D*/false, - event_type_descriptor, - /*desc=3D*/NULL, - /*long_desc=3D*/NULL, - /*encoding_desc=3D*/NULL); - } + while ((pmu =3D perf_pmu__scan(pmu)) !=3D NULL) { + /* + * Skip uncore PMUs for performance. PERF_TYPE_HW_CACHE type + * attributes can accept software PMUs in the extended type, so + * also skip. + */ + if (pmu->is_uncore || pmu->type =3D=3D PERF_TYPE_SOFTWARE) + continue; + + for (int type =3D 0; type < PERF_COUNT_HW_CACHE_MAX; type++) { + for (int op =3D 0; op < PERF_COUNT_HW_CACHE_OP_MAX; op++) { + /* skip invalid cache type */ + if (!evsel__is_cache_op_valid(type, op)) continue; - } - perf_pmu__for_each_hybrid_pmu(pmu) { - if (is_event_supported(PERF_TYPE_HW_CACHE, - type | (op << 8) | (res << 16) | - ((__u64)pmu->type << PERF_PMU_TYPE_SHIFT))) { - char new_name[128]; - snprintf(new_name, sizeof(new_name), - "%s/%s/", pmu->name, name); - print_cb->print_event(print_state, - "cache", - pmu->name, - name, - new_name, - /*scale_unit=3D*/NULL, - /*deprecated=3D*/false, - event_type_descriptor, - /*desc=3D*/NULL, - /*long_desc=3D*/NULL, - /*encoding_desc=3D*/NULL); - } + + for (int res =3D 0; res < PERF_COUNT_HW_CACHE_RESULT_MAX; res++) { + char name[64]; + char alias_name[128]; + __u64 config; + int ret; + + __evsel__hw_cache_type_op_res_name(type, op, res, + name, sizeof(name)); + + ret =3D parse_events__decode_legacy_cache(name, pmu->type, + &config); + if (ret || !is_event_supported(PERF_TYPE_HW_CACHE, config)) + continue; + snprintf(alias_name, sizeof(alias_name), "%s/%s/", + pmu->name, name); + print_cb->print_event(print_state, + "cache", + pmu->name, + name, + alias_name, + /*scale_unit=3D*/NULL, + /*deprecated=3D*/false, + event_type_descriptor, + /*desc=3D*/NULL, + /*long_desc=3D*/NULL, + /*encoding_desc=3D*/NULL); } } } --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A663C77B75 for ; Tue, 2 May 2023 22:43:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230200AbjEBWn2 (ORCPT ); Tue, 2 May 2023 18:43:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59302 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230244AbjEBWnB (ORCPT ); Tue, 2 May 2023 18:43:01 -0400 Received: from mail-pl1-x649.google.com (mail-pl1-x649.google.com [IPv6:2607:f8b0:4864:20::649]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7CECC40FD for ; Tue, 2 May 2023 15:42:32 -0700 (PDT) Received: by mail-pl1-x649.google.com with SMTP id d9443c01a7336-1aae803a5eeso19482185ad.0 for ; Tue, 02 May 2023 15:42:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067342; x=1685659342; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=f/8TJqkQ5vnLaKx87JVN8hYpVBFz1O0XRBKOdoWz1f8=; b=fJLhtbcVJey1ObHBX7e6uuf+KCbjSeSro+UcHz8JlILzgGuXpRzZRMT6by6TCbZChf 8PvOIQNhjP///PZpVyRJ3CQPZdunE23MqA5tymPAPgDRVG+tmEQoBjjWGVywMQetgDm+ XfELo5/lU9yamVrX2Pqq/W8xxoS/qJZyBWeYUH0jI3NeSUoEG4AH194IOTDbEzJkR+HS sHbBiaN90sB0se3XhSJf3R7MJhkxecGuo4CbNUhzGbf34ojsMw3INs8OCJg5EtCkqUTQ 9DHAsTkgVRXyWxpVkN3dJo8gqxx2P3In0rJ6/Av+GxHFAQqGWCK8YSrfmjYe+G+GK8Ci cz0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067342; x=1685659342; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=f/8TJqkQ5vnLaKx87JVN8hYpVBFz1O0XRBKOdoWz1f8=; b=ND5pqt8G+gZiOZurzX3m3Snlflek/hLSm8Mf5FHvW652iJxpy7q+1BiDJXKWHwAETo O/wp6tOuu/ftu5LWRL5mlmh9gqkZx+5XOIPqL81G2zMFwCeM2GDPozGyvRaCnMUS4mKc tdnDXLIbVUCo3Q9hGJJoK/tvGRbKcOebJ0J0uBiC38xHbLWykSMNxeTRr+tRqlNjIh6w GeDwtMwAeu7amj1TISsswDRTx25F/mrSbt7V5CPVmdjorpoTwcjKaEHXrI1dqz72Zw9E m0U+yLioKhW42xt65u+d1VtNLndj9BEBZaD5r3ey0tPLz5Go+17TwuvCjwtxrMQv5lrU 6Y+Q== X-Gm-Message-State: AC+VfDxdcJ9r14yhqUQ39k97x3ANl71fJbzGaHUt6LubmvWcbxFOwjoM /mCxYLFU9Uj82vkB/TyrF3mIuSuDQT9P X-Google-Smtp-Source: ACHHUZ74WWJhk+5dD3m5Fo+4j9FiF3JPXm23LzxAChofkMmrwddZXcIUmphhU51K7DDz0bbQiNC5uL0FYE0W X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a17:902:8a96:b0:1a5:15bb:e3cb with SMTP id p22-20020a1709028a9600b001a515bbe3cbmr15025plo.12.1683067341882; Tue, 02 May 2023 15:42:21 -0700 (PDT) Date: Tue, 2 May 2023 15:38:33 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-27-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 26/44] perf parse-events: Support wildcards on raw events From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Legacy raw events like r1a open as PERF_TYPE_RAW on non-hybrid systems and on each hybrid PMU on hybrid systems. Rather than iterate hybrid PMUs add a perf_pmu__supports_wildcard_numeric function that says when a numeric event should be opened upon it. If the parsed event specifies the type of the PMU then don't wildcard match PMUs, use the specified PMU type. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/util/parse-events.c | 50 ++++++++++++++++++++++++---------- tools/perf/util/parse-events.h | 3 +- tools/perf/util/parse-events.y | 13 ++++++--- tools/perf/util/pmu.c | 5 ++++ tools/perf/util/pmu.h | 1 + 5 files changed, 52 insertions(+), 20 deletions(-) diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index ec72f11fb37f..c8b4ec076825 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -25,7 +25,6 @@ #include "util/parse-branch-options.h" #include "util/evsel_config.h" #include "util/event.h" -#include "util/parse-events-hybrid.h" #include "util/pmu-hybrid.h" #include "util/bpf-filter.h" #include "util/util.h" @@ -1448,15 +1447,14 @@ int parse_events_add_tracepoint(struct list_head *l= ist, int *idx, #endif } =20 -int parse_events_add_numeric(struct parse_events_state *parse_state, - struct list_head *list, - u32 type, u64 config, - struct list_head *head_config) +static int __parse_events_add_numeric(struct parse_events_state *parse_sta= te, + struct list_head *list, + struct perf_pmu *pmu, u32 type, u64 config, + struct list_head *head_config) { struct perf_event_attr attr; LIST_HEAD(config_terms); const char *name, *metric_id; - bool hybrid; int ret; =20 memset(&attr, 0, sizeof(attr)); @@ -1474,19 +1472,41 @@ int parse_events_add_numeric(struct parse_events_st= ate *parse_state, =20 name =3D get_config_name(head_config); metric_id =3D get_config_metric_id(head_config); - ret =3D parse_events__add_numeric_hybrid(parse_state, list, &attr, - name, metric_id, - &config_terms, &hybrid); - if (hybrid) - goto out_free_terms; - - ret =3D add_event(list, &parse_state->idx, &attr, name, metric_id, - &config_terms); -out_free_terms: + ret =3D __add_event(list, &parse_state->idx, &attr, /*init_attr*/true, na= me, + metric_id, pmu, &config_terms, /*auto_merge_stats=3D*/false, + /*cpu_list=3D*/NULL) ? 0 : -ENOMEM; free_config_terms(&config_terms); return ret; } =20 +int parse_events_add_numeric(struct parse_events_state *parse_state, + struct list_head *list, + u32 type, u64 config, + struct list_head *head_config, + bool wildcard) +{ + struct perf_pmu *pmu =3D NULL; + bool found_supported =3D false; + + if (!wildcard) + return __parse_events_add_numeric(parse_state, list, /*pmu=3D*/NULL, + type, config, head_config); + + while ((pmu =3D perf_pmu__scan(pmu)) !=3D NULL) { + int ret; + + if (!perf_pmu__supports_wildcard_numeric(pmu)) + continue; + + found_supported =3D true; + ret =3D __parse_events_add_numeric(parse_state, list, pmu, pmu->type, + config, head_config); + if (ret) + return ret; + } + return found_supported ? 0 : -EINVAL; +} + int parse_events_add_tool(struct parse_events_state *parse_state, struct list_head *list, int tool_event) diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index 4e49be290209..831cd1ff4702 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -166,7 +166,8 @@ int parse_events_load_bpf_obj(struct parse_events_state= *parse_state, int parse_events_add_numeric(struct parse_events_state *parse_state, struct list_head *list, u32 type, u64 config, - struct list_head *head_config); + struct list_head *head_config, + bool wildcard); int parse_events_add_tool(struct parse_events_state *parse_state, struct list_head *list, int tool_event); diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y index cc7528558845..5055a29a448f 100644 --- a/tools/perf/util/parse-events.y +++ b/tools/perf/util/parse-events.y @@ -435,7 +435,8 @@ value_sym '/' event_config '/' =20 list =3D alloc_list(); ABORT_ON(!list); - err =3D parse_events_add_numeric(_parse_state, list, type, config, $3); + err =3D parse_events_add_numeric(_parse_state, list, type, config, $3, + /*wildcard=3D*/false); parse_events_terms__delete($3); if (err) { free_list_evsel(list); @@ -452,7 +453,9 @@ value_sym sep_slash_slash_dc =20 list =3D alloc_list(); ABORT_ON(!list); - ABORT_ON(parse_events_add_numeric(_parse_state, list, type, config, NULL)= ); + ABORT_ON(parse_events_add_numeric(_parse_state, list, type, config, + /*head_config=3D*/NULL, + /*wildcard=3D*/false)); $$ =3D list; } | @@ -596,7 +599,8 @@ PE_VALUE ':' PE_VALUE opt_event_config =20 list =3D alloc_list(); ABORT_ON(!list); - err =3D parse_events_add_numeric(_parse_state, list, (u32)$1, $3, $4); + err =3D parse_events_add_numeric(_parse_state, list, (u32)$1, $3, $4, + /*wildcard=3D*/false); parse_events_terms__delete($4); if (err) { free(list); @@ -618,7 +622,8 @@ PE_RAW opt_event_config num =3D strtoull($1 + 1, NULL, 16); ABORT_ON(errno); free($1); - err =3D parse_events_add_numeric(_parse_state, list, PERF_TYPE_RAW, num, = $2); + err =3D parse_events_add_numeric(_parse_state, list, PERF_TYPE_RAW, num, = $2, + /*wildcard=3D*/true); parse_events_terms__delete($2); if (err) { free(list); diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index 63071d876190..cd4247a379d4 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -1655,6 +1655,11 @@ bool perf_pmu__supports_legacy_cache(const struct pe= rf_pmu *pmu) return is_pmu_core(pmu->name) || perf_pmu__is_hybrid(pmu->name); } =20 +bool perf_pmu__supports_wildcard_numeric(const struct perf_pmu *pmu) +{ + return is_pmu_core(pmu->name) || perf_pmu__is_hybrid(pmu->name); +} + static bool pmu_alias_is_duplicate(struct sevent *alias_a, struct sevent *alias_b) { diff --git a/tools/perf/util/pmu.h b/tools/perf/util/pmu.h index 05702bc4bcf8..5a19536a5449 100644 --- a/tools/perf/util/pmu.h +++ b/tools/perf/util/pmu.h @@ -221,6 +221,7 @@ struct perf_pmu *perf_pmu__scan(struct perf_pmu *pmu); =20 bool is_pmu_core(const char *name); bool perf_pmu__supports_legacy_cache(const struct perf_pmu *pmu); +bool perf_pmu__supports_wildcard_numeric(const struct perf_pmu *pmu); void print_pmu_events(const struct print_callbacks *print_cb, void *print_= state); bool pmu_have_event(const char *pname, const char *name); =20 --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68BB7C7EE24 for ; Tue, 2 May 2023 22:43:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230340AbjEBWnt (ORCPT ); Tue, 2 May 2023 18:43:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58878 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230130AbjEBWnZ (ORCPT ); Tue, 2 May 2023 18:43:25 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B11ED2118 for ; Tue, 2 May 2023 15:43:01 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-b9a7766d220so5489780276.2 for ; Tue, 02 May 2023 15:43:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067348; x=1685659348; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=sk/Af9OhGeiAb3O189dXvyWycv0TC2mq/SKExWqmmO4=; b=lJD4dSrBRnmA0K6Bgf0sSiY8CVchmh80k67poKvC2NtaucG8hIsOUR1zdrHD2nvCxK e3p0PyAExWdbAvCDYmzY3/s5cTN/GQwMhzLmAej9rYpV75yU9/nS8rvOz9VuNFzcHT90 AwiYkGBp22iwg6Ovtoj7JzayeZirt1zJQ4uzpcTabt97ArDaqVUnUMLpqtDvYBiDZqBf Fb1B1goAWUIH96evDpamToxCHQXpxVRWgLnasjgljSnbOhX4gZymsw/f2uWASvu9yngY 7mkHKl/LotHI899o1EOzGh6cjxC7/OMXvmaI3V4/JUO5lZo9V9EzPgf2KWBNcWZg59MV fnww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067348; x=1685659348; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=sk/Af9OhGeiAb3O189dXvyWycv0TC2mq/SKExWqmmO4=; b=U3Cwkw50rviNpf/+i+mUIxeza1cj/Xac106zAGUPWFQ9PnHJnFiPhZuorC140MzuCF /0NLDtBhQxkOeLIO2Ex1OkDgJpZcRMopELn7ncsAIh8EdyW0Yj5rDZyLR2uNTNXmiVzt UAAhMaDmYeTs8WMUk8zZvoz7LkufK2QN+tLwg0CX5qRmbIEDvgwXRC3Caiw1KMkVYA5M jSYBIROAOOrHZr34TjQz1ZaXg/CfYo3Zlx1qflUGSp/N5BEpyree6Q4VvPeEhrzCBrfc v1ZW4Lrk0WneKj0sMi2ux+Jygl+BVFQFXHSBBDZDEuNSRSf8m+EtsOOjrKgv7bWkdPxP 6l4A== X-Gm-Message-State: AC+VfDyS1ydqWQsAkaRNJI+tr4jLT38fTmB4jrLr04qOgXZcvNZ4JR6L ZXCAFK9cwBIsAAa1R6I08O/6kRlX9UAy X-Google-Smtp-Source: ACHHUZ7xUyxCswP1gnH1lEItuYulCCTIebZ1PmqoD0WGiE29dlvCAM1VV7BGVgxR5u6kQ1Gm4itGkI/EjA0O X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a05:6902:1028:b0:b8c:607:7669 with SMTP id x8-20020a056902102800b00b8c06077669mr11812052ybt.5.1683067348598; Tue, 02 May 2023 15:42:28 -0700 (PDT) Date: Tue, 2 May 2023 15:38:34 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-28-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 27/44] perf parse-events: Remove now unused hybrid logic From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The event parser no longer needs to recurse in case of a legacy cache event in a PMU, the necessary wild card logic has moved to perf_pmu__supports_legacy_cache and perf_pmu__supports_wildcard_numeric. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/util/Build | 1 - tools/perf/util/parse-events-hybrid.c | 181 -------------------------- tools/perf/util/parse-events-hybrid.h | 18 --- tools/perf/util/parse-events.c | 74 ----------- tools/perf/util/parse-events.h | 8 -- 5 files changed, 282 deletions(-) delete mode 100644 tools/perf/util/parse-events-hybrid.c delete mode 100644 tools/perf/util/parse-events-hybrid.h diff --git a/tools/perf/util/Build b/tools/perf/util/Build index bd18fe5f2719..c146736ead19 100644 --- a/tools/perf/util/Build +++ b/tools/perf/util/Build @@ -24,7 +24,6 @@ perf-y +=3D llvm-utils.o perf-y +=3D mmap.o perf-y +=3D memswap.o perf-y +=3D parse-events.o -perf-y +=3D parse-events-hybrid.o perf-y +=3D print-events.o perf-y +=3D tracepoint.o perf-y +=3D perf_regs.o diff --git a/tools/perf/util/parse-events-hybrid.c b/tools/perf/util/parse-= events-hybrid.c deleted file mode 100644 index d2c0be051d46..000000000000 --- a/tools/perf/util/parse-events-hybrid.c +++ /dev/null @@ -1,181 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include -#include -#include -#include "evlist.h" -#include "evsel.h" -#include "parse-events.h" -#include "parse-events-hybrid.h" -#include "debug.h" -#include "pmu.h" -#include "pmu-hybrid.h" -#include "perf.h" - -static void config_hybrid_attr(struct perf_event_attr *attr, - int type, int pmu_type) -{ - /* - * attr.config layout for type PERF_TYPE_HARDWARE and - * PERF_TYPE_HW_CACHE - * - * PERF_TYPE_HARDWARE: 0xEEEEEEEE000000AA - * AA: hardware event ID - * EEEEEEEE: PMU type ID - * PERF_TYPE_HW_CACHE: 0xEEEEEEEE00DDCCBB - * BB: hardware cache ID - * CC: hardware cache op ID - * DD: hardware cache op result ID - * EEEEEEEE: PMU type ID - * If the PMU type ID is 0, the PERF_TYPE_RAW will be applied. - */ - attr->type =3D type; - attr->config =3D (attr->config & PERF_HW_EVENT_MASK) | - ((__u64)pmu_type << PERF_PMU_TYPE_SHIFT); -} - -static int create_event_hybrid(__u32 config_type, int *idx, - struct list_head *list, - struct perf_event_attr *attr, const char *name, - const char *metric_id, - struct list_head *config_terms, - struct perf_pmu *pmu) -{ - struct evsel *evsel; - __u32 type =3D attr->type; - __u64 config =3D attr->config; - - config_hybrid_attr(attr, config_type, pmu->type); - - /* - * Some hybrid hardware cache events are only available on one CPU - * PMU. For example, the 'L1-dcache-load-misses' is only available - * on cpu_core, while the 'L1-icache-loads' is only available on - * cpu_atom. We need to remove "not supported" hybrid cache events. - */ - if (attr->type =3D=3D PERF_TYPE_HW_CACHE - && !is_event_supported(attr->type, attr->config)) - return 0; - - evsel =3D parse_events__add_event_hybrid(list, idx, attr, name, metric_id, - pmu, config_terms); - if (evsel) { - evsel->pmu_name =3D strdup(pmu->name); - if (!evsel->pmu_name) - return -ENOMEM; - } else - return -ENOMEM; - attr->type =3D type; - attr->config =3D config; - return 0; -} - -static int pmu_cmp(struct parse_events_state *parse_state, - struct perf_pmu *pmu) -{ - if (parse_state->evlist && parse_state->evlist->hybrid_pmu_name) - return strcmp(parse_state->evlist->hybrid_pmu_name, pmu->name); - - if (parse_state->hybrid_pmu_name) - return strcmp(parse_state->hybrid_pmu_name, pmu->name); - - return 0; -} - -static int add_hw_hybrid(struct parse_events_state *parse_state, - struct list_head *list, struct perf_event_attr *attr, - const char *name, const char *metric_id, - struct list_head *config_terms) -{ - struct perf_pmu *pmu; - int ret; - - perf_pmu__for_each_hybrid_pmu(pmu) { - LIST_HEAD(terms); - - if (pmu_cmp(parse_state, pmu)) - continue; - - copy_config_terms(&terms, config_terms); - ret =3D create_event_hybrid(PERF_TYPE_HARDWARE, - &parse_state->idx, list, attr, name, - metric_id, &terms, pmu); - free_config_terms(&terms); - if (ret) - return ret; - } - - return 0; -} - -static int create_raw_event_hybrid(int *idx, struct list_head *list, - struct perf_event_attr *attr, - const char *name, - const char *metric_id, - struct list_head *config_terms, - struct perf_pmu *pmu) -{ - struct evsel *evsel; - - attr->type =3D pmu->type; - evsel =3D parse_events__add_event_hybrid(list, idx, attr, name, metric_id, - pmu, config_terms); - if (evsel) - evsel->pmu_name =3D strdup(pmu->name); - else - return -ENOMEM; - - return 0; -} - -static int add_raw_hybrid(struct parse_events_state *parse_state, - struct list_head *list, struct perf_event_attr *attr, - const char *name, const char *metric_id, - struct list_head *config_terms) -{ - struct perf_pmu *pmu; - int ret; - - perf_pmu__for_each_hybrid_pmu(pmu) { - LIST_HEAD(terms); - - if (pmu_cmp(parse_state, pmu)) - continue; - - copy_config_terms(&terms, config_terms); - ret =3D create_raw_event_hybrid(&parse_state->idx, list, attr, - name, metric_id, &terms, pmu); - free_config_terms(&terms); - if (ret) - return ret; - } - - return 0; -} - -int parse_events__add_numeric_hybrid(struct parse_events_state *parse_stat= e, - struct list_head *list, - struct perf_event_attr *attr, - const char *name, const char *metric_id, - struct list_head *config_terms, - bool *hybrid) -{ - *hybrid =3D false; - if (attr->type =3D=3D PERF_TYPE_SOFTWARE) - return 0; - - if (!perf_pmu__has_hybrid()) - return 0; - - *hybrid =3D true; - if (attr->type !=3D PERF_TYPE_RAW) { - return add_hw_hybrid(parse_state, list, attr, name, metric_id, - config_terms); - } - - return add_raw_hybrid(parse_state, list, attr, name, metric_id, - config_terms); -} diff --git a/tools/perf/util/parse-events-hybrid.h b/tools/perf/util/parse-= events-hybrid.h deleted file mode 100644 index bc2966e73897..000000000000 --- a/tools/perf/util/parse-events-hybrid.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __PERF_PARSE_EVENTS_HYBRID_H -#define __PERF_PARSE_EVENTS_HYBRID_H - -#include -#include -#include -#include -#include - -int parse_events__add_numeric_hybrid(struct parse_events_state *parse_stat= e, - struct list_head *list, - struct perf_event_attr *attr, - const char *name, const char *metric_id, - struct list_head *config_terms, - bool *hybrid); - -#endif /* __PERF_PARSE_EVENTS_HYBRID_H */ diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index c8b4ec076825..1d8c3cf9c185 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -25,7 +25,6 @@ #include "util/parse-branch-options.h" #include "util/evsel_config.h" #include "util/event.h" -#include "util/pmu-hybrid.h" #include "util/bpf-filter.h" #include "util/util.h" #include "tracepoint.h" @@ -39,9 +38,6 @@ extern int parse_events_debug; int parse_events_parse(void *parse_state, void *scanner); static int get_config_terms(struct list_head *head_config, struct list_head *head_terms __maybe_unused); -static int parse_events__with_hybrid_pmu(struct parse_events_state *parse_= state, - const char *str, char *pmu_name, - struct list_head *list); =20 struct event_symbol event_symbols_hw[PERF_COUNT_HW_MAX] =3D { [PERF_COUNT_HW_CPU_CYCLES] =3D { @@ -1526,33 +1522,6 @@ static bool config_term_percore(struct list_head *co= nfig_terms) return false; } =20 -static int parse_events__inside_hybrid_pmu(struct parse_events_state *pars= e_state, - struct list_head *list, char *name, - struct list_head *head_config) -{ - struct parse_events_term *term; - int ret =3D -1; - - if (parse_state->fake_pmu || !head_config || list_empty(head_config) || - !perf_pmu__is_hybrid(name)) { - return -1; - } - - /* - * More than one term in list. - */ - if (head_config->next && head_config->next->next !=3D head_config) - return -1; - - term =3D list_first_entry(head_config, struct parse_events_term, list); - if (term && term->config && strcmp(term->config, "event")) { - ret =3D parse_events__with_hybrid_pmu(parse_state, term->config, - name, list); - } - - return ret; -} - int parse_events_add_pmu(struct parse_events_state *parse_state, struct list_head *list, char *name, struct list_head *head_config, @@ -1642,11 +1611,6 @@ int parse_events_add_pmu(struct parse_events_state *= parse_state, if (pmu->default_config && get_config_chgs(pmu, head_config, &config_term= s)) return -ENOMEM; =20 - if (!parse_events__inside_hybrid_pmu(parse_state, list, name, - head_config)) { - return 0; - } - if (!parse_state->fake_pmu && perf_pmu__config(pmu, &attr, head_config, p= arse_state->error)) { free_config_terms(&config_terms); return -EINVAL; @@ -2023,32 +1987,6 @@ int parse_events_terms(struct list_head *terms, cons= t char *str) return ret; } =20 -static int parse_events__with_hybrid_pmu(struct parse_events_state *parse_= state, - const char *str, char *pmu_name, - struct list_head *list) -{ - struct parse_events_state ps =3D { - .list =3D LIST_HEAD_INIT(ps.list), - .stoken =3D PE_START_EVENTS, - .hybrid_pmu_name =3D pmu_name, - .idx =3D parse_state->idx, - }; - int ret; - - ret =3D parse_events__scanner(str, &ps); - - if (!ret) { - if (!list_empty(&ps.list)) { - list_splice(&ps.list, list); - parse_state->idx =3D ps.idx; - return 0; - } else - return -1; - } - - return ret; -} - __weak int arch_evlist__cmp(const struct evsel *lhs, const struct evsel *r= hs) { /* Order by insertion index. */ @@ -2779,15 +2717,3 @@ char *parse_events_formats_error_string(char *additi= onal_terms) fail: return NULL; } - -struct evsel *parse_events__add_event_hybrid(struct list_head *list, int *= idx, - struct perf_event_attr *attr, - const char *name, - const char *metric_id, - struct perf_pmu *pmu, - struct list_head *config_terms) -{ - return __add_event(list, idx, attr, /*init_attr=3D*/true, name, metric_id, - pmu, config_terms, /*auto_merge_stats=3D*/false, - /*cpu_list=3D*/NULL); -} diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index 831cd1ff4702..77b8f7efdb94 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -122,7 +122,6 @@ struct parse_events_state { struct list_head *terms; int stoken; struct perf_pmu *fake_pmu; - char *hybrid_pmu_name; /* Should PE_LEGACY_NAME tokens be generated for config terms? */ bool match_legacy_cache_terms; bool wild_card_pmus; @@ -235,11 +234,4 @@ static inline bool is_sdt_event(char *str __maybe_unus= ed) } #endif /* HAVE_LIBELF_SUPPORT */ =20 -struct evsel *parse_events__add_event_hybrid(struct list_head *list, int *= idx, - struct perf_event_attr *attr, - const char *name, - const char *metric_id, - struct perf_pmu *pmu, - struct list_head *config_terms); - #endif /* __PERF_PARSE_EVENTS_H */ --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01645C77B75 for ; Tue, 2 May 2023 22:43:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230343AbjEBWnx (ORCPT ); Tue, 2 May 2023 18:43:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59958 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230214AbjEBWn2 (ORCPT ); Tue, 2 May 2023 18:43:28 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9388040DE for ; Tue, 2 May 2023 15:43:05 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-b9a6eeea78cso659926276.0 for ; Tue, 02 May 2023 15:43:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067355; x=1685659355; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=feNyjAPtIUSUDrmLxKNanb31JNx+5xcJ7s4SppqU3s8=; b=REXrHwCTXLTnSbe1iZkuQgxh4N12mruI5ZipwMyoTVHW9B/m4ZTEC5/0pGb4jd0+0J aZgEUrG6P5DbICT9hQP3KqWH/5vqphaU9l9Bg3B4RWRoDuHjr8l15+/BZWGuoSdjTk3O +jNU4EVRImubU9+JS5RKb2Vf2wlF60uPxLouuaGQd5vkuH+GTtQI/sV/Tou0LKAgISkh iSJcmsNVJ9Y7G7KdVZhpPLaA5xX+ECe4eo67Ku3U+YK18BXhg08PnS0bMyHUq3DTrw9z QI1lnGjtn/sV9ZUJb6XUKrSdL03RTJowG/dBqZNzc+bC7nH31PwYpetaovAzR2Ih2vwJ rjvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067355; x=1685659355; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=feNyjAPtIUSUDrmLxKNanb31JNx+5xcJ7s4SppqU3s8=; b=XzBiMTMJE/ehM2W8SYUI3aa0DFlguw1hRUjTtHQoCPxU9bWc1mIJwc1D68CVegAFOG X4yp0AHCDf4TY5ABPoKvNlQUUaLYP9t+Gf4T/eKnVrWVGE8WjWe+euqSJFy3YcRhPmZ5 K4OVYphqLN+ltERle7NsAmIuVkBPEKkzN+/bic8bvI8UNKnQEB1FEQZad4PJLBgFI14U c1QtBQKugb7PAYoaDm1Gbcn9T0ZI20/1lpGG+zgtTP3c8XeHH03SCS2vGQS9Ekoj8s1t d7Y4dvruqU09ZX0jfadYHrQTwLQt9dqFU6HlLYfc5SsmPBlrj3tdy3gr6LXhJN9EVogI dpSQ== X-Gm-Message-State: AC+VfDx3TLlwBq8KXAKQEkzv6rSP1slXUhLk2vc5kDBNYvKmPb5Fj3Bu 48PA2Su+BaeWaO0hqMU6YHd42JdwsVtX X-Google-Smtp-Source: ACHHUZ4ommsB49l5fRU7dRorIPbrQE2zo3ipn3gCL6a0IbyEM+FSgowB3hMePeNVeCLm9UotuDiZBImfPCHx X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a25:5485:0:b0:b9e:5dbe:7535 with SMTP id i127-20020a255485000000b00b9e5dbe7535mr101773ybb.5.1683067355524; Tue, 02 May 2023 15:42:35 -0700 (PDT) Date: Tue, 2 May 2023 15:38:35 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-29-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 28/44] perf parse-events: Minor type safety cleanup From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use the typed parse_state rather than void* _parse_state when available. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/util/parse-events.y | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y index 5055a29a448f..e709508b1d6e 100644 --- a/tools/perf/util/parse-events.y +++ b/tools/perf/util/parse-events.y @@ -301,7 +301,7 @@ PE_NAME opt_pmu_config if (!list) CLEANUP_YYABORT; /* Attempt to add to list assuming $1 is a PMU name. */ - if (parse_events_add_pmu(_parse_state, list, $1, $2, /*auto_merge_stats= =3D*/false)) { + if (parse_events_add_pmu(parse_state, list, $1, $2, /*auto_merge_stats=3D= */false)) { struct perf_pmu *pmu =3D NULL; int ok =3D 0; =20 @@ -319,7 +319,7 @@ PE_NAME opt_pmu_config !perf_pmu__match(pattern, pmu->alias_name, $1)) { if (parse_events_copy_term_list(orig_terms, &terms)) CLEANUP_YYABORT; - if (!parse_events_add_pmu(_parse_state, list, pmu->name, terms, + if (!parse_events_add_pmu(parse_state, list, pmu->name, terms, /*auto_merge_stats=3D*/true)) { ok++; parse_state->wild_card_pmus =3D true; @@ -331,7 +331,7 @@ PE_NAME opt_pmu_config if (!ok) { /* Failure to add, assume $1 is an event name. */ zfree(&list); - ok =3D !parse_events_multi_pmu_add(_parse_state, $1, $2, &list); + ok =3D !parse_events_multi_pmu_add(parse_state, $1, $2, &list); $2 =3D NULL; } if (!ok) --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E21BDC19F20 for ; Tue, 2 May 2023 22:44:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230216AbjEBWoL (ORCPT ); Tue, 2 May 2023 18:44:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60396 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230309AbjEBWnp (ORCPT ); Tue, 2 May 2023 18:43:45 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A787830DD for ; Tue, 2 May 2023 15:43:14 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-b9a8023ccf1so8699729276.2 for ; Tue, 02 May 2023 15:43:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067362; x=1685659362; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=rIy1w7Suqr6o3m/wJrfSKrKWSdqbzqB7RJQwe4p4GGY=; b=XsMbJlHkDCMgrHHR0sONjvSl1QaHIlCBfs7hrYO9z7BqSaH0YUOBD46md6wq/ky+10 IDg3thG6w1jz7abHSyp50Sbxbv/aAddV3ouaO/YiZHckNHKEKjrkns05qNSviYwjiddL 0GCeN3hNrZmHyqyXPpKtevSMyC3nSDN4cT4qVtGp/l2cVn6CEMWr5dREL9vizVlIoR59 Ltfg0yvP7TXIWa0j7/ampcUKlUgq0FcQdj9D6GXx+xc+nVG9Gu8GtqQXR91Kg45ATzLl W/yU8a/7CGz9vDcA13jYJKjmsTGaKMBG3nIPCj7GTNUjUSH+45U5abWbNbOSmqWGN0YB E6Ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067362; x=1685659362; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=rIy1w7Suqr6o3m/wJrfSKrKWSdqbzqB7RJQwe4p4GGY=; b=T8IvDt4yBK8A9Mc/c8v8iAIGEeb9h+flV9i1vykyKooEr5Vrg62SB3nfhmEwdg4HcE 7BcgGOBS3btCCoVsEMhLISC9uIZGmdjkhm1fWi9A00WEQKWCuNM3KPfHpr05s/e1iZMB GS+18F/CmbmKfhcc2m9yRmH2cK8gglZJ8/BqRu54+XX42D+YUxyFm/PkgtjnhRi5H5pI UcBKyBzQ4YMVRtOH5cz1J+5Wb8aktWCOy0U8oOugD8G7yhoABsvMfl1HNz/y91aQThQa jqCBoeOH6wY4XjnU0NVuaEDWEAcpT7vMxZF6rBa+gcCeEffxixvjkxKKmN9OjZTN4LUy rQ1A== X-Gm-Message-State: AC+VfDw9V2/sUSeHfVWYpretcjI6gywyKpIscLyn+ujjCpB56Dx187my uQBD/fFK+WwL2dRdYP2w6QZau2vjmtnG X-Google-Smtp-Source: ACHHUZ7TZGwSrb219E1b+bY23owoCyi2h24jldDYMrySXgPgVNaxdPQjbUYN1rDDiB37NJholkaP59A7/cF+ X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a25:4884:0:b0:b9a:6a68:7c25 with SMTP id v126-20020a254884000000b00b9a6a687c25mr11147022yba.5.1683067362583; Tue, 02 May 2023 15:42:42 -0700 (PDT) Date: Tue, 2 May 2023 15:38:36 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-30-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 29/44] perf parse-events: Add pmu filter From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To support the cputype argument added to "perf stat" for hybrid it is necessary to filter events during wildcard matching. Add a scanner argument for the filter and checking it when wildcard matching. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/builtin-record.c | 13 +++++++-- tools/perf/builtin-stat.c | 10 +++++-- tools/perf/builtin-top.c | 5 +++- tools/perf/builtin-trace.c | 5 +++- tools/perf/tests/parse-events.c | 3 +- tools/perf/tests/pmu-events.c | 3 +- tools/perf/util/evlist.h | 1 - tools/perf/util/metricgroup.c | 4 +-- tools/perf/util/parse-events.c | 51 ++++++++++++++++++++++++--------- tools/perf/util/parse-events.h | 21 ++++++++++---- tools/perf/util/parse-events.y | 6 ++-- 11 files changed, 90 insertions(+), 32 deletions(-) diff --git a/tools/perf/builtin-record.c b/tools/perf/builtin-record.c index 7b7e74a56346..7e4490dfc0b5 100644 --- a/tools/perf/builtin-record.c +++ b/tools/perf/builtin-record.c @@ -3335,6 +3335,14 @@ const char record_callchain_help[] =3D CALLCHAIN_REC= ORD_HELP =20 static bool dry_run; =20 +static struct parse_events_option_args parse_events_option_args =3D { + .evlistp =3D &record.evlist, +}; + +static struct parse_events_option_args switch_output_parse_events_option_a= rgs =3D { + .evlistp =3D &record.sb_evlist, +}; + /* * XXX Will stay a global variable till we fix builtin-script.c to stop me= ssing * with it and switch to use the library functions in perf_evlist that came @@ -3343,7 +3351,7 @@ static bool dry_run; * using pipes, etc. */ static struct option __record_options[] =3D { - OPT_CALLBACK('e', "event", &record.evlist, "event", + OPT_CALLBACK('e', "event", &parse_events_option_args, "event", "event selector. use 'perf list' to list available events", parse_events_option), OPT_CALLBACK(0, "filter", &record.evlist, "filter", @@ -3496,7 +3504,8 @@ static struct option __record_options[] =3D { &record.switch_output.set, "signal or size[BKMG] or time[smhd]", "Switch output when receiving SIGUSR2 (signal) or cross a size or tim= e threshold", "signal"), - OPT_CALLBACK_SET(0, "switch-output-event", &record.sb_evlist, &record.swi= tch_output_event_set, "switch output event", + OPT_CALLBACK_SET(0, "switch-output-event", &switch_output_parse_events_op= tion_args, + &record.switch_output_event_set, "switch output event", "switch output event selector. use 'perf list' to list available event= s", parse_events_option_new_evlist), OPT_INTEGER(0, "switch-max-files", &record.switch_output.num_files, diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index ffb47b166098..3b25fcab5cd1 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -101,6 +101,10 @@ static void print_counters(struct timespec *ts, int argc, const char **arg= v); =20 static struct evlist *evsel_list; +static struct parse_events_option_args parse_events_option_args =3D { + .evlistp =3D &evsel_list, +}; + static bool all_counters_use_bpf =3D true; =20 static struct target target =3D { @@ -1096,8 +1100,8 @@ static int parse_hybrid_type(const struct option *opt, return -1; } =20 - evlist->hybrid_pmu_name =3D perf_pmu__hybrid_type_to_pmu(str); - if (!evlist->hybrid_pmu_name) { + parse_events_option_args.pmu_filter =3D perf_pmu__hybrid_type_to_pmu(str); + if (!parse_events_option_args.pmu_filter) { fprintf(stderr, "--cputype %s is not supported!\n", str); return -1; } @@ -1108,7 +1112,7 @@ static int parse_hybrid_type(const struct option *opt, static struct option stat_options[] =3D { OPT_BOOLEAN('T', "transaction", &transaction_run, "hardware transaction statistics"), - OPT_CALLBACK('e', "event", &evsel_list, "event", + OPT_CALLBACK('e', "event", &parse_events_option_args, "event", "event selector. use 'perf list' to list available events", parse_events_option), OPT_CALLBACK(0, "filter", &evsel_list, "filter", diff --git a/tools/perf/builtin-top.c b/tools/perf/builtin-top.c index eb5740154bc0..48ee49e95c5e 100644 --- a/tools/perf/builtin-top.c +++ b/tools/perf/builtin-top.c @@ -1440,12 +1440,15 @@ int cmd_top(int argc, const char **argv) .max_stack =3D sysctl__max_stack(), .nr_threads_synthesize =3D UINT_MAX, }; + struct parse_events_option_args parse_events_option_args =3D { + .evlistp =3D &top.evlist, + }; bool branch_call_mode =3D false; struct record_opts *opts =3D &top.record_opts; struct target *target =3D &opts->target; const char *disassembler_style =3D NULL, *objdump_path =3D NULL, *addr2li= ne_path =3D NULL; const struct option options[] =3D { - OPT_CALLBACK('e', "event", &top.evlist, "event", + OPT_CALLBACK('e', "event", &parse_events_option_args, "event", "event selector. use 'perf list' to list available events", parse_events_option), OPT_U64('c', "count", &opts->user_interval, "event period to sample"), diff --git a/tools/perf/builtin-trace.c b/tools/perf/builtin-trace.c index 8ee3a45c3c54..b49d3abb1203 100644 --- a/tools/perf/builtin-trace.c +++ b/tools/perf/builtin-trace.c @@ -4591,8 +4591,11 @@ static int trace__parse_events_option(const struct o= ption *opt, const char *str, err =3D 0; =20 if (lists[0]) { + struct parse_events_option_args parse_events_option_args =3D { + .evlistp =3D &trace->evlist, + }; struct option o =3D { - .value =3D &trace->evlist, + .value =3D &parse_events_option_args, }; err =3D parse_events_option(&o, lists[0], 0); } diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index c3afd0b129bb..0d0c869d2d09 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -1952,7 +1952,8 @@ static int test_event_fake_pmu(const char *str) return -ENOMEM; =20 parse_events_error__init(&err); - ret =3D __parse_events(evlist, str, &err, &perf_pmu__fake, /*warn_if_reor= dered=3D*/true); + ret =3D __parse_events(evlist, str, /*pmu_filter=3D*/NULL, &err, + &perf_pmu__fake, /*warn_if_reordered=3D*/true); if (ret) { pr_debug("failed to parse event '%s', err %d, str '%s'\n", str, ret, err.str); diff --git a/tools/perf/tests/pmu-events.c b/tools/perf/tests/pmu-events.c index a2cde61b1c77..734004f1a37d 100644 --- a/tools/perf/tests/pmu-events.c +++ b/tools/perf/tests/pmu-events.c @@ -776,7 +776,8 @@ static int check_parse_id(const char *id, struct parse_= events_error *error, for (cur =3D strchr(dup, '@') ; cur; cur =3D strchr(++cur, '@')) *cur =3D '/'; =20 - ret =3D __parse_events(evlist, dup, error, fake_pmu, /*warn_if_reordered= =3D*/true); + ret =3D __parse_events(evlist, dup, /*pmu_filter=3D*/NULL, error, fake_pm= u, + /*warn_if_reordered=3D*/true); free(dup); =20 evlist__delete(evlist); diff --git a/tools/perf/util/evlist.h b/tools/perf/util/evlist.h index 46cf402add93..e7e5540cc970 100644 --- a/tools/perf/util/evlist.h +++ b/tools/perf/util/evlist.h @@ -67,7 +67,6 @@ struct evlist { struct evsel *selected; struct events_stats stats; struct perf_env *env; - const char *hybrid_pmu_name; void (*trace_event_sample_raw)(struct evlist *evlist, union perf_event *event, struct perf_sample *sample); diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index e1acb0d23b95..1afc8d7a5838 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -1441,8 +1441,8 @@ static int parse_ids(bool metric_no_merge, struct per= f_pmu *fake_pmu, } pr_debug("Parsing metric events '%s'\n", events.buf); parse_events_error__init(&parse_error); - ret =3D __parse_events(parsed_evlist, events.buf, &parse_error, fake_pmu, - /*warn_if_reordered=3D*/false); + ret =3D __parse_events(parsed_evlist, events.buf, /*pmu_filter=3D*/NULL, + &parse_error, fake_pmu, /*warn_if_reordered=3D*/false); if (ret) { parse_events_error__print(&parse_error, events.buf); goto err_out; diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index 1d8c3cf9c185..d9d964bbc0e2 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -465,8 +465,24 @@ int parse_events__decode_legacy_cache(const char *name= , int pmu_type, __u64 *con return 0; } =20 +/** + * parse_events__filter_pmu - returns false if a wildcard PMU should be + * considered, true if it should be filtered. + */ +bool parse_events__filter_pmu(const struct parse_events_state *parse_state, + const struct perf_pmu *pmu) +{ + if (parse_state->pmu_filter =3D=3D NULL) + return false; + + if (pmu->name =3D=3D NULL) + return true; + + return strcmp(parse_state->pmu_filter, pmu->name) !=3D 0; +} + int parse_events_add_cache(struct list_head *list, int *idx, const char *n= ame, - struct parse_events_error *err, + struct parse_events_state *parse_state, struct list_head *head_config) { struct perf_pmu *pmu =3D NULL; @@ -483,6 +499,9 @@ int parse_events_add_cache(struct list_head *list, int = *idx, const char *name, if (!perf_pmu__supports_legacy_cache(pmu)) continue; =20 + if (parse_events__filter_pmu(parse_state, pmu)) + continue; + memset(&attr, 0, sizeof(attr)); attr.type =3D PERF_TYPE_HW_CACHE; =20 @@ -493,8 +512,7 @@ int parse_events_add_cache(struct list_head *list, int = *idx, const char *name, found_supported =3D true; =20 if (head_config) { - if (config_attr(&attr, head_config, err, - config_term_common)) + if (config_attr(&attr, head_config, parse_state->error, config_term_com= mon)) return -EINVAL; =20 if (get_config_terms(head_config, &config_terms)) @@ -1494,6 +1512,9 @@ int parse_events_add_numeric(struct parse_events_stat= e *parse_state, if (!perf_pmu__supports_wildcard_numeric(pmu)) continue; =20 + if (parse_events__filter_pmu(parse_state, pmu)) + continue; + found_supported =3D true; ret =3D __parse_events_add_numeric(parse_state, list, pmu, pmu->type, config, head_config); @@ -1682,6 +1703,9 @@ int parse_events_multi_pmu_add(struct parse_events_st= ate *parse_state, while ((pmu =3D perf_pmu__scan(pmu)) !=3D NULL) { struct perf_pmu_alias *alias; =20 + if (parse_events__filter_pmu(parse_state, pmu)) + continue; + list_for_each_entry(alias, &pmu->aliases, list) { if (!strcasecmp(alias->name, str)) { parse_events_copy_term_list(head, &orig_head); @@ -2121,7 +2145,7 @@ static bool parse_events__sort_events_and_fix_groups(= struct list_head *list) return idx_changed || num_leaders !=3D orig_num_leaders; } =20 -int __parse_events(struct evlist *evlist, const char *str, +int __parse_events(struct evlist *evlist, const char *str, const char *pmu= _filter, struct parse_events_error *err, struct perf_pmu *fake_pmu, bool warn_if_reordered) { @@ -2132,6 +2156,7 @@ int __parse_events(struct evlist *evlist, const char = *str, .evlist =3D evlist, .stoken =3D PE_START_EVENTS, .fake_pmu =3D fake_pmu, + .pmu_filter =3D pmu_filter, .match_legacy_cache_terms =3D true, }; int ret; @@ -2313,12 +2338,13 @@ void parse_events_error__print(struct parse_events_= error *err, int parse_events_option(const struct option *opt, const char *str, int unset __maybe_unused) { - struct evlist *evlist =3D *(struct evlist **)opt->value; + struct parse_events_option_args *args =3D opt->value; struct parse_events_error err; int ret; =20 parse_events_error__init(&err); - ret =3D parse_events(evlist, str, &err); + ret =3D __parse_events(*args->evlistp, str, args->pmu_filter, &err, + /*fake_pmu=3D*/NULL, /*warn_if_reordered=3D*/true); =20 if (ret) { parse_events_error__print(&err, str); @@ -2331,22 +2357,21 @@ int parse_events_option(const struct option *opt, c= onst char *str, =20 int parse_events_option_new_evlist(const struct option *opt, const char *s= tr, int unset) { - struct evlist **evlistp =3D opt->value; + struct parse_events_option_args *args =3D opt->value; int ret; =20 - if (*evlistp =3D=3D NULL) { - *evlistp =3D evlist__new(); + if (*args->evlistp =3D=3D NULL) { + *args->evlistp =3D evlist__new(); =20 - if (*evlistp =3D=3D NULL) { + if (*args->evlistp =3D=3D NULL) { fprintf(stderr, "Not enough memory to create evlist\n"); return -1; } } - ret =3D parse_events_option(opt, str, unset); if (ret) { - evlist__delete(*evlistp); - *evlistp =3D NULL; + evlist__delete(*args->evlistp); + *args->evlistp =3D NULL; } =20 return ret; diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index 77b8f7efdb94..d4cbda6e946a 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -22,17 +22,24 @@ bool is_event_supported(u8 type, u64 config); =20 const char *event_type(int type); =20 +/* Arguments encoded in opt->value. */ +struct parse_events_option_args { + struct evlist **evlistp; + const char *pmu_filter; +}; int parse_events_option(const struct option *opt, const char *str, int uns= et); int parse_events_option_new_evlist(const struct option *opt, const char *s= tr, int unset); -__attribute__((nonnull(1, 2, 3))) -int __parse_events(struct evlist *evlist, const char *str, struct parse_ev= ents_error *error, - struct perf_pmu *fake_pmu, bool warn_if_reordered); +__attribute__((nonnull(1, 2, 4))) +int __parse_events(struct evlist *evlist, const char *str, const char *pmu= _filter, + struct parse_events_error *error, struct perf_pmu *fake_pmu, + bool warn_if_reordered); =20 __attribute__((nonnull(1, 2, 3))) static inline int parse_events(struct evlist *evlist, const char *str, struct parse_events_error *err) { - return __parse_events(evlist, str, err, /*fake_pmu=3D*/NULL, /*warn_if_re= ordered=3D*/true); + return __parse_events(evlist, str, /*pmu_filter=3D*/NULL, err, /*fake_pmu= =3D*/NULL, + /*warn_if_reordered=3D*/true); } =20 int parse_event(struct evlist *evlist, const char *str); @@ -122,11 +129,15 @@ struct parse_events_state { struct list_head *terms; int stoken; struct perf_pmu *fake_pmu; + /* If non-null, when wildcard matching only match the given PMU. */ + const char *pmu_filter; /* Should PE_LEGACY_NAME tokens be generated for config terms? */ bool match_legacy_cache_terms; bool wild_card_pmus; }; =20 +bool parse_events__filter_pmu(const struct parse_events_state *parse_state, + const struct perf_pmu *pmu); void parse_events__shrink_config_terms(void); int parse_events__is_hardcoded_term(struct parse_events_term *term); int parse_events_term__num(struct parse_events_term **term, @@ -171,7 +182,7 @@ int parse_events_add_tool(struct parse_events_state *pa= rse_state, struct list_head *list, int tool_event); int parse_events_add_cache(struct list_head *list, int *idx, const char *n= ame, - struct parse_events_error *error, + struct parse_events_state *parse_state, struct list_head *head_config); int parse_events__decode_legacy_cache(const char *name, int pmu_type, __u6= 4 *config); int parse_events_add_breakpoint(struct list_head *list, int *idx, diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y index e709508b1d6e..c95877cbd6cf 100644 --- a/tools/perf/util/parse-events.y +++ b/tools/perf/util/parse-events.y @@ -312,6 +312,9 @@ PE_NAME opt_pmu_config while ((pmu =3D perf_pmu__scan(pmu)) !=3D NULL) { char *name =3D pmu->name; =20 + if (parse_events__filter_pmu(parse_state, pmu)) + continue; + if (!strncmp(name, "uncore_", 7) && strncmp($1, "uncore_", 7)) name +=3D 7; @@ -473,13 +476,12 @@ event_legacy_cache: PE_LEGACY_CACHE opt_event_config { struct parse_events_state *parse_state =3D _parse_state; - struct parse_events_error *error =3D parse_state->error; struct list_head *list; int err; =20 list =3D alloc_list(); ABORT_ON(!list); - err =3D parse_events_add_cache(list, &parse_state->idx, $1, error, $2); + err =3D parse_events_add_cache(list, &parse_state->idx, $1, parse_state, = $2); =20 parse_events_terms__delete($2); free($1); --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D676AC19F20 for ; Tue, 2 May 2023 22:44:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230150AbjEBWok (ORCPT ); Tue, 2 May 2023 18:44:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32954 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230247AbjEBWoT (ORCPT ); Tue, 2 May 2023 18:44:19 -0400 Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 47A0F3C19 for ; Tue, 2 May 2023 15:43:41 -0700 (PDT) Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-552cb28adfeso46982197b3.3 for ; Tue, 02 May 2023 15:43:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067369; x=1685659369; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=nd3SY7n/4GmW7g26C/L+L2VFGm0wHwLBiLx1Iujwe/4=; b=yB8bEGP7mbNhr19aLbzpFI0YeixPdCy75g+/nWqphXrruE0wxjHpGMNLBrh1RsPauN v5rz0NfFXRmAWRmrisaj9kJoT9tXvoztVXiQU/oG6rWFagvze2af2mmzw+DTjDthg4lj jSxjh2oRC7lrfyax1SQVfJDvCdQbVPNV4CbiPPvZ0EEuFh0/VDoj4DgXt09PLH6hrJV6 yoQszFNRKufHa1F5CWylIQ/nN8OK3liWkIsicT2gLMyPesiGW5F5XSe+egHwxTVRHu0Q vJQQP6so+ehxGEkNQFvAhUb/CCakkrZcJd6ZGE7G2eXC9Nsh6S2/luV81KhVQtla1nOJ Fybg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067369; x=1685659369; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=nd3SY7n/4GmW7g26C/L+L2VFGm0wHwLBiLx1Iujwe/4=; b=c/BhRj4shcwF7zrGP40mFLZxSrjCYItmi9gqgQhOYaY/57EzmKj/+cNElBu2qq43Ks hD+vwIijPiRLdxtB/iEJSyr0A9lXmqOWYbhZmka2WJhBSQAnw8NpnSHD7PsvrKSMmlBb 4HnTjcQJ8OcjqDv4GPe1OcN9LC6dK20B7adbXSrQw86Jp4ze4yphx+NEwkf/JcnwLn9i EJ/UcJBNBSVS5yIwRWSOYmgz5rZ2kJ5QtMdbDicJAYcq3rs6rfpEQUcz/DhUQomSYMLV 9mC9ZK63+vsaGh/GGT5DfvnmxJwvFP8WM3apPk3WtbLgtQqWa5rUN1xslkqyFqOHjTji FbRA== X-Gm-Message-State: AC+VfDwW2DqJHzGFLnNZ4SIo63DogcTA2jG3cBPkhVdCnp9zVPRy5Ivt NC82IIyIrvKZBknFRI6iMQK3yBBuSvBm X-Google-Smtp-Source: ACHHUZ5WIEuhiDyV14paA0txvMApoSS/nTbiLNIO8J6hKnF/yuV6jFifvjtZ7XcdDGKUFRjlMerq0QXpcbm0 X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a81:b708:0:b0:559:ed25:34cb with SMTP id v8-20020a81b708000000b00559ed2534cbmr6992044ywh.2.1683067369148; Tue, 02 May 2023 15:42:49 -0700 (PDT) Date: Tue, 2 May 2023 15:38:37 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-31-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 30/44] perf stat: Make cputype filter generic From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rather than limit the --cputype argument for "perf list" and "perf stat" to hybrid PMUs of just cpu_atom and cpu_core, allow any PMU. Note, that if cpu_atom isn't mounted but a filter of cpu_atom is requested, then this will now fail. As such a filter would never succeed, no events can come from that unmounted PMU, then this behavior could never have been useful and failing is clearer. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/builtin-list.c | 21 +++++++++++++-------- tools/perf/builtin-stat.c | 12 +++++++----- tools/perf/util/pmu-hybrid.c | 20 -------------------- tools/perf/util/pmu-hybrid.h | 1 - tools/perf/util/pmus.c | 25 ++++++++++++++++++++++++- tools/perf/util/pmus.h | 3 +++ 6 files changed, 47 insertions(+), 35 deletions(-) diff --git a/tools/perf/builtin-list.c b/tools/perf/builtin-list.c index 1f5dbd5f0ba4..c6bd0aa4a56e 100644 --- a/tools/perf/builtin-list.c +++ b/tools/perf/builtin-list.c @@ -11,8 +11,8 @@ #include "builtin.h" =20 #include "util/print-events.h" +#include "util/pmus.h" #include "util/pmu.h" -#include "util/pmu-hybrid.h" #include "util/debug.h" #include "util/metricgroup.h" #include "util/string2.h" @@ -429,7 +429,7 @@ int cmd_list(int argc, const char **argv) .print_event =3D default_print_event, .print_metric =3D default_print_metric, }; - const char *hybrid_name =3D NULL; + const char *cputype =3D NULL; const char *unit_name =3D NULL; bool json =3D false; struct option list_options[] =3D { @@ -443,8 +443,8 @@ int cmd_list(int argc, const char **argv) "Print information on the perf event names and expressions used int= ernally by events."), OPT_BOOLEAN(0, "deprecated", &default_ps.deprecated, "Print deprecated events."), - OPT_STRING(0, "cputype", &hybrid_name, "hybrid cpu type", - "Limit PMU or metric printing to the given hybrid PMU (e.g. core or = atom)."), + OPT_STRING(0, "cputype", &cputype, "cpu type", + "Limit PMU or metric printing to the given PMU (e.g. cpu, core or at= om)."), OPT_STRING(0, "unit", &unit_name, "PMU name", "Limit PMU or metric printing to the specified PMU."), OPT_INCR(0, "debug", &verbose, @@ -484,10 +484,15 @@ int cmd_list(int argc, const char **argv) assert(default_ps.visited_metrics); if (unit_name) default_ps.pmu_glob =3D strdup(unit_name); - else if (hybrid_name) { - default_ps.pmu_glob =3D perf_pmu__hybrid_type_to_pmu(hybrid_name); - if (!default_ps.pmu_glob) - pr_warning("WARNING: hybrid cputype is not supported!\n"); + else if (cputype) { + const struct perf_pmu *pmu =3D perf_pmus__pmu_for_pmu_filter(cputype); + + if (!pmu) { + pr_err("ERROR: cputype is not supported!\n"); + ret =3D -1; + goto out; + } + default_ps.pmu_glob =3D pmu->name; } } print_cb.print_start(ps); diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index 3b25fcab5cd1..06a1d71a49a5 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -44,6 +44,7 @@ #include "util/cgroup.h" #include #include "util/parse-events.h" +#include "util/pmus.h" #include "util/pmu.h" #include "util/event.h" #include "util/evlist.h" @@ -69,7 +70,6 @@ #include "util/pfm.h" #include "util/bpf_counter.h" #include "util/iostat.h" -#include "util/pmu-hybrid.h" #include "util/util.h" #include "asm/bug.h" =20 @@ -1089,10 +1089,11 @@ static int parse_stat_cgroups(const struct option *= opt, return parse_cgroups(opt, str, unset); } =20 -static int parse_hybrid_type(const struct option *opt, +static int parse_cputype(const struct option *opt, const char *str, int unset __maybe_unused) { + const struct perf_pmu *pmu; struct evlist *evlist =3D *(struct evlist **)opt->value; =20 if (!list_empty(&evlist->core.entries)) { @@ -1100,11 +1101,12 @@ static int parse_hybrid_type(const struct option *o= pt, return -1; } =20 - parse_events_option_args.pmu_filter =3D perf_pmu__hybrid_type_to_pmu(str); - if (!parse_events_option_args.pmu_filter) { + pmu =3D perf_pmus__pmu_for_pmu_filter(str); + if (!pmu) { fprintf(stderr, "--cputype %s is not supported!\n", str); return -1; } + parse_events_option_args.pmu_filter =3D pmu->name; =20 return 0; } @@ -1230,7 +1232,7 @@ static struct option stat_options[] =3D { OPT_CALLBACK(0, "cputype", &evsel_list, "hybrid cpu type", "Only enable events on applying cpu with this type " "for hybrid platform (e.g. core or atom)", - parse_hybrid_type), + parse_cputype), #ifdef HAVE_LIBPFM OPT_CALLBACK(0, "pfm-events", &evsel_list, "event", "libpfm4 event selector. use 'perf list' to list available events", diff --git a/tools/perf/util/pmu-hybrid.c b/tools/perf/util/pmu-hybrid.c index 38628805a952..bc4cb0738c35 100644 --- a/tools/perf/util/pmu-hybrid.c +++ b/tools/perf/util/pmu-hybrid.c @@ -50,23 +50,3 @@ bool perf_pmu__is_hybrid(const char *name) { return perf_pmu__find_hybrid_pmu(name) !=3D NULL; } - -char *perf_pmu__hybrid_type_to_pmu(const char *type) -{ - char *pmu_name =3D NULL; - - if (asprintf(&pmu_name, "cpu_%s", type) < 0) - return NULL; - - if (perf_pmu__is_hybrid(pmu_name)) - return pmu_name; - - /* - * pmu may be not scanned, check the sysfs. - */ - if (perf_pmu__hybrid_mounted(pmu_name)) - return pmu_name; - - free(pmu_name); - return NULL; -} diff --git a/tools/perf/util/pmu-hybrid.h b/tools/perf/util/pmu-hybrid.h index 2b186c26a43e..206b94931531 100644 --- a/tools/perf/util/pmu-hybrid.h +++ b/tools/perf/util/pmu-hybrid.h @@ -17,7 +17,6 @@ bool perf_pmu__hybrid_mounted(const char *name); =20 struct perf_pmu *perf_pmu__find_hybrid_pmu(const char *name); bool perf_pmu__is_hybrid(const char *name); -char *perf_pmu__hybrid_type_to_pmu(const char *type); =20 static inline int perf_pmu__hybrid_pmu_num(void) { diff --git a/tools/perf/util/pmus.c b/tools/perf/util/pmus.c index 7f3b93c4d229..140e11f00b29 100644 --- a/tools/perf/util/pmus.c +++ b/tools/perf/util/pmus.c @@ -1,5 +1,28 @@ // SPDX-License-Identifier: GPL-2.0 #include -#include +#include +#include "pmus.h" +#include "pmu.h" =20 LIST_HEAD(pmus); + +const struct perf_pmu *perf_pmus__pmu_for_pmu_filter(const char *str) +{ + struct perf_pmu *pmu =3D NULL; + + while ((pmu =3D perf_pmu__scan(pmu)) !=3D NULL) { + if (!strcmp(pmu->name, str)) + return pmu; + /* Ignore "uncore_" prefix. */ + if (!strncmp(pmu->name, "uncore_", 7)) { + if (!strcmp(pmu->name + 7, str)) + return pmu; + } + /* Ignore "cpu_" prefix on Intel hybrid PMUs. */ + if (!strncmp(pmu->name, "cpu_", 4)) { + if (!strcmp(pmu->name + 4, str)) + return pmu; + } + } + return NULL; +} diff --git a/tools/perf/util/pmus.h b/tools/perf/util/pmus.h index 5ec12007eb5c..d475e2960c10 100644 --- a/tools/perf/util/pmus.h +++ b/tools/perf/util/pmus.h @@ -3,7 +3,10 @@ #define __PMUS_H =20 extern struct list_head pmus; +struct perf_pmu; =20 #define perf_pmus__for_each_pmu(pmu) list_for_each_entry(pmu, &pmus, list) =20 +const struct perf_pmu *perf_pmus__pmu_for_pmu_filter(const char *str); + #endif /* __PMUS_H */ --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D2FBC77B75 for ; Tue, 2 May 2023 22:45:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230352AbjEBWp1 (ORCPT ); Tue, 2 May 2023 18:45:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33216 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230125AbjEBWpM (ORCPT ); Tue, 2 May 2023 18:45:12 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A92BE1FFB for ; Tue, 2 May 2023 15:44:48 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-b8f6bef3d4aso9047878276.0 for ; Tue, 02 May 2023 15:44:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067375; x=1685659375; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=uX2HSmx6kEz7AF/sikU4sT7+5OfRWtA69N2zyZbBkbM=; b=b4ljozXGX0AGJpe8wzIsr+iwUusd1XtgfvWYQSPq+erkm5D4Em6RBqk9GA04hrEJ9R mxdIyAN9H2huOAksfR9s+QEEDi4h3Tdz6w9IW4I+3xRng4V4yth2X6C5GLc6JAEi8fQ6 sMmFi8L99/tGgsPl1uZC+AidH8jKjSQzYfQiTReYzH4d3JgnxAJfVtzCGYO4atXao1lb y0kN5/t6Gu+D4JKBIwUd9p+haXRXOf9LAzukTEkRQ7cRjZ8tUy1ZQWmyylcK4JXQ8Bdk gZMZtXw00CdRgDfNvk9UzbmjWbK5TpnV3hhZHPdVghdIvpfUTE5gEW89LSyBHFQ9uAzD 2AMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067375; x=1685659375; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=uX2HSmx6kEz7AF/sikU4sT7+5OfRWtA69N2zyZbBkbM=; b=Z9nPaFZnQSDAV8t1WuA9u3hNTEZuIa7CApBh2Mw8qxH2jwDsvtJqfSr1xZ1iFIrShd VfsqGPfMDAWO+YcVrfMaPOFUfUYEtSl0Y2goDG1ygX1jKb1JeWwvdzwiKi2e38GqhyNr rT8Q/5GQo1vPpTi68G8KPRm8z4WZ5BBjjtlXv6dciFEpfdVX2F8/PLAHxZDz/AsSiPA9 wmxmc7RduFVWxavlVIZWlg7PQWpupU4HFU4DwhJMJdSBncSf+CzGyD7HMB84eOvROPtH WmRGtoW3yx+sE80tfuS9RJklwU5z/fD85jUoeS2o3+er6wrhalM/SQtwMUr54dHIR/2j 0ZvA== X-Gm-Message-State: AC+VfDyurzwPfdXFRXQByEnhKm1lRO1ilfHUsIETXXanZuuEqsWBTyvi TktRkUuyEkaszlRb/RT1fgmME/9U7dCI X-Google-Smtp-Source: ACHHUZ5M9/CQ9k1r5X88Vqj7nyogkOweBJ6MjlyJszgJ4oyYuvz+nM/zMhTKFX0AUFD22vbQmtQoejLWC6Mu X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a05:6902:1081:b0:b9d:d5dc:5971 with SMTP id v1-20020a056902108100b00b9dd5dc5971mr6040545ybu.2.1683067375581; Tue, 02 May 2023 15:42:55 -0700 (PDT) Date: Tue, 2 May 2023 15:38:38 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-32-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 31/44] perf test: Add cputype testing to perf stat From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Check a bogus PMU fails and that a known PMU succeeds. Limit to PMUs known cpu, cpu_atom and armv8_pmuv3_0 ones. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/tests/shell/stat.sh | 44 ++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/tools/perf/tests/shell/stat.sh b/tools/perf/tests/shell/stat.sh index 2c1d3f704995..fe1283ca39d1 100755 --- a/tools/perf/tests/shell/stat.sh +++ b/tools/perf/tests/shell/stat.sh @@ -91,9 +91,53 @@ test_topdown_weak_groups() { echo "Topdown weak groups test [Success]" } =20 +test_cputype() { + # Test --cputype argument. + echo "cputype test" + + # Bogus PMU should fail. + if perf stat --cputype=3D"123" -e instructions true > /dev/null 2>&1 + then + echo "cputype test [Bogus PMU didn't fail]" + err=3D1 + return + fi + + # Find a known PMU for cputype. + pmu=3D"" + for i in cpu cpu_atom armv8_pmuv3_0 + do + if test -d "/sys/devices/$i" + then + pmu=3D"$i" + break + fi + if perf stat -e "$i/instructions/" true > /dev/null 2>&1 + then + pmu=3D"$i" + break + fi + done + if test "x$pmu" =3D "x" + then + echo "cputype test [Skipped known PMU not found]" + return + fi + + # Test running with cputype produces output. + if ! perf stat --cputype=3D"$pmu" -e instructions true 2>&1 | grep -E -q= "instructions" + then + echo "cputype test [Failed count missed with given filter]" + err=3D1 + return + fi + echo "cputype test [Success]" +} + test_default_stat test_stat_record_report test_stat_repeat_weak_groups test_topdown_groups test_topdown_weak_groups +test_cputype exit $err --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAC90C77B75 for ; Tue, 2 May 2023 22:44:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230290AbjEBWo6 (ORCPT ); Tue, 2 May 2023 18:44:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59632 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230337AbjEBWoq (ORCPT ); Tue, 2 May 2023 18:44:46 -0400 Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D55273A9B for ; Tue, 2 May 2023 15:44:08 -0700 (PDT) Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-55a7d1f6914so42354487b3.1 for ; Tue, 02 May 2023 15:44:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067382; x=1685659382; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=AxzMWV72g/5LziCMw5rVJi/60zDX6vPO62VzJj3WeeM=; b=L4zp+ojO3/dsaN9Zl2hNxzuW4CpOJRMKBu7ZFqlXtU4AXmrpeGxoBzosaxxnP0owgq S7Pzz3cEGPNiSSh7xDRORyKwPBBz7pnU8jvUKzCPIPntZydSl59yxTmzEXNusJFXsE6J O+SIXNQUN3LLVXrftvbRVJcXfnmCCBtIKBPPeMeZ8HxIFYqeAm+tsOYZFdZxA9PCYjwX K35WTi5yAuJXI1yj4CALnlgid2vtfEaME6gGM4/ec2ZBdYIki2vWOlw0t+eRGY/jPpod vOd5OeUJ1JB7fdDzn8fJAGalObHZ6oMZ4ULnEs7DgLvWQXNom1FARATtPdJDiPMEbjxm 9WLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067382; x=1685659382; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=AxzMWV72g/5LziCMw5rVJi/60zDX6vPO62VzJj3WeeM=; b=HjYo3EC7JMlcTbg7uuHIWbDCud+b939DE96xr6TembUy99wkFV6aFpfjPI4Z5ZdQ/b PfvpnYqjsndUvlJfOYXcqov2b8RF7md6GtYCBIiZq/rOWPSmqM/W61zQkPFRsbOySJCJ DUhTUbPTR+S39P5vWjsfypZAFMYyJPKiW1i9DLeyNChJHj1qkZzyq8InQqsPbyPvbduO SybwNcC1kN8yFdNn3f0XEVm35fG0B+X5+Qjo19IUMH8+mYbm+YMfaH6EgT9OdQPsGPSl 4EPlpV+FhA9a/RmX01V7MWJPdeQmPGhTW2vxH7jog33Af6UG0Phza7U/I3AGrUp1X0XH 1Z3Q== X-Gm-Message-State: AC+VfDxqyO1uLFRDfihburzKcq6Y6O9h2UzshQfpUvzE9JOQhSQ3B9S3 kv9Lf4xC6DlPHtQa9qe4bEu6/yocpzQj X-Google-Smtp-Source: ACHHUZ66soYnECQZp4BbCJ1RSj4aYgqWSOEyD2imVPLgT2TYJ0Y8Te3meALarRq8sIBkqYNumKYmNUWQvSJ/ X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a81:a747:0:b0:55a:8fe8:4fc8 with SMTP id e68-20020a81a747000000b0055a8fe84fc8mr2609297ywh.3.1683067381833; Tue, 02 May 2023 15:43:01 -0700 (PDT) Date: Tue, 2 May 2023 15:38:39 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-33-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 32/44] perf test: Fix parse-events tests for >1 core PMU From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove assumptions of just 1 core PMU. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/tests/parse-events.c | 177 +++++++++++++++++++------------- 1 file changed, 105 insertions(+), 72 deletions(-) diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index 0d0c869d2d09..71c77d9d2744 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -35,6 +35,11 @@ static bool test_config(const struct evsel *evsel, __u64= expected_config) return config =3D=3D expected_config; } =20 +static bool test_perf_config(const struct perf_evsel *evsel, __u64 expecte= d_config) +{ + return (evsel->attr.config & PERF_HW_EVENT_MASK) =3D=3D expected_config; +} + #ifdef HAVE_LIBTRACEEVENT =20 #if defined(__s390x__) @@ -97,11 +102,27 @@ static int test__checkevent_tracepoint_multi(struct ev= list *evlist) =20 static int test__checkevent_raw(struct evlist *evlist) { - struct evsel *evsel =3D evlist__first(evlist); + struct perf_evsel *evsel; + bool raw_type_match =3D false; =20 - TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); + TEST_ASSERT_VAL("wrong number of entries", 0 !=3D evlist->core.nr_entries= ); + + perf_evlist__for_each_evsel(&evlist->core, evsel) { + struct perf_pmu *pmu; + bool type_matched =3D false; + + TEST_ASSERT_VAL("wrong config", test_perf_config(evsel, 0x1a)); + perf_pmus__for_each_pmu(pmu) { + if (pmu->type =3D=3D evsel->attr.type) { + TEST_ASSERT_VAL("PMU type expected once", !type_matched); + type_matched =3D true; + if (pmu->type =3D=3D PERF_TYPE_RAW) + raw_type_match =3D true; + } + } + TEST_ASSERT_VAL("No PMU found for type", type_matched); + } + TEST_ASSERT_VAL("Raw PMU not matched", raw_type_match); return TEST_OK; } =20 @@ -117,31 +138,35 @@ static int test__checkevent_numeric(struct evlist *ev= list) =20 static int test__checkevent_symbolic_name(struct evlist *evlist) { - struct evsel *evsel =3D evlist__first(evlist); + struct perf_evsel *evsel; =20 - TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_INSTRUCT= IONS)); + TEST_ASSERT_VAL("wrong number of entries", 0 !=3D evlist->core.nr_entries= ); + + perf_evlist__for_each_evsel(&evlist->core, evsel) { + TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->attr.type= ); + TEST_ASSERT_VAL("wrong config", + test_perf_config(evsel, PERF_COUNT_HW_INSTRUCTIONS)); + } return TEST_OK; } =20 static int test__checkevent_symbolic_name_config(struct evlist *evlist) { - struct evsel *evsel =3D evlist__first(evlist); + struct perf_evsel *evsel; =20 - TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); - /* - * The period value gets configured within evlist__config, - * while this test executes only parse events method. - */ - TEST_ASSERT_VAL("wrong period", - 0 =3D=3D evsel->core.attr.sample_period); - TEST_ASSERT_VAL("wrong config1", - 0 =3D=3D evsel->core.attr.config1); - TEST_ASSERT_VAL("wrong config2", - 1 =3D=3D evsel->core.attr.config2); + TEST_ASSERT_VAL("wrong number of entries", 0 !=3D evlist->core.nr_entries= ); + + perf_evlist__for_each_evsel(&evlist->core, evsel) { + TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->attr.type= ); + TEST_ASSERT_VAL("wrong config", test_perf_config(evsel, PERF_COUNT_HW_CP= U_CYCLES)); + /* + * The period value gets configured within evlist__config, + * while this test executes only parse events method. + */ + TEST_ASSERT_VAL("wrong period", 0 =3D=3D evsel->attr.sample_period); + TEST_ASSERT_VAL("wrong config1", 0 =3D=3D evsel->attr.config1); + TEST_ASSERT_VAL("wrong config2", 1 =3D=3D evsel->attr.config2); + } return TEST_OK; } =20 @@ -157,11 +182,14 @@ static int test__checkevent_symbolic_alias(struct evl= ist *evlist) =20 static int test__checkevent_genhw(struct evlist *evlist) { - struct evsel *evsel =3D evlist__first(evlist); + struct perf_evsel *evsel; =20 - TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_HW_CACHE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 1 << 16)); + TEST_ASSERT_VAL("wrong number of entries", 0 !=3D evlist->core.nr_entries= ); + + perf_evlist__for_each_entry(&evlist->core, evsel) { + TEST_ASSERT_VAL("wrong type", PERF_TYPE_HW_CACHE =3D=3D evsel->attr.type= ); + TEST_ASSERT_VAL("wrong config", test_perf_config(evsel, 1 << 16)); + } return TEST_OK; } =20 @@ -253,17 +281,15 @@ static int test__checkevent_tracepoint_modifier(struc= t evlist *evlist) static int test__checkevent_tracepoint_multi_modifier(struct evlist *evlist) { - struct evsel *evsel; + struct perf_evsel *evsel; =20 TEST_ASSERT_VAL("wrong number of entries", evlist->core.nr_entries > 1); =20 - evlist__for_each_entry(evlist, evsel) { - TEST_ASSERT_VAL("wrong exclude_user", - !evsel->core.attr.exclude_user); - TEST_ASSERT_VAL("wrong exclude_kernel", - evsel->core.attr.exclude_kernel); - TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); - TEST_ASSERT_VAL("wrong precise_ip", !evsel->core.attr.precise_ip); + perf_evlist__for_each_entry(&evlist->core, evsel) { + TEST_ASSERT_VAL("wrong exclude_user", !evsel->attr.exclude_user); + TEST_ASSERT_VAL("wrong exclude_kernel", evsel->attr.exclude_kernel); + TEST_ASSERT_VAL("wrong exclude_hv", evsel->attr.exclude_hv); + TEST_ASSERT_VAL("wrong precise_ip", !evsel->attr.precise_ip); } =20 return test__checkevent_tracepoint_multi(evlist); @@ -272,25 +298,27 @@ test__checkevent_tracepoint_multi_modifier(struct evl= ist *evlist) =20 static int test__checkevent_raw_modifier(struct evlist *evlist) { - struct evsel *evsel =3D evlist__first(evlist); - - TEST_ASSERT_VAL("wrong exclude_user", evsel->core.attr.exclude_user); - TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); - TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); - TEST_ASSERT_VAL("wrong precise_ip", evsel->core.attr.precise_ip); + struct perf_evsel *evsel; =20 + perf_evlist__for_each_entry(&evlist->core, evsel) { + TEST_ASSERT_VAL("wrong exclude_user", evsel->attr.exclude_user); + TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->attr.exclude_kernel); + TEST_ASSERT_VAL("wrong exclude_hv", evsel->attr.exclude_hv); + TEST_ASSERT_VAL("wrong precise_ip", evsel->attr.precise_ip); + } return test__checkevent_raw(evlist); } =20 static int test__checkevent_numeric_modifier(struct evlist *evlist) { - struct evsel *evsel =3D evlist__first(evlist); - - TEST_ASSERT_VAL("wrong exclude_user", evsel->core.attr.exclude_user); - TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); - TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); - TEST_ASSERT_VAL("wrong precise_ip", evsel->core.attr.precise_ip); + struct perf_evsel *evsel; =20 + perf_evlist__for_each_entry(&evlist->core, evsel) { + TEST_ASSERT_VAL("wrong exclude_user", evsel->attr.exclude_user); + TEST_ASSERT_VAL("wrong exclude_kernel", evsel->attr.exclude_kernel); + TEST_ASSERT_VAL("wrong exclude_hv", !evsel->attr.exclude_hv); + TEST_ASSERT_VAL("wrong precise_ip", evsel->attr.precise_ip); + } return test__checkevent_numeric(evlist); } =20 @@ -308,21 +336,23 @@ static int test__checkevent_symbolic_name_modifier(st= ruct evlist *evlist) =20 static int test__checkevent_exclude_host_modifier(struct evlist *evlist) { - struct evsel *evsel =3D evlist__first(evlist); - - TEST_ASSERT_VAL("wrong exclude guest", !evsel->core.attr.exclude_guest); - TEST_ASSERT_VAL("wrong exclude host", evsel->core.attr.exclude_host); + struct perf_evsel *evsel; =20 + perf_evlist__for_each_entry(&evlist->core, evsel) { + TEST_ASSERT_VAL("wrong exclude guest", !evsel->attr.exclude_guest); + TEST_ASSERT_VAL("wrong exclude host", evsel->attr.exclude_host); + } return test__checkevent_symbolic_name(evlist); } =20 static int test__checkevent_exclude_guest_modifier(struct evlist *evlist) { - struct evsel *evsel =3D evlist__first(evlist); - - TEST_ASSERT_VAL("wrong exclude guest", evsel->core.attr.exclude_guest); - TEST_ASSERT_VAL("wrong exclude host", !evsel->core.attr.exclude_host); + struct perf_evsel *evsel; =20 + perf_evlist__for_each_entry(&evlist->core, evsel) { + TEST_ASSERT_VAL("wrong exclude guest", evsel->attr.exclude_guest); + TEST_ASSERT_VAL("wrong exclude host", !evsel->attr.exclude_host); + } return test__checkevent_symbolic_name(evlist); } =20 @@ -340,13 +370,14 @@ static int test__checkevent_symbolic_alias_modifier(s= truct evlist *evlist) =20 static int test__checkevent_genhw_modifier(struct evlist *evlist) { - struct evsel *evsel =3D evlist__first(evlist); - - TEST_ASSERT_VAL("wrong exclude_user", evsel->core.attr.exclude_user); - TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); - TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); - TEST_ASSERT_VAL("wrong precise_ip", evsel->core.attr.precise_ip); + struct perf_evsel *evsel; =20 + perf_evlist__for_each_entry(&evlist->core, evsel) { + TEST_ASSERT_VAL("wrong exclude_user", evsel->attr.exclude_user); + TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->attr.exclude_kernel); + TEST_ASSERT_VAL("wrong exclude_hv", evsel->attr.exclude_hv); + TEST_ASSERT_VAL("wrong precise_ip", evsel->attr.precise_ip); + } return test__checkevent_genhw(evlist); } =20 @@ -476,21 +507,23 @@ static int test__checkevent_list(struct evlist *evlis= t) { struct evsel *evsel =3D evlist__first(evlist); =20 - TEST_ASSERT_VAL("wrong number of entries", 3 =3D=3D evlist->core.nr_entri= es); + TEST_ASSERT_VAL("wrong number of entries", 3 <=3D evlist->core.nr_entries= ); =20 /* r1 */ - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 1)); - TEST_ASSERT_VAL("wrong config1", 0 =3D=3D evsel->core.attr.config1); - TEST_ASSERT_VAL("wrong config2", 0 =3D=3D evsel->core.attr.config2); - TEST_ASSERT_VAL("wrong config3", 0 =3D=3D evsel->core.attr.config3); - TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); - TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); - TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); - TEST_ASSERT_VAL("wrong precise_ip", !evsel->core.attr.precise_ip); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_TRACEPOINT !=3D evsel->core.attr.= type); + while (evsel->core.attr.type !=3D PERF_TYPE_TRACEPOINT) { + TEST_ASSERT_VAL("wrong config", test_config(evsel, 1)); + TEST_ASSERT_VAL("wrong config1", 0 =3D=3D evsel->core.attr.config1); + TEST_ASSERT_VAL("wrong config2", 0 =3D=3D evsel->core.attr.config2); + TEST_ASSERT_VAL("wrong config3", 0 =3D=3D evsel->core.attr.config3); + TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); + TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel= ); + TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); + TEST_ASSERT_VAL("wrong precise_ip", !evsel->core.attr.precise_ip); + evsel =3D evsel__next(evsel); + } =20 /* syscalls:sys_enter_openat:k */ - evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_TRACEPOINT =3D=3D evsel->core.att= r.type); TEST_ASSERT_VAL("wrong sample_type", PERF_TP_SAMPLE_TYPE =3D=3D evsel->core.attr.sample_type); @@ -1930,7 +1963,7 @@ static int test_event(const struct evlist_test *e) e->name, ret, err.str); parse_events_error__print(&err, e->name); ret =3D TEST_FAIL; - if (strstr(err.str, "can't access trace events")) + if (err.str && strstr(err.str, "can't access trace events")) ret =3D TEST_SKIP; } else { ret =3D e->check(evlist); --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42595C77B75 for ; Tue, 2 May 2023 22:50:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229947AbjEBWuS (ORCPT ); Tue, 2 May 2023 18:50:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40238 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231149AbjEBWuO (ORCPT ); Tue, 2 May 2023 18:50:14 -0400 Received: from mail-yb1-f202.google.com (mail-yb1-f202.google.com [209.85.219.202]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9AA8035BF for ; Tue, 2 May 2023 15:49:34 -0700 (PDT) Received: by mail-yb1-f202.google.com with SMTP id 3f1490d57ef6-b9a6f15287eso567697276.1 for ; Tue, 02 May 2023 15:49:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067388; x=1685659388; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=1Qu3vikmEfUxXQQE9RxnSDWQf7NIfaIZbF4t0DF1X4A=; b=gLuGfKSjIcfzxIZ/EcXqW6O2HCVW1PMrGzr/9v8ETQgp9/FzFj8eX6ZMAg/QGUHdMr t2v0Zk8aSgZnhv6/2eshzAjOavACzt4vA8I1r9APQXT7VOxHDD8ArE0FOMriXqSij0or 0bXhmj1B5pF1ZgGtfkRpH2sD9+8qezz3kLW/MeZ2PnNNBidz3Ao4hQ8QVvyeiUUWq91k mWEz7qIM8Ogu2iFq61sOGnlay9+kFU4XGC/dutSFRyQLcA4c0G3BEvyNJo2gmMJ7O/th hBvZfa9E3xvlGumZS0WrNtx4s+HF8ZtYCnrE2tD2X9QcIGn/7xR7wWmyBIYNwVj0tVCk G8tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067388; x=1685659388; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=1Qu3vikmEfUxXQQE9RxnSDWQf7NIfaIZbF4t0DF1X4A=; b=jVnnleAC/HGWwHklzmmpG2Min1IkflWxesdUDUNNR0wdtvuiuybuighFZDFQ7/dqCZ b23+Uss8O8szsqgHcg3M3UkDIR2HM8DzKG4wUvjoqF5GOP4lQvgr+Kpm7/Zyj2s93xzT xEa//F/+Qt4s/ahUcAi9ZWy2ms0dADjiUtw+a/CprRC1ATg4EWE3WHkwnHPckcOfQj8W zoXaF5MRLEkeezOmO4v0GzjLw+dbVM+iN3aiC8RByys7ztl05ThQGvhcsk8ZiJ5Ntgjc rnQ36kZkHz/XIfOUnHutEHPwP5kvN/HPQlw1W+82HgXrn+TJ56yZxa2r58mVvzXXOA9W /jRQ== X-Gm-Message-State: AC+VfDxA/pUkGo0yP22DEGTgTKKwounYA9VhGAqZ2KC5lWbx06C1bTCK +Ez7+rFU7mrnIdyqRbjsZnfIuN9O/KWH X-Google-Smtp-Source: ACHHUZ7rlUYpI19g9WaU92TdQeV/HRvQ57YgpN+qLwckZgQ0TtrCnbhuMqtbjWFoj/xPzcIy0ROppz7QLIaf X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a81:4504:0:b0:557:616:7d63 with SMTP id s4-20020a814504000000b0055706167d63mr105335ywa.1.1683067388769; Tue, 02 May 2023 15:43:08 -0700 (PDT) Date: Tue, 2 May 2023 15:38:40 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-34-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 33/44] perf parse-events: Support hardware events as terms From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" An event like "cpu/instructions/" typically parses due to there being a sysfs event called instructions. On hybrid recursive parsing means that the hardware event is encoded in the attribute, with the PMU being placed in the high bits of the config: ''' $ perf stat -vv -e 'cpu_core/cycles/' true ... Tested-by: Kan Liang ------------------------------------------------------------ perf_event_attr: size 136 config 0x400000000 sample_type IDENTIFIER read_format TOTAL_TIME_ENABLED|TOTAL_TIME_RUNNING disabled 1 inherit 1 enable_on_exec 1 exclude_guest 1 ------------------------------------------------------------ ''' Make this behavior the default by adding a new term type and token for hardware events. The token gathers both the numeric config and the parsed name, so that if the token appears like "cycles/name=3Dcycles/" then the token can be handled like a name. The numeric value isn't sufficient to distinguish say "cpu-cycles" from "cycles". Extend the parse-events test so that all current non-PMU hardware parsing tests, also test with the PMU cpu - more than half the change. Signed-off-by: Ian Rogers --- tools/perf/tests/parse-events.c | 126 ++++++++++++++++++++++++++++++++ tools/perf/util/parse-events.c | 37 +++------- tools/perf/util/parse-events.h | 3 +- tools/perf/util/parse-events.l | 20 +++++ tools/perf/util/parse-events.y | 34 +++++++-- 5 files changed, 187 insertions(+), 33 deletions(-) diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index 71c77d9d2744..9ca8e19bda00 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -1926,6 +1926,132 @@ static const struct evlist_test test__events_pmu[] = =3D { .check =3D test__checkevent_config_cache, /* 8 */ }, + { + .name =3D "cpu/instructions/", + .valid =3D test__pmu_cpu_valid, + .check =3D test__checkevent_symbolic_name, + /* 9 */ + }, + { + .name =3D "cpu/cycles,period=3D100000,config2/", + .valid =3D test__pmu_cpu_valid, + .check =3D test__checkevent_symbolic_name_config, + /* 0 */ + }, + { + .name =3D "cpu/instructions/h", + .valid =3D test__pmu_cpu_valid, + .check =3D test__checkevent_symbolic_name_modifier, + /* 1 */ + }, + { + .name =3D "cpu/instructions/G", + .valid =3D test__pmu_cpu_valid, + .check =3D test__checkevent_exclude_host_modifier, + /* 2 */ + }, + { + .name =3D "cpu/instructions/H", + .valid =3D test__pmu_cpu_valid, + .check =3D test__checkevent_exclude_guest_modifier, + /* 3 */ + }, + { + .name =3D "{cpu/instructions/k,cpu/cycles/upp}", + .valid =3D test__pmu_cpu_valid, + .check =3D test__group1, + /* 4 */ + }, + { + .name =3D "{cpu/cycles/u,cpu/instructions/kp}:p", + .valid =3D test__pmu_cpu_valid, + .check =3D test__group4, + /* 5 */ + }, + { + .name =3D "{cpu/cycles/,cpu/cache-misses/G}:H", + .valid =3D test__pmu_cpu_valid, + .check =3D test__group_gh1, + /* 6 */ + }, + { + .name =3D "{cpu/cycles/,cpu/cache-misses/H}:G", + .valid =3D test__pmu_cpu_valid, + .check =3D test__group_gh2, + /* 7 */ + }, + { + .name =3D "{cpu/cycles/G,cpu/cache-misses/H}:u", + .valid =3D test__pmu_cpu_valid, + .check =3D test__group_gh3, + /* 8 */ + }, + { + .name =3D "{cpu/cycles/G,cpu/cache-misses/H}:uG", + .valid =3D test__pmu_cpu_valid, + .check =3D test__group_gh4, + /* 9 */ + }, + { + .name =3D "{cpu/cycles/,cpu/cache-misses/,cpu/branch-misses/}:S", + .valid =3D test__pmu_cpu_valid, + .check =3D test__leader_sample1, + /* 0 */ + }, + { + .name =3D "{cpu/instructions/,cpu/branch-misses/}:Su", + .valid =3D test__pmu_cpu_valid, + .check =3D test__leader_sample2, + /* 1 */ + }, + { + .name =3D "cpu/instructions/uDp", + .valid =3D test__pmu_cpu_valid, + .check =3D test__checkevent_pinned_modifier, + /* 2 */ + }, + { + .name =3D "{cpu/cycles/,cpu/cache-misses/,cpu/branch-misses/}:D", + .valid =3D test__pmu_cpu_valid, + .check =3D test__pinned_group, + /* 3 */ + }, + { + .name =3D "cpu/instructions/I", + .valid =3D test__pmu_cpu_valid, + .check =3D test__checkevent_exclude_idle_modifier, + /* 4 */ + }, + { + .name =3D "cpu/instructions/kIG", + .valid =3D test__pmu_cpu_valid, + .check =3D test__checkevent_exclude_idle_modifier_1, + /* 5 */ + }, + { + .name =3D "cpu/cycles/u", + .valid =3D test__pmu_cpu_valid, + .check =3D test__sym_event_slash, + /* 6 */ + }, + { + .name =3D "cpu/cycles/k", + .valid =3D test__pmu_cpu_valid, + .check =3D test__sym_event_dc, + /* 7 */ + }, + { + .name =3D "cpu/instructions/uep", + .valid =3D test__pmu_cpu_valid, + .check =3D test__checkevent_exclusive_modifier, + /* 8 */ + }, + { + .name =3D "{cpu/cycles/,cpu/cache-misses/,cpu/branch-misses/}:e", + .valid =3D test__pmu_cpu_valid, + .check =3D test__exclusive_group, + /* 9 */ + }, }; =20 struct terms_test { diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index d9d964bbc0e2..dea27bc0b376 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -1052,6 +1052,7 @@ static const char *config_term_names[__PARSE_EVENTS__= TERM_TYPE_NR] =3D { [PARSE_EVENTS__TERM_TYPE_METRIC_ID] =3D "metric-id", [PARSE_EVENTS__TERM_TYPE_RAW] =3D "raw", [PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE] =3D "legacy-cache", + [PARSE_EVENTS__TERM_TYPE_HARDWARE] =3D "hardware", }; =20 static bool config_term_shrinked; @@ -1239,6 +1240,17 @@ static int config_term_pmu(struct perf_event_attr *a= ttr, } else term->type_term =3D PARSE_EVENTS__TERM_TYPE_USER; } + if (term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_HARDWARE) { + const struct perf_pmu *pmu =3D perf_pmu__find_by_type(attr->type); + + if (!pmu) { + pr_debug("Failed to find PMU for type %d", attr->type); + return -EINVAL; + } + attr->type =3D PERF_TYPE_HARDWARE; + attr->config =3D ((__u64)pmu->type << PERF_PMU_TYPE_SHIFT) | term->val.n= um; + return 0; + } if (term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_USER || term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_DRV_CFG) { /* @@ -2569,31 +2581,6 @@ int parse_events_term__str(struct parse_events_term = **term, return new_term(term, &temp, str, 0); } =20 -int parse_events_term__sym_hw(struct parse_events_term **term, - char *config, unsigned idx) -{ - struct event_symbol *sym; - char *str; - struct parse_events_term temp =3D { - .type_val =3D PARSE_EVENTS__TERM_TYPE_STR, - .type_term =3D PARSE_EVENTS__TERM_TYPE_USER, - .config =3D config, - }; - - if (!temp.config) { - temp.config =3D strdup("event"); - if (!temp.config) - return -ENOMEM; - } - BUG_ON(idx >=3D PERF_COUNT_HW_MAX); - sym =3D &event_symbols_hw[idx]; - - str =3D strdup(sym->symbol); - if (!str) - return -ENOMEM; - return new_term(term, &temp, str, 0); -} - int parse_events_term__clone(struct parse_events_term **new, struct parse_events_term *term) { diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index d4cbda6e946a..7fe80b416143 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -79,6 +79,7 @@ enum { PARSE_EVENTS__TERM_TYPE_METRIC_ID, PARSE_EVENTS__TERM_TYPE_RAW, PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE, + PARSE_EVENTS__TERM_TYPE_HARDWARE, __PARSE_EVENTS__TERM_TYPE_NR, }; =20 @@ -147,8 +148,6 @@ int parse_events_term__num(struct parse_events_term **t= erm, int parse_events_term__str(struct parse_events_term **term, int type_term, char *config, char *str, void *loc_term, void *loc_val); -int parse_events_term__sym_hw(struct parse_events_term **term, - char *config, unsigned idx); int parse_events_term__clone(struct parse_events_term **new, struct parse_events_term *term); void parse_events_term__delete(struct parse_events_term *term); diff --git a/tools/perf/util/parse-events.l b/tools/perf/util/parse-events.l index abe0ce681d29..6deb70c25984 100644 --- a/tools/perf/util/parse-events.l +++ b/tools/perf/util/parse-events.l @@ -149,6 +149,16 @@ static int term(yyscan_t scanner, int type) return PE_TERM; } =20 +static int hw_term(yyscan_t scanner, int config) +{ + YYSTYPE *yylval =3D parse_events_get_lval(scanner); + char *text =3D parse_events_get_text(scanner); + + yylval->hardware_term.str =3D strdup(text); + yylval->hardware_term.num =3D PERF_TYPE_HARDWARE + config; + return PE_TERM_HW; +} + #define YY_USER_ACTION \ do { \ yylloc->last_column =3D yylloc->first_column; \ @@ -269,6 +279,16 @@ percore { return term(yyscanner, PARSE_EVENTS__TERM_= TYPE_PERCORE); } aux-output { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_AUX_OUTPUT); } aux-sample-size { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_AUX_SAMP= LE_SIZE); } metric-id { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_METRIC_ID); } +cpu-cycles|cycles { return hw_term(yyscanner, PERF_COUNT_HW_CPU_CYCLES)= ; } +stalled-cycles-frontend|idle-cycles-frontend { return hw_term(yyscanner, P= ERF_COUNT_HW_STALLED_CYCLES_FRONTEND); } +stalled-cycles-backend|idle-cycles-backend { return hw_term(yyscanner, PER= F_COUNT_HW_STALLED_CYCLES_BACKEND); } +instructions { return hw_term(yyscanner, PERF_COUNT_HW_INSTRUCTIONS); } +cache-references { return hw_term(yyscanner, PERF_COUNT_HW_CACHE_REFERE= NCES); } +cache-misses { return hw_term(yyscanner, PERF_COUNT_HW_CACHE_MISSES); } +branch-instructions|branches { return hw_term(yyscanner, PERF_COUNT_HW_B= RANCH_INSTRUCTIONS); } +branch-misses { return hw_term(yyscanner, PERF_COUNT_HW_BRANCH_MISSES)= ; } +bus-cycles { return hw_term(yyscanner, PERF_COUNT_HW_BUS_CYCLES); } +ref-cycles { return hw_term(yyscanner, PERF_COUNT_HW_REF_CPU_CYCLES); } r{num_raw_hex} { return str(yyscanner, PE_RAW); } r0x{num_raw_hex} { return str(yyscanner, PE_RAW); } , { return ','; } diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y index c95877cbd6cf..819a5123fd77 100644 --- a/tools/perf/util/parse-events.y +++ b/tools/perf/util/parse-events.y @@ -65,6 +65,7 @@ static void free_list_evsel(struct list_head* list_evsel) %token PE_KERNEL_PMU_EVENT PE_PMU_EVENT_FAKE %token PE_ARRAY_ALL PE_ARRAY_RANGE %token PE_DRV_CFG_TERM +%token PE_TERM_HW %type PE_VALUE %type PE_VALUE_SYM_HW %type PE_VALUE_SYM_SW @@ -112,6 +113,8 @@ static void free_list_evsel(struct list_head* list_evse= l) %type array_term %type array_terms %destructor { free ($$.ranges); } +%type PE_TERM_HW +%destructor { free ($$.str); } =20 %union { @@ -125,6 +128,10 @@ static void free_list_evsel(struct list_head* list_evs= el) char *event; } tracepoint_name; struct parse_events_array array; + struct hardware_term { + char *str; + u64 num; + } hardware_term; } %% =20 @@ -770,13 +777,14 @@ name_or_raw '=3D' PE_VALUE $$ =3D term; } | -name_or_raw '=3D' PE_VALUE_SYM_HW +name_or_raw '=3D' PE_TERM_HW { struct parse_events_term *term; - int config =3D $3 & 255; =20 - if (parse_events_term__sym_hw(&term, $1, config)) { + if (parse_events_term__str(&term, PARSE_EVENTS__TERM_TYPE_USER, + $1, $3.str, &@1, &@3)) { free($1); + free($3.str); YYABORT; } $$ =3D term; @@ -806,12 +814,15 @@ PE_NAME $$ =3D term; } | -PE_VALUE_SYM_HW +PE_TERM_HW { struct parse_events_term *term; - int config =3D $1 & 255; =20 - ABORT_ON(parse_events_term__sym_hw(&term, NULL, config)); + if (parse_events_term__num(&term, PARSE_EVENTS__TERM_TYPE_HARDWARE, + $1.str, $1.num & 255, false, &@1, NULL)) { + free($1.str); + YYABORT; + } $$ =3D term; } | @@ -826,6 +837,17 @@ PE_TERM '=3D' PE_NAME $$ =3D term; } | +PE_TERM '=3D' PE_TERM_HW +{ + struct parse_events_term *term; + + if (parse_events_term__str(&term, (int)$1, NULL, $3.str, &@1, &@3)) { + free($3.str); + YYABORT; + } + $$ =3D term; +} +| PE_TERM '=3D' PE_VALUE { struct parse_events_term *term; --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5601BC7EE21 for ; Tue, 2 May 2023 22:45:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230234AbjEBWpV (ORCPT ); Tue, 2 May 2023 18:45:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34336 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230347AbjEBWpI (ORCPT ); Tue, 2 May 2023 18:45:08 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D392635BF for ; Tue, 2 May 2023 15:44:39 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-b9a8075bd7cso7758993276.1 for ; Tue, 02 May 2023 15:44:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067395; x=1685659395; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=jgxNy0ApXBVjzvhQZgVvxx7rNPPhGpKow0V3CkUrSSM=; b=hBl2zlApmK/DF51KUpwd95LcHd56hvZaXqxjDJJ9bKdL8d/ljP8HNkT4WX/m5bJWtS gGh/Zv2WIYEPwQRQ0aQpZt3YLOvIPJv5XHM3GqtSrfnNdOO1XK6dCLxBEEiQRMBJKkiG 59ZuLftpveBWITKoO+zEprZ3rI/vwf7/XkeIlCrX2D+vipWGyJXtWU4UT8x8a++d+kzY n59CntWOWDnAz/FCGUrv9XUpTkXZWXbnE+8imtFZ/pW+MSMXm222CLd4jnNo+i+EJSga 7k631Oph6eR361e6qyjgQCRZB7dgFFhWecYn0dY+4t87nauVYy7qrMdlxCE9mmbUKKBo ygCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067395; x=1685659395; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=jgxNy0ApXBVjzvhQZgVvxx7rNPPhGpKow0V3CkUrSSM=; b=IRffTLAaSrkxmvkV5CbXZiIB+XbhP1TJndD/tFSJPSQcsViTOMOHBk00JF7pWHDnwE tgl6z4jU0FPlI+Rlj8JFEzvQhtY9JBkv6jr5txDU2g6ViI9I7iJFcCfS4diLrvu1ahIy k/ZP73aaRPHQGCNYnPxzWtGyu1wUiRZueNsDaUF98m5RtavpxANeNhhCQpYgJV9mQsaE bU9IU076TyJ0l5lO7zsFK5WQFo1yKGsSlWZ/EjoOIA7+1Qb73c9xGJG0C+T9mTKIZul6 vjJQiG/FuwJ2kXP6+EI7ojJ4Q6kLup0qiXL/BrlEIlKlsJCwxM83t37TqtnBCQzDNM/2 pfpw== X-Gm-Message-State: AC+VfDwRwNpLYznZepBu84JFYMDbmsYyQt2kp8DGepHUNyLtIxL49RXn pA3GL48G2J+RzwHmWT20f/fiKGJgFEN7 X-Google-Smtp-Source: ACHHUZ7LNMMVhEJZZrX8sDNyDbONiX9SJSvoR3ihvfRCdx9SKcU8VKRA3bjAmDpCkaqRv5x0u3+ElwMoTDf8 X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a05:6902:100e:b0:b8b:f584:6b73 with SMTP id w14-20020a056902100e00b00b8bf5846b73mr7537984ybt.10.1683067394974; Tue, 02 May 2023 15:43:14 -0700 (PDT) Date: Tue, 2 May 2023 15:38:41 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-35-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 34/44] perf parse-events: Avoid error when assigning a term From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Avoid the parser error: ''' $ perf stat -e 'cycles/name=3Dname/' true event syntax error: 'cycles/name=3Dname/' \___ parser error ''' by turning the term back to a string if it is on the right. Add PMU and generic parsing tests. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/tests/parse-events.c | 21 +++++++++++++++++++++ tools/perf/util/parse-events.c | 9 +++++++++ tools/perf/util/parse-events.h | 3 +++ tools/perf/util/parse-events.y | 8 ++++++++ 4 files changed, 41 insertions(+) diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index 9ca8e19bda00..eb893cc15878 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -1499,6 +1499,16 @@ static int test__sym_event_dc(struct evlist *evlist) return TEST_OK; } =20 +static int test__term_equal_term(struct evlist *evlist) +{ + struct evsel *evsel =3D evlist__first(evlist); + + TEST_ASSERT_VAL("wrong type", evsel->core.attr.type =3D=3D PERF_TYPE_HARD= WARE); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); + TEST_ASSERT_VAL("wrong name setting", strcmp(evsel->name, "name") =3D=3D = 0); + return TEST_OK; +} + #ifdef HAVE_LIBTRACEEVENT static int count_tracepoints(void) { @@ -1871,6 +1881,11 @@ static const struct evlist_test test__events[] =3D { .check =3D test__exclusive_group, /* 7 */ }, + { + .name =3D "cycles/name=3Dname/", + .check =3D test__term_equal_term, + /* 8 */ + }, }; =20 static const struct evlist_test test__events_pmu[] =3D { @@ -2052,6 +2067,12 @@ static const struct evlist_test test__events_pmu[] = =3D { .check =3D test__exclusive_group, /* 9 */ }, + { + .name =3D "cpu/cycles,name=3Dname/", + .valid =3D test__pmu_cpu_valid, + .check =3D test__term_equal_term, + /* 0 */ + }, }; =20 struct terms_test { diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index dea27bc0b376..5d5d77fa398b 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -2581,6 +2581,15 @@ int parse_events_term__str(struct parse_events_term = **term, return new_term(term, &temp, str, 0); } =20 +int parse_events_term__term(struct parse_events_term **term, + int term_lhs, int term_rhs, + void *loc_term, void *loc_val) +{ + return parse_events_term__str(term, term_lhs, NULL, + strdup(config_term_names[term_rhs]), + loc_term, loc_val); +} + int parse_events_term__clone(struct parse_events_term **new, struct parse_events_term *term) { diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index 7fe80b416143..2a8cafe0ee8f 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -148,6 +148,9 @@ int parse_events_term__num(struct parse_events_term **t= erm, int parse_events_term__str(struct parse_events_term **term, int type_term, char *config, char *str, void *loc_term, void *loc_val); +int parse_events_term__term(struct parse_events_term **term, + int term_lhs, int term_rhs, + void *loc_term, void *loc_val); int parse_events_term__clone(struct parse_events_term **new, struct parse_events_term *term); void parse_events_term__delete(struct parse_events_term *term); diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y index 819a5123fd77..0aaebc57748e 100644 --- a/tools/perf/util/parse-events.y +++ b/tools/perf/util/parse-events.y @@ -848,6 +848,14 @@ PE_TERM '=3D' PE_TERM_HW $$ =3D term; } | +PE_TERM '=3D' PE_TERM +{ + struct parse_events_term *term; + + ABORT_ON(parse_events_term__term(&term, (int)$1, (int)$3, &@1, &@3)); + $$ =3D term; +} +| PE_TERM '=3D' PE_VALUE { struct parse_events_term *term; --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1DC1AC77B75 for ; Tue, 2 May 2023 22:52:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230298AbjEBWwP (ORCPT ); Tue, 2 May 2023 18:52:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229766AbjEBWwJ (ORCPT ); Tue, 2 May 2023 18:52:09 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C2BF3AB2 for ; Tue, 2 May 2023 15:51:23 -0700 (PDT) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-55a07969b10so934007b3.1 for ; Tue, 02 May 2023 15:51:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067825; x=1685659825; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=aRrQWfMbhp+rlO4pd/8kREfyV/ueQNA+MFq0luWCz2E=; b=birtAO/fNgJeeNe1EUuoa3hSX/1QwUqIjZZj7a+1BdVQTVNEQGQaXl+14G52zHHfhj 52v91gnKt0mrexc2JAFHifoaVpuMhBn2PaN5M8zdnmjAgD+4FhLrWg1TaPtZwu/2nF/l MEmTjC/JVv1REQ7XiXZOMKjDzMEzZskMk7uN5rZ5abY78UL+9u+ecoB94yXgpCaKz4dF XUMmTNVyQL3QMHbDOizDpK2KMX0iPaaUdVb70/+9dueB5Igwl0gKCiZGAGdL8hdsFaa5 SX0ZAdX473YGopCtceGGhrcV85iR1caW7t8w/CsQ555pI+FQY8Pao7/2WA5AaJ1D4S51 P/Sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067825; x=1685659825; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=aRrQWfMbhp+rlO4pd/8kREfyV/ueQNA+MFq0luWCz2E=; b=AIj9kuoB1H2QtWJ7kvcXeLvrvyxs6oZzl2HQBTFM+Bxv8wpq5j5/U/XiI8B+ty/q3B FqorlADhIFV12unVADYvukAnu+zJuQmdOUhJWy1lE8fbv+txdBvsKCe6+xJ07VpjbNb6 gPHtrd2rhtXqRxvO7bIIwHc4Xzi+stV33od4F7XnT4530puCbhltO1bJUqeXuiQiXHXn xUdCi/T5o4O9kcNqQzsKvOCZDST/DH3vlkItSFOeFEtKcIGzryFbib26BU/IBZl6OZvb nMZNyQblZGiLjmJDofxnJYetgw5b38z5VzTavxdrDpQ2nAJmT7QFdnNKqp5Ht/2bpren 35GQ== X-Gm-Message-State: AC+VfDwrk1EgzJ8muIGeOsFSu+dAUW7GbXhWPnzdOPF5QeHlDNcrdiNv JTaa9axVzVwMQXW0lpiOc4qTw04/tl3Z X-Google-Smtp-Source: ACHHUZ6l6yQT0eNizaa54wKMpaY+fppvn7gI2uSsn6yH/Kk1CrNSxJL7CW+d6Nmv2hlVj0VFHbeLUspxXl1Q X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a17:903:408d:b0:1a9:7f45:8711 with SMTP id z13-20020a170903408d00b001a97f458711mr8155plc.6.1683067402755; Tue, 02 May 2023 15:43:22 -0700 (PDT) Date: Tue, 2 May 2023 15:38:42 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-36-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 35/44] perf parse-events: Avoid error when assigning a legacy cache term From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Avoid the parser error: ''' $ perf stat -e 'cycles/name=3Dl1d/' true event syntax error: 'cycles/name=3Dl1d/' \___ parser error ''' by combining the name and legacy cache cases in the parser. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/tests/parse-events.c | 21 +++++++++++++++++++++ tools/perf/util/parse-events.y | 10 ++++++---- 2 files changed, 27 insertions(+), 4 deletions(-) diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index eb893cc15878..72a10bed84fd 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -1509,6 +1509,16 @@ static int test__term_equal_term(struct evlist *evli= st) return TEST_OK; } =20 +static int test__term_equal_legacy(struct evlist *evlist) +{ + struct evsel *evsel =3D evlist__first(evlist); + + TEST_ASSERT_VAL("wrong type", evsel->core.attr.type =3D=3D PERF_TYPE_HARD= WARE); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); + TEST_ASSERT_VAL("wrong name setting", strcmp(evsel->name, "l1d") =3D=3D 0= ); + return TEST_OK; +} + #ifdef HAVE_LIBTRACEEVENT static int count_tracepoints(void) { @@ -1886,6 +1896,11 @@ static const struct evlist_test test__events[] =3D { .check =3D test__term_equal_term, /* 8 */ }, + { + .name =3D "cycles/name=3Dl1d/", + .check =3D test__term_equal_legacy, + /* 9 */ + }, }; =20 static const struct evlist_test test__events_pmu[] =3D { @@ -2073,6 +2088,12 @@ static const struct evlist_test test__events_pmu[] = =3D { .check =3D test__term_equal_term, /* 0 */ }, + { + .name =3D "cpu/cycles,name=3Dl1d/", + .valid =3D test__pmu_cpu_valid, + .check =3D test__term_equal_legacy, + /* 1 */ + }, }; =20 struct terms_test { diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y index 0aaebc57748e..f4ee03b5976b 100644 --- a/tools/perf/util/parse-events.y +++ b/tools/perf/util/parse-events.y @@ -82,7 +82,7 @@ static void free_list_evsel(struct list_head* list_evsel) %type PE_EVENT_NAME %type PE_KERNEL_PMU_EVENT PE_PMU_EVENT_FAKE %type PE_DRV_CFG_TERM -%type name_or_raw +%type name_or_raw name_or_legacy %destructor { free ($$); } %type event_term %destructor { parse_events_term__delete ($$); } @@ -739,6 +739,8 @@ event_term =20 name_or_raw: PE_RAW | PE_NAME | PE_LEGACY_CACHE =20 +name_or_legacy: PE_NAME | PE_LEGACY_CACHE + event_term: PE_RAW { @@ -752,7 +754,7 @@ PE_RAW $$ =3D term; } | -name_or_raw '=3D' PE_NAME +name_or_raw '=3D' name_or_legacy { struct parse_events_term *term; =20 @@ -826,7 +828,7 @@ PE_TERM_HW $$ =3D term; } | -PE_TERM '=3D' PE_NAME +PE_TERM '=3D' name_or_legacy { struct parse_events_term *term; =20 @@ -872,7 +874,7 @@ PE_TERM $$ =3D term; } | -name_or_raw array '=3D' PE_NAME +name_or_raw array '=3D' name_or_legacy { struct parse_events_term *term; =20 --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE3BEC7EE21 for ; Tue, 2 May 2023 22:45:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229452AbjEBWpk (ORCPT ); Tue, 2 May 2023 18:45:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34248 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230326AbjEBWpX (ORCPT ); Tue, 2 May 2023 18:45:23 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 56ABD35BB for ; Tue, 2 May 2023 15:45:01 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-b9e50081556so3638294276.3 for ; Tue, 02 May 2023 15:45:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067410; x=1685659410; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=QMun7Fi9IhPa9JZ/I5pL4DGzuErIcYuCD85NRlCGuw4=; b=0rFVASj+MSiqSWWxtPzcsqp9e1zX7xibGro7CptCCBzSV6GSpUGdPbRpUEljzuK67g te0V1rJ+rNptkbNiYSsJ6U9UcV4oKUSZyoGZPYoZ2aOZeSPX9QdVFLMcDh0ChrimOQRA wCwMAVEFXpwXF2UmJm+DEV44lF1NbffBOi5PzcgTtNFF4cuTd3TCkNBswu/5BmjPP+rF syk9iHV/CYBNAlDpE+NRQQ+YMFgYpJQlU7b8oreSE9CMJ0OIK9VQ+24ttAqK4ms8zOYR 9rey7ubWK3EQiC0w7oakYIjjqcJnjhU6z3AS6/MCOSvyuB2Tr95qTKd2NVlwlmWhiDG4 n2eA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067410; x=1685659410; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=QMun7Fi9IhPa9JZ/I5pL4DGzuErIcYuCD85NRlCGuw4=; b=f09ma4xH8rQnOHX2eJJMH/x3+3wKGXxUMhtd5S+AcS8eL2g0nBrbRTGlvXzhTf1+We P2+dzfi08i5kLUgPLn++g4zrCgRRvFxzPYQLdJPeJXRoY5n1ckz5CXq8JdNqUxJat+dR B8WcTGpnLmAxzlxV79TMA7/2Tj/LbgVYzbF94Y87Dqx5+w58TMgwaf8nYT+4vIxts+h5 eczKOyvZ4pWMKeQdDUWMo136InxhpMVof9Pp/A2fmfM0hALlhVnHediBFWA/zwBp8wgh k4VLlIRaQf0lUQot9miToZv60kggyxHSgFg9TScHoBGZYrPHqr1BQPu8dhREDsFLIWR5 WGQA== X-Gm-Message-State: AC+VfDyahrPAtOD6OjZvTKZjs+3kl3PR1GGOo28l+dRAjOqQC+Kf7VgZ Wq7y/4j7Diuz5D1RIQq8SOyrQAvlw4Bg X-Google-Smtp-Source: ACHHUZ4lWGFd17WAQ+n3PFZEKj9tszZE7ynjvyLhtJMqHopAzrTcHJhP7ll2IAKwdDa1NwdvXrd82SqUeQRc X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a05:6902:18c4:b0:b99:45a4:3f96 with SMTP id ck4-20020a05690218c400b00b9945a43f96mr7961851ybb.5.1683067410339; Tue, 02 May 2023 15:43:30 -0700 (PDT) Date: Tue, 2 May 2023 15:38:43 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-37-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 36/44] perf parse-events: Don't auto merge hybrid wildcard events From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Bring back the behavior of not auto-merging hybrid events by delegating to a test in pmu. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/util/parse-events.c | 5 ++++- tools/perf/util/parse-events.y | 4 +++- tools/perf/util/pmu.c | 5 +++++ tools/perf/util/pmu.h | 1 + 4 files changed, 13 insertions(+), 2 deletions(-) diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index 5d5d77fa398b..2dad88a6bf19 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -1714,16 +1714,19 @@ int parse_events_multi_pmu_add(struct parse_events_= state *parse_state, =20 while ((pmu =3D perf_pmu__scan(pmu)) !=3D NULL) { struct perf_pmu_alias *alias; + bool auto_merge_stats; =20 if (parse_events__filter_pmu(parse_state, pmu)) continue; =20 + auto_merge_stats =3D perf_pmu__auto_merge_stats(pmu); + list_for_each_entry(alias, &pmu->aliases, list) { if (!strcasecmp(alias->name, str)) { parse_events_copy_term_list(head, &orig_head); if (!parse_events_add_pmu(parse_state, list, pmu->name, orig_head, - /*auto_merge_stats=3D*/true)) { + auto_merge_stats)) { pr_debug("%s -> %s/%s/\n", str, pmu->name, alias->str); ok++; diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y index f4ee03b5976b..4e1f5de35be8 100644 --- a/tools/perf/util/parse-events.y +++ b/tools/perf/util/parse-events.y @@ -327,10 +327,12 @@ PE_NAME opt_pmu_config name +=3D 7; if (!perf_pmu__match(pattern, name, $1) || !perf_pmu__match(pattern, pmu->alias_name, $1)) { + bool auto_merge_stats =3D perf_pmu__auto_merge_stats(pmu); + if (parse_events_copy_term_list(orig_terms, &terms)) CLEANUP_YYABORT; if (!parse_events_add_pmu(parse_state, list, pmu->name, terms, - /*auto_merge_stats=3D*/true)) { + auto_merge_stats)) { ok++; parse_state->wild_card_pmus =3D true; } diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index cd4247a379d4..f4f0afbc391c 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -1660,6 +1660,11 @@ bool perf_pmu__supports_wildcard_numeric(const struc= t perf_pmu *pmu) return is_pmu_core(pmu->name) || perf_pmu__is_hybrid(pmu->name); } =20 +bool perf_pmu__auto_merge_stats(const struct perf_pmu *pmu) +{ + return !perf_pmu__is_hybrid(pmu->name); +} + static bool pmu_alias_is_duplicate(struct sevent *alias_a, struct sevent *alias_b) { diff --git a/tools/perf/util/pmu.h b/tools/perf/util/pmu.h index 5a19536a5449..0e0cb6283594 100644 --- a/tools/perf/util/pmu.h +++ b/tools/perf/util/pmu.h @@ -222,6 +222,7 @@ struct perf_pmu *perf_pmu__scan(struct perf_pmu *pmu); bool is_pmu_core(const char *name); bool perf_pmu__supports_legacy_cache(const struct perf_pmu *pmu); bool perf_pmu__supports_wildcard_numeric(const struct perf_pmu *pmu); +bool perf_pmu__auto_merge_stats(const struct perf_pmu *pmu); void print_pmu_events(const struct print_callbacks *print_cb, void *print_= state); bool pmu_have_event(const char *pname, const char *name); =20 --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 226FDC19F20 for ; Tue, 2 May 2023 22:45:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230326AbjEBWpn (ORCPT ); Tue, 2 May 2023 18:45:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34664 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230333AbjEBWpY (ORCPT ); Tue, 2 May 2023 18:45:24 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 94CEB4200 for ; Tue, 2 May 2023 15:45:03 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-b9e2b65f2eeso4325052276.2 for ; Tue, 02 May 2023 15:45:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067417; x=1685659417; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=Z5la9qJcqL6gBH6h4UORwyXdD/ZlzmqtItJD5+R0Siw=; b=o+yo5QO2m0Arr3Ssf8bJlRG++UZNEHFNdoC52cVkU6VcrPtyd85tgK2ep2b4NIR1F7 svxp4QSwm/55im0KW8ePdCqUQNIqdMYhEfFhoWAmhXQ3nQHIpCJZhm1DnKcGq7swhlbL TYIbA/aX+U5TLZl5eyVfKQF97J1Saf9gw+MaR6S33C7d25zbuWJjOdocSz2DR+AHbij0 NWpmhzTFaAbQYMqMunjTlnqbLKs95kiXbWB52wUS559hByrHHYdvLq8haSpSnPSDVw2R GJPg8BfZSgpGrprpblYrBHWyWQAgyP9VKEyuhBCAlLErW3VTrcUkvFe4R+t+eHcI2DRi mxag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067417; x=1685659417; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Z5la9qJcqL6gBH6h4UORwyXdD/ZlzmqtItJD5+R0Siw=; b=cTOlb83Sm5YUpmBkZ10LsBwcjsyNvjNm/grS2DL/pgKYP0C+NdR2+s3AOtzZM7IBn2 dSU1vXV3Qgi++hYdZqQ8d3PTf0cercp8YGCWAYjg+wHylWacXVP4slke+yzoo478LjCA 3ujg6+C8vDah58+I+Lscq/PuVkmhvGOklOZj7m2U3CNq0BdUTHXxjdzvnAvTJqmE7zve gxswjtbd1zTXPVC5wAFaoMHp2ebGEHZxQB2USYDwhF/gSu7UAijqlHlWstIs0f6AeDFU /7CZ9De6oW8960xc7lGBsGD0l6zITTqLU+bFrjQJhBx/ja58yrSA0DkCRYXs2NahuVqv GMjw== X-Gm-Message-State: AC+VfDyEykddowagQeV0erqvdEo0KxZRXWqPmYkKPaQgILJKypZt9oew 8IIl8FZM0UOiv0h3wcigVqWsPqHQ+w6q X-Google-Smtp-Source: ACHHUZ7R624gU7PAQPBwrYcf7FXoTBGq+e/cbUC9fM+4MWzco4gFBqz9uOkKNurXZKUOfK60Mtf/IBgIVwfT X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a25:13c1:0:b0:b39:b0d3:9a7f with SMTP id 184-20020a2513c1000000b00b39b0d39a7fmr7344538ybt.7.1683067417109; Tue, 02 May 2023 15:43:37 -0700 (PDT) Date: Tue, 2 May 2023 15:38:44 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-38-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 37/44] perf parse-events: Don't reorder atom cpu events From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On hybrid systems the topdown events don't share a fixed counter on the atom core, so they don't require the sorting the perf metric supporting PMUs do. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/arch/x86/util/evlist.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/perf/arch/x86/util/evlist.c b/tools/perf/arch/x86/util/e= vlist.c index d4193479a364..1b6065841fb0 100644 --- a/tools/perf/arch/x86/util/evlist.c +++ b/tools/perf/arch/x86/util/evlist.c @@ -6,6 +6,7 @@ #include "util/event.h" #include "util/pmu-hybrid.h" #include "topdown.h" +#include "evsel.h" =20 static int ___evlist__add_default_attrs(struct evlist *evlist, struct perf_event_attr *attrs, @@ -67,8 +68,7 @@ int arch_evlist__add_default_attrs(struct evlist *evlist, =20 int arch_evlist__cmp(const struct evsel *lhs, const struct evsel *rhs) { - if (topdown_sys_has_perf_metrics() && - (!lhs->pmu_name || !strncmp(lhs->pmu_name, "cpu", 3))) { + if (topdown_sys_has_perf_metrics() && evsel__sys_has_perf_metrics(lhs)) { /* Ensure the topdown slots comes first. */ if (strcasestr(lhs->name, "slots")) return -1; --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8FA02C77B75 for ; Tue, 2 May 2023 22:46:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230402AbjEBWqq (ORCPT ); Tue, 2 May 2023 18:46:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230360AbjEBWqZ (ORCPT ); Tue, 2 May 2023 18:46:25 -0400 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 444673AB2 for ; Tue, 2 May 2023 15:45:51 -0700 (PDT) Received: by mail-yw1-f201.google.com with SMTP id 00721157ae682-55a04468981so75132807b3.0 for ; Tue, 02 May 2023 15:45:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067425; x=1685659425; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=+u0fif1vqEW0/J+d1lw722skZP4Uon5UbkaqbwSy+30=; b=Q4zTcsdmA2DZnQaI4yinZojAyvDnycTbYavNcwKkCZEDKv3zr9OC3ZR2HNS4l7XQn4 Wk5xZe7MPleFDXSIinUgNSAyNpFTHRxJxXBaFFe67qYv0T7XAPCfIesQEoyEef2d4+C5 zxuwEyaiy0Nc01WhCk9oUsi1WYFd7ccL/QhvVlWu10OhMfiJxpq7M/PiTgUMf9HpwvvD Stj+E/AQHkYrILDnUAcU1oKEOepjo/Iq6857UrlCv7pRDgNejTn0fulIFGirlGBcMXqL LZFnmUNsTQ3Wtmwhub3GI/kCJlZCCJCKoYo4UdQHT7MW36KxnDxb11GLv+bDpQ8REA4i TEfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067425; x=1685659425; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=+u0fif1vqEW0/J+d1lw722skZP4Uon5UbkaqbwSy+30=; b=NsvB+z3Nt2xrHeVaT5M1sEZUtkRo7n1SpGKtBGXYtrW7LVXSyfpYEYh35B4nXRPETl evTtg0eAOYbchWumHk0iY24G6nyoaXDmZo1tN4QyiARM6JlMIgFpdD98L1VIOn6rBfuH 7DgILmqMVL3e/LyyJBVUS/LVTX0fgqXs8919IFCoktAiGlDZOdN+hjElOZ9Q1odAoCq4 ZjiQzz9ww3R+joaWp07AWmjCgaOXPvucdNjuljDYDO4jed1tEwPGpboNv3+8WA71tq+4 MC02FZZZYE8soN9uItf3cHiQpsPos5GJDcgwAWUdGnDn4mxFg6tMo/fwHNXh1OlDqfBq Wibg== X-Gm-Message-State: AC+VfDwvxC6bEsDgKcrltNdM6LSxKFxjjJ+MoqVWjaZke7uXsjEJvW5L AsHAzQM1cNEqk/z4Dz77BU4ek7tLwJPU X-Google-Smtp-Source: ACHHUZ71/u2ByJA/xBRV82K5e9QUs1aUmfSldDJJJJbHoXvIas+/dVi9n+nEZhLjBsObp1H5sPtkZpVrojnX X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a05:690c:725:b0:54f:bb71:c7b3 with SMTP id bt5-20020a05690c072500b0054fbb71c7b3mr11277965ywb.9.1683067425138; Tue, 02 May 2023 15:43:45 -0700 (PDT) Date: Tue, 2 May 2023 15:38:45 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-39-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 38/44] perf metrics: Be PMU specific for referenced metrics. From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Hybrid systems may define the same metric for different PMUs, this can cause confusion of events. To avoid this make the referenced metric searches PMU specific, matching that in the table. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/builtin-stat.c | 6 +- tools/perf/pmu-events/jevents.py | 4 +- tools/perf/pmu-events/pmu-events.h | 1 + tools/perf/util/metricgroup.c | 94 +++++++++++++++++++++--------- tools/perf/util/metricgroup.h | 2 +- 5 files changed, 75 insertions(+), 32 deletions(-) diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index 06a1d71a49a5..bb1a4ecd7558 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -1794,7 +1794,7 @@ static int add_default_attributes(void) * will use this approach. To determine transaction support * on an architecture test for such a metric name. */ - if (!metricgroup__has_metric("transaction")) { + if (!metricgroup__has_metric("all", "transaction")) { pr_err("Missing transaction metrics"); return -1; } @@ -1823,7 +1823,7 @@ static int add_default_attributes(void) smi_reset =3D true; } =20 - if (!metricgroup__has_metric("smi")) { + if (!metricgroup__has_metric("all", "smi")) { pr_err("Missing smi metrics"); return -1; } @@ -1903,7 +1903,7 @@ static int add_default_attributes(void) * caused by exposing latent bugs. This is fixed properly in: * https://lore.kernel.org/lkml/bff481ba-e60a-763f-0aa0-3ee53302c480@lin= ux.intel.com/ */ - if (metricgroup__has_metric("TopdownL1") && !perf_pmu__has_hybrid()) { + if (metricgroup__has_metric("all", "TopdownL1") && !perf_pmu__has_hybrid= ()) { struct evlist *metric_evlist =3D evlist__new(); struct evsel *metric_evsel; =20 diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jeven= ts.py index f57a8f274025..b18dd2fcbf04 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -51,8 +51,8 @@ _json_event_attributes =3D [ =20 # Attributes that are in pmu_metric rather than pmu_event. _json_metric_attributes =3D [ - 'metric_name', 'metric_group', 'metric_expr', 'metric_threshold', 'des= c', - 'long_desc', 'unit', 'compat', 'metricgroup_no_group', 'aggr_mode', + 'pmu', 'metric_name', 'metric_group', 'metric_expr', 'metric_threshold= ', + 'desc', 'long_desc', 'unit', 'compat', 'metricgroup_no_group', 'aggr_m= ode', 'event_grouping' ] # Attributes that are bools or enum int values, encoded as '0', '1',... diff --git a/tools/perf/pmu-events/pmu-events.h b/tools/perf/pmu-events/pmu= -events.h index 80349685cf4d..3549e6971a4d 100644 --- a/tools/perf/pmu-events/pmu-events.h +++ b/tools/perf/pmu-events/pmu-events.h @@ -51,6 +51,7 @@ struct pmu_event { }; =20 struct pmu_metric { + const char *pmu; const char *metric_name; const char *metric_group; const char *metric_expr; diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index 1afc8d7a5838..17478eb33bdc 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -123,6 +123,7 @@ struct metric { * within the expression. */ struct expr_parse_ctx *pctx; + const char *pmu; /** The name of the metric such as "IPC". */ const char *metric_name; /** Modifier on the metric such as "u" or NULL for none. */ @@ -216,6 +217,7 @@ static struct metric *metric__new(const struct pmu_metr= ic *pm, if (!m->pctx) goto out_err; =20 + m->pmu =3D pm->pmu ?: "cpu"; m->metric_name =3D pm->metric_name; m->modifier =3D NULL; if (modifier) { @@ -259,11 +261,12 @@ static bool contains_metric_id(struct evsel **metric_= events, int num_events, /** * setup_metric_events - Find a group of events in metric_evlist that corr= espond * to the IDs from a parsed metric expression. + * @pmu: The PMU for the IDs. * @ids: the metric IDs to match. * @metric_evlist: the list of perf events. * @out_metric_events: holds the created metric events array. */ -static int setup_metric_events(struct hashmap *ids, +static int setup_metric_events(const char *pmu, struct hashmap *ids, struct evlist *metric_evlist, struct evsel ***out_metric_events) { @@ -271,6 +274,7 @@ static int setup_metric_events(struct hashmap *ids, const char *metric_id; struct evsel *ev; size_t ids_size, matched_events, i; + bool all_pmus =3D !strcmp(pmu, "all"); =20 *out_metric_events =3D NULL; ids_size =3D hashmap__size(ids); @@ -283,6 +287,8 @@ static int setup_metric_events(struct hashmap *ids, evlist__for_each_entry(metric_evlist, ev) { struct expr_id_data *val_ptr; =20 + if (!all_pmus && strcmp(ev->pmu_name, pmu)) + continue; /* * Check for duplicate events with the same name. For * example, uncore_imc/cas_count_read/ will turn into 6 @@ -355,8 +361,13 @@ static bool match_metric(const char *n, const char *li= st) return false; } =20 -static bool match_pm_metric(const struct pmu_metric *pm, const char *metri= c) +static bool match_pm_metric(const struct pmu_metric *pm, const char *pmu, = const char *metric) { + const char *pm_pmu =3D pm->pmu ?: "cpu"; + + if (strcmp(pmu, "all") && strcmp(pm_pmu, pmu)) + return false; + return match_metric(pm->metric_group, metric) || match_metric(pm->metric_name, metric); } @@ -766,6 +777,7 @@ struct visited_metric { =20 struct metricgroup_add_iter_data { struct list_head *metric_list; + const char *pmu; const char *metric_name; const char *modifier; int *ret; @@ -779,7 +791,8 @@ struct metricgroup_add_iter_data { const struct pmu_metrics_table *table; }; =20 -static bool metricgroup__find_metric(const char *metric, +static bool metricgroup__find_metric(const char *pmu, + const char *metric, const struct pmu_metrics_table *table, struct pmu_metric *pm); =20 @@ -798,6 +811,7 @@ static int add_metric(struct list_head *metric_list, * resolve_metric - Locate metrics within the root metric and recursively = add * references to them. * @metric_list: The list the metric is added to. + * @pmu: The PMU name to resolve metrics on, or "all" for all PMUs. * @modifier: if non-null event modifiers like "u". * @metric_no_group: Should events written to events be grouped "{}" or * global. Grouping is the default but due to multiplexi= ng the @@ -813,6 +827,7 @@ static int add_metric(struct list_head *metric_list, * architecture perf is running upon. */ static int resolve_metric(struct list_head *metric_list, + const char *pmu, const char *modifier, bool metric_no_group, bool metric_no_threshold, @@ -842,7 +857,7 @@ static int resolve_metric(struct list_head *metric_list, hashmap__for_each_entry(root_metric->pctx->ids, cur, bkt) { struct pmu_metric pm; =20 - if (metricgroup__find_metric(cur->pkey, table, &pm)) { + if (metricgroup__find_metric(pmu, cur->pkey, table, &pm)) { pending =3D realloc(pending, (pending_cnt + 1) * sizeof(struct to_resolve)); if (!pending) @@ -993,9 +1008,12 @@ static int __add_metric(struct list_head *metric_list, } if (!ret) { /* Resolve referenced metrics. */ - ret =3D resolve_metric(metric_list, modifier, metric_no_group, + const char *pmu =3D pm->pmu ?: "cpu"; + + ret =3D resolve_metric(metric_list, pmu, modifier, metric_no_group, metric_no_threshold, user_requested_cpu_list, - system_wide, root_metric, &visited_node, table); + system_wide, root_metric, &visited_node, + table); } if (ret) { if (is_root) @@ -1008,6 +1026,7 @@ static int __add_metric(struct list_head *metric_list, } =20 struct metricgroup__find_metric_data { + const char *pmu; const char *metric; struct pmu_metric *pm; }; @@ -1017,6 +1036,10 @@ static int metricgroup__find_metric_callback(const s= truct pmu_metric *pm, void *vdata) { struct metricgroup__find_metric_data *data =3D vdata; + const char *pm_pmu =3D pm->pmu ?: "cpu"; + + if (strcmp(data->pmu, "all") && strcmp(pm_pmu, data->pmu)) + return 0; =20 if (!match_metric(pm->metric_name, data->metric)) return 0; @@ -1025,11 +1048,13 @@ static int metricgroup__find_metric_callback(const = struct pmu_metric *pm, return 1; } =20 -static bool metricgroup__find_metric(const char *metric, +static bool metricgroup__find_metric(const char *pmu, + const char *metric, const struct pmu_metrics_table *table, struct pmu_metric *pm) { struct metricgroup__find_metric_data data =3D { + .pmu =3D pmu, .metric =3D metric, .pm =3D pm, }; @@ -1083,7 +1108,7 @@ static int metricgroup__add_metric_sys_event_iter(con= st struct pmu_metric *pm, struct metricgroup_add_iter_data *d =3D data; int ret; =20 - if (!match_pm_metric(pm, d->metric_name)) + if (!match_pm_metric(pm, d->pmu, d->metric_name)) return 0; =20 ret =3D add_metric(d->metric_list, pm, d->modifier, d->metric_no_group, @@ -1128,6 +1153,7 @@ static int metric_list_cmp(void *priv __maybe_unused,= const struct list_head *l, =20 struct metricgroup__add_metric_data { struct list_head *list; + const char *pmu; const char *metric_name; const char *modifier; const char *user_requested_cpu_list; @@ -1144,7 +1170,7 @@ static int metricgroup__add_metric_callback(const str= uct pmu_metric *pm, struct metricgroup__add_metric_data *data =3D vdata; int ret =3D 0; =20 - if (pm->metric_expr && match_pm_metric(pm, data->metric_name)) { + if (pm->metric_expr && match_pm_metric(pm, data->pmu, data->metric_name))= { bool metric_no_group =3D data->metric_no_group || match_metric(data->metric_name, pm->metricgroup_no_group); =20 @@ -1159,6 +1185,7 @@ static int metricgroup__add_metric_callback(const str= uct pmu_metric *pm, =20 /** * metricgroup__add_metric - Find and add a metric, or a metric group. + * @pmu: The PMU name to search for metrics on, or "all" for all PMUs. * @metric_name: The name of the metric or metric group. For example, "IPC" * could be the name of a metric and "TopDownL1" the name of= a * metric group. @@ -1172,7 +1199,7 @@ static int metricgroup__add_metric_callback(const str= uct pmu_metric *pm, * @table: The table that is searched for metrics, most commonly the table= for the * architecture perf is running upon. */ -static int metricgroup__add_metric(const char *metric_name, const char *mo= difier, +static int metricgroup__add_metric(const char *pmu, const char *metric_nam= e, const char *modifier, bool metric_no_group, bool metric_no_threshold, const char *user_requested_cpu_list, bool system_wide, @@ -1186,6 +1213,7 @@ static int metricgroup__add_metric(const char *metric= _name, const char *modifier { struct metricgroup__add_metric_data data =3D { .list =3D &list, + .pmu =3D pmu, .metric_name =3D metric_name, .modifier =3D modifier, .metric_no_group =3D metric_no_group, @@ -1210,6 +1238,7 @@ static int metricgroup__add_metric(const char *metric= _name, const char *modifier .fn =3D metricgroup__add_metric_sys_event_iter, .data =3D (void *) &(struct metricgroup_add_iter_data) { .metric_list =3D &list, + .pmu =3D pmu, .metric_name =3D metric_name, .modifier =3D modifier, .metric_no_group =3D metric_no_group, @@ -1239,6 +1268,7 @@ static int metricgroup__add_metric(const char *metric= _name, const char *modifier /** * metricgroup__add_metric_list - Find and add metrics, or metric groups, * specified in a list. + * @pmu: A pmu to restrict the metrics to, or "all" for all PMUS. * @list: the list of metrics or metric groups. For example, "IPC,CPI,TopD= ownL1" * would match the IPC and CPI metrics, and TopDownL1 would match a= ll * the metrics in the TopDownL1 group. @@ -1251,7 +1281,8 @@ static int metricgroup__add_metric(const char *metric= _name, const char *modifier * @table: The table that is searched for metrics, most commonly the table= for the * architecture perf is running upon. */ -static int metricgroup__add_metric_list(const char *list, bool metric_no_g= roup, +static int metricgroup__add_metric_list(const char *pmu, const char *list, + bool metric_no_group, bool metric_no_threshold, const char *user_requested_cpu_list, bool system_wide, struct list_head *metric_list, @@ -1270,7 +1301,7 @@ static int metricgroup__add_metric_list(const char *l= ist, bool metric_no_group, if (modifier) *modifier++ =3D '\0'; =20 - ret =3D metricgroup__add_metric(metric_name, modifier, + ret =3D metricgroup__add_metric(pmu, metric_name, modifier, metric_no_group, metric_no_threshold, user_requested_cpu_list, system_wide, metric_list, table); @@ -1460,7 +1491,8 @@ static int parse_ids(bool metric_no_merge, struct per= f_pmu *fake_pmu, return ret; } =20 -static int parse_groups(struct evlist *perf_evlist, const char *str, +static int parse_groups(struct evlist *perf_evlist, + const char *pmu, const char *str, bool metric_no_group, bool metric_no_merge, bool metric_no_threshold, @@ -1478,7 +1510,7 @@ static int parse_groups(struct evlist *perf_evlist, c= onst char *str, =20 if (metric_events_list->nr_entries =3D=3D 0) metricgroup__rblist_init(metric_events_list); - ret =3D metricgroup__add_metric_list(str, metric_no_group, metric_no_thre= shold, + ret =3D metricgroup__add_metric_list(pmu, str, metric_no_group, metric_no= _threshold, user_requested_cpu_list, system_wide, &metric_list, table); if (ret) @@ -1535,6 +1567,11 @@ static int parse_groups(struct evlist *perf_evlist, = const char *str, strcmp(m->modifier, n->modifier))) continue; =20 + if ((!m->pmu && n->pmu) || + (m->pmu && !n->pmu) || + (m->pmu && n->pmu && strcmp(m->pmu, n->pmu))) + continue; + if (expr__subset_of_ids(n->pctx, m->pctx)) { pr_debug("Events in '%s' fully contained within '%s'\n", m->metric_name, n->metric_name); @@ -1552,7 +1589,8 @@ static int parse_groups(struct evlist *perf_evlist, c= onst char *str, =20 metric_evlist =3D m->evlist; } - ret =3D setup_metric_events(m->pctx->ids, metric_evlist, &metric_events); + ret =3D setup_metric_events(fake_pmu ? "all" : m->pmu, m->pctx->ids, + metric_evlist, &metric_events); if (ret) { pr_debug("Cannot resolve IDs for %s: %s\n", m->metric_name, m->metric_expr); @@ -1623,7 +1661,7 @@ int metricgroup__parse_groups(struct evlist *perf_evl= ist, if (!table) return -EINVAL; =20 - return parse_groups(perf_evlist, str, metric_no_group, metric_no_merge, + return parse_groups(perf_evlist, "all", str, metric_no_group, metric_no_m= erge, metric_no_threshold, user_requested_cpu_list, system_wide, /*fake_pmu=3D*/NULL, metric_events, table); } @@ -1633,7 +1671,7 @@ int metricgroup__parse_groups_test(struct evlist *evl= ist, const char *str, struct rblist *metric_events) { - return parse_groups(evlist, str, + return parse_groups(evlist, "all", str, /*metric_no_group=3D*/false, /*metric_no_merge=3D*/false, /*metric_no_threshold=3D*/false, @@ -1642,28 +1680,32 @@ int metricgroup__parse_groups_test(struct evlist *e= vlist, &perf_pmu__fake, metric_events, table); } =20 +struct metricgroup__has_metric_data { + const char *pmu; + const char *metric; +}; static int metricgroup__has_metric_callback(const struct pmu_metric *pm, const struct pmu_metrics_table *table __maybe_unused, void *vdata) { - const char *metric =3D vdata; - - if (match_metric(pm->metric_name, metric) || - match_metric(pm->metric_group, metric)) - return 1; + struct metricgroup__has_metric_data *data =3D vdata; =20 - return 0; + return match_pm_metric(pm, data->pmu, data->metric) ? 1 : 0; } =20 -bool metricgroup__has_metric(const char *metric) +bool metricgroup__has_metric(const char *pmu, const char *metric) { const struct pmu_metrics_table *table =3D pmu_metrics_table__find(); + struct metricgroup__has_metric_data data =3D { + .pmu =3D pmu, + .metric =3D metric, + }; =20 if (!table) return false; =20 - return pmu_metrics_table_for_each_metric(table, metricgroup__has_metric_c= allback, - (void *)metric) ? true : false; + return pmu_metrics_table_for_each_metric(table, metricgroup__has_metric_c= allback, &data) + ? true : false; } =20 static int metricgroup__topdown_max_level_callback(const struct pmu_metric= *pm, diff --git a/tools/perf/util/metricgroup.h b/tools/perf/util/metricgroup.h index 77472e35705e..08e9b9e953ec 100644 --- a/tools/perf/util/metricgroup.h +++ b/tools/perf/util/metricgroup.h @@ -80,7 +80,7 @@ int metricgroup__parse_groups_test(struct evlist *evlist, struct rblist *metric_events); =20 void metricgroup__print(const struct print_callbacks *print_cb, void *prin= t_state); -bool metricgroup__has_metric(const char *metric); +bool metricgroup__has_metric(const char *pmu, const char *metric); unsigned int metricgroups__topdown_max_level(void); int arch_get_runtimeparam(const struct pmu_metric *pm); void metricgroup__rblist_exit(struct rblist *metric_events); --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2884C19F20 for ; Tue, 2 May 2023 22:45:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230372AbjEBWpq (ORCPT ); Tue, 2 May 2023 18:45:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34256 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230336AbjEBWpZ (ORCPT ); Tue, 2 May 2023 18:45:25 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 623883AA5 for ; Tue, 2 May 2023 15:45:04 -0700 (PDT) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-559fb850e08so59971647b3.3 for ; Tue, 02 May 2023 15:45:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067432; x=1685659432; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=9J7avGu03QLF3OzvxpAd+rFmIiyVUKJL1J9REWiEeQ0=; b=08tXE7YwmZ5Zzxd9BAlqC1LukNL7m13wC3KLBDxKxpCYXC+ZnMUVOchpY1ZAPh9p6K WhE99u+/MKrl5F6qjjb0iBX28XHoqBeJ+OlAO2+Q29LM86c57fQ2CtTkVYDpcgnC8g9+ gCxV2AHiueRuM46ZiOg2xmsAa6UGcS14PLlTCkb/jC2NbtRz6xRjs0gqycFOa3kEQ+UA rHzRd/gGi+NnpCNHoGuiiG0LhRvcMutvaWkS2OAbvnnxcSriqOIIYERou9o3TbDwAIej 081rjgH+Try4yw8K0teDlhNplvRrBBVSd2Y0hPS2X67xIqPRTu/CwhCDlM+sQOE0QxrI 6Vog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067432; x=1685659432; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=9J7avGu03QLF3OzvxpAd+rFmIiyVUKJL1J9REWiEeQ0=; b=AaQqstVkHyW2foB4mnZwJtg3J2bAsyR2GyNilso0ldT+9I0lKShVHDZDGrzH1v6QB8 3+w75B/l44CsY8q9O/JVJGOt0uA6GrTKZCAkoqx4bGfx4R+YRN3ghwsbBkA+Rkjmyr9n Lg42NRjA8nYSMPl2guvmpnLfwEYf0ItQoMXcLv++xfTi3yalGwvAgTtXqPF53jZSuQD1 tcmN4r58D8rG02+IbSLOUGdnjBCrcQnD4QUIJxxM0neC8e3eHP6tk47qq+tNkSVUa0xp RTtLap3FeQ7R6VbXcm4BSkM4GrSb7cAESo4GMLhu2L35LCn3+JFKpGh0lwfVxhAWnsMy jbWA== X-Gm-Message-State: AC+VfDwDWbJpYyjOFrL4hWi+Dkv9q/pl2qZN6YCFSU68gd8igMocWin7 n2GJJC6qx7OsfKqEDHHROC67bUTfoKUS X-Google-Smtp-Source: ACHHUZ4QqfkYLMIGE+StYfSBmF8j9IPJCRIVeVN8WAvZ4mBnyhVVIj7f9bLqCCSJ7IF+tmsC7clNc56jJFW4 X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a0d:ec4c:0:b0:55a:20a3:5ce3 with SMTP id r12-20020a0dec4c000000b0055a20a35ce3mr5260768ywn.3.1683067431876; Tue, 02 May 2023 15:43:51 -0700 (PDT) Date: Tue, 2 May 2023 15:38:46 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-40-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 39/44] perf stat: Command line PMU metric filtering From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Wire up the --cputype value to limit which metrics are parsed. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/builtin-stat.c | 20 ++++++++++++-------- tools/perf/util/metricgroup.c | 3 ++- tools/perf/util/metricgroup.h | 1 + 3 files changed, 15 insertions(+), 9 deletions(-) diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index bb1a4ecd7558..f4e572f9de6b 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -1783,6 +1783,7 @@ static int add_default_attributes(void) }; =20 struct perf_event_attr default_null_attrs[] =3D {}; + const char *pmu =3D parse_events_option_args.pmu_filter ?: "all"; =20 /* Set attrs if no event is selected and !null_run: */ if (stat_config.null_run) @@ -1794,11 +1795,11 @@ static int add_default_attributes(void) * will use this approach. To determine transaction support * on an architecture test for such a metric name. */ - if (!metricgroup__has_metric("all", "transaction")) { + if (!metricgroup__has_metric(pmu, "transaction")) { pr_err("Missing transaction metrics"); return -1; } - return metricgroup__parse_groups(evsel_list, "transaction", + return metricgroup__parse_groups(evsel_list, pmu, "transaction", stat_config.metric_no_group, stat_config.metric_no_merge, stat_config.metric_no_threshold, @@ -1823,7 +1824,7 @@ static int add_default_attributes(void) smi_reset =3D true; } =20 - if (!metricgroup__has_metric("all", "smi")) { + if (!metricgroup__has_metric(pmu, "smi")) { pr_err("Missing smi metrics"); return -1; } @@ -1831,7 +1832,7 @@ static int add_default_attributes(void) if (!force_metric_only) stat_config.metric_only =3D true; =20 - return metricgroup__parse_groups(evsel_list, "smi", + return metricgroup__parse_groups(evsel_list, pmu, "smi", stat_config.metric_no_group, stat_config.metric_no_merge, stat_config.metric_no_threshold, @@ -1864,7 +1865,8 @@ static int add_default_attributes(void) "Please print the result regularly, e.g. -I1000\n"); } str[8] =3D stat_config.topdown_level + '0'; - if (metricgroup__parse_groups(evsel_list, str, + if (metricgroup__parse_groups(evsel_list, + pmu, str, /*metric_no_group=3D*/false, /*metric_no_merge=3D*/false, /*metric_no_threshold=3D*/true, @@ -1903,14 +1905,14 @@ static int add_default_attributes(void) * caused by exposing latent bugs. This is fixed properly in: * https://lore.kernel.org/lkml/bff481ba-e60a-763f-0aa0-3ee53302c480@lin= ux.intel.com/ */ - if (metricgroup__has_metric("all", "TopdownL1") && !perf_pmu__has_hybrid= ()) { + if (metricgroup__has_metric(pmu, "TopdownL1") && !perf_pmu__has_hybrid()= ) { struct evlist *metric_evlist =3D evlist__new(); struct evsel *metric_evsel; =20 if (!metric_evlist) return -1; =20 - if (metricgroup__parse_groups(metric_evlist, "TopdownL1", + if (metricgroup__parse_groups(metric_evlist, pmu, "TopdownL1", /*metric_no_group=3D*/false, /*metric_no_merge=3D*/false, /*metric_no_threshold=3D*/true, @@ -2434,7 +2436,9 @@ int cmd_stat(int argc, const char **argv) * knowing the target is system-wide. */ if (metrics) { - metricgroup__parse_groups(evsel_list, metrics, + const char *pmu =3D parse_events_option_args.pmu_filter ?: "all"; + + metricgroup__parse_groups(evsel_list, pmu, metrics, stat_config.metric_no_group, stat_config.metric_no_merge, stat_config.metric_no_threshold, diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index 17478eb33bdc..4245b23d8efe 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -1648,6 +1648,7 @@ static int parse_groups(struct evlist *perf_evlist, } =20 int metricgroup__parse_groups(struct evlist *perf_evlist, + const char *pmu, const char *str, bool metric_no_group, bool metric_no_merge, @@ -1661,7 +1662,7 @@ int metricgroup__parse_groups(struct evlist *perf_evl= ist, if (!table) return -EINVAL; =20 - return parse_groups(perf_evlist, "all", str, metric_no_group, metric_no_m= erge, + return parse_groups(perf_evlist, pmu, str, metric_no_group, metric_no_mer= ge, metric_no_threshold, user_requested_cpu_list, system_wide, /*fake_pmu=3D*/NULL, metric_events, table); } diff --git a/tools/perf/util/metricgroup.h b/tools/perf/util/metricgroup.h index 08e9b9e953ec..bf18274c15df 100644 --- a/tools/perf/util/metricgroup.h +++ b/tools/perf/util/metricgroup.h @@ -67,6 +67,7 @@ struct metric_event *metricgroup__lookup(struct rblist *m= etric_events, struct evsel *evsel, bool create); int metricgroup__parse_groups(struct evlist *perf_evlist, + const char *pmu, const char *str, bool metric_no_group, bool metric_no_merge, --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A494C19F20 for ; Tue, 2 May 2023 22:46:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229606AbjEBWqC (ORCPT ); Tue, 2 May 2023 18:46:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34338 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230015AbjEBWpf (ORCPT ); Tue, 2 May 2023 18:45:35 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 95C8340E3 for ; Tue, 2 May 2023 15:45:13 -0700 (PDT) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-55a40d32a6bso32977657b3.2 for ; Tue, 02 May 2023 15:45:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067439; x=1685659439; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:from:to:cc:subject:date :message-id:reply-to; bh=FdzKhr+YXtuoJzMV7YR4Ngtu/fNDqpDHPWq8uJ6vwU0=; b=43DYgG4VyI9y02nPjuqQkfO8zgPWD+/a+TrIsKMyiFjADVIICPlCbfcKYTaMpgn4N6 FXxUJnIVnJAZqZYS6WM7+jc2toWprD+Wi3bztuBcTsIS/11xjKr8IlcE7Vf7GKI3XbSe y0YaI+DlfGAvOMMo26/szJ98D20h1xQm3VuB52LecKPW1V741NbqREi9fgTgyqdikOUp cOj59bWRL46pMcOe8Fx6rIGoJtCmap4WGon7GC9s5jHEtgr4HVpRAd2VoUrBSQjYzXOU vnvJi/V5k5Q8nC/x7WvlkRBplmV/+Pz1wvlN+khU+yYIReu4IeY1cL2qVkybRoELhHvZ 660w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067440; x=1685659440; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=FdzKhr+YXtuoJzMV7YR4Ngtu/fNDqpDHPWq8uJ6vwU0=; b=TSSvuMqAu2Ckq+cd468HSQLgmP/7jr4QhZdDutLAhedOuDJX+PuRVR1MkNd1tlNM5O +TRi4atiNMASZJ6bHIhGo8CemqaHcgQKypOeFTXbNNn41O9oITQDCxCvTzWfC4+SSJTn 1aN71HX0Ebj4QBKFXuI+XZ1QC0IfoJkRFlPEU141vDVg3N5aR4zrIDbDl+TdaJs+Tmsu 5xh6PbPHFwdtAezSrM3m+k+x8HxgKtmeIm74ZRWYGIIN6/kbqoK6fd5npd/mRwsN1RIR 5MM9AuHf6812Ak2Fe91mQwR9EiRZFgn7Z2DNp+3M7X6Ne2l7CfUW5ZMVWsbjKV5E9eEA R+IA== X-Gm-Message-State: AC+VfDzrpsSNK/iXAlLyhiT1tJiQOUJAWsJwrrTA7XDCuJohGF8v3BE7 epnRtvpBD2gbeD2tPFxyMSFNsaqHADmk X-Google-Smtp-Source: ACHHUZ5VDYBRqCpE+7NDQ4G2ZEezbOMBcHh+Ir9TRExIY49glMjSshqvWNyYOckRMiIyd5cc6/xCdM7zUbaI X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a81:bd0a:0:b0:54e:8b9a:65be with SMTP id b10-20020a81bd0a000000b0054e8b9a65bemr11452036ywi.6.1683067439742; Tue, 02 May 2023 15:43:59 -0700 (PDT) Date: Tue, 2 May 2023 15:38:47 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-41-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 40/44] perf vendor events intel: Correct alderlake metrics From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Fix the metrics tma_memory_bound on alderlake cpu_core and tma_microcode_sequencer on alderlake cpu_atom, where metrics had be rewritten across PMUs. Fix MEM_BOUND_STALLS_AT_RET_CORRECTION which is an aux metric but lacks a hash prefix. Add PMU prefixes for cpu_core/cpu_atom events to avoid wildcard opening the events. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- .../arch/x86/alderlake/adl-metrics.json | 238 +++++++++--------- .../arch/x86/alderlaken/adln-metrics.json | 6 +- 2 files changed, 122 insertions(+), 122 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json b/to= ols/perf/pmu-events/arch/x86/alderlake/adl-metrics.json index 4c2a14ea5a1c..840f6f6fc8c5 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json @@ -151,7 +151,7 @@ }, { "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend because allocation is stalled due to a misp= redicted jump or a machine clear", - "MetricExpr": "(tma_info_slots - (TOPDOWN_FE_BOUND.ALL + TOPDOWN_B= E_BOUND.ALL + TOPDOWN_RETIRING.ALL)) / tma_info_slots", + "MetricExpr": "(tma_info_slots - (cpu_atom@TOPDOWN_FE_BOUND.ALL@ += cpu_atom@TOPDOWN_BE_BOUND.ALL@ + cpu_atom@TOPDOWN_RETIRING.ALL@)) / tma_in= fo_slots", "MetricGroup": "TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", @@ -162,7 +162,7 @@ }, { "BriefDescription": "Counts the number of uops that are not from t= he microsequencer.", - "MetricExpr": "(TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS) / tma_info= _slots", + "MetricExpr": "(cpu_atom@TOPDOWN_RETIRING.ALL@ - cpu_atom@UOPS_RET= IRED.MS@) / tma_info_slots", "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", "MetricName": "tma_base", "MetricThreshold": "tma_base > 0.6", @@ -229,7 +229,7 @@ }, { "BriefDescription": "Counts the number of machine clears relative = to the number of nuke slots due to memory disambiguation.", - "MetricExpr": "tma_nuke * (MACHINE_CLEARS.DISAMBIGUATION / MACHINE= _CLEARS.SLOW)", + "MetricExpr": "tma_nuke * (cpu_atom@MACHINE_CLEARS.DISAMBIGUATION@= / cpu_atom@MACHINE_CLEARS.SLOW@)", "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", "MetricName": "tma_disambiguation", "MetricThreshold": "tma_disambiguation > 0.02", @@ -239,7 +239,7 @@ { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / tma_info_clks - ME= M_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOU= ND_STALLS.LOAD", + "MetricExpr": "cpu_atom@MEM_BOUND_STALLS.LOAD_DRAM_HIT@ / tma_info= _clks - max((cpu_atom@MEM_BOUND_STALLS.LOAD@ - cpu_atom@LD_HEAD.L1_MISS_AT_= RET@) / tma_info_clks, 0) * cpu_atom@MEM_BOUND_STALLS.LOAD_DRAM_HIT@ / cpu_= atom@MEM_BOUND_STALLS.LOAD@", "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_dram_bound", "MetricThreshold": "tma_dram_bound > 0.1", @@ -277,7 +277,7 @@ }, { "BriefDescription": "Counts the number of machine clears relative = to the number of nuke slots due to FP assists.", - "MetricExpr": "tma_nuke * (MACHINE_CLEARS.FP_ASSIST / MACHINE_CLEA= RS.SLOW)", + "MetricExpr": "tma_nuke * (cpu_atom@MACHINE_CLEARS.FP_ASSIST@ / cp= u_atom@MACHINE_CLEARS.SLOW@)", "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", "MetricName": "tma_fp_assist", "MetricThreshold": "tma_fp_assist > 0.02", @@ -314,7 +314,7 @@ }, { "BriefDescription": "Percentage of total non-speculative loads wit= h a address aliasing block", - "MetricExpr": "100 * LD_BLOCKS.4K_ALIAS / MEM_UOPS_RETIRED.ALL_LOA= DS", + "MetricExpr": "100 * cpu_atom@LD_BLOCKS.4K_ALIAS@ / MEM_UOPS_RETIR= ED.ALL_LOADS", "MetricName": "tma_info_address_alias_blocks", "Unit": "cpu_atom" }, @@ -334,14 +334,14 @@ }, { "BriefDescription": "", - "MetricExpr": "CPU_CLK_UNHALTED.CORE", + "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.CORE@", "MetricGroup": " ", "MetricName": "tma_info_clks", "Unit": "cpu_atom" }, { "BriefDescription": "", - "MetricExpr": "CPU_CLK_UNHALTED.CORE_P", + "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.CORE_P@", "MetricGroup": " ", "MetricName": "tma_info_clks_p", "Unit": "cpu_atom" @@ -383,35 +383,35 @@ }, { "BriefDescription": "Percentage of all uops which are FPDiv uops", - "MetricExpr": "100 * UOPS_RETIRED.FPDIV / UOPS_RETIRED.ALL", + "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.FPDIV@ / UOPS_RETIRED.A= LL", "MetricGroup": " ", "MetricName": "tma_info_fpdiv_uop_ratio", "Unit": "cpu_atom" }, { "BriefDescription": "Percentage of all uops which are IDiv uops", - "MetricExpr": "100 * UOPS_RETIRED.IDIV / UOPS_RETIRED.ALL", + "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.IDIV@ / UOPS_RETIRED.AL= L", "MetricGroup": " ", "MetricName": "tma_info_idiv_uop_ratio", "Unit": "cpu_atom" }, { "BriefDescription": "Percent of instruction miss cost that hit in = DRAM", - "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_DRAM_HIT / MEM_BOUND_= STALLS.IFETCH", + "MetricExpr": "100 * cpu_atom@MEM_BOUND_STALLS.IFETCH_DRAM_HIT@ / = cpu_atom@MEM_BOUND_STALLS.IFETCH@", "MetricGroup": " ", "MetricName": "tma_info_inst_miss_cost_dramhit_percent", "Unit": "cpu_atom" }, { "BriefDescription": "Percent of instruction miss cost that hit in = the L2", - "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_L2_HIT / MEM_BOUND_ST= ALLS.IFETCH", + "MetricExpr": "100 * cpu_atom@MEM_BOUND_STALLS.IFETCH_L2_HIT@ / cp= u_atom@MEM_BOUND_STALLS.IFETCH@", "MetricGroup": " ", "MetricName": "tma_info_inst_miss_cost_l2hit_percent", "Unit": "cpu_atom" }, { "BriefDescription": "Percent of instruction miss cost that hit in = the L3", - "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_LLC_HIT / MEM_BOUND_S= TALLS.IFETCH", + "MetricExpr": "100 * cpu_atom@MEM_BOUND_STALLS.IFETCH_LLC_HIT@ / c= pu_atom@MEM_BOUND_STALLS.IFETCH@", "MetricGroup": " ", "MetricName": "tma_info_inst_miss_cost_l3hit_percent", "Unit": "cpu_atom" @@ -439,7 +439,7 @@ }, { "BriefDescription": "Instructions per Far Branch", - "MetricExpr": "INST_RETIRED.ANY / (BR_INST_RETIRED.FAR_BRANCH / 2)= ", + "MetricExpr": "INST_RETIRED.ANY / (cpu_atom@BR_INST_RETIRED.FAR_BR= ANCH@ / 2)", "MetricGroup": " ", "MetricName": "tma_info_ipfarbranch", "Unit": "cpu_atom" @@ -453,7 +453,7 @@ }, { "BriefDescription": "Instructions per retired conditional Branch M= isprediction where the branch was not taken", - "MetricExpr": "INST_RETIRED.ANY / (BR_MISP_RETIRED.COND - BR_MISP_= RETIRED.COND_TAKEN)", + "MetricExpr": "INST_RETIRED.ANY / (cpu_atom@BR_MISP_RETIRED.COND@ = - cpu_atom@BR_MISP_RETIRED.COND_TAKEN@)", "MetricName": "tma_info_ipmisp_cond_ntaken", "Unit": "cpu_atom" }, @@ -498,20 +498,20 @@ }, { "BriefDescription": "Percentage of total non-speculative loads tha= t are splits", - "MetricExpr": "100 * MEM_UOPS_RETIRED.SPLIT_LOADS / MEM_UOPS_RETIR= ED.ALL_LOADS", + "MetricExpr": "100 * cpu_atom@MEM_UOPS_RETIRED.SPLIT_LOADS@ / MEM_= UOPS_RETIRED.ALL_LOADS", "MetricName": "tma_info_load_splits", "Unit": "cpu_atom" }, { "BriefDescription": "load ops retired per 1000 instruction", - "MetricExpr": "1e3 * MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY= ", + "MetricExpr": "1e3 * cpu_atom@MEM_UOPS_RETIRED.ALL_LOADS@ / INST_R= ETIRED.ANY", "MetricGroup": " ", "MetricName": "tma_info_memloadpki", "Unit": "cpu_atom" }, { "BriefDescription": "Percentage of all uops which are ucode ops", - "MetricExpr": "100 * UOPS_RETIRED.MS / UOPS_RETIRED.ALL", + "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.MS@ / UOPS_RETIRED.ALL", "MetricGroup": " ", "MetricName": "tma_info_microcode_uop_ratio", "Unit": "cpu_atom" @@ -525,7 +525,7 @@ }, { "BriefDescription": "Percentage of total non-speculative loads wit= h a store forward or unknown store address block", - "MetricExpr": "100 * LD_BLOCKS.DATA_UNKNOWN / MEM_UOPS_RETIRED.ALL= _LOADS", + "MetricExpr": "100 * cpu_atom@LD_BLOCKS.DATA_UNKNOWN@ / MEM_UOPS_R= ETIRED.ALL_LOADS", "MetricName": "tma_info_store_fwd_blocks", "Unit": "cpu_atom" }, @@ -545,7 +545,7 @@ }, { "BriefDescription": "Percentage of all uops which are x87 uops", - "MetricExpr": "100 * UOPS_RETIRED.X87 / UOPS_RETIRED.ALL", + "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.X87@ / UOPS_RETIRED.ALL= ", "MetricGroup": " ", "MetricName": "tma_info_x87_uop_ratio", "Unit": "cpu_atom" @@ -571,7 +571,7 @@ { "BriefDescription": "Counts the number of cycles a core is stalled= due to a demand load which hit in the L2 Cache.", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / tma_info_clks - MEM_= BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_S= TALLS.LOAD", + "MetricExpr": "cpu_atom@MEM_BOUND_STALLS.LOAD_L2_HIT@ / tma_info_c= lks - max((cpu_atom@MEM_BOUND_STALLS.LOAD@ - cpu_atom@LD_HEAD.L1_MISS_AT_RE= T@) / tma_info_clks, 0) * cpu_atom@MEM_BOUND_STALLS.LOAD_L2_HIT@ / cpu_atom= @MEM_BOUND_STALLS.LOAD@", "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l2_bound", "MetricThreshold": "tma_l2_bound > 0.1", @@ -580,7 +580,7 @@ }, { "BriefDescription": "Counts the number of cycles a core is stalled= due to a demand load which hit in the Last Level Cache (LLC) or other core= with HITE/F/M.", - "MetricExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / tma_info_clks - MEM= _BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND= _STALLS.LOAD", + "MetricExpr": "cpu_atom@MEM_BOUND_STALLS.LOAD_LLC_HIT@ / tma_info_= clks - max((cpu_atom@MEM_BOUND_STALLS.LOAD@ - cpu_atom@LD_HEAD.L1_MISS_AT_R= ET@) / tma_info_clks, 0) * cpu_atom@MEM_BOUND_STALLS.LOAD_LLC_HIT@ / cpu_at= om@MEM_BOUND_STALLS.LOAD@", "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l3_bound", "MetricThreshold": "tma_l3_bound > 0.1", @@ -589,7 +589,7 @@ }, { "BriefDescription": "Counts the number of cycles, relative to the = number of mem_scheduler slots, in which uops are blocked due to load buffer= full", - "MetricExpr": "tma_mem_scheduler * MEM_SCHEDULER_BLOCK.LD_BUF / ME= M_SCHEDULER_BLOCK.ALL", + "MetricExpr": "tma_mem_scheduler * cpu_atom@MEM_SCHEDULER_BLOCK.LD= _BUF@ / MEM_SCHEDULER_BLOCK.ALL", "MetricGroup": "TopdownL4;tma_L4_group;tma_mem_scheduler_group", "MetricName": "tma_ld_buffer", "MetricThreshold": "tma_ld_buffer > 0.05", @@ -617,7 +617,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to stores or loads.", - "MetricExpr": "min(tma_backend_bound, LD_HEAD.ANY_AT_RET / tma_inf= o_clks + tma_store_bound)", + "MetricExpr": "min(cpu_atom@TOPDOWN_BE_BOUND.ALL@ / tma_info_slots= , cpu_atom@LD_HEAD.ANY_AT_RET@ / tma_info_clks + tma_store_bound)", "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2", @@ -627,7 +627,7 @@ }, { "BriefDescription": "Counts the number of machine clears relative = to the number of nuke slots due to memory ordering.", - "MetricExpr": "tma_nuke * (MACHINE_CLEARS.MEMORY_ORDERING / MACHIN= E_CLEARS.SLOW)", + "MetricExpr": "tma_nuke * (cpu_atom@MACHINE_CLEARS.MEMORY_ORDERING= @ / cpu_atom@MACHINE_CLEARS.SLOW@)", "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", "MetricName": "tma_memory_ordering", "MetricThreshold": "tma_memory_ordering > 0.02", @@ -636,7 +636,7 @@ }, { "BriefDescription": "Counts the number of uops that are from the c= omplex flows issued by the micro-sequencer (MS)", - "MetricExpr": "tma_microcode_sequencer", + "MetricExpr": "UOPS_RETIRED.MS / tma_info_slots", "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", "MetricName": "tma_ms_uops", "MetricThreshold": "tma_ms_uops > 0.05", @@ -692,7 +692,7 @@ }, { "BriefDescription": "Counts the number of uops retired excluding m= s and fp div uops.", - "MetricExpr": "(TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS - UOPS_RETI= RED.FPDIV) / tma_info_slots", + "MetricExpr": "(cpu_atom@TOPDOWN_RETIRING.ALL@ - cpu_atom@UOPS_RET= IRED.MS@ - cpu_atom@UOPS_RETIRED.FPDIV@) / tma_info_slots", "MetricGroup": "TopdownL3;tma_L3_group;tma_base_group", "MetricName": "tma_other_ret", "MetricThreshold": "tma_other_ret > 0.3", @@ -701,7 +701,7 @@ }, { "BriefDescription": "Counts the number of machine clears relative = to the number of nuke slots due to page faults.", - "MetricExpr": "tma_nuke * (MACHINE_CLEARS.PAGE_FAULT / MACHINE_CLE= ARS.SLOW)", + "MetricExpr": "tma_nuke * (cpu_atom@MACHINE_CLEARS.PAGE_FAULT@ / c= pu_atom@MACHINE_CLEARS.SLOW@)", "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", "MetricName": "tma_page_fault", "MetricThreshold": "tma_page_fault > 0.02", @@ -758,7 +758,7 @@ }, { "BriefDescription": "Counts the number of cycles, relative to the = number of mem_scheduler slots, in which uops are blocked due to RSV full re= lative", - "MetricExpr": "tma_mem_scheduler * MEM_SCHEDULER_BLOCK.RSV / MEM_S= CHEDULER_BLOCK.ALL", + "MetricExpr": "tma_mem_scheduler * cpu_atom@MEM_SCHEDULER_BLOCK.RS= V@ / MEM_SCHEDULER_BLOCK.ALL", "MetricGroup": "TopdownL4;tma_L4_group;tma_mem_scheduler_group", "MetricName": "tma_rsv", "MetricThreshold": "tma_rsv > 0.05", @@ -776,7 +776,7 @@ }, { "BriefDescription": "Counts the number of machine clears relative = to the number of nuke slots due to SMC.", - "MetricExpr": "tma_nuke * (MACHINE_CLEARS.SMC / MACHINE_CLEARS.SLO= W)", + "MetricExpr": "tma_nuke * (cpu_atom@MACHINE_CLEARS.SMC@ / cpu_atom= @MACHINE_CLEARS.SLOW@)", "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", "MetricName": "tma_smc", "MetricThreshold": "tma_smc > 0.02", @@ -812,7 +812,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to store buffer full.", - "MetricExpr": "tma_mem_scheduler * (MEM_SCHEDULER_BLOCK.ST_BUF / M= EM_SCHEDULER_BLOCK.ALL)", + "MetricExpr": "tma_mem_scheduler * (cpu_atom@MEM_SCHEDULER_BLOCK.S= T_BUF@ / cpu_atom@MEM_SCHEDULER_BLOCK.ALL@)", "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_store_bound", "MetricThreshold": "tma_store_bound > 0.1", @@ -830,7 +830,7 @@ }, { "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution ports for ALU operations.", - "MetricExpr": "(UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + = UOPS_DISPATCHED.PORT_5_11 + UOPS_DISPATCHED.PORT_6) / (5 * tma_info_core_cl= ks)", + "MetricExpr": "(cpu_core@UOPS_DISPATCHED.PORT_0@ + cpu_core@UOPS_D= ISPATCHED.PORT_1@ + cpu_core@UOPS_DISPATCHED.PORT_5_11@ + cpu_core@UOPS_DIS= PATCHED.PORT_6@) / (5 * tma_info_core_clks)", "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group= ", "MetricName": "tma_alu_op_utilization", "MetricThreshold": "tma_alu_op_utilization > 0.6", @@ -849,7 +849,7 @@ }, { "BriefDescription": "This metric estimates fraction of slots the C= PU retired uops as a result of handing SSE to AVX* or AVX* to SSE transitio= n Assists.", - "MetricExpr": "63 * ASSISTS.SSE_AVX_MIX / tma_info_slots", + "MetricExpr": "63 * cpu_core@ASSISTS.SSE_AVX_MIX@ / tma_info_slots= ", "MetricGroup": "HPC;TopdownL5;tma_L5_group;tma_assists_group", "MetricName": "tma_avx_assists", "MetricThreshold": "tma_avx_assists > 0.1", @@ -858,7 +858,7 @@ }, { "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", - "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topd= own\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_inf= o_slots", + "MetricExpr": "cpu_core@topdown\\-be\\-bound@ / (cpu_core@topdown\= \-fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ + cpu_core@topdown\\-retirin= g@ + cpu_core@topdown\\-be\\-bound@) + 0 * tma_info_slots", "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", @@ -880,7 +880,7 @@ }, { "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Branch Misprediction", - "MetricExpr": "topdown\\-br\\-mispredict / (topdown\\-fe\\-bound += topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tm= a_info_slots", + "MetricExpr": "cpu_core@topdown\\-br\\-mispredict@ / (cpu_core@top= down\\-fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ + cpu_core@topdown\\-re= tiring@ + cpu_core@topdown\\-be\\-bound@) + 0 * tma_info_slots", "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", @@ -911,7 +911,7 @@ }, { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Branch Resteers as a result of Machine Clears", - "MetricExpr": "(1 - tma_branch_mispredicts / tma_bad_speculation) = * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_clks", + "MetricExpr": "(1 - tma_branch_mispredicts / tma_bad_speculation) = * cpu_core@INT_MISC.CLEAR_RESTEER_CYCLES@ / tma_info_clks", "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_b= ranch_resteers_group;tma_issueMC", "MetricName": "tma_clears_resteers", "MetricThreshold": "tma_clears_resteers > 0.05 & (tma_branch_reste= ers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", @@ -922,7 +922,7 @@ { "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to contested acces= ses", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "(25 * tma_info_average_frequency * (MEM_LOAD_L3_HIT= _RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DAT= A_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + = 24 * tma_info_average_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 += MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricExpr": "(25 * tma_info_average_frequency * (cpu_core@MEM_LO= AD_L3_HIT_RETIRED.XSNP_FWD@ * (cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT= M@ / (cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM@ + cpu_core@OCR.DEMAND_= DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD@))) + 24 * tma_info_average_frequency * c= pu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS@) * (1 + cpu_core@MEM_LOAD_RETIRE= D.FB_HIT@ / cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / 2) / tma_info_clks", "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_l3_bound_group", "MetricName": "tma_contested_accesses", "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound = > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", @@ -944,7 +944,7 @@ { "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to data-sharing ac= cesses", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "24 * tma_info_average_frequency * (MEM_LOAD_L3_HIT_= RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - OCR.DEMAND_DA= TA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAN= D_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM= _LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricExpr": "24 * tma_info_average_frequency * (cpu_core@MEM_LOA= D_L3_HIT_RETIRED.XSNP_NO_FWD@ + cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD@ = * (1 - cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM@ / (cpu_core@OCR.DEMAN= D_DATA_RD.L3_HIT.SNOOP_HITM@ + cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT= _WITH_FWD@))) * (1 + cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / cpu_core@MEM_LOAD_= RETIRED.L1_MISS@ / 2) / tma_info_clks", "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSync= xn;tma_l3_bound_group", "MetricName": "tma_data_sharing", "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", @@ -975,7 +975,7 @@ { "BriefDescription": "This metric estimates how often the CPU was s= talled on accesses to external memory (DRAM) by loads", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "MEMORY_ACTIVITY.STALLS_L3_MISS / tma_info_clks", + "MetricExpr": "cpu_core@MEMORY_ACTIVITY.STALLS_L3_MISS@ / tma_info= _clks", "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_me= mory_bound_group", "MetricName": "tma_dram_bound", "MetricThreshold": "tma_dram_bound > 0.1 & (tma_memory_bound > 0.2= & tma_backend_bound > 0.2)", @@ -985,7 +985,7 @@ }, { "BriefDescription": "This metric represents Core fraction of cycle= s in which CPU was likely limited due to DSB (decoded uop cache) fetch pipe= line", - "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / tma_info= _core_clks / 2", + "MetricExpr": "(cpu_core@IDQ.DSB_CYCLES_ANY@ - cpu_core@IDQ.DSB_CY= CLES_OK@) / tma_info_core_clks / 2", "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandw= idth_group", "MetricName": "tma_dsb", "MetricThreshold": "tma_dsb > 0.15 & (tma_fetch_bandwidth > 0.1 & = tma_frontend_bound > 0.15 & tma_info_ipc / 6 > 0.35)", @@ -1005,7 +1005,7 @@ }, { "BriefDescription": "This metric roughly estimates the fraction of= cycles where the Data TLB (DTLB) was missed by load accesses", - "MetricExpr": "min(7 * cpu_core@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\= \=3D1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - = MEMORY_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_clks", + "MetricExpr": "min(7 * cpu_core@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\= \=3D1@ + cpu_core@DTLB_LOAD_MISSES.WALK_ACTIVE@, max(cpu_core@CYCLE_ACTIVIT= Y.CYCLES_MEM_ANY@ - cpu_core@MEMORY_ACTIVITY.CYCLES_L1D_MISS@, 0)) / tma_in= fo_clks", "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= l1_bound_group", "MetricName": "tma_dtlb_load", "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (t= ma_memory_bound > 0.2 & tma_backend_bound > 0.2))", @@ -1015,7 +1015,7 @@ }, { "BriefDescription": "This metric roughly estimates the fraction of= cycles spent handling first-level data TLB store misses", - "MetricExpr": "(7 * cpu_core@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\= =3D1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / tma_info_core_clks", + "MetricExpr": "(7 * cpu_core@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\= =3D1@ + cpu_core@DTLB_STORE_MISSES.WALK_ACTIVE@) / tma_info_core_clks", "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= store_bound_group", "MetricName": "tma_dtlb_store", "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", @@ -1025,7 +1025,7 @@ }, { "BriefDescription": "This metric roughly estimates how often CPU w= as handling synchronizations due to False Sharing", - "MetricExpr": "28 * tma_info_average_frequency * OCR.DEMAND_RFO.L3= _HIT.SNOOP_HITM / tma_info_clks", + "MetricExpr": "28 * tma_info_average_frequency * cpu_core@OCR.DEMA= ND_RFO.L3_HIT.SNOOP_HITM@ / tma_info_clks", "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_store_bound_group", "MetricName": "tma_false_sharing", "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > = 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", @@ -1056,7 +1056,7 @@ }, { "BriefDescription": "This metric represents fraction of slots the = CPU was stalled due to Frontend latency issues", - "MetricExpr": "topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + top= down\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.U= OP_DROPPING / tma_info_slots", + "MetricExpr": "cpu_core@topdown\\-fetch\\-lat@ / (cpu_core@topdown= \\-fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ + cpu_core@topdown\\-retiri= ng@ + cpu_core@topdown\\-be\\-bound@) - cpu_core@INT_MISC.UOP_DROPPING@ / t= ma_info_slots", "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", @@ -1088,7 +1088,7 @@ }, { "BriefDescription": "This metric roughly estimates fraction of slo= ts the CPU retired uops as a result of handing Floating Point (FP) Assists", - "MetricExpr": "30 * ASSISTS.FP / tma_info_slots", + "MetricExpr": "30 * cpu_core@ASSISTS.FP@ / tma_info_slots", "MetricGroup": "HPC;TopdownL5;tma_L5_group;tma_assists_group", "MetricName": "tma_fp_assists", "MetricThreshold": "tma_fp_assists > 0.1", @@ -1118,7 +1118,7 @@ }, { "BriefDescription": "This metric approximates arithmetic FP vector= uops fraction the CPU has retired for 128-bit wide vectors", - "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARIT= H_INST_RETIRED.128B_PACKED_SINGLE) / (tma_retiring * tma_info_slots)", + "MetricExpr": "(cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE@= + cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE@) / (tma_retiring * tm= a_info_slots)", "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector= _group;tma_issue2P", "MetricName": "tma_fp_vector_128b", "MetricThreshold": "tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.= 1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", @@ -1128,7 +1128,7 @@ }, { "BriefDescription": "This metric approximates arithmetic FP vector= uops fraction the CPU has retired for 256-bit wide vectors", - "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARIT= H_INST_RETIRED.256B_PACKED_SINGLE) / (tma_retiring * tma_info_slots)", + "MetricExpr": "(cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE@= + cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE@) / (tma_retiring * tm= a_info_slots)", "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector= _group;tma_issue2P", "MetricName": "tma_fp_vector_256b", "MetricThreshold": "tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.= 1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", @@ -1138,7 +1138,7 @@ }, { "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", - "MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topd= own\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UO= P_DROPPING / tma_info_slots", + "MetricExpr": "cpu_core@topdown\\-fe\\-bound@ / (cpu_core@topdown\= \-fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ + cpu_core@topdown\\-retirin= g@ + cpu_core@topdown\\-be\\-bound@) - cpu_core@INT_MISC.UOP_DROPPING@ / tm= a_info_slots", "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", @@ -1149,7 +1149,7 @@ }, { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring fused instructions -- where one uop can represent mu= ltiple contiguous instructions", - "MetricExpr": "tma_light_operations * INST_RETIRED.MACRO_FUSED / (= tma_retiring * tma_info_slots)", + "MetricExpr": "tma_light_operations * cpu_core@INST_RETIRED.MACRO_= FUSED@ / (tma_retiring * tma_info_slots)", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", "MetricName": "tma_fused_instructions", "MetricThreshold": "tma_fused_instructions > 0.1 & tma_light_opera= tions > 0.6", @@ -1159,7 +1159,7 @@ }, { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring heavy-weight operations -- instructions that require= two or more uops or micro-coded sequences", - "MetricExpr": "topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + top= down\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_in= fo_slots", + "MetricExpr": "cpu_core@topdown\\-heavy\\-ops@ / (cpu_core@topdown= \\-fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ + cpu_core@topdown\\-retiri= ng@ + cpu_core@topdown\\-be\\-bound@) + 0 * tma_info_slots", "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", @@ -1213,7 +1213,7 @@ }, { "BriefDescription": "Total pipeline cost of branch related instruc= tions (used for program control-flow including function calls)", - "MetricExpr": "100 * ((BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED.= NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * = BR_INST_RETIRED.NEAR_CALL)) / tma_info_slots)", + "MetricExpr": "100 * ((cpu_core@BR_INST_RETIRED.COND@ + 3 * cpu_co= re@BR_INST_RETIRED.NEAR_CALL@ + (cpu_core@BR_INST_RETIRED.NEAR_TAKEN@ - cpu= _core@BR_INST_RETIRED.COND_TAKEN@ - 2 * cpu_core@BR_INST_RETIRED.NEAR_CALL@= )) / tma_info_slots)", "MetricGroup": "Ret;tma_issueBC", "MetricName": "tma_info_branching_overhead", "MetricThreshold": "tma_info_branching_overhead > 10", @@ -1222,21 +1222,21 @@ }, { "BriefDescription": "Fraction of branches that are CALL or RET", - "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_R= ETURN) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricExpr": "(cpu_core@BR_INST_RETIRED.NEAR_CALL@ + cpu_core@BR_= INST_RETIRED.NEAR_RETURN@) / BR_INST_RETIRED.ALL_BRANCHES", "MetricGroup": "Bad;Branches", "MetricName": "tma_info_callret", "Unit": "cpu_core" }, { "BriefDescription": "Per-Logical Processor actual clocks when the = Logical Processor is active.", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD", + "MetricExpr": "cpu_core@CPU_CLK_UNHALTED.THREAD@", "MetricGroup": "Pipeline", "MetricName": "tma_info_clks", "Unit": "cpu_core" }, { "BriefDescription": "STLB (2nd level TLB) code speculative misses = per kilo instruction (misses of any page-size that complete the page walk)", - "MetricExpr": "1e3 * ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY= ", + "MetricExpr": "1e3 * cpu_core@ITLB_MISSES.WALK_COMPLETED@ / INST_R= ETIRED.ANY", "MetricGroup": "Fed;MemoryTLB", "MetricName": "tma_info_code_stlb_mpki", "Unit": "cpu_core" @@ -1266,7 +1266,7 @@ }, { "BriefDescription": "Core actual clocks when any Logical Processor= is active on the Physical Core", - "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED", + "MetricExpr": "cpu_core@CPU_CLK_UNHALTED.DISTRIBUTED@", "MetricGroup": "SMT", "MetricName": "tma_info_core_clks", "Unit": "cpu_core" @@ -1309,7 +1309,7 @@ }, { "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / UOPS_ISSUED.ANY", + "MetricExpr": "IDQ.DSB_UOPS / cpu_core@UOPS_ISSUED.ANY@", "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", "MetricName": "tma_info_dsb_coverage", "MetricThreshold": "tma_info_dsb_coverage < 0.7 & tma_info_ipc / 6= > 0.35", @@ -1350,7 +1350,7 @@ }, { "BriefDescription": "Fill Buffer (FB) hits per kilo instructions f= or retired demand loads (L1D misses that merge into ongoing miss-handling e= ntries)", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", + "MetricExpr": "1e3 * cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / INST_RETI= RED.ANY", "MetricGroup": "CacheMisses;Mem", "MetricName": "tma_info_fb_hpki", "Unit": "cpu_core" @@ -1365,7 +1365,7 @@ { "BriefDescription": "Floating Point Operations Per Cycle", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INS= T_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 = * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PA= CKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / tma_info_cor= e_clks", + "MetricExpr": "(cpu_core@FP_ARITH_INST_RETIRED.SCALAR_SINGLE@ + cp= u_core@FP_ARITH_INST_RETIRED.SCALAR_DOUBLE@ + 2 * cpu_core@FP_ARITH_INST_RE= TIRED.128B_PACKED_DOUBLE@ + 4 * (cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED= _SINGLE@ + cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE@) + 8 * cpu_co= re@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE@) / tma_info_core_clks", "MetricGroup": "Flops;Ret", "MetricName": "tma_info_flopc", "Unit": "cpu_core" @@ -1373,7 +1373,7 @@ { "BriefDescription": "Actual per-core usage of the Floating Point n= on-X87 execution units (regardless of precision or vector-width)", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "(FP_ARITH_DISPATCHED.PORT_0 + FP_ARITH_DISPATCHED.P= ORT_1 + FP_ARITH_DISPATCHED.PORT_5) / (2 * tma_info_core_clks)", + "MetricExpr": "(cpu_core@FP_ARITH_DISPATCHED.PORT_0@ + cpu_core@FP= _ARITH_DISPATCHED.PORT_1@ + cpu_core@FP_ARITH_DISPATCHED.PORT_5@) / (2 * tm= a_info_core_clks)", "MetricGroup": "Cor;Flops;HPC", "MetricName": "tma_info_fp_arith_utilization", "PublicDescription": "Actual per-core usage of the Floating Point = non-X87 execution units (regardless of precision or vector-width). Values >= 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; = [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less commo= n).", @@ -1381,7 +1381,7 @@ }, { "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INS= T_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 = * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PA= CKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / durati= on_time", + "MetricExpr": "(cpu_core@FP_ARITH_INST_RETIRED.SCALAR_SINGLE@ + cp= u_core@FP_ARITH_INST_RETIRED.SCALAR_DOUBLE@ + 2 * cpu_core@FP_ARITH_INST_RE= TIRED.128B_PACKED_DOUBLE@ + 4 * (cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED= _SINGLE@ + cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE@) + 8 * cpu_co= re@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE@) / 1e9 / duration_time", "MetricGroup": "Cor;Flops;HPC", "MetricName": "tma_info_gflops", "PublicDescription": "Giga Floating Point Operations Per Second. A= ggregate across all supported options of: FP precisions, scalar and vector = instructions, vector-width and AMX engine.", @@ -1405,7 +1405,7 @@ }, { "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per-core", - "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_G= E_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", + "MetricExpr": "UOPS_EXECUTED.THREAD / (cpu_core@UOPS_EXECUTED.CORE= _CYCLES_GE_1@ / 2 if #SMT_on else cpu_core@UOPS_EXECUTED.CORE_CYCLES_GE_1@)= ", "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "tma_info_ilp", "Unit": "cpu_core" @@ -1421,7 +1421,7 @@ }, { "BriefDescription": "Total number of retired Instructions", - "MetricExpr": "INST_RETIRED.ANY", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@", "MetricGroup": "Summary;TmaL1;tma_L1_group", "MetricName": "tma_info_instructions", "PublicDescription": "Total number of retired Instructions. Sample= with: INST_RETIRED.PREC_DIST", @@ -1438,7 +1438,7 @@ }, { "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bi= t instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACK= ED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)", + "MetricExpr": "INST_RETIRED.ANY / (cpu_core@FP_ARITH_INST_RETIRED.= 128B_PACKED_DOUBLE@ + cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE@)", "MetricGroup": "Flops;FpVector;InsType", "MetricName": "tma_info_iparith_avx128", "MetricThreshold": "tma_info_iparith_avx128 < 10", @@ -1447,7 +1447,7 @@ }, { "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit i= nstruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACK= ED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", + "MetricExpr": "INST_RETIRED.ANY / (cpu_core@FP_ARITH_INST_RETIRED.= 256B_PACKED_DOUBLE@ + cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE@)", "MetricGroup": "Flops;FpVector;InsType", "MetricName": "tma_info_iparith_avx256", "MetricThreshold": "tma_info_iparith_avx256 < 10", @@ -1514,7 +1514,7 @@ }, { "BriefDescription": "Instructions per Far Branch ( Far Branches ap= ply upon transition from application to operating system, handling interrup= ts, exceptions) [lower number means higher occurrence rate]", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricExpr": "INST_RETIRED.ANY / cpu_core@BR_INST_RETIRED.FAR_BRA= NCH@u", "MetricGroup": "Branches;OS", "MetricName": "tma_info_ipfarbranch", "MetricThreshold": "tma_info_ipfarbranch < 1e6", @@ -1522,7 +1522,7 @@ }, { "BriefDescription": "Instructions per Floating Point (FP) Operatio= n (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SI= NGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B= _PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_I= NST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SIN= GLE)", + "MetricExpr": "INST_RETIRED.ANY / (cpu_core@FP_ARITH_INST_RETIRED.= SCALAR_SINGLE@ + cpu_core@FP_ARITH_INST_RETIRED.SCALAR_DOUBLE@ + 2 * cpu_co= re@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE@ + 4 * (cpu_core@FP_ARITH_INST_= RETIRED.128B_PACKED_SINGLE@ + cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_DO= UBLE@) + 8 * cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE@)", "MetricGroup": "Flops;InsType", "MetricName": "tma_info_ipflop", "MetricThreshold": "tma_info_ipflop < 10", @@ -1610,14 +1610,14 @@ }, { "BriefDescription": "Fraction of branches that are unconditional (= direct or indirect) jumps", - "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_= TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricExpr": "(cpu_core@BR_INST_RETIRED.NEAR_TAKEN@ - cpu_core@BR= _INST_RETIRED.COND_TAKEN@ - 2 * cpu_core@BR_INST_RETIRED.NEAR_CALL@) / BR_I= NST_RETIRED.ALL_BRANCHES", "MetricGroup": "Bad;Branches", "MetricName": "tma_info_jump", "Unit": "cpu_core" }, { "BriefDescription": "Cycles Per Instruction for the Operating Syst= em (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / cpu_core@INST_RETIRED= .ANY_P@k", "MetricGroup": "OS", "MetricName": "tma_info_kernel_cpi", "Unit": "cpu_core" @@ -1632,7 +1632,7 @@ }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", + "MetricExpr": "64 * cpu_core@L1D.REPLACEMENT@ / 1e9 / duration_tim= e", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_l1d_cache_fill_bw", "Unit": "cpu_core" @@ -1646,21 +1646,21 @@ }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricExpr": "1e3 * cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / INST_RET= IRED.ANY", "MetricGroup": "CacheMisses;Mem", "MetricName": "tma_info_l1mpki", "Unit": "cpu_core" }, { "BriefDescription": "L1 cache true misses per kilo instruction for= all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.AN= Y", + "MetricExpr": "1e3 * cpu_core@L2_RQSTS.ALL_DEMAND_DATA_RD@ / INST_= RETIRED.ANY", "MetricGroup": "CacheMisses;Mem", "MetricName": "tma_info_l1mpki_load", "Unit": "cpu_core" }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 2 cache [GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", + "MetricExpr": "64 * cpu_core@L2_LINES_IN.ALL@ / 1e9 / duration_tim= e", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_l2_cache_fill_bw", "Unit": "cpu_core" @@ -1674,56 +1674,56 @@ }, { "BriefDescription": "L2 cache hits per kilo instruction for all re= quest types (including speculative)", - "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_= RETIRED.ANY", + "MetricExpr": "1e3 * (cpu_core@L2_RQSTS.REFERENCES@ - cpu_core@L2_= RQSTS.MISS@) / INST_RETIRED.ANY", "MetricGroup": "CacheMisses;Mem", "MetricName": "tma_info_l2hpki_all", "Unit": "cpu_core" }, { "BriefDescription": "L2 cache hits per kilo instruction for all de= mand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.AN= Y", + "MetricExpr": "1e3 * cpu_core@L2_RQSTS.DEMAND_DATA_RD_HIT@ / INST_= RETIRED.ANY", "MetricGroup": "CacheMisses;Mem", "MetricName": "tma_info_l2hpki_load", "Unit": "cpu_core" }, { "BriefDescription": "L2 cache true misses per kilo instruction for= retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricExpr": "1e3 * cpu_core@MEM_LOAD_RETIRED.L2_MISS@ / INST_RET= IRED.ANY", "MetricGroup": "Backend;CacheMisses;Mem", "MetricName": "tma_info_l2mpki", "Unit": "cpu_core" }, { "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instru= ction for all request types (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY", + "MetricExpr": "1e3 * cpu_core@L2_RQSTS.MISS@ / INST_RETIRED.ANY", "MetricGroup": "CacheMisses;Mem;Offcore", "MetricName": "tma_info_l2mpki_all", "Unit": "cpu_core" }, { "BriefDescription": "L2 cache true code cacheline misses per kilo = instruction", - "MetricExpr": "1e3 * FRONTEND_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricExpr": "1e3 * cpu_core@FRONTEND_RETIRED.L2_MISS@ / INST_RET= IRED.ANY", "MetricGroup": "IcMiss", "MetricName": "tma_info_l2mpki_code", "Unit": "cpu_core" }, { "BriefDescription": "L2 cache speculative code cacheline misses pe= r kilo instruction", - "MetricExpr": "1e3 * L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", + "MetricExpr": "1e3 * cpu_core@L2_RQSTS.CODE_RD_MISS@ / INST_RETIRE= D.ANY", "MetricGroup": "IcMiss", "MetricName": "tma_info_l2mpki_code_all", "Unit": "cpu_core" }, { "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instru= ction for all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.A= NY", + "MetricExpr": "1e3 * cpu_core@L2_RQSTS.DEMAND_DATA_RD_MISS@ / INST= _RETIRED.ANY", "MetricGroup": "CacheMisses;Mem", "MetricName": "tma_info_l2mpki_load", "Unit": "cpu_core" }, { "BriefDescription": "Average per-core data access bandwidth to the= L3 cache [GB / sec]", - "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration= _time", + "MetricExpr": "64 * cpu_core@OFFCORE_REQUESTS.ALL_REQUESTS@ / 1e9 = / duration_time", "MetricGroup": "Mem;MemoryBW;Offcore", "MetricName": "tma_info_l3_cache_access_bw", "Unit": "cpu_core" @@ -1737,7 +1737,7 @@ }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", + "MetricExpr": "64 * cpu_core@LONGEST_LAT_CACHE.MISS@ / 1e9 / durat= ion_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_l3_cache_fill_bw", "Unit": "cpu_core" @@ -1751,7 +1751,7 @@ }, { "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", + "MetricExpr": "1e3 * cpu_core@MEM_LOAD_RETIRED.L3_MISS@ / INST_RET= IRED.ANY", "MetricGroup": "CacheMisses;Mem", "MetricName": "tma_info_l3mpki", "Unit": "cpu_core" @@ -1786,14 +1786,14 @@ }, { "BriefDescription": "STLB (2nd level TLB) data load speculative mi= sses per kilo instruction (misses of any page-size that complete the page w= alk)", - "MetricExpr": "1e3 * DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRE= D.ANY", + "MetricExpr": "1e3 * cpu_core@DTLB_LOAD_MISSES.WALK_COMPLETED@ / I= NST_RETIRED.ANY", "MetricGroup": "Mem;MemoryTLB", "MetricName": "tma_info_load_stlb_mpki", "Unit": "cpu_core" }, { "BriefDescription": "Fraction of Uops delivered by the LSD (Loop S= tream Detector; aka Loop Cache)", - "MetricExpr": "LSD.UOPS / UOPS_ISSUED.ANY", + "MetricExpr": "LSD.UOPS / cpu_core@UOPS_ISSUED.ANY@", "MetricGroup": "Fed;LSD", "MetricName": "tma_info_lsd_coverage", "Unit": "cpu_core" @@ -1877,7 +1877,7 @@ }, { "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_P= ENDING + DTLB_STORE_MISSES.WALK_PENDING) / (4 * tma_info_core_clks)", + "MetricExpr": "(cpu_core@ITLB_MISSES.WALK_PENDING@ + cpu_core@DTLB= _LOAD_MISSES.WALK_PENDING@ + cpu_core@DTLB_STORE_MISSES.WALK_PENDING@) / (4= * tma_info_core_clks)", "MetricGroup": "Mem;MemoryTLB", "MetricName": "tma_info_page_walks_utilization", "MetricThreshold": "tma_info_page_walks_utilization > 0.5", @@ -1893,21 +1893,21 @@ }, { "BriefDescription": "Total issue-pipeline slots (per-Physical Core= till ICL; per-Logical Processor ICL onward)", - "MetricExpr": "TOPDOWN.SLOTS", + "MetricExpr": "cpu_core@TOPDOWN.SLOTS@", "MetricGroup": "TmaL1;tma_L1_group", "MetricName": "tma_info_slots", "Unit": "cpu_core" }, { "BriefDescription": "Fraction of Physical Core issue-slots utilize= d by this Logical Processor", - "MetricExpr": "(tma_info_slots / (TOPDOWN.SLOTS / 2) if #SMT_on el= se 1)", + "MetricExpr": "(tma_info_slots / (cpu_core@TOPDOWN.SLOTS@ / 2) if = #SMT_on else 1)", "MetricGroup": "SMT;TmaL1;tma_L1_group", "MetricName": "tma_info_slots_utilization", "Unit": "cpu_core" }, { "BriefDescription": "Fraction of cycles where both hardware Logica= l Processors were active", - "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_U= NHALTED.REF_DISTRIBUTED if #SMT_on else 0)", + "MetricExpr": "(1 - cpu_core@CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE@ /= cpu_core@CPU_CLK_UNHALTED.REF_DISTRIBUTED@ if #SMT_on else 0)", "MetricGroup": "SMT", "MetricName": "tma_info_smt_2t_utilization", "Unit": "cpu_core" @@ -1921,7 +1921,7 @@ }, { "BriefDescription": "STLB (2nd level TLB) data store speculative m= isses per kilo instruction (misses of any page-size that complete the page = walk)", - "MetricExpr": "1e3 * DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIR= ED.ANY", + "MetricExpr": "1e3 * cpu_core@DTLB_STORE_MISSES.WALK_COMPLETED@ / = INST_RETIRED.ANY", "MetricGroup": "Mem;MemoryTLB", "MetricName": "tma_info_store_stlb_mpki", "Unit": "cpu_core" @@ -1969,7 +1969,7 @@ }, { "BriefDescription": "This metric represents 128-bit vector Integer= ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the= CPU has retired", - "MetricExpr": "(INT_VEC_RETIRED.ADD_128 + INT_VEC_RETIRED.VNNI_128= ) / (tma_retiring * tma_info_slots)", + "MetricExpr": "(cpu_core@INT_VEC_RETIRED.ADD_128@ + cpu_core@INT_V= EC_RETIRED.VNNI_128@) / (tma_retiring * tma_info_slots)", "MetricGroup": "Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;= tma_int_operations_group;tma_issue2P", "MetricName": "tma_int_vector_128b", "MetricThreshold": "tma_int_vector_128b > 0.1 & (tma_int_operation= s > 0.1 & tma_light_operations > 0.6)", @@ -1979,7 +1979,7 @@ }, { "BriefDescription": "This metric represents 256-bit vector Integer= ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the= CPU has retired", - "MetricExpr": "(INT_VEC_RETIRED.ADD_256 + INT_VEC_RETIRED.MUL_256 = + INT_VEC_RETIRED.VNNI_256) / (tma_retiring * tma_info_slots)", + "MetricExpr": "(cpu_core@INT_VEC_RETIRED.ADD_256@ + cpu_core@INT_V= EC_RETIRED.MUL_256@ + cpu_core@INT_VEC_RETIRED.VNNI_256@) / (tma_retiring *= tma_info_slots)", "MetricGroup": "Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;= tma_int_operations_group;tma_issue2P", "MetricName": "tma_int_vector_256b", "MetricThreshold": "tma_int_vector_256b > 0.1 & (tma_int_operation= s > 0.1 & tma_light_operations > 0.6)", @@ -1999,7 +1999,7 @@ }, { "BriefDescription": "This metric estimates how often the CPU was s= talled without loads missing the L1 data cache", - "MetricExpr": "max((EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.= STALLS_L1D_MISS) / tma_info_clks, 0)", + "MetricExpr": "max((cpu_core@EXE_ACTIVITY.BOUND_ON_LOADS@ - cpu_co= re@MEMORY_ACTIVITY.STALLS_L1D_MISS@) / tma_info_clks, 0)", "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_= group;tma_issueL1;tma_issueMC;tma_memory_bound_group", "MetricName": "tma_l1_bound", "MetricThreshold": "tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 &= tma_backend_bound > 0.2)", @@ -2010,7 +2010,7 @@ { "BriefDescription": "This metric estimates how often the CPU was s= talled due to L2 cache accesses by loads", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.= STALLS_L2_MISS) / tma_info_clks", + "MetricExpr": "(cpu_core@MEMORY_ACTIVITY.STALLS_L1D_MISS@ - cpu_co= re@MEMORY_ACTIVITY.STALLS_L2_MISS@) / tma_info_clks", "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_= group;tma_memory_bound_group", "MetricName": "tma_l2_bound", "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 = & tma_backend_bound > 0.2)", @@ -2020,7 +2020,7 @@ }, { "BriefDescription": "This metric estimates how often the CPU was s= talled due to loads accesses to L3 cache or contended with a sibling Core", - "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.S= TALLS_L3_MISS) / tma_info_clks", + "MetricExpr": "(cpu_core@MEMORY_ACTIVITY.STALLS_L2_MISS@ - cpu_cor= e@MEMORY_ACTIVITY.STALLS_L3_MISS@) / tma_info_clks", "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_= group;tma_memory_bound_group", "MetricName": "tma_l3_bound", "MetricThreshold": "tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 = & tma_backend_bound > 0.2)", @@ -2030,7 +2030,7 @@ }, { "BriefDescription": "This metric represents fraction of cycles wit= h demand load accesses that hit the L3 cache under unloaded scenarios (poss= ibly L3 latency limited)", - "MetricExpr": "9 * tma_info_average_frequency * MEM_LOAD_RETIRED.L= 3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_= info_clks", + "MetricExpr": "9 * tma_info_average_frequency * cpu_core@MEM_LOAD_= RETIRED.L3_HIT@ * (1 + cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / cpu_core@MEM_LOA= D_RETIRED.L1_MISS@ / 2) / tma_info_clks", "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_= l3_bound_group", "MetricName": "tma_l3_hit_latency", "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.0= 5 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", @@ -2090,7 +2090,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU spent handling cache misses due to lock operations", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS= .ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (10= * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTAN= DING.CYCLES_WITH_DEMAND_RFO))) / tma_info_clks", + "MetricExpr": "(16 * max(0, cpu_core@MEM_INST_RETIRED.LOCK_LOADS@ = - cpu_core@L2_RQSTS.ALL_RFO@) + cpu_core@MEM_INST_RETIRED.LOCK_LOADS@ / cpu= _core@MEM_INST_RETIRED.ALL_STORES@ * (10 * cpu_core@L2_RQSTS.RFO_HIT@ + min= (cpu_core@CPU_CLK_UNHALTED.THREAD@, cpu_core@OFFCORE_REQUESTS_OUTSTANDING.C= YCLES_WITH_DEMAND_RFO@))) / tma_info_clks", "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1= _bound_group", "MetricName": "tma_lock_latency", "MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 &= (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", @@ -2100,7 +2100,7 @@ }, { "BriefDescription": "This metric represents Core fraction of cycle= s in which CPU was likely limited due to LSD (Loop Stream Detector) unit", - "MetricExpr": "(LSD.CYCLES_ACTIVE - LSD.CYCLES_OK) / tma_info_core= _clks / 2", + "MetricExpr": "(cpu_core@LSD.CYCLES_ACTIVE@ - cpu_core@LSD.CYCLES_= OK@) / tma_info_core_clks / 2", "MetricGroup": "FetchBW;LSD;TopdownL3;tma_L3_group;tma_fetch_bandw= idth_group", "MetricName": "tma_lsd", "MetricThreshold": "tma_lsd > 0.15 & (tma_fetch_bandwidth > 0.1 & = tma_frontend_bound > 0.15 & tma_info_ipc / 6 > 0.35)", @@ -2121,7 +2121,7 @@ }, { "BriefDescription": "This metric estimates fraction of cycles wher= e the core's performance was likely hurt due to approaching bandwidth limit= s of external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu_core@OFFCORE_REQUE= STS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=3D4@) / tma_info_clks", + "MetricExpr": "min(cpu_core@CPU_CLK_UNHALTED.THREAD@, cpu_core@OFF= CORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=3D4@) / tma_info_clks", "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_b= ound_group;tma_issueBW", "MetricName": "tma_mem_bandwidth", "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.= 1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", @@ -2131,7 +2131,7 @@ }, { "BriefDescription": "This metric estimates fraction of cycles wher= e the performance was likely hurt due to latency from external memory (DRAM= )", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTST= ANDING.CYCLES_WITH_DATA_RD) / tma_info_clks - tma_mem_bandwidth", + "MetricExpr": "min(cpu_core@CPU_CLK_UNHALTED.THREAD@, cpu_core@OFF= CORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD@) / tma_info_clks - tma_mem_b= andwidth", "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_= bound_group;tma_issueLat", "MetricName": "tma_mem_latency", "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 = & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", @@ -2141,7 +2141,7 @@ }, { "BriefDescription": "This metric represents fraction of slots the = Memory subsystem within the Backend was a bottleneck", - "MetricExpr": "min(tma_backend_bound, LD_HEAD.ANY_AT_RET / tma_inf= o_clks + tma_store_bound)", + "MetricExpr": "cpu_core@topdown\\-mem\\-bound@ / (cpu_core@topdown= \\-fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ + cpu_core@topdown\\-retiri= ng@ + cpu_core@topdown\\-be\\-bound@) + 0 * tma_info_slots", "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", @@ -2152,7 +2152,7 @@ }, { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to LFENCE Instructions.", - "MetricExpr": "13 * MISC2_RETIRED.LFENCE / tma_info_clks", + "MetricExpr": "13 * cpu_core@MISC2_RETIRED.LFENCE@ / tma_info_clks= ", "MetricGroup": "TopdownL6;tma_L6_group;tma_serializing_operation_g= roup", "MetricName": "tma_memory_fence", "MetricThreshold": "tma_memory_fence > 0.05 & (tma_serializing_ope= ration > 0.1 & (tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 = & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))))", @@ -2162,7 +2162,7 @@ { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring memory operations -- uops for memory load or store a= ccesses.", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "tma_light_operations * MEM_UOP_RETIRED.ANY / (tma_r= etiring * tma_info_slots)", + "MetricExpr": "tma_light_operations * cpu_core@MEM_UOP_RETIRED.ANY= @ / (tma_retiring * tma_info_slots)", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", "MetricName": "tma_memory_operations", "MetricThreshold": "tma_memory_operations > 0.1 & tma_light_operat= ions > 0.6", @@ -2181,7 +2181,7 @@ }, { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Branch Resteers as a result of Branch Misprediction= at execution stage", - "MetricExpr": "tma_branch_mispredicts / tma_bad_speculation * INT_= MISC.CLEAR_RESTEER_CYCLES / tma_info_clks", + "MetricExpr": "tma_branch_mispredicts / tma_bad_speculation * cpu_= core@INT_MISC.CLEAR_RESTEER_CYCLES@ / tma_info_clks", "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_b= ranch_resteers_group;tma_issueBM", "MetricName": "tma_mispredicts_resteers", "MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_= resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", @@ -2191,7 +2191,7 @@ }, { "BriefDescription": "This metric represents Core fraction of cycle= s in which CPU was likely limited due to the MITE pipeline (the legacy deco= de pipeline)", - "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / tma_in= fo_core_clks / 2", + "MetricExpr": "(cpu_core@IDQ.MITE_CYCLES_ANY@ - cpu_core@IDQ.MITE_= CYCLES_OK@) / tma_info_core_clks / 2", "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_b= andwidth_group", "MetricName": "tma_mite", "MetricThreshold": "tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & = tma_frontend_bound > 0.15 & tma_info_ipc / 6 > 0.35)", @@ -2201,7 +2201,7 @@ }, { "BriefDescription": "The Mixing_Vectors metric gives the percentag= e of injected blend uops out of all uops issued", - "MetricExpr": "160 * ASSISTS.SSE_AVX_MIX / tma_info_clks", + "MetricExpr": "160 * cpu_core@ASSISTS.SSE_AVX_MIX@ / tma_info_clks= ", "MetricGroup": "TopdownL5;tma_L5_group;tma_issueMV;tma_ports_utili= zed_0_group", "MetricName": "tma_mixing_vectors", "MetricThreshold": "tma_mixing_vectors > 0.05", @@ -2211,7 +2211,7 @@ }, { "BriefDescription": "This metric estimates the fraction of cycles = when the CPU was stalled due to switches of uop delivery to the Microcode S= equencer (MS)", - "MetricExpr": "3 * cpu_core@UOPS_RETIRED.MS\\,cmask\\=3D1\\,edge@ = / (tma_retiring * tma_info_slots / UOPS_ISSUED.ANY) / tma_info_clks", + "MetricExpr": "3 * cpu_core@UOPS_RETIRED.MS\\,cmask\\=3D1\\,edge@ = / (tma_retiring * tma_info_slots / cpu_core@UOPS_ISSUED.ANY@) / tma_info_cl= ks", "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch= _latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO", "MetricName": "tma_ms_switches", "MetricThreshold": "tma_ms_switches > 0.05 & (tma_fetch_latency > = 0.1 & tma_frontend_bound > 0.15)", @@ -2221,7 +2221,7 @@ }, { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring branch instructions that were not fused", - "MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHE= S - INST_RETIRED.MACRO_FUSED) / (tma_retiring * tma_info_slots)", + "MetricExpr": "tma_light_operations * (cpu_core@BR_INST_RETIRED.AL= L_BRANCHES@ - cpu_core@INST_RETIRED.MACRO_FUSED@) / (tma_retiring * tma_inf= o_slots)", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", "MetricName": "tma_non_fused_branches", "MetricThreshold": "tma_non_fused_branches > 0.1 & tma_light_opera= tions > 0.6", @@ -2231,7 +2231,7 @@ }, { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring NOP (no op) instructions", - "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / (tma_reti= ring * tma_info_slots)", + "MetricExpr": "tma_light_operations * cpu_core@INST_RETIRED.NOP@ /= (tma_retiring * tma_info_slots)", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", "MetricName": "tma_nop_instructions", "MetricThreshold": "tma_nop_instructions > 0.1 & tma_light_operati= ons > 0.6", @@ -2252,7 +2252,7 @@ }, { "BriefDescription": "This metric roughly estimates fraction of slo= ts the CPU retired uops as a result of handing Page Faults", - "MetricExpr": "99 * ASSISTS.PAGE_FAULT / tma_info_slots", + "MetricExpr": "99 * cpu_core@ASSISTS.PAGE_FAULT@ / tma_info_slots", "MetricGroup": "TopdownL5;tma_L5_group;tma_assists_group", "MetricName": "tma_page_faults", "MetricThreshold": "tma_page_faults > 0.05", @@ -2292,7 +2292,7 @@ }, { "BriefDescription": "This metric estimates fraction of cycles the = CPU performance was potentially limited due to Core computation issues (non= divider-related)", - "MetricExpr": "((cpu_core@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=3D0x= 80@ + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVI= TY.BOUND_ON_LOADS) + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu_core@E= XE_ACTIVITY.2_PORTS_UTIL\\,umask\\=3D0xc@)) / tma_info_clks if ARITH.DIV_AC= TIVE < CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS else (EXE_= ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu_core@EXE_ACTIVITY.2_PORTS_UTIL\\= ,umask\\=3D0xc@) / tma_info_clks)", + "MetricExpr": "((cpu_core@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=3D0x= 80@ + tma_serializing_operation * (cpu_core@CYCLE_ACTIVITY.STALLS_TOTAL@ - = cpu_core@EXE_ACTIVITY.BOUND_ON_LOADS@) + (cpu_core@EXE_ACTIVITY.1_PORTS_UTI= L@ + tma_retiring * cpu_core@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=3D0xc@)) /= tma_info_clks if cpu_core@ARITH.DIV_ACTIVE@ < cpu_core@CYCLE_ACTIVITY.STAL= LS_TOTAL@ - cpu_core@EXE_ACTIVITY.BOUND_ON_LOADS@ else (cpu_core@EXE_ACTIVI= TY.1_PORTS_UTIL@ + tma_retiring * cpu_core@EXE_ACTIVITY.2_PORTS_UTIL\\,umas= k\\=3D0xc@) / tma_info_clks)", "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_gr= oup", "MetricName": "tma_ports_utilization", "MetricThreshold": "tma_ports_utilization > 0.15 & (tma_core_bound= > 0.1 & tma_backend_bound > 0.2)", @@ -2302,7 +2302,7 @@ }, { "BriefDescription": "This metric represents fraction of cycles CPU= executed no uops on any execution port (Logical Processor cycles since ICL= , Physical Core cycles otherwise)", - "MetricExpr": "cpu_core@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=3D0x80= @ / tma_info_clks + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTA= L - EXE_ACTIVITY.BOUND_ON_LOADS) / tma_info_clks", + "MetricExpr": "cpu_core@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=3D0x80= @ / tma_info_clks + tma_serializing_operation * (cpu_core@CYCLE_ACTIVITY.ST= ALLS_TOTAL@ - cpu_core@EXE_ACTIVITY.BOUND_ON_LOADS@) / tma_info_clks", "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utiliza= tion_group", "MetricName": "tma_ports_utilized_0", "MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utiliz= ation > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", @@ -2342,7 +2342,7 @@ }, { "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdow= n\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_info_= slots", + "MetricExpr": "cpu_core@topdown\\-retiring@ / (cpu_core@topdown\\-= fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ + cpu_core@topdown\\-retiring@= + cpu_core@topdown\\-be\\-bound@) + 0 * tma_info_slots", "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", @@ -2382,7 +2382,7 @@ }, { "BriefDescription": "This metric estimates fraction of cycles hand= ling memory load split accesses - load that cross 64-byte cache line bounda= ry", - "MetricExpr": "tma_info_load_miss_real_latency * LD_BLOCKS.NO_SR /= tma_info_clks", + "MetricExpr": "tma_info_load_miss_real_latency * cpu_core@LD_BLOCK= S.NO_SR@ / tma_info_clks", "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", "MetricName": "tma_split_loads", "MetricThreshold": "tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & = (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", @@ -2402,7 +2402,7 @@ }, { "BriefDescription": "This metric measures fraction of cycles where= the Super Queue (SQ) was full taking into account all request-types and bo= th hardware SMT threads (Logical Processors)", - "MetricExpr": "(XQ.FULL_CYCLES + L1D_PEND_MISS.L2_STALLS) / tma_in= fo_clks", + "MetricExpr": "(cpu_core@XQ.FULL_CYCLES@ + cpu_core@L1D_PEND_MISS.= L2_STALLS@) / tma_info_clks", "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueB= W;tma_l3_bound_group", "MetricName": "tma_sq_full", "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tm= a_memory_bound > 0.2 & tma_backend_bound > 0.2))", @@ -2422,7 +2422,7 @@ }, { "BriefDescription": "This metric roughly estimates fraction of cyc= les when the memory subsystem had loads blocked since they could not forwar= d data from earlier (in program order) overlapping stores", - "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / tma_info_clks", + "MetricExpr": "13 * cpu_core@LD_BLOCKS.STORE_FORWARD@ / tma_info_c= lks", "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", "MetricName": "tma_store_fwd_blk", "MetricThreshold": "tma_store_fwd_blk > 0.1 & (tma_l1_bound > 0.1 = & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", @@ -2432,7 +2432,7 @@ }, { "BriefDescription": "This metric estimates fraction of cycles the = CPU spent handling L1D store misses", - "MetricExpr": "(MEM_STORE_RETIRED.L2_HIT * 10 * (1 - MEM_INST_RETI= RED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_= LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE= _REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_clks", + "MetricExpr": "(cpu_core@MEM_STORE_RETIRED.L2_HIT@ * 10 * (1 - cpu= _core@MEM_INST_RETIRED.LOCK_LOADS@ / cpu_core@MEM_INST_RETIRED.ALL_STORES@)= + (1 - cpu_core@MEM_INST_RETIRED.LOCK_LOADS@ / cpu_core@MEM_INST_RETIRED.A= LL_STORES@) * min(cpu_core@CPU_CLK_UNHALTED.THREAD@, cpu_core@OFFCORE_REQUE= STS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO@)) / tma_info_clks", "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issue= RFO;tma_issueSL;tma_store_bound_group", "MetricName": "tma_store_latency", "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0= .2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", @@ -2442,7 +2442,7 @@ }, { "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution port for Store operations", - "MetricExpr": "(UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_= 8) / (4 * tma_info_core_clks)", + "MetricExpr": "(cpu_core@UOPS_DISPATCHED.PORT_4_9@ + cpu_core@UOPS= _DISPATCHED.PORT_7_8@) / (4 * tma_info_core_clks)", "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group= ", "MetricName": "tma_store_op_utilization", "MetricThreshold": "tma_store_op_utilization > 0.6", @@ -2470,7 +2470,7 @@ }, { "BriefDescription": "This metric estimates how often CPU was stall= ed due to Streaming store memory accesses; Streaming store optimize out a = read request required by RFO stores", - "MetricExpr": "9 * OCR.STREAMING_WR.ANY_RESPONSE / tma_info_clks", + "MetricExpr": "9 * cpu_core@OCR.STREAMING_WR.ANY_RESPONSE@ / tma_i= nfo_clks", "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueS= mSt;tma_store_bound_group", "MetricName": "tma_streaming_stores", "MetricThreshold": "tma_streaming_stores > 0.2 & (tma_store_bound = > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", @@ -2490,7 +2490,7 @@ }, { "BriefDescription": "This metric serves as an approximation of leg= acy x87 usage", - "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.TH= READ", + "MetricExpr": "tma_retiring * cpu_core@UOPS_EXECUTED.X87@ / UOPS_E= XECUTED.THREAD", "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", "MetricName": "tma_x87_use", "MetricThreshold": "tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_= light_operations > 0.6)", diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json b/= tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json index 0402adbf7d92..f4b3c3883643 100644 --- a/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json +++ b/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json @@ -193,7 +193,7 @@ { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / tma_info_clks - ME= M_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOU= ND_STALLS.LOAD", + "MetricExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / tma_info_clks - ma= x((MEM_BOUND_STALLS.LOAD - LD_HEAD.L1_MISS_AT_RET) / tma_info_clks, 0) * ME= M_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOUND_STALLS.LOAD", "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_dram_bound", "MetricThreshold": "tma_dram_bound > 0.1", @@ -480,7 +480,7 @@ { "BriefDescription": "Counts the number of cycles a core is stalled= due to a demand load which hit in the L2 Cache.", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / tma_info_clks - MEM_= BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_S= TALLS.LOAD", + "MetricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / tma_info_clks - max(= (MEM_BOUND_STALLS.LOAD - LD_HEAD.L1_MISS_AT_RET) / tma_info_clks, 0) * MEM_= BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_STALLS.LOAD", "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l2_bound", "MetricThreshold": "tma_l2_bound > 0.1", @@ -488,7 +488,7 @@ }, { "BriefDescription": "Counts the number of cycles a core is stalled= due to a demand load which hit in the Last Level Cache (LLC) or other core= with HITE/F/M.", - "MetricExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / tma_info_clks - MEM= _BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND= _STALLS.LOAD", + "MetricExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / tma_info_clks - max= ((MEM_BOUND_STALLS.LOAD - LD_HEAD.L1_MISS_AT_RET) / tma_info_clks, 0) * MEM= _BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND_STALLS.LOAD", "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l3_bound", "MetricThreshold": "tma_l3_bound > 0.1", --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 444E5C19F20 for ; Tue, 2 May 2023 22:46:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230367AbjEBWqe (ORCPT ); Tue, 2 May 2023 18:46:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35218 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230333AbjEBWqJ (ORCPT ); Tue, 2 May 2023 18:46:09 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 80F6530DD for ; Tue, 2 May 2023 15:45:41 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-b8f46dc51bdso8824755276.3 for ; Tue, 02 May 2023 15:45:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067446; x=1685659446; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=6DTTYiMDl8Yj+KSHhgdntFRxS2mVbWmHBiQYwku76Lg=; b=qIcCu4F4ipXFP1KhlrrY9hAFQfjYfnyjIWVRg/pF9X7JgwHFFfYH7JtWKWyF9h5stw DJHUzgE1eUF8HTsIfz2WQSiczrMJ/oOZB5y1bKeZBZqEXU8DZtULsiR09zCXDoc9Ky1t washr7kW4cKiaTY0DlaBKC3g9ex1OKc/uE+WOJXex2+3J9/271LWsJZMNGLYDFaLezBp OTfrA9TbdYrpGw+li83pG1E9dFbKYSDXXH3SgfBJS+rpBDK8yTx31dEy89Ibgq+0S8Sk xV4RcPkQ2/JGLUDGASSUjW9oYvno+6JqhLTZxpZxCinYdw67vtyCpi73aK00ku7MsGYp PhUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067446; x=1685659446; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=6DTTYiMDl8Yj+KSHhgdntFRxS2mVbWmHBiQYwku76Lg=; b=Rg/R5ukcTGJLFC5rHc6hgE+/SnI7m+/kRWXhtKeyN34ZLz5+Wpzor7jE1liIa77ogu rQmfAeb+yDxmh+rpwzz0SdCNw72ewTeegUtX6oRh6WycDYvvQ8QhhtUoCJgmb2QEacoi sy5n3z/OWqGWRPv86cnGiWpDr3OjiTMQ2t2+NZmjR1Uggu/EGblg/9hAX7IPgYlXCV+5 nYpYLNZRVFYC0GTGa0kwccM4YEz2DcwyIQpn8zyFj/qVWoDESz3nLE5csmuJ46plpbZC Q88+BfsmnFlkc0vcjcsJkBHbQFaTfh1nXU8Le/v3XE3Y8hEsV0qGIDiC79tiqTLApUDP tLww== X-Gm-Message-State: AC+VfDyEL/6p2LB+HrV+dxDrzznTw9oOPHvLae/YiweM0eqlHOQNAtQu ggAxhju4VdfSFYf902jCj2cXWD1Zsttw X-Google-Smtp-Source: ACHHUZ50FvgH7uzzNsRsTpHfx2O0DdSxoHTLqRCtSA04JIA1l31TAUW3CsOQl6k5Qu6HoOcow0aM5KXrPfmO X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a25:5802:0:b0:b9d:b6cd:2dfd with SMTP id m2-20020a255802000000b00b9db6cd2dfdmr6428740ybb.8.1683067446252; Tue, 02 May 2023 15:44:06 -0700 (PDT) Date: Tue, 2 May 2023 15:38:48 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-42-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 41/44] perf jevents: Don't rewrite metrics across PMUs From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Don't rewrite metrics across PMUs as the result events likely won't be found. Identify metrics with a pair of PMU name and metric name. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/pmu-events/jevents.py | 4 ++-- tools/perf/pmu-events/metric.py | 28 +++++++++++++++++----------- tools/perf/pmu-events/metric_test.py | 6 +++--- 3 files changed, 22 insertions(+), 16 deletions(-) diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jeven= ts.py index b18dd2fcbf04..487ff01baf1b 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -391,11 +391,11 @@ def read_json_events(path: str, topic: str) -> Sequen= ce[JsonEvent]: except BaseException as err: print(f"Exception processing {path}") raise - metrics: list[Tuple[str, metric.Expression]] =3D [] + metrics: list[Tuple[str, str, metric.Expression]] =3D [] for event in events: event.topic =3D topic if event.metric_name and '-' not in event.metric_name: - metrics.append((event.metric_name, event.metric_expr)) + metrics.append((event.pmu, event.metric_name, event.metric_expr)) updates =3D metric.RewriteMetricsInTermsOfOthers(metrics) if updates: for event in events: diff --git a/tools/perf/pmu-events/metric.py b/tools/perf/pmu-events/metric= .py index 8ec0ba884673..af58b74d1644 100644 --- a/tools/perf/pmu-events/metric.py +++ b/tools/perf/pmu-events/metric.py @@ -552,28 +552,34 @@ def ParsePerfJson(orig: str) -> Expression: return _Constify(eval(compile(parsed, orig, 'eval'))) =20 =20 -def RewriteMetricsInTermsOfOthers(metrics: List[Tuple[str, Expression]] - )-> Dict[str, Expression]: +def RewriteMetricsInTermsOfOthers(metrics: List[Tuple[str, str, Expression= ]] + )-> Dict[Tuple[str, str], Expression]: """Shorten metrics by rewriting in terms of others. =20 Args: - metrics (list): pairs of metric names and their expressions. + metrics (list): pmus, metric names and their expressions. Returns: - Dict: mapping from a metric name to a shortened expression. + Dict: mapping from a pmu, metric name pair to a shortened expression. """ - updates: Dict[str, Expression] =3D dict() - for outer_name, outer_expression in metrics: + updates: Dict[Tuple[str, str], Expression] =3D dict() + for outer_pmu, outer_name, outer_expression in metrics: + if outer_pmu is None: + outer_pmu =3D 'cpu' updated =3D outer_expression while True: - for inner_name, inner_expression in metrics: + for inner_pmu, inner_name, inner_expression in metrics: + if inner_pmu is None: + inner_pmu =3D 'cpu' + if inner_pmu.lower() !=3D outer_pmu.lower(): + continue if inner_name.lower() =3D=3D outer_name.lower(): continue - if inner_name in updates: - inner_expression =3D updates[inner_name] + if (inner_pmu, inner_name) in updates: + inner_expression =3D updates[(inner_pmu, inner_name)] updated =3D updated.Substitute(inner_name, inner_expression) if updated.Equals(outer_expression): break - if outer_name in updates and updated.Equals(updates[outer_name]): + if (outer_pmu, outer_name) in updates and updated.Equals(updates[(ou= ter_pmu, outer_name)]): break - updates[outer_name] =3D updated + updates[(outer_pmu, outer_name)] =3D updated return updates diff --git a/tools/perf/pmu-events/metric_test.py b/tools/perf/pmu-events/m= etric_test.py index 40a3c7d8b2bc..ee22ff43ddd7 100755 --- a/tools/perf/pmu-events/metric_test.py +++ b/tools/perf/pmu-events/metric_test.py @@ -158,9 +158,9 @@ class TestMetricExpressions(unittest.TestCase): =20 def test_RewriteMetricsInTermsOfOthers(self): Expression.__eq__ =3D lambda e1, e2: e1.Equals(e2) - before =3D [('m1', ParsePerfJson('a + b + c + d')), - ('m2', ParsePerfJson('a + b + c'))] - after =3D {'m1': ParsePerfJson('m2 + d')} + before =3D [('cpu', 'm1', ParsePerfJson('a + b + c + d')), + ('cpu', 'm2', ParsePerfJson('a + b + c'))] + after =3D {('cpu', 'm1'): ParsePerfJson('m2 + d')} self.assertEqual(RewriteMetricsInTermsOfOthers(before), after) Expression.__eq__ =3D None =20 --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB70DC77B75 for ; Tue, 2 May 2023 22:46:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230353AbjEBWqK (ORCPT ); Tue, 2 May 2023 18:46:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34754 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229785AbjEBWpm (ORCPT ); Tue, 2 May 2023 18:45:42 -0400 Received: from mail-pg1-x54a.google.com (mail-pg1-x54a.google.com [IPv6:2607:f8b0:4864:20::54a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C0212D69 for ; Tue, 2 May 2023 15:45:24 -0700 (PDT) Received: by mail-pg1-x54a.google.com with SMTP id 41be03b00d2f7-5289f93ad94so2353883a12.0 for ; Tue, 02 May 2023 15:45:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067453; x=1685659453; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=zMkOwzwif+XT0+nBV5mOmwMnUg0kBSArT43+8IsF+QA=; b=DiVr58NKnqrNa0PQ4s2HvZYJODLIFvfXb8It+Z4M5+iCIdFJl7S7DAEMKsQ69BcuSf bYCLu0BHbbJQLd77EJSH/gAjXR/uE9dl+P49sOB0DUsD6hy7B3RcRtyXcRd8LoTulUGX crklksll2IrovGv52zukTueeu2ssNuKvDU2+2uFy32gLhv5zaXAR/MGgu/CeJ8bk81Zs LYuK6W0utDlAPgW4EsrwYLrBFdoyj1YB+Zo8jNjv8sQ6m3lwmtLZ9J+s3zOKRAAl4RmL QMny6ECo4pJZ4eM5axsLEZn4fvwHTrJw3P5pAEGTqZXepeUJ6HHwTtE0hSBM/+NMrkqU nuwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067453; x=1685659453; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=zMkOwzwif+XT0+nBV5mOmwMnUg0kBSArT43+8IsF+QA=; b=Fn57CiDidlOOrD2fWkSXAkklskMtq0xsUCuqTZWU8bmrVGmW8CBFfWaMJtmzvtZigE gkQSeeym1rK96vIEYED//2qrbP33OeVp+mLBu+HsJyiOiFxFqVkQcNVQp86gYY3lIVvJ Uaop3nY17ywT9b7xxlc16uYjbrfUJ2Cec4sipAMUBrSx4aEUJkGrw+ERDx1TFt4rZGZ6 F0OZUEc4+B2SCUl9nSQYokTEfYmK7EKv50AD06bXy8Q5aygBn8igZ/LuE8etulUUk3QB /tWB+LUe/mD/MVS1E9tiNUAoZQObfomV9JUuMAiDZnIU9Pka1f4UDYblHsf8NVdvRYGo Ph/w== X-Gm-Message-State: AC+VfDzwRNO12Ct3R1rqOap5qPW+pleHU7ZjM1/s/RPAcQkL/39smp99 LAniCxwETTAK4Ymgm4Z3fry/eZw/Kkxy X-Google-Smtp-Source: ACHHUZ7ap0xtN41qtnwK/fzVQw9n9WtCXHcFSd4DNZI35fUjtZVM5Xpb1//5i3q2RLMUaEOVVhPNP2dYHZv8 X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a63:2aca:0:b0:51f:54dc:1646 with SMTP id q193-20020a632aca000000b0051f54dc1646mr17578pgq.7.1683067453102; Tue, 02 May 2023 15:44:13 -0700 (PDT) Date: Tue, 2 May 2023 15:38:49 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-43-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 42/44] perf metrics: Be PMU specific in event match From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Ids/events from a metric are turned into an event string and parsed; setup_metric_events matches the id back to the parsed evsel. With hybrid the same event may exist on both PMUs with the same name and be being used by metrics at the same time. A metric on cpu_core therefore shouldn't match against evsels on cpu_atom, or the metric will compute the wrong value. Make the matching sensitive to the PMU being parsed. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/util/metricgroup.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index 4245b23d8efe..490561f430f2 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -274,7 +274,7 @@ static int setup_metric_events(const char *pmu, struct = hashmap *ids, const char *metric_id; struct evsel *ev; size_t ids_size, matched_events, i; - bool all_pmus =3D !strcmp(pmu, "all"); + bool all_pmus =3D !strcmp(pmu, "all") || !perf_pmu__is_hybrid(pmu); =20 *out_metric_events =3D NULL; ids_size =3D hashmap__size(ids); @@ -287,7 +287,10 @@ static int setup_metric_events(const char *pmu, struct= hashmap *ids, evlist__for_each_entry(metric_evlist, ev) { struct expr_id_data *val_ptr; =20 - if (!all_pmus && strcmp(ev->pmu_name, pmu)) + /* Don't match events for the wrong hybrid PMU. */ + if (!all_pmus && ev->pmu_name && + perf_pmu__is_hybrid(ev->pmu_name) && + strcmp(ev->pmu_name, pmu)) continue; /* * Check for duplicate events with the same name. For @@ -304,6 +307,7 @@ static int setup_metric_events(const char *pmu, struct = hashmap *ids, * about this event. */ if (hashmap__find(ids, metric_id, &val_ptr)) { + pr_debug("Matched metric-id %s to %s\n", metric_id, evsel__name(ev)); metric_events[matched_events++] =3D ev; =20 if (matched_events >=3D ids_size) @@ -1592,7 +1596,7 @@ static int parse_groups(struct evlist *perf_evlist, ret =3D setup_metric_events(fake_pmu ? "all" : m->pmu, m->pctx->ids, metric_evlist, &metric_events); if (ret) { - pr_debug("Cannot resolve IDs for %s: %s\n", + pr_err("Cannot resolve IDs for %s: %s\n", m->metric_name, m->metric_expr); goto out; } --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE4E8C7EE21 for ; Tue, 2 May 2023 22:47:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230395AbjEBWrH (ORCPT ); Tue, 2 May 2023 18:47:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33872 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230397AbjEBWqq (ORCPT ); Tue, 2 May 2023 18:46:46 -0400 Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC31C3AA2 for ; Tue, 2 May 2023 15:46:16 -0700 (PDT) Received: by mail-yw1-f202.google.com with SMTP id 00721157ae682-559f142fce7so71447187b3.3 for ; Tue, 02 May 2023 15:46:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683067459; x=1685659459; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=udIESTQJWghJ0eXfw1zjkQa1ohgrnaNqFMimydoVXZk=; b=gojl9HwHH6dSomxA0iNDxmuQP/iGSlTIAnnlpuwgAwND6HM9nhykps55V9hrixO7GH JqqMikZyvzC9grNkp52yXWH6Zx8COeV321VVi53ed6Xx8I3VGnICqY3cYUJAos95eVe2 qlUatBbFGGJYZbckoX48NQC1R/fhQj9H3NkdcNHtr1s5y4UDCtzjeHOyOWD8N+MYnRVa yrMpVe6C4X4UOmZucbVlNOGBrWOEaLM6AoPH2wUReYOcjyTBWPLhXsP2srxjBxt9d72A V2uhVYBNstyLerh3Mhaj/PktKJLTji+8nYZi7xFblE0D3UtQJCVrQkfxufV/hUCrFGK5 v8ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683067459; x=1685659459; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=udIESTQJWghJ0eXfw1zjkQa1ohgrnaNqFMimydoVXZk=; b=BmrFIwdEfvcMuNMee09l3QGn0EYxf/IIl6PXDB1E6dyXcF/Ea9dIBVC0/aWbLCcEZL iLF1x+828N8k9DfqkjXzPeXTI8/2158LQdFfw5lc+9MUMVuzbkJzOWCMS8H0RzpjfZ7k lbYG7aIIo+dH2x7SmbbLgVB0B/afrF2g6hVZwP840tPsGNGjk3+NXGiKWgQvKReHnAeH usowdCe2BC3+DbfgL6jeIlT/YdVSbOflfhEhPddiKK7geyZrWKueZvIwLFyIK/SeVL/t 2OIB8EmGmnMdMnGhHlyRd0cbLo6ROCX7FPbQZxIFHNO+QNic29S8YoEwHNWou8iiOgUR FQyg== X-Gm-Message-State: AC+VfDwaFrGt4SkVzIBMNjjMVMY/wepb7uLxwEcMJoFmiwAiXICAFlmg NmNbmimWfxS8TtsyfJsR+++UiJ6gvKHQ X-Google-Smtp-Source: ACHHUZ5zFcnSGoYy10fGDH40vDdIwUQ+uQ6vQnbd4Izu2cHsmeAi8zbJBTEGQqFzRAOUO0v/SGTjrmnnvfNE X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a81:ad58:0:b0:559:f1b0:6eb with SMTP id l24-20020a81ad58000000b00559f1b006ebmr6888406ywk.4.1683067459645; Tue, 02 May 2023 15:44:19 -0700 (PDT) Date: Tue, 2 May 2023 15:38:50 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-44-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 43/44] perf stat: Don't disable TopdownL1 metric on hybrid From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that hybrid bugs are fixed sufficient to run TopdownL1 metrics, don't implicitly disable them for hybrid. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/builtin-stat.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index f4e572f9de6b..67dc69270ae4 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -1900,12 +1900,7 @@ static int add_default_attributes(void) * Add TopdownL1 metrics if they exist. To minimize * multiplexing, don't request threshold computation. */ - /* - * TODO: TopdownL1 is disabled on hybrid CPUs to avoid a crashes - * caused by exposing latent bugs. This is fixed properly in: - * https://lore.kernel.org/lkml/bff481ba-e60a-763f-0aa0-3ee53302c480@lin= ux.intel.com/ - */ - if (metricgroup__has_metric(pmu, "TopdownL1") && !perf_pmu__has_hybrid()= ) { + if (metricgroup__has_metric(pmu, "TopdownL1")) { struct evlist *metric_evlist =3D evlist__new(); struct evsel *metric_evsel; =20 --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 12:14:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87791C19F20 for ; Tue, 2 May 2023 22:57:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230469AbjEBW5Z (ORCPT ); Tue, 2 May 2023 18:57:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47050 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230255AbjEBW5X (ORCPT ); Tue, 2 May 2023 18:57:23 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9D4DA3A88 for ; Tue, 2 May 2023 15:56:59 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-b9a776a5eb2so9973169276.0 for ; Tue, 02 May 2023 15:56:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1683068137; x=1685660137; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=vEgpbeTkYS2FHMjnmLxMSY6ngIlZOzdEJwjzo/4s4WU=; b=3dYfCJ2DpUmnAGItcsliPghXbfkdsbtO8Pv7WiOm01YrcwNDqg1rtAK7dKsEpLIa3w fKkAC+QCYK7efMokE8kOKI1svB2GgePo9SEeq2DXv8yxkaLIfVL68rvgO/1TDQX8UOpE UowMwrED8lLczAwPcKPHvAs0o1QntXdEh43ka1dahWo8gGLlF2yRWBZCSz/9+SZrsFTj CSA4W3gpuiXR6tscdAZhw39LFgQO8K+UCuAwVWVMbk0QguTsTozWCXPlqCSE5e1i40FN ppXuONpzY46APqdwuMM07G/Zazp0+xf0RbhvmwmSlGyelFqCrgJDpYlmihd0jZxDw3VP wRPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683068137; x=1685660137; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=vEgpbeTkYS2FHMjnmLxMSY6ngIlZOzdEJwjzo/4s4WU=; b=k/lRDB4RRpp6IDpESrrEB2l+Dz8BARD36H61ki30w7WvSHiUvsn+OPUvMv1HChPCB1 Natfg+SfamKVAeslRDiesfZhKIojW/U936gN5hl406/ZD4BsdS6OFNNkYUMO2eHogEhN rYHktiFQiHa7GGMGX/mfsoQXnOeWJVBAIRvZq4ueo3stCItHV/LZgDiVKBkb6IVPk/0C sJO2NJFwRiXSHR83wSxLigLymq2/Z+0njrmydgGVE7Q7i2hyKWIozxlugTZnV0Oy2MCR aMrM25Vrzh6SGY+3uAw4G5OPPHn9wZJ1ywk++Ejmwd8jyhuba3QRIgHWrB9WnguvT5KR F0ig== X-Gm-Message-State: AC+VfDw607i7dy0FEri0p4nEh/US7It/VxIklD4o5G09dHYAXXNv8cCS MgxgSzKbObXSgTUxQF6yOFXdC7SrgMdm X-Google-Smtp-Source: ACHHUZ7iAK7rWgSBX+DL5Qb5w89koRRW8YSxJzIwr8QMxTu7l35yOhMQy7ytDbOexlY9ioNBFJwmz0SHhJO1 X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:e70c:446b:d23b:982e]) (user=irogers job=sendgmr) by 2002:a81:a745:0:b0:545:f7cc:f30 with SMTP id e66-20020a81a745000000b00545f7cc0f30mr11393988ywh.0.1683067466155; Tue, 02 May 2023 15:44:26 -0700 (PDT) Date: Tue, 2 May 2023 15:38:51 -0700 In-Reply-To: <20230502223851.2234828-1-irogers@google.com> Message-Id: <20230502223851.2234828-45-irogers@google.com> Mime-Version: 1.0 References: <20230502223851.2234828-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v4 44/44] perf parse-events: Reduce scope of is_event_supported From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move to print-events.c and make static. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/util/parse-events.c | 39 ---------------------------------- tools/perf/util/parse-events.h | 2 -- tools/perf/util/print-events.c | 39 ++++++++++++++++++++++++++++++++++ 3 files changed, 39 insertions(+), 41 deletions(-) diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index 2dad88a6bf19..b93264f8a37c 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -28,7 +28,6 @@ #include "util/bpf-filter.h" #include "util/util.h" #include "tracepoint.h" -#include "thread_map.h" =20 #define MAX_NAME_LEN 100 =20 @@ -133,44 +132,6 @@ struct event_symbol event_symbols_sw[PERF_COUNT_SW_MAX= ] =3D { }, }; =20 -bool is_event_supported(u8 type, u64 config) -{ - bool ret =3D true; - int open_return; - struct evsel *evsel; - struct perf_event_attr attr =3D { - .type =3D type, - .config =3D config, - .disabled =3D 1, - }; - struct perf_thread_map *tmap =3D thread_map__new_by_tid(0); - - if (tmap =3D=3D NULL) - return false; - - evsel =3D evsel__new(&attr); - if (evsel) { - open_return =3D evsel__open(evsel, NULL, tmap); - ret =3D open_return >=3D 0; - - if (open_return =3D=3D -EACCES) { - /* - * This happens if the paranoid value - * /proc/sys/kernel/perf_event_paranoid is set to 2 - * Re-run with exclude_kernel set; we don't do that - * by default as some ARM machines do not support it. - * - */ - evsel->core.attr.exclude_kernel =3D 1; - ret =3D evsel__open(evsel, NULL, tmap) >=3D 0; - } - evsel__delete(evsel); - } - - perf_thread_map__put(tmap); - return ret; -} - const char *event_type(int type) { switch (type) { diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index 2a8cafe0ee8f..2021fe145410 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -18,8 +18,6 @@ struct parse_events_error; struct option; struct perf_pmu; =20 -bool is_event_supported(u8 type, u64 config); - const char *event_type(int type); =20 /* Arguments encoded in opt->value. */ diff --git a/tools/perf/util/print-events.c b/tools/perf/util/print-events.c index d148842b205a..69492cbd6921 100644 --- a/tools/perf/util/print-events.c +++ b/tools/perf/util/print-events.c @@ -27,6 +27,7 @@ #include "tracepoint.h" #include "pfm.h" #include "pmu-hybrid.h" +#include "thread_map.h" =20 #define MAX_NAME_LEN 100 =20 @@ -228,6 +229,44 @@ void print_sdt_events(const struct print_callbacks *pr= int_cb, void *print_state) strlist__delete(sdtlist); } =20 +static bool is_event_supported(u8 type, u64 config) +{ + bool ret =3D true; + int open_return; + struct evsel *evsel; + struct perf_event_attr attr =3D { + .type =3D type, + .config =3D config, + .disabled =3D 1, + }; + struct perf_thread_map *tmap =3D thread_map__new_by_tid(0); + + if (tmap =3D=3D NULL) + return false; + + evsel =3D evsel__new(&attr); + if (evsel) { + open_return =3D evsel__open(evsel, NULL, tmap); + ret =3D open_return >=3D 0; + + if (open_return =3D=3D -EACCES) { + /* + * This happens if the paranoid value + * /proc/sys/kernel/perf_event_paranoid is set to 2 + * Re-run with exclude_kernel set; we don't do that + * by default as some ARM machines do not support it. + * + */ + evsel->core.attr.exclude_kernel =3D 1; + ret =3D evsel__open(evsel, NULL, tmap) >=3D 0; + } + evsel__delete(evsel); + } + + perf_thread_map__put(tmap); + return ret; +} + int print_hwcache_events(const struct print_callbacks *print_cb, void *pri= nt_state) { struct perf_pmu *pmu =3D NULL; --=20 2.40.1.495.gc816e09b53d-goog