From nobody Wed Sep 10 02:27:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0AEF5C77B73 for ; Tue, 2 May 2023 12:10:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234117AbjEBMKB (ORCPT ); Tue, 2 May 2023 08:10:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234030AbjEBMJ4 (ORCPT ); Tue, 2 May 2023 08:09:56 -0400 Received: from smtp-out2.suse.de (smtp-out2.suse.de [195.135.220.29]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 19D1644BF for ; Tue, 2 May 2023 05:09:54 -0700 (PDT) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id 92A261F8C4; Tue, 2 May 2023 12:09:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1683029393; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gVBUKM5fVdXUpPFkRUIn5N9J3pTHqSbjbMSZMdYf6OE=; b=AVx9e94ce1YQjDOweHYjuUzNmx3XQ1tCeCHLuY6tUkd/Bdf8Fhl3Xo1VRjo1pdmo5oRtee JWrsLOhtsmo7fjtRar4VlTX7Ivpdy3DwygPWfiZwbemhPLVLsxn72dx30u53NM/cbEASCi 1RXkV+PWWulMErVLTTBAX5Sjhn8tFDI= Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id 4FAF0139C3; Tue, 2 May 2023 12:09:53 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id DGszEpH9UGSPLwAAMHmgww (envelope-from ); Tue, 02 May 2023 12:09:53 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: mikelley@microsoft.com, Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH v6 02/16] x86/mtrr: replace some constants with defines Date: Tue, 2 May 2023 14:09:17 +0200 Message-Id: <20230502120931.20719-3-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230502120931.20719-1-jgross@suse.com> References: <20230502120931.20719-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Instead of using constants in MTRR code, use some new #defines. Replace size_or_mask and size_and_mask with the much easier concept of high reserved bits. Signed-off-by: Juergen Gross --- V5: - new patch (inspired by a request of Boris Petkov) V6: - switch macro names to match SDM nomenclature of MSRs (Boris Petkov) - replace size_or_mask and size_and_mask (Boris Petkov) --- arch/x86/include/asm/mtrr.h | 24 ++++++++++- arch/x86/kernel/cpu/mtrr/cleanup.c | 2 +- arch/x86/kernel/cpu/mtrr/generic.c | 68 +++++++++++++++--------------- arch/x86/kernel/cpu/mtrr/mtrr.c | 2 +- 4 files changed, 59 insertions(+), 37 deletions(-) diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index f0eeaf6e5f5f..15379aa41edc 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -23,8 +23,27 @@ #ifndef _ASM_X86_MTRR_H #define _ASM_X86_MTRR_H =20 +#include #include =20 +/* Defines for hardware MTRR registers. */ +#define MTRR_CAP_VCNT GENMASK(7, 0) +#define MTRR_CAP_FIX BIT_MASK(8) +#define MTRR_CAP_WC BIT_MASK(10) + +#define MTRR_DEF_TYPE_TYPE GENMASK(7, 0) +#define MTRR_DEF_TYPE_FE BIT_MASK(10) +#define MTRR_DEF_TYPE_E BIT_MASK(11) + +#define MTRR_DEF_TYPE_ENABLE (MTRR_DEF_TYPE_FE | MTRR_DEF_TYPE_E) +#define MTRR_DEF_TYPE_DISABLE ~(MTRR_DEF_TYPE_TYPE | MTRR_DEF_TYPE_ENABLE) + +#define MTRR_PHYSBASE_TYPE GENMASK(7, 0) +#define MTRR_PHYSBASE_RSVD GENMASK(11, 8) + +#define MTRR_PHYSMASK_RSVD GENMASK(10, 0) +#define MTRR_PHYSMASK_V BIT_MASK(11) + /* * The following functions are for use by other drivers that cannot use * arch_phys_wc_add and arch_phys_wc_del. @@ -121,7 +140,8 @@ struct mtrr_gentry32 { #endif /* CONFIG_COMPAT */ =20 /* Bit fields for enabled in struct mtrr_state_type */ -#define MTRR_STATE_MTRR_FIXED_ENABLED 0x01 -#define MTRR_STATE_MTRR_ENABLED 0x02 +#define MTRR_STATE_SHIFT 10 +#define MTRR_STATE_MTRR_FIXED_ENABLED (MTRR_DEF_TYPE_FE >> MTRR_STATE_SHIF= T) +#define MTRR_STATE_MTRR_ENABLED (MTRR_DEF_TYPE_E >> MTRR_STATE_SHIFT) =20 #endif /* _ASM_X86_MTRR_H */ diff --git a/arch/x86/kernel/cpu/mtrr/cleanup.c b/arch/x86/kernel/cpu/mtrr/= cleanup.c index 70314093bb9b..ca2d567e729e 100644 --- a/arch/x86/kernel/cpu/mtrr/cleanup.c +++ b/arch/x86/kernel/cpu/mtrr/cleanup.c @@ -890,7 +890,7 @@ int __init mtrr_trim_uncached_memory(unsigned long end_= pfn) return 0; =20 rdmsr(MSR_MTRRdefType, def, dummy); - def &=3D 0xff; + def &=3D MTRR_DEF_TYPE_TYPE; if (def !=3D MTRR_TYPE_UNCACHABLE) return 0; =20 diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/= generic.c index 3922552340b1..ad2a396233c1 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -38,14 +38,13 @@ u64 mtrr_tom2; struct mtrr_state_type mtrr_state; EXPORT_SYMBOL_GPL(mtrr_state); =20 -static u64 size_or_mask, size_and_mask; +static u32 phys_hi_rsvd; =20 void __init mtrr_set_mask(void) { unsigned int phys_addr =3D boot_cpu_data.x86_phys_bits; =20 - size_or_mask =3D ~GENMASK_ULL(phys_addr - PAGE_SHIFT - 1, 0); - size_and_mask =3D ~size_or_mask & GENMASK_ULL(39, 20); + phys_hi_rsvd =3D GENMASK(31, phys_addr - 32); } =20 /* @@ -79,10 +78,9 @@ static u64 get_mtrr_size(u64 mask) { u64 size; =20 - mask >>=3D PAGE_SHIFT; - mask |=3D size_or_mask; + mask |=3D (u64)phys_hi_rsvd << 32; size =3D -mask; - size <<=3D PAGE_SHIFT; + return size; } =20 @@ -181,7 +179,7 @@ static u8 mtrr_type_lookup_variable(u64 start, u64 end,= u64 *partial_end, for (i =3D 0; i < num_var_ranges; ++i) { unsigned short start_state, end_state, inclusive; =20 - if (!(mtrr_state.var_ranges[i].mask_lo & (1 << 11))) + if (!(mtrr_state.var_ranges[i].mask_lo & MTRR_PHYSMASK_V)) continue; =20 base =3D (((u64)mtrr_state.var_ranges[i].base_hi) << 32) + @@ -233,7 +231,8 @@ static u8 mtrr_type_lookup_variable(u64 start, u64 end,= u64 *partial_end, if ((start & mask) !=3D (base & mask)) continue; =20 - curr_match =3D mtrr_state.var_ranges[i].base_lo & 0xff; + curr_match =3D mtrr_state.var_ranges[i].base_lo & + MTRR_PHYSBASE_TYPE; if (prev_match =3D=3D MTRR_TYPE_INVALID) { prev_match =3D curr_match; continue; @@ -435,7 +434,7 @@ static void __init print_mtrr_state(void) high_width =3D (boot_cpu_data.x86_phys_bits - (32 - PAGE_SHIFT) + 3) / 4; =20 for (i =3D 0; i < num_var_ranges; ++i) { - if (mtrr_state.var_ranges[i].mask_lo & (1 << 11)) + if (mtrr_state.var_ranges[i].mask_lo & MTRR_PHYSMASK_V) pr_debug(" %u base %0*X%05X000 mask %0*X%05X000 %s\n", i, high_width, @@ -444,7 +443,8 @@ static void __init print_mtrr_state(void) high_width, mtrr_state.var_ranges[i].mask_hi, mtrr_state.var_ranges[i].mask_lo >> 12, - mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo & 0xff)); + mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo & + MTRR_PHYSBASE_TYPE)); else pr_debug(" %u disabled\n", i); } @@ -462,7 +462,7 @@ bool __init get_mtrr_state(void) vrs =3D mtrr_state.var_ranges; =20 rdmsr(MSR_MTRRcap, lo, dummy); - mtrr_state.have_fixed =3D (lo >> 8) & 1; + mtrr_state.have_fixed =3D !!(lo & MTRR_CAP_FIX); =20 for (i =3D 0; i < num_var_ranges; i++) get_mtrr_var_range(i, &vrs[i]); @@ -470,8 +470,9 @@ bool __init get_mtrr_state(void) get_fixed_ranges(mtrr_state.fixed_ranges); =20 rdmsr(MSR_MTRRdefType, lo, dummy); - mtrr_state.def_type =3D (lo & 0xff); - mtrr_state.enabled =3D (lo & 0xc00) >> 10; + mtrr_state.def_type =3D lo & MTRR_DEF_TYPE_TYPE; + mtrr_state.enabled =3D (lo & MTRR_DEF_TYPE_ENABLE) >> + MTRR_STATE_SHIFT; =20 if (amd_special_default_mtrr()) { unsigned low, high; @@ -584,7 +585,7 @@ static void generic_get_mtrr(unsigned int reg, unsigned= long *base, =20 rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi); =20 - if ((mask_lo & 0x800) =3D=3D 0) { + if ((mask_lo & MTRR_PHYSMASK_V) =3D=3D 0) { /* Invalid (i.e. free) range */ *base =3D 0; *size =3D 0; @@ -595,8 +596,8 @@ static void generic_get_mtrr(unsigned int reg, unsigned= long *base, rdmsr(MTRRphysBase_MSR(reg), base_lo, base_hi); =20 /* Work out the shifted address mask: */ - tmp =3D (u64)mask_hi << (32 - PAGE_SHIFT) | mask_lo >> PAGE_SHIFT; - mask =3D size_or_mask | tmp; + tmp =3D (u64)mask_hi << 32 | (mask_lo & PAGE_MASK); + mask =3D (u64)phys_hi_rsvd << 32 | tmp; =20 /* Expand tmp with high bits to all 1s: */ hi =3D fls64(tmp); @@ -614,9 +615,9 @@ static void generic_get_mtrr(unsigned int reg, unsigned= long *base, * This works correctly if size is a power of two, i.e. a * contiguous range: */ - *size =3D -mask; + *size =3D -mask >> PAGE_SHIFT; *base =3D (u64)base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT; - *type =3D base_lo & 0xff; + *type =3D base_lo & MTRR_PHYSBASE_TYPE; =20 out_put_cpu: put_cpu(); @@ -654,9 +655,8 @@ static bool set_mtrr_var_ranges(unsigned int index, str= uct mtrr_var_range *vr) bool changed =3D false; =20 rdmsr(MTRRphysBase_MSR(index), lo, hi); - if ((vr->base_lo & 0xfffff0ffUL) !=3D (lo & 0xfffff0ffUL) - || (vr->base_hi & (size_and_mask >> (32 - PAGE_SHIFT))) !=3D - (hi & (size_and_mask >> (32 - PAGE_SHIFT)))) { + if ((vr->base_lo & MTRR_PHYSBASE_RSVD) !=3D (lo & MTRR_PHYSBASE_RSVD) + || (vr->base_hi & ~phys_hi_rsvd) !=3D (hi & ~phys_hi_rsvd)) { =20 mtrr_wrmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi); changed =3D true; @@ -664,9 +664,8 @@ static bool set_mtrr_var_ranges(unsigned int index, str= uct mtrr_var_range *vr) =20 rdmsr(MTRRphysMask_MSR(index), lo, hi); =20 - if ((vr->mask_lo & 0xfffff800UL) !=3D (lo & 0xfffff800UL) - || (vr->mask_hi & (size_and_mask >> (32 - PAGE_SHIFT))) !=3D - (hi & (size_and_mask >> (32 - PAGE_SHIFT)))) { + if ((vr->mask_lo & MTRR_PHYSMASK_RSVD) !=3D (lo & MTRR_PHYSMASK_RSVD) + || (vr->mask_hi & ~phys_hi_rsvd) !=3D (hi & ~phys_hi_rsvd)) { mtrr_wrmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi); changed =3D true; } @@ -701,11 +700,13 @@ static unsigned long set_mtrr_state(void) * Set_mtrr_restore restores the old value of MTRRdefType, * so to set it we fiddle with the saved value: */ - if ((deftype_lo & 0xff) !=3D mtrr_state.def_type - || ((deftype_lo & 0xc00) >> 10) !=3D mtrr_state.enabled) { + if ((deftype_lo & MTRR_DEF_TYPE_TYPE) !=3D mtrr_state.def_type + || ((deftype_lo & MTRR_DEF_TYPE_ENABLE) >> MTRR_STATE_SHIFT) !=3D + mtrr_state.enabled) { =20 - deftype_lo =3D (deftype_lo & ~0xcff) | mtrr_state.def_type | - (mtrr_state.enabled << 10); + deftype_lo =3D (deftype_lo & MTRR_DEF_TYPE_DISABLE) | + mtrr_state.def_type | + (mtrr_state.enabled << MTRR_STATE_SHIFT); change_mask |=3D MTRR_CHANGE_MASK_DEFTYPE; } =20 @@ -718,7 +719,8 @@ void mtrr_disable(void) rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi); =20 /* Disable MTRRs, and set the default type to uncached */ - mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & ~0xcff, deftype_hi); + mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & MTRR_DEF_TYPE_DISABLE, + deftype_hi); } =20 void mtrr_enable(void) @@ -772,9 +774,9 @@ static void generic_set_mtrr(unsigned int reg, unsigned= long base, memset(vr, 0, sizeof(struct mtrr_var_range)); } else { vr->base_lo =3D base << PAGE_SHIFT | type; - vr->base_hi =3D (base & size_and_mask) >> (32 - PAGE_SHIFT); - vr->mask_lo =3D -size << PAGE_SHIFT | 0x800; - vr->mask_hi =3D (-size & size_and_mask) >> (32 - PAGE_SHIFT); + vr->base_hi =3D (base >> (32 - PAGE_SHIFT)) & ~phys_hi_rsvd; + vr->mask_lo =3D -size << PAGE_SHIFT | MTRR_PHYSMASK_V; + vr->mask_hi =3D (-size >> (32 - PAGE_SHIFT)) & ~phys_hi_rsvd; =20 mtrr_wrmsr(MTRRphysBase_MSR(reg), vr->base_lo, vr->base_hi); mtrr_wrmsr(MTRRphysMask_MSR(reg), vr->mask_lo, vr->mask_hi); @@ -827,7 +829,7 @@ static int generic_have_wrcomb(void) { unsigned long config, dummy; rdmsr(MSR_MTRRcap, config, dummy); - return config & (1 << 10); + return config & MTRR_CAP_WC; } =20 int positive_have_wrcomb(void) diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtr= r.c index 1bdab16f16bd..fddc4e0c6626 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -115,7 +115,7 @@ static void __init set_num_var_ranges(bool use_generic) else if (is_cpu(CYRIX) || is_cpu(CENTAUR)) config =3D 8; =20 - num_var_ranges =3D config & 0xff; + num_var_ranges =3D config & MTRR_CAP_VCNT; } =20 static void __init init_table(void) --=20 2.35.3