From nobody Wed Sep 10 02:29:35 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A06A0C77B73 for ; Tue, 2 May 2023 12:11:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234192AbjEBMLg (ORCPT ); Tue, 2 May 2023 08:11:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38416 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234189AbjEBMLV (ORCPT ); Tue, 2 May 2023 08:11:21 -0400 Received: from smtp-out2.suse.de (smtp-out2.suse.de [IPv6:2001:67c:2178:6::1d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E93B65FE7; Tue, 2 May 2023 05:10:56 -0700 (PDT) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id BF8FD1F8BE; Tue, 2 May 2023 12:10:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1683029450; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UokXgkWhNqi0xmtTfifqq0OnoWcJAag/Oc0h5DkNreY=; b=KrWOrtFCJedieSykS9Jct4rTuBScw/RdGMiGR1JONhQcMlsDbdJihM1pMvv6wLXAdaIcsf /Fwzw0GF3GmtcjAZgGfp074ngH/Llni/vZRTou42txOR+hmAj0R82XuqJl5XZwRTG6VHWQ TZ7VV1l/7lV2H4/e53JhaCjmOfFZM0I= Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id 78192139C3; Tue, 2 May 2023 12:10:50 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id MlsRHMr9UGQsMAAAMHmgww (envelope-from ); Tue, 02 May 2023 12:10:50 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, linux-doc@vger.kernel.org Cc: mikelley@microsoft.com, Juergen Gross , Jonathan Corbet , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH v6 12/16] x86/mtrr: add mtrr=debug command line option Date: Tue, 2 May 2023 14:09:27 +0200 Message-Id: <20230502120931.20719-13-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230502120931.20719-1-jgross@suse.com> References: <20230502120931.20719-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a new command line option "mtrr=3Ddebug" for getting debug output after building the new cache mode map. The output will include MTRR register values and the resulting map. For printing the MTRR register values print_mtrr_state() can be used. Just change it to use pr_info() instead of pr_debug() and call it only if mtrr=3Ddebug was specified. Signed-off-by: Juergen Gross --- V6: - new patch (Boris Petkov) --- .../admin-guide/kernel-parameters.txt | 4 ++ arch/x86/kernel/cpu/mtrr/generic.c | 64 +++++++++++++------ 2 files changed, 49 insertions(+), 19 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index 9e5bab29685f..44a87ada7145 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -3423,6 +3423,10 @@ [HW] Make the MicroTouch USB driver use raw coordinates ('y', default) or cooked coordinates ('n') =20 + mtrr=3Ddebug [X86] + Enable printing debug information related to MTRR + registers at boot time. + mtrr_chunk_size=3Dnn[KMG] [X86] used for mtrr cleanup. It is largest continuous chunk that could hold holes aka. UC entries. diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/= generic.c index a6dd240a09cb..e002856a5f4e 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c @@ -41,6 +41,23 @@ struct cache_map { u64 fixed:1; }; =20 +static bool mtrr_debug; + +static int __init mtrr_param_setup(char *str) +{ + int rc =3D 0; + + if (!str) + return -EINVAL; + if (!strcmp(str, "debug")) + mtrr_debug =3D true; + else + rc =3D -EINVAL; + + return rc; +} +early_param("mtrr", mtrr_param_setup); + /* * CACHE_MAP_MAX is the maximum number of memory ranges in cache_map, where * no 2 adjacent ranges have the same cache mode (those would be merged). @@ -519,6 +536,14 @@ void __init mtrr_build_map(void) pr_info("MTRR map: %u entries (%u fixed + %u variable; max %u), built fro= m %u variable MTRRs\n", cache_map_n, cache_map_fixed, cache_map_n - cache_map_fixed, get_cache_map_size(), num_var_ranges + (mtrr_tom2 !=3D 0)); + + if (mtrr_debug) { + for (i =3D 0; i < cache_map_n; i++) { + pr_info("%3u: %016llx-%016llx %s\n", i, + cache_map[i].start, cache_map[i].end - 1, + mtrr_attrib_to_str(cache_map[i].type)); + } + } } =20 /* Copy the cache_map from __initdata memory to dynamically allocated one.= */ @@ -725,8 +750,8 @@ static void __init print_fixed_last(void) if (!last_fixed_end) return; =20 - pr_debug(" %05X-%05X %s\n", last_fixed_start, - last_fixed_end - 1, mtrr_attrib_to_str(last_fixed_type)); + pr_info(" %05X-%05X %s\n", last_fixed_start, + last_fixed_end - 1, mtrr_attrib_to_str(last_fixed_type)); =20 last_fixed_end =3D 0; } @@ -764,10 +789,10 @@ static void __init print_mtrr_state(void) unsigned int i; int high_width; =20 - pr_debug("MTRR default type: %s\n", - mtrr_attrib_to_str(mtrr_state.def_type)); + pr_info("MTRR default type: %s\n", + mtrr_attrib_to_str(mtrr_state.def_type)); if (mtrr_state.have_fixed) { - pr_debug("MTRR fixed ranges %sabled:\n", + pr_info("MTRR fixed ranges %sabled:\n", ((mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED) && (mtrr_state.enabled & MTRR_STATE_MTRR_FIXED_ENABLED)) ? "en" : "dis"); @@ -782,27 +807,27 @@ static void __init print_mtrr_state(void) /* tail */ print_fixed_last(); } - pr_debug("MTRR variable ranges %sabled:\n", - mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED ? "en" : "dis"); + pr_info("MTRR variable ranges %sabled:\n", + mtrr_state.enabled & MTRR_STATE_MTRR_ENABLED ? "en" : "dis"); high_width =3D (boot_cpu_data.x86_phys_bits - (32 - PAGE_SHIFT) + 3) / 4; =20 for (i =3D 0; i < num_var_ranges; ++i) { if (mtrr_state.var_ranges[i].mask_lo & MTRR_PHYSMASK_V) - pr_debug(" %u base %0*X%05X000 mask %0*X%05X000 %s\n", - i, - high_width, - mtrr_state.var_ranges[i].base_hi, - mtrr_state.var_ranges[i].base_lo >> 12, - high_width, - mtrr_state.var_ranges[i].mask_hi, - mtrr_state.var_ranges[i].mask_lo >> 12, - mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo & + pr_info(" %u base %0*X%05X000 mask %0*X%05X000 %s\n", + i, + high_width, + mtrr_state.var_ranges[i].base_hi, + mtrr_state.var_ranges[i].base_lo >> 12, + high_width, + mtrr_state.var_ranges[i].mask_hi, + mtrr_state.var_ranges[i].mask_lo >> 12, + mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo & MTRR_PHYSBASE_TYPE)); else - pr_debug(" %u disabled\n", i); + pr_info(" %u disabled\n", i); } if (mtrr_tom2) - pr_debug("TOM2: %016llx aka %lldM\n", mtrr_tom2, mtrr_tom2>>20); + pr_info("TOM2: %016llx aka %lldM\n", mtrr_tom2, mtrr_tom2>>20); } =20 /* Grab all of the MTRR state for this CPU into *state */ @@ -838,7 +863,8 @@ bool __init get_mtrr_state(void) mtrr_tom2 &=3D 0xffffff800000ULL; } =20 - print_mtrr_state(); + if (mtrr_debug) + print_mtrr_state(); =20 mtrr_state_set =3D 1; =20 --=20 2.35.3