From nobody Wed Feb 11 21:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4750EC7EE26 for ; Tue, 2 May 2023 08:11:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233777AbjEBILe (ORCPT ); Tue, 2 May 2023 04:11:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57102 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233718AbjEBILb (ORCPT ); Tue, 2 May 2023 04:11:31 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2CB08DD; Tue, 2 May 2023 01:11:30 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3428BKTH077181; Tue, 2 May 2023 03:11:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1683015080; bh=dlS4w7paTqxT2Le+aU65P177HMr0KZ1Y0fE4fR9ZkNs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=zCBI+bqWx/9ahO1dy5pA99CbiqtM50nFouveZHJ10WYukooqlHgk6P7QYBo/sa8IR LssxoDpGZsC63h5dD1WwdgF/JmdJx/oCKFnG16fZurckt977V6QucCU4zmd7a8dr58 JmPgAcIGUtEGcLiWNFCQwrvwk/SwRnTo5BNWTIZE= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3428BKIP113478 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 2 May 2023 03:11:20 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 2 May 2023 03:11:19 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 2 May 2023 03:11:19 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3428BIfc044167; Tue, 2 May 2023 03:11:19 -0500 From: Bhavya Kapoor To: , CC: , , , , , , Subject: [PATCH v2 1/2] arm64: dts: ti: k3-j784s4-mcu-wakeup: Add support for ADC nodes Date: Tue, 2 May 2023 13:41:16 +0530 Message-ID: <20230502081117.21431-2-b-kapoor@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230502081117.21431-1-b-kapoor@ti.com> References: <20230502081117.21431-1-b-kapoor@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" J784S4 has two instances of 8 channel ADCs in MCU domain. Add support for both ADC nodes. Signed-off-by: Bhavya Kapoor --- .../boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index f04fcb614cbe..29daad707935 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -342,4 +342,44 @@ cpts@3d000 { ti,cpts-periodic-outputs =3D <2>; }; }; + + tscadc0: tscadc@40200000 { + compatible =3D "ti,am3359-tscadc"; + reg =3D <0x00 0x40200000 0x00 0x1000>; + interrupts =3D ; + power-domains =3D <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 0 0>; + assigned-clocks =3D <&k3_clks 0 2>; + assigned-clock-rates =3D <60000000>; + clock-names =3D "fck"; + dmas =3D <&main_udmap 0x7400>, + <&main_udmap 0x7401>; + dma-names =3D "fifo0", "fifo1"; + status =3D "disabled"; + + adc { + #io-channel-cells =3D <1>; + compatible =3D "ti,am3359-adc"; + }; + }; + + tscadc1: tscadc@40210000 { + compatible =3D "ti,am3359-tscadc"; + reg =3D <0x00 0x40210000 0x00 0x1000>; + interrupts =3D ; + power-domains =3D <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; + clocks =3D <&k3_clks 1 0>; + assigned-clocks =3D <&k3_clks 1 2>; + assigned-clock-rates =3D <60000000>; + clock-names =3D "fck"; + dmas =3D <&main_udmap 0x7402>, + <&main_udmap 0x7403>; + dma-names =3D "fifo0", "fifo1"; + status =3D "disabled"; + + adc { + #io-channel-cells =3D <1>; + compatible =3D "ti,am3359-adc"; + }; + }; }; --=20 2.34.1 From nobody Wed Feb 11 21:31:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 520ACC77B7E for ; Tue, 2 May 2023 08:11:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231610AbjEBILi (ORCPT ); Tue, 2 May 2023 04:11:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57104 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233714AbjEBILb (ORCPT ); Tue, 2 May 2023 04:11:31 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3CACD107; Tue, 2 May 2023 01:11:30 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3428BLql002142; Tue, 2 May 2023 03:11:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1683015081; bh=a6ZI53yX9DUPvOIQBXTrqbrRhFD0WsrUoQeABYfmphE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=uTC92QycX7VKP3zGc5wnavW4po2bjFnBJlffUfSzF0lwPNGI/ZMpUW8te9SyAotiF 8Ai90BfocGrm638+Yb6T3D4CMEJOo+FfurBhCL7+0zdSJt7+wTxQ00x3otKC+UFc/j F/1Ch3WHGGXqPAgCQwvjpnq84ll1G1HhcujQ71ww= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3428BLf5113485 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 2 May 2023 03:11:21 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 2 May 2023 03:11:21 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 2 May 2023 03:11:21 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3428BKcs003103; Tue, 2 May 2023 03:11:20 -0500 From: Bhavya Kapoor To: , CC: , , , , , , Subject: [PATCH v2 2/2] arm64: dts: ti: k3-j784s4-evm: Add pinmux information for ADC Date: Tue, 2 May 2023 13:41:17 +0530 Message-ID: <20230502081117.21431-3-b-kapoor@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230502081117.21431-1-b-kapoor@ti.com> References: <20230502081117.21431-1-b-kapoor@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" J784S4 has two instances of 8 channel ADCs in MCU domain. Add pinmux information for both ADC nodes. Signed-off-by: Bhavya Kapoor --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 44 ++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts= /ti/k3-j784s4-evm.dts index f33815953e77..292edf2f62ad 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -165,6 +165,32 @@ J784S4_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A36) MCU_M= DIO0_MDC */ J784S4_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ >; }; + + mcu_adc0_pins_default: mcu-adc0-pins-default { + pinctrl-single,pins =3D < + J784S4_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */ + J784S4_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */ + J784S4_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (T34) MCU_ADC0_AIN2 */ + J784S4_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (T36) MCU_ADC0_AIN3 */ + J784S4_WKUP_IOPAD(0x144, PIN_INPUT, 0) /* (P34) MCU_ADC0_AIN4 */ + J784S4_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (R37) MCU_ADC0_AIN5 */ + J784S4_WKUP_IOPAD(0x14c, PIN_INPUT, 0) /* (R33) MCU_ADC0_AIN6 */ + J784S4_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (V38) MCU_ADC0_AIN7 */ + >; + }; + + mcu_adc1_pins_default: mcu-adc1-pins-default { + pinctrl-single,pins =3D < + J784S4_WKUP_IOPAD(0x154, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */ + J784S4_WKUP_IOPAD(0x158, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */ + J784S4_WKUP_IOPAD(0x15c, PIN_INPUT, 0) /* (V34) MCU_ADC1_AIN2 */ + J784S4_WKUP_IOPAD(0x160, PIN_INPUT, 0) /* (W37) MCU_ADC1_AIN3 */ + J784S4_WKUP_IOPAD(0x164, PIN_INPUT, 0) /* (AA37) MCU_ADC1_AIN4 */ + J784S4_WKUP_IOPAD(0x168, PIN_INPUT, 0) /* (W33) MCU_ADC1_AIN5 */ + J784S4_WKUP_IOPAD(0x16c, PIN_INPUT, 0) /* (U33) MCU_ADC1_AIN6 */ + J784S4_WKUP_IOPAD(0x170, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ + >; + }; }; =20 &main_uart8 { @@ -253,3 +279,21 @@ &mcu_cpsw_port1 { phy-mode =3D "rgmii-rxid"; phy-handle =3D <&mcu_phy0>; }; + +&tscadc0 { + pinctrl-0 =3D <&mcu_adc0_pins_default>; + pinctrl-names =3D "default"; + status =3D "okay"; + adc { + ti,adc-channels =3D <0 1 2 3 4 5 6 7>; + }; +}; + +&tscadc1 { + pinctrl-0 =3D <&mcu_adc1_pins_default>; + pinctrl-names =3D "default"; + status =3D "okay"; + adc { + ti,adc-channels =3D <0 1 2 3 4 5 6 7>; + }; +}; --=20 2.34.1