From nobody Thu Feb 12 04:49:55 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB6D5C77B60 for ; Fri, 28 Apr 2023 19:06:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346603AbjD1TGg (ORCPT ); Fri, 28 Apr 2023 15:06:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46062 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346616AbjD1TG3 (ORCPT ); Fri, 28 Apr 2023 15:06:29 -0400 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24A0B59F4 for ; Fri, 28 Apr 2023 12:06:27 -0700 (PDT) Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-1a9253d4551so2779925ad.0 for ; Fri, 28 Apr 2023 12:06:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1682708786; x=1685300786; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jFqKaSshbd38sYLtbvsFAsIC70cXgzSexspJ+qNkyV8=; b=XnAwbOcj3oIdGm5mgK/A1KMo0zl0NXPLsK6Ex+j8wTHj+YS4AYBq7F0FGQ9EepC3AF f4g18o9k3NnlNok/OmbZTwiPhH7Xtpg5hYXbZPE7BppyipgRFvEIyb3ORWx46F3Zl9NX YRdibn90f2gEVEtCJijmmlViY71zsqd9e2JsieEzo7eK68Onw032p4Zw7kKqhC4onVrM fnwI1OUbLF2SlPyb8Qeo80sjBjkeZGskUE6W1tjBTUUsoTkMf6BDwclOUA2/DAs5IoWh jHfKhpJjHTjfMGJSZcgqE6rUGXD34lTbp/VA/OWdkOgPZD/kbiB/uQofgLQvPeZcNGZa 9R1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682708786; x=1685300786; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jFqKaSshbd38sYLtbvsFAsIC70cXgzSexspJ+qNkyV8=; b=SglD5mc81EetWst1AqxUPbPuf1c586NQoa7kHRXZ1max+FzSBcJHptKudHFGMZj7oJ eqvGv1tHdpkksejBqkofycgw+vw5QiHWzzgJJXj2xqTr6Bua9rP9P5RAxt/GZ/XVkS5D KCbXDRtk4tQPz7g/QQJ8XzbkeIo1LAN0iD4A7a05cvA31bnc2M8kakJ3nLN9LcA72xC7 4jmcM1vOklgZdoyZVPz7msDaF0MZlZYV4BRVDHnlZ0WgHkY2iOLDqycpmA7RRC2cLiUi YacXU17x86MB3Iw8wQfe+Pd/xgRk3xXBYwn5A0y2FMHczTxfPrHhsGttpKz+fBsrD1lc 2kLQ== X-Gm-Message-State: AC+VfDxv2Kw1PNBprIde0GghL+7CqFL6a9TuEMvvqYrXlMX7n7iqiSGq N1cRC+isBdh207S5Ue1b44Ueiw== X-Google-Smtp-Source: ACHHUZ6zsK/rXeuvueCzLKmEwUjIV1KR62eq0QfUEx2BJ11PBtuHXRuJ+WOwWqzn3qupChOIwIMv7Q== X-Received: by 2002:a17:903:228b:b0:1a1:b174:836c with SMTP id b11-20020a170903228b00b001a1b174836cmr8128192plh.16.1682708786587; Fri, 28 Apr 2023 12:06:26 -0700 (PDT) Received: from evan.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id w15-20020a170902d70f00b001a6c58e95d7sm13580733ply.269.2023.04.28.12.06.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Apr 2023 12:06:26 -0700 (PDT) From: Evan Green To: Palmer Dabbelt Cc: Evan Green , Albert Ou , Andrew Bresticker , Andrew Jones , Celeste Liu , Conor Dooley , Heiko Stuebner , Jonathan Corbet , Palmer Dabbelt , Paul Walmsley , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 3/3] RISC-V: hwprobe: Expose Zba and Zbb Date: Fri, 28 Apr 2023 12:06:08 -0700 Message-Id: <20230428190609.3239486-4-evan@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230428190609.3239486-1-evan@rivosinc.com> References: <20230428190609.3239486-1-evan@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add two new bits to the IMA_EXT_0 key for ZBA and ZBB extensions. These are accurately reported per CPU. Signed-off-by: Evan Green --- Documentation/riscv/hwprobe.rst | 7 +++++ arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ arch/riscv/kernel/sys_riscv.c | 43 ++++++++++++++++++++++----- 3 files changed, 45 insertions(+), 7 deletions(-) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.= rst index 9f0dd62dcb5d..21f444a38359 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -64,6 +64,13 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defin= ed by version 2.2 of the RISC-V ISA manual. =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension= is + supported, as defined in version 1.0 of the Bit-Manipulation ISA + extensions. + + * :c:macro:`RISCV_HWPROBE_IMA_ZBB`: The Zbb extension is supporte, as de= fined + in version 1.0 of the Bit-Manipulation ISA extensions. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 8d745a4ad8a2..ef3b060d4e8d 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -25,6 +25,8 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_KEY_IMA_EXT_0 4 #define RISCV_HWPROBE_IMA_FD (1 << 0) #define RISCV_HWPROBE_IMA_C (1 << 1) +#define RISCV_HWPROBE_EXT_ZBA (1 << 2) +#define RISCV_HWPROBE_EXT_ZBB (1 << 3) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 5db29683ebee..adfcb6b64db7 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -121,6 +121,41 @@ static void hwprobe_arch_id(struct riscv_hwprobe *pair, pair->value =3D id; } =20 +static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, + const struct cpumask *cpus) +{ + int cpu; + u64 missing =3D 0; + + pair->value =3D 0; + if (has_fpu()) + pair->value |=3D RISCV_HWPROBE_IMA_FD; + + if (riscv_isa_extension_available(NULL, c)) + pair->value |=3D RISCV_HWPROBE_IMA_C; + + /* + * Loop through and record extensions that 1) anyone has, and 2) anyone + * doesn't have. + */ + for_each_cpu(cpu, cpus) { + struct riscv_isainfo *isainfo =3D &hart_isa[cpu]; + + if (riscv_isa_extension_available(isainfo->isa, ZBA)) + pair->value |=3D RISCV_HWPROBE_EXT_ZBA; + else + missing |=3D RISCV_HWPROBE_EXT_ZBA; + + if (riscv_isa_extension_available(isainfo->isa, ZBB)) + pair->value |=3D RISCV_HWPROBE_EXT_ZBB; + else + missing |=3D RISCV_HWPROBE_EXT_ZBB; + } + + /* Now turn off reporting features if any CPU is missing it. */ + pair->value &=3D ~missing; +} + static u64 hwprobe_misaligned(const struct cpumask *cpus) { int cpu; @@ -164,13 +199,7 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pai= r, break; =20 case RISCV_HWPROBE_KEY_IMA_EXT_0: - pair->value =3D 0; - if (has_fpu()) - pair->value |=3D RISCV_HWPROBE_IMA_FD; - - if (riscv_isa_extension_available(NULL, c)) - pair->value |=3D RISCV_HWPROBE_IMA_C; - + hwprobe_isa_ext0(pair, cpus); break; =20 case RISCV_HWPROBE_KEY_CPUPERF_0: --=20 2.25.1