From nobody Thu Feb 12 03:18:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49B21C77B60 for ; Fri, 28 Apr 2023 19:06:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346596AbjD1TGZ (ORCPT ); Fri, 28 Apr 2023 15:06:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45820 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229578AbjD1TGW (ORCPT ); Fri, 28 Apr 2023 15:06:22 -0400 Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F06D82109 for ; Fri, 28 Apr 2023 12:06:20 -0700 (PDT) Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1a67bcde3a7so3167525ad.3 for ; Fri, 28 Apr 2023 12:06:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1682708780; x=1685300780; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Sje7w9+fB+EH+MGgG1/UMH/D2qIYNdlPqE6SA4WS6wE=; b=pVZ8HJMgQ3+xH35RV27J8SoRUhfsr98Jkc7MmLi6Bgcfx+F6nTPr35spG+gI0r8vME 7n5sAbd8B17cb2joGxEXMQOU/5+4UGqAgpsR5DH/ha+9kFGodY7MhwFoZ7LdIPC3YwCk MaFcWYCrH21MaVVGd1CQmwInR0iQSeQPuAfEkilVt+X/bRn2BuRvpPsbxY5vFfgxxN6L xkAEpscd1A4oH/sLbHch/BYMh9e8vc00OA8w4kRnQ0h8k/t6kufFuf4gsX7SkEF8srUp TL4c3hfx0Qw+k/rGR5dKZ+uAB9J12TaSu9C7daravYg/Ddo2LLF1AsdL+BPSRWCNrCM6 g/kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682708780; x=1685300780; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Sje7w9+fB+EH+MGgG1/UMH/D2qIYNdlPqE6SA4WS6wE=; b=P72D2vKAMuVBfd8IWLRY47i8KRAjoL8xGxVKnq1nbVxiA8R5esVJtxoFlf0KbRa/JF 43ah4h6BhtJA/0LJuc1BYWnvHN21w10VAeuijj2eG+KOwLqJNWIuaDZ3Bq1cuo3dTZ8U 2L1psKMP7wz07+5inaKj/yscbsSxhnQV63lOu7W5Y/bqMf+8HTU8pXfR70zUSYatpXJq kny54oVd47iT0Z9OpHDIGOfhA2XGQOK0M7NBnJ11Crv7iJOSgQAP07+Rc9o9zCugGpoY KHV69nzlL+fhd0nQDwNEsEB/nfuFiOWvxvVx/wc3FEdk2NKaVgtWIR2oQf+PwHH7DTq8 q+yg== X-Gm-Message-State: AC+VfDwSfasKwbFi5Q7xNtccm+01iAINFyHLlZzJSfLLgwd9RpuCDzbi ibGEF+T9o14z+QOT5r4D40gP2g== X-Google-Smtp-Source: ACHHUZ7QWo75WIrdyvyPauWX13WT4/nosdMHz5KIWESIS91E35ZRIbR5lIwAnVKK/fFCxGXw2g3xmQ== X-Received: by 2002:a17:902:7208:b0:1a5:1b94:e63d with SMTP id ba8-20020a170902720800b001a51b94e63dmr5691012plb.65.1682708780417; Fri, 28 Apr 2023 12:06:20 -0700 (PDT) Received: from evan.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id w15-20020a170902d70f00b001a6c58e95d7sm13580733ply.269.2023.04.28.12.06.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Apr 2023 12:06:20 -0700 (PDT) From: Evan Green To: Palmer Dabbelt Cc: Evan Green , Albert Ou , Andrew Jones , Anup Patel , Conor Dooley , Dao Lu , Heiko Stuebner , Jisheng Zhang , Palmer Dabbelt , Paul Walmsley , Sunil V L , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 1/3] RISC-V: Add Zba extension probing Date: Fri, 28 Apr 2023 12:06:06 -0700 Message-Id: <20230428190609.3239486-2-evan@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230428190609.3239486-1-evan@rivosinc.com> References: <20230428190609.3239486-1-evan@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the Zba address bit manipulation extension into those the kernel is aware of and maintains in its riscv_isa bitmap. Signed-off-by: Evan Green Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley Reviewed-by: Palmer Dabbelt --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpu.c | 1 + arch/riscv/kernel/cpufeature.c | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 9af793970855..fa36db9281ab 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -44,6 +44,7 @@ #define RISCV_ISA_EXT_ZIHINTPAUSE 32 #define RISCV_ISA_EXT_SVNAPOT 33 #define RISCV_ISA_EXT_ZICBOZ 34 +#define RISCV_ISA_EXT_ZBA 35 =20 #define RISCV_ISA_EXT_MAX 64 #define RISCV_ISA_EXT_NAME_LEN_MAX 32 diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 3df38052dcbd..2f85b1656557 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -184,6 +184,7 @@ static struct riscv_isa_ext_data isa_ext_arr[] =3D { __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), + __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 52585e088873..1a80474e308e 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -233,6 +233,7 @@ void __init riscv_fill_hwcap(void) SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL); SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT); SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); + SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA); SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB); SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM); SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ); --=20 2.25.1 From nobody Thu Feb 12 03:18:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50D40C77B7E for ; Fri, 28 Apr 2023 19:06:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346618AbjD1TG3 (ORCPT ); Fri, 28 Apr 2023 15:06:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45904 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346598AbjD1TGZ (ORCPT ); Fri, 28 Apr 2023 15:06:25 -0400 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 521FC5BB3 for ; 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charset="utf-8" The kernel maintains a mask of ISA extensions ANDed together across all harts. Let's also keep a bitmap of ISA extensions for each CPU. Although the kernel is currently unlikely to enable a feature that exists only on some CPUs, we want the ability to report asymmetric CPU extensions accurately to usermode. Note that riscv_fill_hwcaps() runs before the per_cpu_offsets are built, which is why I've used a [NR_CPUS] array rather than per_cpu() data. Signed-off-by: Evan Green Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley Reviewed-by: Palmer Dabbelt --- arch/riscv/include/asm/cpufeature.h | 10 ++++++++++ arch/riscv/kernel/cpufeature.c | 18 ++++++++++++------ 2 files changed, 22 insertions(+), 6 deletions(-) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h index 808d5403f2ac..23fed53b8815 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -6,6 +6,9 @@ #ifndef _ASM_CPUFEATURE_H #define _ASM_CPUFEATURE_H =20 +#include +#include + /* * These are probed via a device_initcall(), via either the SBI or directly * from the corresponding CSRs. @@ -16,8 +19,15 @@ struct riscv_cpuinfo { unsigned long mimpid; }; =20 +struct riscv_isainfo { + DECLARE_BITMAP(isa, RISCV_ISA_EXT_MAX); +}; + DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); =20 DECLARE_PER_CPU(long, misaligned_access_speed); =20 +/* Per-cpu ISA extensions. */ +extern struct riscv_isainfo hart_isa[NR_CPUS]; + #endif diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 1a80474e308e..0e9d66580478 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -25,6 +26,9 @@ unsigned long elf_hwcap __read_mostly; /* Host ISA bitmap */ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; =20 +/* Per-cpu ISA extensions. */ +struct riscv_isainfo hart_isa[NR_CPUS]; + /* Performance information */ DEFINE_PER_CPU(long, misaligned_access_speed); =20 @@ -112,14 +116,17 @@ void __init riscv_fill_hwcap(void) bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX); =20 for_each_of_cpu_node(node) { + struct riscv_isainfo *isainfo; unsigned long this_hwcap =3D 0; - DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); const char *temp; + unsigned int cpu_id; =20 rc =3D riscv_of_processor_hartid(node, &hartid); if (rc < 0) continue; =20 + cpu_id =3D riscv_hartid_to_cpuid(hartid); + isainfo =3D &hart_isa[cpu_id]; if (of_property_read_string(node, "riscv,isa", &isa)) { pr_warn("Unable to find \"riscv,isa\" devicetree entry\n"); continue; @@ -136,7 +143,6 @@ void __init riscv_fill_hwcap(void) /* The riscv,isa DT property must start with rv64 or rv32 */ if (temp =3D=3D isa) continue; - bitmap_zero(this_isa, RISCV_ISA_EXT_MAX); for (; *isa; ++isa) { const char *ext =3D isa++; const char *ext_end =3D isa; @@ -214,7 +220,7 @@ void __init riscv_fill_hwcap(void) if ((ext_end - ext =3D=3D sizeof(name) - 1) && \ !memcmp(ext, name, sizeof(name) - 1) && \ riscv_isa_extension_check(bit)) \ - set_bit(bit, this_isa); \ + set_bit(bit, isainfo->isa); \ } while (false) \ =20 if (unlikely(ext_err)) @@ -224,7 +230,7 @@ void __init riscv_fill_hwcap(void) =20 if (riscv_isa_extension_check(nr)) { this_hwcap |=3D isa2hwcap[nr]; - set_bit(nr, this_isa); + set_bit(nr, isainfo->isa); } } else { /* sorted alphabetically */ @@ -253,9 +259,9 @@ void __init riscv_fill_hwcap(void) elf_hwcap =3D this_hwcap; =20 if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX)) - bitmap_copy(riscv_isa, this_isa, RISCV_ISA_EXT_MAX); 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Fri, 28 Apr 2023 12:06:26 -0700 (PDT) From: Evan Green To: Palmer Dabbelt Cc: Evan Green , Albert Ou , Andrew Bresticker , Andrew Jones , Celeste Liu , Conor Dooley , Heiko Stuebner , Jonathan Corbet , Palmer Dabbelt , Paul Walmsley , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH 3/3] RISC-V: hwprobe: Expose Zba and Zbb Date: Fri, 28 Apr 2023 12:06:08 -0700 Message-Id: <20230428190609.3239486-4-evan@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230428190609.3239486-1-evan@rivosinc.com> References: <20230428190609.3239486-1-evan@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add two new bits to the IMA_EXT_0 key for ZBA and ZBB extensions. These are accurately reported per CPU. Signed-off-by: Evan Green Reviewed-by: Andrew Jones --- Documentation/riscv/hwprobe.rst | 7 +++++ arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ arch/riscv/kernel/sys_riscv.c | 43 ++++++++++++++++++++++----- 3 files changed, 45 insertions(+), 7 deletions(-) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.= rst index 9f0dd62dcb5d..21f444a38359 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -64,6 +64,13 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defin= ed by version 2.2 of the RISC-V ISA manual. =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension= is + supported, as defined in version 1.0 of the Bit-Manipulation ISA + extensions. + + * :c:macro:`RISCV_HWPROBE_IMA_ZBB`: The Zbb extension is supporte, as de= fined + in version 1.0 of the Bit-Manipulation ISA extensions. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index 8d745a4ad8a2..ef3b060d4e8d 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -25,6 +25,8 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_KEY_IMA_EXT_0 4 #define RISCV_HWPROBE_IMA_FD (1 << 0) #define RISCV_HWPROBE_IMA_C (1 << 1) +#define RISCV_HWPROBE_EXT_ZBA (1 << 2) +#define RISCV_HWPROBE_EXT_ZBB (1 << 3) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 5db29683ebee..adfcb6b64db7 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -121,6 +121,41 @@ static void hwprobe_arch_id(struct riscv_hwprobe *pair, pair->value =3D id; } =20 +static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, + const struct cpumask *cpus) +{ + int cpu; + u64 missing =3D 0; + + pair->value =3D 0; + if (has_fpu()) + pair->value |=3D RISCV_HWPROBE_IMA_FD; + + if (riscv_isa_extension_available(NULL, c)) + pair->value |=3D RISCV_HWPROBE_IMA_C; + + /* + * Loop through and record extensions that 1) anyone has, and 2) anyone + * doesn't have. + */ + for_each_cpu(cpu, cpus) { + struct riscv_isainfo *isainfo =3D &hart_isa[cpu]; + + if (riscv_isa_extension_available(isainfo->isa, ZBA)) + pair->value |=3D RISCV_HWPROBE_EXT_ZBA; + else + missing |=3D RISCV_HWPROBE_EXT_ZBA; + + if (riscv_isa_extension_available(isainfo->isa, ZBB)) + pair->value |=3D RISCV_HWPROBE_EXT_ZBB; + else + missing |=3D RISCV_HWPROBE_EXT_ZBB; + } + + /* Now turn off reporting features if any CPU is missing it. */ + pair->value &=3D ~missing; +} + static u64 hwprobe_misaligned(const struct cpumask *cpus) { int cpu; @@ -164,13 +199,7 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pai= r, break; =20 case RISCV_HWPROBE_KEY_IMA_EXT_0: - pair->value =3D 0; - if (has_fpu()) - pair->value |=3D RISCV_HWPROBE_IMA_FD; - - if (riscv_isa_extension_available(NULL, c)) - pair->value |=3D RISCV_HWPROBE_IMA_C; - + hwprobe_isa_ext0(pair, cpus); break; =20 case RISCV_HWPROBE_KEY_CPUPERF_0: --=20 2.25.1