From nobody Tue Dec 16 12:21:35 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80490C77B7E for ; Thu, 27 Apr 2023 20:45:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344228AbjD0Upz (ORCPT ); Thu, 27 Apr 2023 16:45:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41400 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344295AbjD0Upt (ORCPT ); Thu, 27 Apr 2023 16:45:49 -0400 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0338E3C07 for ; Thu, 27 Apr 2023 13:45:47 -0700 (PDT) Received: by mail-ej1-x62e.google.com with SMTP id a640c23a62f3a-959a3e2dd27so1077479166b.3 for ; Thu, 27 Apr 2023 13:45:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1682628346; x=1685220346; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Hf8K+LPV3HpQoodPsHclIndfavzTHfh5H+b7Pu9+qX0=; b=lYQb9N0DXJFaYlcVpdVJTsWypegS4pxbOgWG4uYPWRv0tlbBFBKpgdjjuIJ7l89OKn MjxoNkkecvtACZfe3IMOjhngU6dFPvHM6Jb0dKqxdqG2fY33lE5vlStJ4DhOLLou9+Oc EFPe8U5O53BQC+dflc06JM2/KRewWS9Fgm8wY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682628346; x=1685220346; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Hf8K+LPV3HpQoodPsHclIndfavzTHfh5H+b7Pu9+qX0=; b=SNIQD5LzVPq0t4bj8Z6XjFfopm//xoA212uQ9j7WAvOeJyyu3SpHFLGa2TpGpYujI2 2RdMEIQ5Ss8JGWz+dkFHEXusdC8J5PPawGUrkAFSXRaSQTjQ2JWrVlI1DtFsmjV7M3bu FU4Zw8rfMpsS3OfeCgyMhfeTcbSUFRu6mfn1cUG6rM94BD4zIamyPI6gv8ThKv3LHsQY xiV8SN3AdHI8CuBSvx9CVihYKE4jkLIqWYarQmRd92Whp48a8hu1BFSq0udiB++kK4jT 9AdmML+aUUNQnbliB6oWcU0/6yK6h64U1i6slw3kQ5WeSgX+jpS/f7yWI9q/D9YXNjm+ sPWw== X-Gm-Message-State: AC+VfDyG/cDYpL996hgqmZTEIJV3FudT4ru0LOuZNDpAJRQW19KkDr/c sbsNj6rY41/x/MF3IpZBFDjyviUpgEHCdlBtjugPLg== X-Google-Smtp-Source: ACHHUZ7f+2fEQbl7Qy1ajgnJooRSCuUwsjTRMFmMCuy0tPNeKm5PO7GL8KTfujgsTrfBLu+ShkBDpA== X-Received: by 2002:a17:906:9b86:b0:957:758e:df57 with SMTP id dd6-20020a1709069b8600b00957758edf57mr3360655ejc.65.1682628346138; Thu, 27 Apr 2023 13:45:46 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-87-5-99-194.retail.telecomitalia.it. [87.5.99.194]) by smtp.gmail.com with ESMTPSA id s12-20020a170906bc4c00b00947ed087a2csm10171360ejv.154.2023.04.27.13.45.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Apr 2023 13:45:45 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, Amarula patchwork , Dario Binacchi , Alexandre Torgue , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Krzysztof Kozlowski , Marc Kleine-Budde , Maxime Coquelin , Paolo Abeni , Rob Herring , Wolfgang Grandegger , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-can@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, netdev@vger.kernel.org Subject: [PATCH v2 1/5] dt-bindings: net: can: add "st,can-secondary" property Date: Thu, 27 Apr 2023 22:45:36 +0200 Message-Id: <20230427204540.3126234-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20230427204540.3126234-1-dario.binacchi@amarulasolutions.com> References: <20230427204540.3126234-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" On the stm32f7 Socs the can peripheral can be in single or dual configuration. In the dual configuration, in turn, it can be in primary or secondary mode. The addition of the 'st,can-secondary' property allows you to specify this mode in the dual configuration. CAN peripheral nodes in single configuration contain neither "st,can-primary" nor "st,can-secondary". Signed-off-by: Dario Binacchi Reviewed-by: Rob Herring --- (no changes since v1) .../bindings/net/can/st,stm32-bxcan.yaml | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml = b/Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml index 769fa5c27b76..de1d4298893b 100644 --- a/Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml +++ b/Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml @@ -21,11 +21,22 @@ properties: =20 st,can-primary: description: - Primary and secondary mode of the bxCAN peripheral is only relevant - if the chip has two CAN peripherals. In that case they share some - of the required logic. + Primary mode of the bxCAN peripheral is only relevant if the chip has + two CAN peripherals in dual CAN configuration. In that case they sha= re + some of the required logic. + Not to be used if the peripheral is in single CAN configuration. To avoid misunderstandings, it should be noted that ST documentation - uses the terms master/slave instead of primary/secondary. + uses the terms master instead of primary. + type: boolean + + st,can-secondary: + description: + Secondary mode of the bxCAN peripheral is only relevant if the chip + has two CAN peripherals in dual CAN configuration. In that case they + share some of the required logic. + Not to be used if the peripheral is in single CAN configuration. + To avoid misunderstandings, it should be noted that ST documentation + uses the terms slave instead of secondary. type: boolean =20 reg: --=20 2.32.0 From nobody Tue Dec 16 12:21:35 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8895C77B73 for ; Thu, 27 Apr 2023 20:45:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344326AbjD0Up6 (ORCPT ); Thu, 27 Apr 2023 16:45:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41448 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344310AbjD0Upu (ORCPT ); Thu, 27 Apr 2023 16:45:50 -0400 Received: from mail-ed1-x529.google.com (mail-ed1-x529.google.com [IPv6:2a00:1450:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8AA5744A3 for ; Thu, 27 Apr 2023 13:45:49 -0700 (PDT) Received: by mail-ed1-x529.google.com with SMTP id 4fb4d7f45d1cf-505934ccc35so15618545a12.2 for ; Thu, 27 Apr 2023 13:45:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1682628348; x=1685220348; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=v2A7EdpRRw4uhUr29cHp9TanChHdCrYmggTLXrFrhPk=; b=hIxfVLSq+nmegxqmVyJw4MiJ83Xqb06fTI1IBsWQL4pGWYAnJTdpzju1aNI+zZuuwD xX5hlc5OhhvXhAJ28lcUTKhZpgp1fGOlxaPd7NsrEqXBWSv7t71UqARcnrEmMUdvbMrX ht0H7epNLh2eseqd5EQA6gI8DPVQZq+ED5daQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682628348; x=1685220348; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v2A7EdpRRw4uhUr29cHp9TanChHdCrYmggTLXrFrhPk=; b=dyc6i7oQNmH0709eK12rNXqSvXr6VS1DyRnM+eXf2uiiXlPnAlKj/cyf1M6Lc1JxB2 bVRhOiDg79TGUOlKOEi8ePvybpBwWxm/S+wWVupLFf4eHmy/uASxzFmiO+RCQJyKHvVq 7OUfTwWN5qJbj2PsfrQHfBFd9H4GynAq+TH+WdJYKxHVnNn2Vw7UdNFXOO1RNXSn0mdg pE1e7bOBerGaiUhXBfDRb94aAj3IEfBH4w7QAlCIic/wZfVtL7PQa3bs2+x33feqbUCl ttL87XmUQENFSdkDCQ9cFSD6DZ84ojL6KJ/v2hw1fX6h8KXYZj7xS8qggAhjBzW7diHU 0NkA== X-Gm-Message-State: AC+VfDwb20wMC9Yu6WnXKELBNZQJaEBcaW5coUpjD6/BI/o3g3CatsiY OhhgGmMEQbCkR/LU8P0HRbomdzM1zUsrWtoB7hppcw== X-Google-Smtp-Source: ACHHUZ5pkrfEo97jWwEggqo9NSV1NaQsI4JAPpU1paNohPHEtxduAxt0kbk7S9GKgqHPZwm14QdW9g== X-Received: by 2002:a17:907:9807:b0:94f:24d7:64d4 with SMTP id ji7-20020a170907980700b0094f24d764d4mr3007723ejc.37.1682628347769; Thu, 27 Apr 2023 13:45:47 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-87-5-99-194.retail.telecomitalia.it. [87.5.99.194]) by smtp.gmail.com with ESMTPSA id s12-20020a170906bc4c00b00947ed087a2csm10171360ejv.154.2023.04.27.13.45.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Apr 2023 13:45:47 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, Amarula patchwork , Dario Binacchi , Alexandre Torgue , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v2 2/5] ARM: dts: stm32f429: put can2 in secondary mode Date: Thu, 27 Apr 2023 22:45:37 +0200 Message-Id: <20230427204540.3126234-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20230427204540.3126234-1-dario.binacchi@amarulasolutions.com> References: <20230427204540.3126234-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This is a preparation patch for the upcoming support to manage CAN peripherals in single configuration. The addition ensures backwards compatibility. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm/boot/dts/stm32f429.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429= .dtsi index c9e05e3540d6..00bf53f99c29 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -387,6 +387,7 @@ can2: can@40006800 { interrupt-names =3D "tx", "rx0", "rx1", "sce"; resets =3D <&rcc STM32F4_APB1_RESET(CAN2)>; clocks =3D <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>; + st,can-secondary; st,gcan =3D <&gcan>; status =3D "disabled"; }; --=20 2.32.0 From nobody Tue Dec 16 12:21:35 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2183C77B7E for ; Thu, 27 Apr 2023 20:46:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344176AbjD0UqC (ORCPT ); Thu, 27 Apr 2023 16:46:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41442 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344313AbjD0Upx (ORCPT ); Thu, 27 Apr 2023 16:45:53 -0400 Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AAC6946BE for ; Thu, 27 Apr 2023 13:45:51 -0700 (PDT) Received: by mail-ej1-x62c.google.com with SMTP id a640c23a62f3a-953343581a4so1381654766b.3 for ; Thu, 27 Apr 2023 13:45:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1682628350; x=1685220350; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8zgyM9/Qsb7y0LcnLSlDess36RbYnrfbiOfx4wd1SRU=; b=C0kEWeMPUx9aQmFafDeK++7KxvR/FRLnqASxZ467WKjEKHO4kRSWw8X66kfedTFAZV k4bgWFabp/4gWrqn5uyRPdUTMUct44VJOkbw1eGKd/h5Y2DwEUi20UwtyMTHTRKtOzQ/ uDyeKQzPP2dYzVUk6300KOiLOBWtp47JlVaZA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682628350; x=1685220350; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8zgyM9/Qsb7y0LcnLSlDess36RbYnrfbiOfx4wd1SRU=; b=UQ9C2neRg8CTqcozmiW1NJwnHjGedaxpV3Q7CwEvmVOYJjn26uSJn1u48HmyFoN44w 3reNU7I6JMBqPT5uMySTdusTYP9yzjVqnYOHCD0HDqS0WzmyejcL/YhPTNi0mPJ7+9xx XZtQ9ymyvtI/9ajYMLPcGo0VfB8dgPTjhlwwnIj/CEQs1VDZRqk6xX5lsZdlWRMzd2UT d38L/WaHh6LF8Ka2r1pXB/KdbHJLiBpk7lCyie/IxT2mZzGBIdMXO/1oLF9ddiY4bvRD L+OGqDoFPGYey2GRvS7RMaiIGGhlXLm9/MPChs/hBMEnWiKYEKVzTkeQYtNE69BgyrXv TCjQ== X-Gm-Message-State: AC+VfDw9c+7rVMKHI4VxASJMfjwPA/bf54NNNYBsAky+5QrheXzVcVEh DS6qDEUiuRezJazt8Oqp12SHJ/vV7YV/c0i8nXE9wQ== X-Google-Smtp-Source: ACHHUZ7xp3LajXmJwIzUw4bO+6Ie+hY8CRiA9yNimoCacSraqyoqOfQE8akxqqf8UroKvyN6TWHbXQ== X-Received: by 2002:a17:907:3e1a:b0:94f:1a11:e07d with SMTP id hp26-20020a1709073e1a00b0094f1a11e07dmr3458979ejc.32.1682628349735; Thu, 27 Apr 2023 13:45:49 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-87-5-99-194.retail.telecomitalia.it. [87.5.99.194]) by smtp.gmail.com with ESMTPSA id s12-20020a170906bc4c00b00947ed087a2csm10171360ejv.154.2023.04.27.13.45.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Apr 2023 13:45:49 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, Amarula patchwork , Dario Binacchi , Alexandre Torgue , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v2 3/5] ARM: dts: stm32: add pin map for CAN controller on stm32f7 Date: Thu, 27 Apr 2023 22:45:38 +0200 Message-Id: <20230427204540.3126234-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20230427204540.3126234-1-dario.binacchi@amarulasolutions.com> References: <20230427204540.3126234-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add pin configurations for using CAN controller on stm32f7. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm/boot/dts/stm32f7-pinctrl.dtsi | 82 ++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/stm= 32f7-pinctrl.dtsi index c8e6c52fb248..9f65403295ca 100644 --- a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi @@ -283,6 +283,88 @@ pins2 { slew-rate =3D <2>; }; }; + + can1_pins_a: can1-0 { + pins1 { + pinmux =3D ; /* CAN1_TX */ + }; + pins2 { + pinmux =3D ; /* CAN1_RX */ + bias-pull-up; + }; + }; + + can1_pins_b: can1-1 { + pins1 { + pinmux =3D ; /* CAN1_TX */ + }; + pins2 { + pinmux =3D ; /* CAN1_RX */ + bias-pull-up; + }; + }; + + can1_pins_c: can1-2 { + pins1 { + pinmux =3D ; /* CAN1_TX */ + }; + pins2 { + pinmux =3D ; /* CAN1_RX */ + bias-pull-up; + + }; + }; + + can1_pins_d: can1-3 { + pins1 { + pinmux =3D ; /* CAN1_TX */ + }; + pins2 { + pinmux =3D ; /* CAN1_RX */ + bias-pull-up; + + }; + }; + + can2_pins_a: can2-0 { + pins1 { + pinmux =3D ; /* CAN2_TX */ + }; + pins2 { + pinmux =3D ; /* CAN2_RX */ + bias-pull-up; + }; + }; + + can2_pins_b: can2-1 { + pins1 { + pinmux =3D ; /* CAN2_TX */ + }; + pins2 { + pinmux =3D ; /* CAN2_RX */ + bias-pull-up; + }; + }; + + can3_pins_a: can3-0 { + pins1 { + pinmux =3D ; /* CAN3_TX */ + }; + pins2 { + pinmux =3D ; /* CAN3_RX */ + bias-pull-up; + }; + }; + + can3_pins_b: can3-1 { + pins1 { + pinmux =3D ; /* CAN3_TX */ + }; + pins2 { + pinmux =3D ; /* CAN3_RX */ + bias-pull-up; + }; + }; }; }; }; --=20 2.32.0 From nobody Tue Dec 16 12:21:35 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D03EC77B73 for ; Thu, 27 Apr 2023 20:46:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344342AbjD0UqF (ORCPT ); Thu, 27 Apr 2023 16:46:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41652 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344318AbjD0Up4 (ORCPT ); Thu, 27 Apr 2023 16:45:56 -0400 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3FAF146B7 for ; Thu, 27 Apr 2023 13:45:54 -0700 (PDT) Received: by mail-ej1-x62f.google.com with SMTP id a640c23a62f3a-94f3cd32799so1718204266b.0 for ; Thu, 27 Apr 2023 13:45:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1682628352; x=1685220352; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=v1g80Na1OEbBoslJdzzF/Prgy9dbHeWplBduFJrTGTE=; b=DvLGcylpQYmWAth/6x3toQJKgwI8AKXZeYaKAEYk1Qwh5YqdkwBS/r69ziz2Jz0bIk 56inSpEO9OPobT/T6x2tgj1d6O0meEzp1hNVCQSnzkuizUqX+GtJcBj76Qh5EB3IW6/n oYNww7liCyUl+1YC28I882Pv7ewDVb5CnDPsQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682628352; x=1685220352; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v1g80Na1OEbBoslJdzzF/Prgy9dbHeWplBduFJrTGTE=; b=LvDjRWQgVcMWaPagXY8Yalsfb4Gcs5pDmV6CbxFLRwLBuqJfif4J65hNVrDtr9eL84 UOyK3p91crl5806YCxgoFVeF1JjQZMRbgJq9pnIFvt1lkTzy5eYXav89/D0DOUHBTav1 MWwz+dQw5nlpWDeXAi2ag39s1s9tQTyuWa2wVRFbJ1uyq/OtPSVouWlaUzcMiNbEyeXx yXR0lTzrInhut2MuBnSpHZit5wj4luXDFHK1z65PpwZDwOqs8IRsBo5UrBq2yt30bj8I 968BZ9Qos2voLSt1SOeTCYXOi3B/qaPUOPH/qkjvZ9CZPu9R21P7LLNGymjj8EH8/DfE ZC6Q== X-Gm-Message-State: AC+VfDzj+Xl/+2dSX7lFEuza2d/+DPOqtJNDN+j5CSHTIjm+UYseju3H 5yrAftuwukW+SyjJxgbHn3kvHTEKUTHYgjD4ugm5Og== X-Google-Smtp-Source: ACHHUZ4PGI/ct8o2uaXVoBpyRsD8PbY2Jehj2M6pOSB2wOzLfB2wdU6oi6hHy1bXWe3tEjrfYjL7dQ== X-Received: by 2002:a17:906:4fd6:b0:958:2cb5:9ada with SMTP id i22-20020a1709064fd600b009582cb59adamr3071816ejw.39.1682628352378; Thu, 27 Apr 2023 13:45:52 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-87-5-99-194.retail.telecomitalia.it. [87.5.99.194]) by smtp.gmail.com with ESMTPSA id s12-20020a170906bc4c00b00947ed087a2csm10171360ejv.154.2023.04.27.13.45.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Apr 2023 13:45:51 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, Amarula patchwork , Dario Binacchi , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Marc Kleine-Budde , Paolo Abeni , Wolfgang Grandegger , linux-can@vger.kernel.org, netdev@vger.kernel.org Subject: [PATCH v2 4/5] can: bxcan: add support for single peripheral configuration Date: Thu, 27 Apr 2023 22:45:39 +0200 Message-Id: <20230427204540.3126234-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20230427204540.3126234-1-dario.binacchi@amarulasolutions.com> References: <20230427204540.3126234-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for bxCAN controller in single peripheral configuration: - primary bxCAN - dedicated Memory Access Controller unit - 512-byte SRAM memory - 14 filter banks Signed-off-by: Dario Binacchi --- Changes in v2: - s/fiter/filter/ in the commit message - Replace struct bxcan_mb::primary with struct bxcan_mb::cfg. drivers/net/can/bxcan.c | 34 +++++++++++++++++++++++----------- 1 file changed, 23 insertions(+), 11 deletions(-) diff --git a/drivers/net/can/bxcan.c b/drivers/net/can/bxcan.c index e26ccd41e3cb..027a8a162fe4 100644 --- a/drivers/net/can/bxcan.c +++ b/drivers/net/can/bxcan.c @@ -118,7 +118,7 @@ #define BXCAN_FiR1_REG(b) (0x40 + (b) * 8) #define BXCAN_FiR2_REG(b) (0x44 + (b) * 8) =20 -#define BXCAN_FILTER_ID(primary) (primary ? 0 : 14) +#define BXCAN_FILTER_ID(cfg) ((cfg) =3D=3D BXCAN_CFG_DUAL_SECONDARY ? 14 := 0) =20 /* Filter primary register (FMR) bits */ #define BXCAN_FMR_CANSB_MASK GENMASK(13, 8) @@ -135,6 +135,12 @@ enum bxcan_lec_code { BXCAN_LEC_UNUSED }; =20 +enum bxcan_cfg { + BXCAN_CFG_SINGLE =3D 0, + BXCAN_CFG_DUAL_PRIMARY, + BXCAN_CFG_DUAL_SECONDARY +}; + /* Structure of the message buffer */ struct bxcan_mb { u32 id; /* can identifier */ @@ -167,7 +173,7 @@ struct bxcan_priv { struct regmap *gcan; int tx_irq; int sce_irq; - bool primary; + enum bxcan_cfg cfg; struct clk *clk; spinlock_t rmw_lock; /* lock for read-modify-write operations */ unsigned int tx_head; @@ -202,17 +208,17 @@ static inline void bxcan_rmw(struct bxcan_priv *priv,= void __iomem *addr, spin_unlock_irqrestore(&priv->rmw_lock, flags); } =20 -static void bxcan_disable_filters(struct bxcan_priv *priv, bool primary) +static void bxcan_disable_filters(struct bxcan_priv *priv, enum bxcan_cfg = cfg) { - unsigned int fid =3D BXCAN_FILTER_ID(primary); + unsigned int fid =3D BXCAN_FILTER_ID(cfg); u32 fmask =3D BIT(fid); =20 regmap_update_bits(priv->gcan, BXCAN_FA1R_REG, fmask, 0); } =20 -static void bxcan_enable_filters(struct bxcan_priv *priv, bool primary) +static void bxcan_enable_filters(struct bxcan_priv *priv, enum bxcan_cfg c= fg) { - unsigned int fid =3D BXCAN_FILTER_ID(primary); + unsigned int fid =3D BXCAN_FILTER_ID(cfg); u32 fmask =3D BIT(fid); =20 /* Filter settings: @@ -680,7 +686,7 @@ static int bxcan_chip_start(struct net_device *ndev) BXCAN_BTR_BRP_MASK | BXCAN_BTR_TS1_MASK | BXCAN_BTR_TS2_MASK | BXCAN_BTR_SJW_MASK, set); =20 - bxcan_enable_filters(priv, priv->primary); + bxcan_enable_filters(priv, priv->cfg); =20 /* Clear all internal status */ priv->tx_head =3D 0; @@ -806,7 +812,7 @@ static void bxcan_chip_stop(struct net_device *ndev) BXCAN_IER_EPVIE | BXCAN_IER_EWGIE | BXCAN_IER_FOVIE1 | BXCAN_IER_FFIE1 | BXCAN_IER_FMPIE1 | BXCAN_IER_FOVIE0 | BXCAN_IER_FFIE0 | BXCAN_IER_FMPIE0 | BXCAN_IER_TMEIE, 0); - bxcan_disable_filters(priv, priv->primary); + bxcan_disable_filters(priv, priv->cfg); bxcan_enter_sleep_mode(priv); priv->can.state =3D CAN_STATE_STOPPED; } @@ -931,7 +937,7 @@ static int bxcan_probe(struct platform_device *pdev) struct clk *clk =3D NULL; void __iomem *regs; struct regmap *gcan; - bool primary; + enum bxcan_cfg cfg; int err, rx_irq, tx_irq, sce_irq; =20 regs =3D devm_platform_ioremap_resource(pdev, 0); @@ -946,7 +952,13 @@ static int bxcan_probe(struct platform_device *pdev) return PTR_ERR(gcan); } =20 - primary =3D of_property_read_bool(np, "st,can-primary"); + if (of_property_read_bool(np, "st,can-primary")) + cfg =3D BXCAN_CFG_DUAL_PRIMARY; + else if (of_property_read_bool(np, "st,can-secondary")) + cfg =3D BXCAN_CFG_DUAL_SECONDARY; + else + cfg =3D BXCAN_CFG_SINGLE; + clk =3D devm_clk_get(dev, NULL); if (IS_ERR(clk)) { dev_err(dev, "failed to get clock\n"); @@ -992,7 +1004,7 @@ static int bxcan_probe(struct platform_device *pdev) priv->clk =3D clk; priv->tx_irq =3D tx_irq; priv->sce_irq =3D sce_irq; - priv->primary =3D primary; + priv->cfg =3D cfg; priv->can.clock.freq =3D clk_get_rate(clk); spin_lock_init(&priv->rmw_lock); priv->tx_head =3D 0; --=20 2.32.0 From nobody Tue Dec 16 12:21:35 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFBDFC77B61 for ; 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Thu, 27 Apr 2023 13:45:54 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-87-5-99-194.retail.telecomitalia.it. [87.5.99.194]) by smtp.gmail.com with ESMTPSA id s12-20020a170906bc4c00b00947ed087a2csm10171360ejv.154.2023.04.27.13.45.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Apr 2023 13:45:53 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, Amarula patchwork , Dario Binacchi , Alexandre Torgue , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v2 5/5] ARM: dts: stm32: add CAN support on stm32f746 Date: Thu, 27 Apr 2023 22:45:40 +0200 Message-Id: <20230427204540.3126234-6-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20230427204540.3126234-1-dario.binacchi@amarulasolutions.com> References: <20230427204540.3126234-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for bxcan (Basic eXtended CAN controller) to STM32F746. The chip contains three CAN peripherals, CAN1 and CAN2 in dual peripheral configuration and CAN3 in single peripheral configuration: - Dual CAN peripheral configuration: * CAN1: Primary bxCAN for managing the communication between a secondary bxCAN and the 512-byte SRAM memory. * CAN2: Secondary bxCAN with no direct access to the SRAM memory. This means that the two bxCAN cells share the 512-byte SRAM memory and CAN2 can't be used without enabling CAN1. - Single CAN peripheral configuration: * CAN3: Primary bxCAN with dedicated Memory Access Controller unit and 512-byte SRAM memory. ------------------------------------------------------------------------- | features | CAN1 | CAN2 | CAN 3 | ------------------------------------------------------------------------- | SRAM | 512-byte shared between CAN1 & CAN2 | 512-byte | ------------------------------------------------------------------------- | Filters | 26 filters shared between CAN1 & CAN2 | 14 filters | ------------------------------------------------------------------------- Signed-off-by: Dario Binacchi --- Changes in v2: - Move after the patch "can: bxcan: add support for single peripheral confi= guration". - Add node gcan3. - Rename gcan as gcan1. - Add property "st,can-secondary" to can2 node. - Drop patch "dt-bindings: mfd: stm32f7: add binding definition for CAN3" because it has been accepted. - Add patch "ARM: dts: stm32f429: put can2 in secondary mode". - Add patch "dt-bindings: net: can: add "st,can-secondary" property". arch/arm/boot/dts/stm32f746.dtsi | 47 ++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746= .dtsi index dc868e6da40e..973698bc9ef4 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -257,6 +257,23 @@ rtc: rtc@40002800 { status =3D "disabled"; }; =20 + can3: can@40003400 { + compatible =3D "st,stm32f4-bxcan"; + reg =3D <0x40003400 0x200>; + interrupts =3D <104>, <105>, <106>, <107>; + interrupt-names =3D "tx", "rx0", "rx1", "sce"; + resets =3D <&rcc STM32F7_APB1_RESET(CAN3)>; + clocks =3D <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>; + st,gcan =3D <&gcan3>; + status =3D "disabled"; + }; + + gcan3: gcan@40003600 { + compatible =3D "st,stm32f4-gcan", "syscon"; + reg =3D <0x40003600 0x200>; + clocks =3D <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>; + }; + usart2: serial@40004400 { compatible =3D "st,stm32f7-uart"; reg =3D <0x40004400 0x400>; @@ -337,6 +354,36 @@ i2c4: i2c@40006000 { status =3D "disabled"; }; =20 + can1: can@40006400 { + compatible =3D "st,stm32f4-bxcan"; + reg =3D <0x40006400 0x200>; + interrupts =3D <19>, <20>, <21>, <22>; + interrupt-names =3D "tx", "rx0", "rx1", "sce"; + resets =3D <&rcc STM32F7_APB1_RESET(CAN1)>; + clocks =3D <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>; + st,can-primary; + st,gcan =3D <&gcan1>; + status =3D "disabled"; + }; + + gcan1: gcan@40006600 { + compatible =3D "st,stm32f4-gcan", "syscon"; + reg =3D <0x40006600 0x200>; + clocks =3D <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>; + }; + + can2: can@40006800 { + compatible =3D "st,stm32f4-bxcan"; + reg =3D <0x40006800 0x200>; + interrupts =3D <63>, <64>, <65>, <66>; + interrupt-names =3D "tx", "rx0", "rx1", "sce"; + resets =3D <&rcc STM32F7_APB1_RESET(CAN2)>; + clocks =3D <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>; + st,can-secondary; + st,gcan =3D <&gcan1>; + status =3D "disabled"; + }; + cec: cec@40006c00 { compatible =3D "st,stm32-cec"; reg =3D <0x40006C00 0x400>; --=20 2.32.0