From nobody Thu Dec 18 19:46:47 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3ED4EC77B61 for ; Thu, 27 Apr 2023 09:17:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243003AbjD0JRs (ORCPT ); Thu, 27 Apr 2023 05:17:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243320AbjD0JRZ (ORCPT ); Thu, 27 Apr 2023 05:17:25 -0400 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::228]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9E334EC1 for ; Thu, 27 Apr 2023 02:17:10 -0700 (PDT) Received: (Authenticated sender: me@crly.cz) by mail.gandi.net (Postfix) with ESMTPSA id CA9521BF20A; Thu, 27 Apr 2023 09:17:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crly.cz; s=gm1; t=1682587029; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RXbaBNxkiTTV4hInjji5NkCrdDSarnLLhwu9cO3OfTc=; b=dQ4NDlSI58cJBb7iv0QJQowSzJODauNypp2m+QipibmpGjXssSEAgumLdAxs/1KE/x+dyW iZQki3PXi9o87QJvuzqpiZr+gCbfZUC7VaVLjLPDf78HsWOwgcIwc3cgr/vBCoyFaYKpC/ a/RxZyyxDw8hNDyTvDrhMbfBWRoPBz4KRklb/EVp7vJBSA/wiyQT9LDhyDctFFLv8Sv4I8 a8xlWsQY8Y691V4qkX9dXYKccZUpOGcdDFM5/DYylarPGuEl/t5Vs4wIM1v8mmXwVrsX1e bAKFe20aDWyhi/eHbtziQRQ1EYAGc/mbPCy6qCEdMD4hBMfM7oK2D77UtOQycw== From: Roman Beranek To: Maxime Ripard , Chen-Yu Tsai , David Airlie , Daniel Vetter , Jernej Skrabec , Samuel Holland Cc: Roman Beranek , Frank Oltmanns , Icenowy Zheng , Ondrej Jirman , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v3 7/7] drm: sun4i: calculate proper DCLK rate for DSI Date: Thu, 27 Apr 2023 11:16:11 +0200 Message-Id: <20230427091611.99044-8-me@crly.cz> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20230427091611.99044-1-me@crly.cz> References: <20230427091611.99044-1-me@crly.cz> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In DSI mode, TCON0's data clock is required to run at 1/4 the per-lane bit rate. Signed-off-by: Roman Beranek --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 36 +++++++++++++++++------------- 1 file changed, 21 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun= 4i_tcon.c index eec26b1faa4b..b263de7a8237 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -291,18 +291,6 @@ static int sun4i_tcon_get_clk_delay(const struct drm_d= isplay_mode *mode, return delay; } =20 -static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon, - const struct drm_display_mode *mode) -{ - /* Configure the dot clock */ - clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); - - /* Set the resolution */ - regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, - SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) | - SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); -} - static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon, const struct drm_connector *connector) { @@ -367,10 +355,18 @@ static void sun4i_tcon0_mode_set_cpu(struct sun4i_tco= n *tcon, u32 block_space, start_delay; u32 tcon_div; =20 + /* + * dclk is required to run at 1/4 the DSI per-lane bit rate. + */ tcon->dclk_min_div =3D SUN6I_DSI_TCON_DIV; tcon->dclk_max_div =3D SUN6I_DSI_TCON_DIV; + clk_set_rate(tcon->dclk, mode->crtc_clock * 1000 * (bpp / lanes) + / SUN6I_DSI_TCON_DIV); =20 - sun4i_tcon0_mode_set_common(tcon, mode); + /* Set the resolution */ + regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, + SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) | + SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); =20 /* Set dithering if needed */ sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); @@ -438,7 +434,12 @@ static void sun4i_tcon0_mode_set_lvds(struct sun4i_tco= n *tcon, =20 tcon->dclk_min_div =3D 7; tcon->dclk_max_div =3D 7; - sun4i_tcon0_mode_set_common(tcon, mode); + clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); + + /* Set the resolution */ + regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, + SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) | + SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); =20 /* Set dithering if needed */ sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); @@ -515,7 +516,12 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon= *tcon, =20 tcon->dclk_min_div =3D tcon->quirks->dclk_min_div; tcon->dclk_max_div =3D 127; - sun4i_tcon0_mode_set_common(tcon, mode); + clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); + + /* Set the resolution */ + regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, + SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) | + SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); =20 /* Set dithering if needed */ sun4i_tcon0_mode_set_dithering(tcon, connector); --=20 2.34.1