From nobody Thu Dec 18 19:46:47 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CDD19C77B61 for ; Thu, 27 Apr 2023 09:17:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242963AbjD0JRP (ORCPT ); Thu, 27 Apr 2023 05:17:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41248 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243117AbjD0JRD (ORCPT ); Thu, 27 Apr 2023 05:17:03 -0400 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B05D4ED0 for ; Thu, 27 Apr 2023 02:17:02 -0700 (PDT) Received: (Authenticated sender: me@crly.cz) by mail.gandi.net (Postfix) with ESMTPSA id A761F1BF20F; Thu, 27 Apr 2023 09:16:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crly.cz; s=gm1; t=1682587021; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=5d+itg7Hh9nGexE8xtDQBtvYxB28npggmEJJymVnOx0=; b=GiRAFr/UTTGAFRwKFq02UQ3SwuendpSDUVIwVn5Lk3RL8sQiji6+GNYB+ncXZGgcINis2i +hEu6FMUYS79zqH8yhix+kKfWPGUBo+rpAHBsdYsk57vUkb3k71Y9YsADICRi1UtCcSPFu SPRGwpbzcb+YwciZdpbeMznGr9bq22Rwd6b41s5jf1IaHaaRuDQd5QCwbly74kn8+BpsLU oAMDEFV2mXmo/l4ceJ9uWfxrqvEzrOHjpBaN2fEydUYrKIFJp5dEDtj1BaLXLnHvkAZdcX IP6yphZGlER3ked+FWv/4ND24J7f3rpMmHmKQ0FWg4ZnoZMg388aa3Osbml03A== From: Roman Beranek To: Maxime Ripard , Chen-Yu Tsai , David Airlie , Daniel Vetter , Jernej Skrabec , Samuel Holland Cc: Roman Beranek , Frank Oltmanns , Icenowy Zheng , Ondrej Jirman , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v3 4/7] arm64: dts: allwinner: a64: reset pll-video0 rate Date: Thu, 27 Apr 2023 11:16:08 +0200 Message-Id: <20230427091611.99044-5-me@crly.cz> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20230427091611.99044-1-me@crly.cz> References: <20230427091611.99044-1-me@crly.cz> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" With pll-mipi as its source clock, the exact rate to which TCON0's data clock can be set to is constrained by the current rate of pll-video0. Unless changed on a request of another consumer, the rate of pll-video0 is left as inherited from the bootloader. The default rate on reset is 297 MHz, a value preferable to what it is later set to in u-boot (294 MHz). This happens unintentionally though, as u-boot, for the sake of simplicity, rounds the rate requested by DE2 driver (297 MHz) to 6 MHz steps. Reset the PLL to its default rate of 297 MHz. Signed-off-by: Roman Beranek --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boo= t/dts/allwinner/sun50i-a64.dtsi index e6a194db420d..cfc60dce80b0 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -667,6 +667,9 @@ ccu: clock@1c20000 { clock-names =3D "hosc", "losc"; #clock-cells =3D <1>; #reset-cells =3D <1>; + + assigned-clocks =3D <&ccu CLK_PLL_VIDEO0>; + assigned-clock-rates =3D <297000000>; }; =20 pio: pinctrl@1c20800 { --=20 2.34.1