From nobody Thu Dec 18 08:53:36 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97605C7EE22 for ; Thu, 27 Apr 2023 08:59:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243205AbjD0I7z (ORCPT ); Thu, 27 Apr 2023 04:59:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58452 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243042AbjD0I7x (ORCPT ); Thu, 27 Apr 2023 04:59:53 -0400 Received: from mail-sh.amlogic.com (mail-sh.amlogic.com [58.32.228.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F9B9422A; Thu, 27 Apr 2023 01:59:05 -0700 (PDT) Received: from droid01-cd.amlogic.com (10.98.11.200) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.13; Thu, 27 Apr 2023 16:58:59 +0800 From: Xianwei Zhao To: , , , CC: Catalin Marinas , Will Deacon , Neil Armstrong , Kevin Hilman , Rob Herring , Krzysztof Kozlowski , Xianwei Zhao Subject: [PATCH V2] arm64: dts: add support for C3 based Amlogic AW409 Date: Thu, 27 Apr 2023 16:58:59 +0800 Message-ID: <20230427085859.793802-1-xianwei.zhao@amlogic.com> X-Mailer: git-send-email 2.37.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.98.11.200] Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Amlogic C3 is an advanced edge AI processor designed for smart IP camera applications. Add basic support for the C3 based Amlogic AW409 board, which describes the following components: CPU, GIC, IRQ, Timer, UART. It's capable of booting up into the serial console. Signed-off-by: Xianwei Zhao --- V1 -> V2: Remove new arch, and use ARCH_MESON; Modify node name, and delete superfluous blank lines. --- arch/arm64/boot/dts/amlogic/Makefile | 1 + .../amlogic/amlogic-c3-c302x-aw409-256m.dts | 29 +++++++ arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi | 86 +++++++++++++++++++ 3 files changed, 116 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409-256m= .dts create mode 100644 arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/aml= ogic/Makefile index cd1c5b04890a..bcec872c2444 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -74,3 +74,4 @@ dtb-$(CONFIG_ARCH_MESON) +=3D meson-sm1-odroid-hc4.dtb dtb-$(CONFIG_ARCH_MESON) +=3D meson-sm1-sei610.dtb dtb-$(CONFIG_ARCH_MESON) +=3D meson-sm1-x96-air-gbit.dtb dtb-$(CONFIG_ARCH_MESON) +=3D meson-sm1-x96-air.dtb +dtb-$(CONFIG_ARCH_MESON) +=3D amlogic-c3-c302x-aw409-256m.dtb diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409-256m.dts b/= arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409-256m.dts new file mode 100644 index 000000000000..edce8850b338 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/amlogic-c3-c302x-aw409-256m.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "amlogic-c3.dtsi" + +/ { + model =3D "Amlogic C302 aw409 Development Board"; + compatible =3D "amlogic,aw409", "amlogic,c3"; + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + aliases { + serial0 =3D &uart_b; + }; + + memory@0 { + device_type =3D "memory"; + reg =3D <0x0 0x0 0x0 0x10000000>; + }; +}; + +&uart_b { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi b/arch/arm64/boot/= dts/amlogic/amlogic-c3.dtsi new file mode 100644 index 000000000000..93b335aef605 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + */ + +#include +#include +#include + +/ { + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a35"; + reg =3D <0x0 0x0>; + enable-method =3D "psci"; + }; + + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a35"; + reg =3D <0x0 0x1>; + enable-method =3D "psci"; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + xtal: xtal-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <24000000>; + clock-output-names =3D "xtal"; + #clock-cells =3D <0>; + }; + + soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + gic: interrupt-controller@fff01000 { + compatible =3D "arm,gic-400"; + #interrupt-cells =3D <3>; + #address-cells =3D <0>; + interrupt-controller; + reg =3D <0x0 0xfff01000 0 0x1000>, + <0x0 0xfff02000 0 0x2000>, + <0x0 0xfff04000 0 0x2000>, + <0x0 0xfff06000 0 0x2000>; + interrupts =3D ; + }; + + apb4: bus@fe000000 { + compatible =3D "simple-bus"; + reg =3D <0x0 0xfe000000 0x0 0x480000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; + + uart_b: serial@7a000 { + compatible =3D "amlogic,meson-g12a-uart"; + reg =3D <0x0 0x7a000 0x0 0x18>; + interrupts =3D ; + status =3D "disabled"; + clocks =3D <&xtal>, <&xtal>, <&xtal>; + clock-names =3D "xtal", "pclk", "baud"; + }; + + }; + }; +}; base-commit: ae68fb187b59bc8645974320808ab2d7c41b1833 --=20 2.37.1