From nobody Thu Feb 12 07:39:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3115C77B78 for ; Wed, 26 Apr 2023 10:33:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240528AbjDZKde (ORCPT ); Wed, 26 Apr 2023 06:33:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240462AbjDZKdK (ORCPT ); Wed, 26 Apr 2023 06:33:10 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AEF6B4EE1; Wed, 26 Apr 2023 03:32:49 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 33QAWf92060020; Wed, 26 Apr 2023 05:32:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1682505161; bh=YLbJp+mrPrbOBSNwMQ/GRPYyLQR+PpHvyhHbKNPpPRk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=RVL4cpmwehleem4PgUZDW8p9xKmlBdF+pPqpDyMDwz/6FEWgWwju3jRfFfcdqkFbK VAv0y0eae2TxBH8iLzfPruOAPBctLXl9u9VK6l/OEdZ5rxWySL8oVo2wwYwwXVqlc+ EnxezLFn5AcPISGKruHQB4U53CkbRiLoXxF1E4TA= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 33QAWfH2112941 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 26 Apr 2023 05:32:41 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 26 Apr 2023 05:32:41 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 26 Apr 2023 05:32:41 -0500 Received: from udit-HP-Z2-Tower-G9-Workstation-Desktop-PC.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 33QAWLRW036567; Wed, 26 Apr 2023 05:32:38 -0500 From: Udit Kumar To: , , , , , , , , , CC: Udit Kumar Subject: [PATCH 4/5] arm64: dts: ti: k3-j7200: Add uart pin mux in wkup_pmx0 Date: Wed, 26 Apr 2023 16:02:18 +0530 Message-ID: <20230426103219.1565266-5-u-kumar1@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230426103219.1565266-1-u-kumar1@ti.com> References: <20230426103219.1565266-1-u-kumar1@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add uart pin mux of wkup domain into common board file. Signed-off-by: Udit Kumar --- .../dts/ti/k3-j7200-common-proc-board.dts | 22 ++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 37eb24d69924..2cdfd957dd12 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -80,6 +80,24 @@ vdd_sd_dv: gpio-regulator-TLV71033 { }; }; =20 +&wkup_pmx0 { + mcu_uart0_pins_default: mcu_uart0_pins_default { + pinctrl-single,pins =3D < + J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ + J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ + J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20) MCU_UART0_CTSn */ + J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */ + >; + }; + + wkup_uart0_pins_default: wkup_uart0_pins_default { + pinctrl-single,pins =3D < + J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ + J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ + >; + }; +}; + &wkup_pmx2 { mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins =3D < @@ -158,7 +176,9 @@ &wkup_uart0 { =20 &mcu_uart0 { status =3D "okay"; - /* Default pinmux */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_uart0_pins_default>; + clock-frequency =3D <96000000>; }; =20 &main_uart0 { --=20 2.34.1