From nobody Thu Dec 18 01:07:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F474C7618E for ; Wed, 26 Apr 2023 07:02:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239705AbjDZHB5 (ORCPT ); Wed, 26 Apr 2023 03:01:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39194 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239701AbjDZHBo (ORCPT ); Wed, 26 Apr 2023 03:01:44 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 96F5C3AA1 for ; Wed, 26 Apr 2023 00:01:16 -0700 (PDT) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-552f2f940edso110715167b3.0 for ; Wed, 26 Apr 2023 00:01:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1682492475; x=1685084475; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=YuydG1qFgo9tyCKpvgTGlzApy9btpH2tAmMEOTJR24Y=; b=cClS+4JmyXFo4D91gaV1IjGXoOh/ZjxLLqUowhiYwSFQxbTq8LG2HjSjQ5k3Y0aPjP xNqfTFHShpcgVb1ykJ8FiLBuLWGAK6GyDKTkrpToV0egqHJcQuS5+WueqXxrXfh7sbuH EDEuSwDyB1ySs33ud2PeVFSSQlZKpSRaq3ZHIZn6VAS24jOk2GGnSHFhHA/WSk8hC/du 8m4XsJtXdElEUBemv98WyoZINRGs58e6YDflVHJl23MNvXSlaEF52ERddFvMOqBVmulF GP+zpD6CapzDm7uYot1XOuZGL/cA8ZgbYsCpY3ErJ9CtU5PdjhH3W5jRwMPch8B+SB2e NwrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682492475; x=1685084475; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=YuydG1qFgo9tyCKpvgTGlzApy9btpH2tAmMEOTJR24Y=; b=ezmQeH9KVHI9tUX9i4SQ54y34S2EvSuskUHrkk5VEE9nqMelk1hLwPr9i78bB/a9vP DiGD+y0SHh0ZDqp1+K+2bXKi5HrmhXC/WFjZwt9+PFMTES9uL/PtwPqZfCp6TEDb0XY0 QuBNRNWitPw2Xysmzy3DDSZyCtv4//P+YyzOtCXxoXBa9z8UpphQTYeZ4txpH8rwir2V E0DoeRlF3U5hstogVoLD31Fudset3VIOOMm/KE7luvEtWl6cXj8NiC3qqZdY5BJWE6o6 TLO/cQjw3DQ2k4Ahl14/0p+DLO2VCzG4sKnXfpjyAzqwppQKCGprAGaMy+/5AxOTtBR5 Hklg== X-Gm-Message-State: AAQBX9cDCGW9JdZSnnvafRGm+ySLfa8Q5oy3V6cpKyxMu67D4kjxta7C sVR4BkcJUkio3U5WbbKxVwU9QXqM11bB X-Google-Smtp-Source: AKy350aFTsWEldPbnTT3nJnOWArVaA3Z7agxrrJZRsvztigre/Iddq2xjG957c+4CLvamBe2lu2sWfcfblgH X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:144f:e890:2b29:48d9]) (user=irogers job=sendgmr) by 2002:a81:451d:0:b0:54e:e490:d190 with SMTP id s29-20020a81451d000000b0054ee490d190mr9601655ywa.4.1682492475668; Wed, 26 Apr 2023 00:01:15 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:11 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-2-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 01/40] perf stat: Introduce skippable evsels From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Perf stat with no arguments will use default events and metrics. These events may fail to open even with kernel and hypervisor disabled. When these fail then the permissions error appears even though they were implicitly selected. This is particularly a problem with the automatic selection of the TopdownL1 metric group on certain architectures like Skylake: ``` $ perf stat true Error: Access to performance monitoring and observability operations is limited. Consider adjusting /proc/sys/kernel/perf_event_paranoid setting to open access to performance monitoring and observability operations for processes without CAP_PERFMON, CAP_SYS_PTRACE or CAP_SYS_ADMIN Linux capability. More information can be found at 'Perf events and tool security' document: https://www.kernel.org/doc/html/latest/admin-guide/perf-security.html perf_event_paranoid setting is 2: -1: Allow use of (almost) all events by all users Ignore mlock limit after perf_event_mlock_kb without CAP_IPC_LOCK >=3D 0: Disallow raw and ftrace function tracepoint access >=3D 1: Disallow CPU event access >=3D 2: Disallow kernel profiling To make the adjusted perf_event_paranoid setting permanent preserve it in /etc/sysctl.conf (e.g. kernel.perf_event_paranoid =3D ) ``` This patch adds skippable evsels that when they fail to open won't fail and won't appear in output. The TopdownL1 events, from the metric group, are marked as skippable. This turns the failure above to: ``` $ perf stat true Performance counter stats for 'true': 1.26 msec task-clock:u # 0.328 CPUs ut= ilized 0 context-switches:u # 0.000 /sec 0 cpu-migrations:u # 0.000 /sec 49 page-faults:u # 38.930 K/sec 176,449 cycles:u # 0.140 GHz = (48.99%) 122,905 instructions:u # 0.70 insn pe= r cycle 28,264 branches:u # 22.456 M/sec 2,405 branch-misses:u # 8.51% of all = branches 0.003834565 seconds time elapsed 0.000000000 seconds user 0.004130000 seconds sys ``` When the events can have kernel/hypervisor disabled, like on Tigerlake, then it continues to succeed as: ``` $ perf stat true Performance counter stats for 'true': 0.57 msec task-clock:u # 0.385 CPUs ut= ilized 0 context-switches:u # 0.000 /sec 0 cpu-migrations:u # 0.000 /sec 47 page-faults:u # 82.329 K/sec 287,017 cycles:u # 0.503 GHz 133,318 instructions:u # 0.46 insn pe= r cycle 31,396 branches:u # 54.996 M/sec 2,442 branch-misses:u # 7.78% of all = branches 998,790 TOPDOWN.SLOTS:u # 14.5 % tma_= retiring # 27.6 % tma_backend= _bound # 40.9 % tma_fronten= d_bound # 17.0 % tma_bad_spe= culation 144,922 topdown-retiring:u 411,266 topdown-fe-bound:u 258,510 topdown-be-bound:u 184,090 topdown-bad-spec:u 2,585 INT_MISC.UOP_DROPPING:u # 4.528 M/sec 3,434 cpu/INT_MISC.RECOVERY_CYCLES,cmask=3D1,edge/u # = 6.015 M/sec 0.001480954 seconds time elapsed 0.000000000 seconds user 0.001686000 seconds sys ``` And this likewise works if paranoia allows or running as root. Signed-off-by: Ian Rogers --- tools/perf/builtin-stat.c | 39 ++++++++++++++++++++++++++-------- tools/perf/util/evsel.c | 15 +++++++++++-- tools/perf/util/evsel.h | 1 + tools/perf/util/stat-display.c | 4 ++++ 4 files changed, 48 insertions(+), 11 deletions(-) diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index efda63f6bf32..eb34f5418ad3 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -667,6 +667,13 @@ static enum counter_recovery stat_handle_error(struct = evsel *counter) evsel_list->core.threads->err_thread =3D -1; return COUNTER_RETRY; } + } else if (counter->skippable) { + if (verbose > 0) + ui__warning("skipping event %s that kernel failed to open .\n", + evsel__name(counter)); + counter->supported =3D false; + counter->errored =3D true; + return COUNTER_SKIP; } =20 evsel__open_strerror(counter, &target, errno, msg, sizeof(msg)); @@ -1885,15 +1892,29 @@ static int add_default_attributes(void) * Add TopdownL1 metrics if they exist. To minimize * multiplexing, don't request threshold computation. */ - if (metricgroup__has_metric("TopdownL1") && - metricgroup__parse_groups(evsel_list, "TopdownL1", - /*metric_no_group=3D*/false, - /*metric_no_merge=3D*/false, - /*metric_no_threshold=3D*/true, - stat_config.user_requested_cpu_list, - stat_config.system_wide, - &stat_config.metric_events) < 0) - return -1; + if (metricgroup__has_metric("TopdownL1")) { + struct evlist *metric_evlist =3D evlist__new(); + struct evsel *metric_evsel; + + if (!metric_evlist) + return -1; + + if (metricgroup__parse_groups(metric_evlist, "TopdownL1", + /*metric_no_group=3D*/false, + /*metric_no_merge=3D*/false, + /*metric_no_threshold=3D*/true, + stat_config.user_requested_cpu_list, + stat_config.system_wide, + &stat_config.metric_events) < 0) + return -1; + + evlist__for_each_entry(metric_evlist, metric_evsel) { + metric_evsel->skippable =3D true; + } + evlist__splice_list_tail(evsel_list, &metric_evlist->core.entries); + evlist__delete(metric_evlist); + } + /* Platform specific attrs */ if (evlist__add_default_attrs(evsel_list, default_null_attrs) < 0) return -1; diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c index 356c07f03be6..1cd04b5998d2 100644 --- a/tools/perf/util/evsel.c +++ b/tools/perf/util/evsel.c @@ -290,6 +290,7 @@ void evsel__init(struct evsel *evsel, evsel->per_pkg_mask =3D NULL; evsel->collect_stat =3D false; evsel->pmu_name =3D NULL; + evsel->skippable =3D false; } =20 struct evsel *evsel__new_idx(struct perf_event_attr *attr, int idx) @@ -1725,9 +1726,13 @@ static int get_group_fd(struct evsel *evsel, int cpu= _map_idx, int thread) return -1; =20 fd =3D FD(leader, cpu_map_idx, thread); - BUG_ON(fd =3D=3D -1); + BUG_ON(fd =3D=3D -1 && !leader->skippable); =20 - return fd; + /* + * When the leader has been skipped, return -2 to distinguish from no + * group leader case. + */ + return fd =3D=3D -1 ? -2 : fd; } =20 static void evsel__remove_fd(struct evsel *pos, int nr_cpus, int nr_thread= s, int thread_idx) @@ -2109,6 +2114,12 @@ static int evsel__open_cpu(struct evsel *evsel, stru= ct perf_cpu_map *cpus, =20 group_fd =3D get_group_fd(evsel, idx, thread); =20 + if (group_fd =3D=3D -2) { + pr_debug("broken group leader for %s\n", evsel->name); + err =3D -EINVAL; + goto out_close; + } + test_attr__ready(); =20 /* Debug message used by test scripts */ diff --git a/tools/perf/util/evsel.h b/tools/perf/util/evsel.h index 35805dcdb1b9..bf8f01af1c0b 100644 --- a/tools/perf/util/evsel.h +++ b/tools/perf/util/evsel.h @@ -95,6 +95,7 @@ struct evsel { bool weak_group; bool bpf_counter; bool use_config_name; + bool skippable; int bpf_fd; struct bpf_object *bpf_obj; struct list_head config_terms; diff --git a/tools/perf/util/stat-display.c b/tools/perf/util/stat-display.c index e6035ecbeee8..6b46bbb3d322 100644 --- a/tools/perf/util/stat-display.c +++ b/tools/perf/util/stat-display.c @@ -810,6 +810,10 @@ static bool should_skip_zero_counter(struct perf_stat_= config *config, struct perf_cpu cpu; int idx; =20 + /* Skip counters that were speculatively/default enabled rather than requ= ested. */ + if (counter->skippable) + return true; + /* * Skip value 0 when enabling --per-thread globally, * otherwise it will have too many 0 output. --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33F96C77B60 for ; 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Wed, 26 Apr 2023 00:01:22 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:12 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-3-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 02/40] perf vendor events intel: Add alderlake metric constraints From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Previously these constraints were disabled as they contained topdown events. Since: https://lore.kernel.org/all/20230312021543.3060328-9-irogers@google.com/ the topdown events are correctly grouped even if no group exists. This change was created by PR: https://github.com/intel/perfmon/pull/71 Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/alderlake/adl-metrics.json | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json b/to= ols/perf/pmu-events/arch/x86/alderlake/adl-metrics.json index 75d80e70e5cd..d09361dacd4f 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json @@ -1057,6 +1057,7 @@ }, { "BriefDescription": "This metric represents overall arithmetic flo= ating-point (FP) operations fraction the CPU has executed (retired)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_gr= oup", "MetricName": "tma_fp_arith", @@ -1181,6 +1182,7 @@ }, { "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_m= ispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_= misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * tma_info_slots / B= R_MISP_RETIRED.ALL_BRANCHES", "MetricGroup": "Bad;BrMispredicts;tma_issueBM", "MetricName": "tma_info_branch_misprediction_cost", @@ -1233,6 +1235,7 @@ }, { "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization = if tma_core_bound < tma_ports_utilization else 1) if tma_info_smt_2t_utiliz= ation > 0.5 else 0)", "MetricGroup": "Cor;SMT", "MetricName": "tma_info_core_bound_likely", @@ -1293,6 +1296,7 @@ }, { "BriefDescription": "Total pipeline cost of DSB (uop cache) misses= - subset of the Instruction_Fetch_BW Bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_= branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + = tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tm= a_lsd + tma_mite))", "MetricGroup": "DSBmiss;Fed;tma_issueFB", "MetricName": "tma_info_dsb_misses", @@ -1386,6 +1390,7 @@ }, { "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma= _mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icach= e_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_big_cod= e", "MetricGroup": "Fed;FetchBW;Frontend", "MetricName": "tma_info_instruction_fetch_bw", @@ -1805,6 +1810,7 @@ }, { "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_me= mory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + t= ma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_dtlb_load + tma_fb= _full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_stor= e_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tm= a_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tm= a_split_stores + tma_store_latency + tma_streaming_stores)))", "MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB", "MetricName": "tma_info_memory_data_tlbs", @@ -1814,6 +1820,7 @@ }, { "BriefDescription": "Total pipeline cost of Memory Latency related= bottlenecks (external memory and off-core caches)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dra= m_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (= tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (= tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bou= nd) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tm= a_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_= bound + tma_l2_bound + tma_l3_bound + tma_store_bound))", "MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat", "MetricName": "tma_info_memory_latency", @@ -1823,6 +1830,7 @@ }, { "BriefDescription": "Total pipeline cost of Branch Misprediction r= elated bottlenecks", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency *= tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_i= cache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", "MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM", "MetricName": "tma_info_mispredictions", @@ -1855,6 +1863,7 @@ }, { "BriefDescription": "Average number of Uops retired in cycles wher= e at least one uop has retired.", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_retiring * tma_info_slots / cpu_core@UOPS_RETIR= ED.SLOTS\\,cmask\\=3D1@", "MetricGroup": "Pipeline;Ret", "MetricName": "tma_info_retire", @@ -2127,6 +2136,7 @@ }, { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring memory operations -- uops for memory load or store a= ccesses.", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_light_operations * MEM_UOP_RETIRED.ANY / (tma_r= etiring * tma_info_slots)", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", "MetricName": "tma_memory_operations", @@ -2206,6 +2216,7 @@ }, { "BriefDescription": "This metric represents the remaining light uo= ps fraction the CPU has executed - remaining means not covered by other sib= ling nodes", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_i= nt_operations + tma_memory_operations + tma_fused_instructions + tma_non_fu= sed_branches + tma_nop_instructions))", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", "MetricName": "tma_other_light_ops", --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0EC2AC7618E for ; Wed, 26 Apr 2023 07:02:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239772AbjDZHCZ (ORCPT ); Wed, 26 Apr 2023 03:02:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40246 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239671AbjDZHBw (ORCPT ); Wed, 26 Apr 2023 03:01:52 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20BB640F4 for ; Wed, 26 Apr 2023 00:01:30 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-b8f6269ad66so13171180276.1 for ; Wed, 26 Apr 2023 00:01:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1682492489; x=1685084489; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:from:to:cc:subject:date :message-id:reply-to; bh=yTP8ziwcI3PQrC0ZdKvpelWcI9SXx5Jbrotyz+g0L28=; b=tOtq/DaYZsmqaY414vOlGrNdQZiP4JdSFAdAq57q81YRGj6RrJlTsMCTLMiCNtWAST AphPv7sboKBJbo8M/35nw3/5E6Ma29BzDvCCi0CqAn4nfImctRVF0kqXh0jO/Wh3P5+6 HCPWS2q7b+5Ui9FkyBLYUKnOq+4qCORtOcqx963sUWqFVImo6JQti5BMaQZhnswnhDFm Y5GuG5IBQmG+57u2jajUaWJbdNUtyYiMsymxLzHMbDXh1/YA3di5e4Kxc+R2p/I/oYji 4/+YX117Vz4LK45AXwPDTS5LFo6GwzR8b0h6xOpOteyG84HjLjZHq8l67DamFZOu0jGl o3tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682492489; x=1685084489; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=yTP8ziwcI3PQrC0ZdKvpelWcI9SXx5Jbrotyz+g0L28=; b=CcyZj+/tXQqYdBAj2MZnnXtD4DvQDkVhwGrbrgD2gPkqNzCbO2+zsVi843NA10cJ+y Kpj46cAodu66NUp/C4MnseU7DezLUpv1xZzuqqHgjlOvqbWO97p0JbiUfs2jP4K4wioU Sgyw5veCB2/gyrwURGIzrnwVAzmlBv78cNpAdNKwYoAgU/tKvomC8CSmx5W/LZ2AcxSw q1O4zEChjv7EvYqM51Per2Vn4sKMx9XxoZtTl1YBgoGo7Rze0u4PQ71xPLqFdaqGwcfl gXsyR2+YcNs9bWGv/MyIzR/NcdGwd0UMRagXe+8WYiWScmfUVZloqQCzyYI/KLHYV+jB 5wlQ== X-Gm-Message-State: AC+VfDygrZSeFeaVnf9U/UDp98Y9qi95Qj1wGWmBd+52j1uTHkYiQOr7 reH474WDA6D03mAqHGb8fJwH3ozb4e7P X-Google-Smtp-Source: ACHHUZ6kYmjsgPrxRp3sPPWo6sdjYV/XCXpxmK5QDJqZo2cFpiAJ8nd6GOvitg9sFBo/M3WTR7ArGoyFJsaB X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:144f:e890:2b29:48d9]) (user=irogers job=sendgmr) by 2002:a25:d745:0:b0:b99:f228:37fe with SMTP id o66-20020a25d745000000b00b99f22837femr3091495ybg.5.1682492489156; Wed, 26 Apr 2023 00:01:29 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:13 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-4-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 03/40] perf vendor events intel: Add icelake metric constraints From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Previously these constraints were disabled as they contained topdown events. Since: https://lore.kernel.org/all/20230312021543.3060328-9-irogers@google.com/ the topdown events are correctly grouped even if no group exists. This change was created by PR: https://github.com/intel/perfmon/pull/71 Signed-off-by: Ian Rogers --- .../perf/pmu-events/arch/x86/icelake/icl-metrics.json | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json b/tool= s/perf/pmu-events/arch/x86/icelake/icl-metrics.json index f45ae3483df4..cb58317860ea 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json @@ -311,6 +311,7 @@ }, { "BriefDescription": "This metric represents overall arithmetic flo= ating-point (FP) operations fraction the CPU has executed (retired)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_gr= oup", "MetricName": "tma_fp_arith", @@ -413,6 +414,7 @@ }, { "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_m= ispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_= misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * tma_info_slots / B= R_MISP_RETIRED.ALL_BRANCHES", "MetricGroup": "Bad;BrMispredicts;tma_issueBM", "MetricName": "tma_info_branch_misprediction_cost", @@ -458,6 +460,7 @@ }, { "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization = if tma_core_bound < tma_ports_utilization else 1) if tma_info_smt_2t_utiliz= ation > 0.5 else 0)", "MetricGroup": "Cor;SMT", "MetricName": "tma_info_core_bound_likely", @@ -510,6 +513,7 @@ }, { "BriefDescription": "Total pipeline cost of DSB (uop cache) misses= - subset of the Instruction_Fetch_BW Bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_= branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + = tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tm= a_lsd + tma_mite))", "MetricGroup": "DSBmiss;Fed;tma_issueFB", "MetricName": "tma_info_dsb_misses", @@ -591,6 +595,7 @@ }, { "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma= _mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icach= e_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_big_cod= e", "MetricGroup": "Fed;FetchBW;Frontend", "MetricName": "tma_info_instruction_fetch_bw", @@ -929,6 +934,7 @@ }, { "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_me= mory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + t= ma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_= dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fw= d_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound += tma_l3_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_= false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores= )))", "MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB", "MetricName": "tma_info_memory_data_tlbs", @@ -937,6 +943,7 @@ }, { "BriefDescription": "Total pipeline cost of Memory Latency related= bottlenecks (external memory and off-core caches)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dra= m_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (= tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (= tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bou= nd) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tm= a_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_= bound + tma_l2_bound + tma_l3_bound + tma_store_bound))", "MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat", "MetricName": "tma_info_memory_latency", @@ -945,6 +952,7 @@ }, { "BriefDescription": "Total pipeline cost of Branch Misprediction r= elated bottlenecks", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency *= tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_i= cache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", "MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM", "MetricName": "tma_info_mispredictions", @@ -996,6 +1004,7 @@ }, { "BriefDescription": "Average number of Uops retired in cycles wher= e at least one uop has retired.", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_retiring * tma_info_slots / cpu@UOPS_RETIRED.SL= OTS\\,cmask\\=3D1@", "MetricGroup": "Pipeline;Ret", "MetricName": "tma_info_retire" @@ -1196,6 +1205,7 @@ }, { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring memory operations -- uops for memory load or store a= ccesses.", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_= RETIRED.ANY", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", "MetricName": "tma_memory_operations", @@ -1266,6 +1276,7 @@ }, { "BriefDescription": "This metric represents the remaining light uo= ps fraction the CPU has executed - remaining means not covered by other sib= ling nodes", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_m= emory_operations + tma_branch_instructions + tma_nop_instructions))", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", "MetricName": "tma_other_light_ops", --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F825C7618E for ; Wed, 26 Apr 2023 07:02:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239776AbjDZHCb (ORCPT ); Wed, 26 Apr 2023 03:02:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39304 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239760AbjDZHCH (ORCPT ); Wed, 26 Apr 2023 03:02:07 -0400 Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0DAA630F0 for ; Wed, 26 Apr 2023 00:01:37 -0700 (PDT) Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-555f6759323so107911527b3.2 for ; Wed, 26 Apr 2023 00:01:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1682492496; x=1685084496; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:from:to:cc:subject:date :message-id:reply-to; bh=mkYR03Kl9hbGU61ZrkXLFlnCaPGBBbrk7RCQFspPZao=; b=bro/pDSMMiKALqlSDAIYEcTzBCNylgFQI2bizmZSxRNvc1xbHXBIc6tjkLFJwsXidm M5o9eIw03pb4PtdcjmuSL27CQjWh36VsuNYNW3t7DFPJpOAQda2Uzl8MClYzKC3WTyV5 5zjVGntRjN/k/o2O5cj7aSkjywV7rsKikgqg+n7D+9aughYwNiX7SdKXuTFoJZIRju4P mGndM+FURGwLOXXY8lZyyYtMm7bcBqdhRdh9irM1FyEHWoq7xiDL6tvlHtdZ2s9P6kcC V++4M3QLu9jG2g9zeW3WlclX9vemywaujgEV6hNDNVHedtg2k8iVPEepdqONP6jch+PD n7uA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682492496; x=1685084496; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=mkYR03Kl9hbGU61ZrkXLFlnCaPGBBbrk7RCQFspPZao=; b=LgKpFJtI/NbgSd8BEidUBHia3x3W/EyxksAZP7fjd8JWUNNog91gm/K/SMYjW79JAc 1knU6l6/SOEj0LdVD2Zf204pVqdJkhzqbr/wRC5VYhwjmThT9ep04Z/JFpbK6zKou/ZX MAD28fbAS7ey9mwPpyuRaFxCVAHv+AaQsHqebwx/cbQ5OxTPHZBKw3KPPwQOXFeKT3fR +PtbM6nITdH7X3mBmND5MPt66HQ4yaHCWv+yhYAAJkZvNn/gtda5KHx/NYl8CG4cXP3E vh3cZVLS/siRGTaATF+f1z/t6TK2wtBidJWvIpWyUh8GVEuUuI6YxR+raXIjkxHUIclf OfKQ== X-Gm-Message-State: AAQBX9eEEGqn5A1xfW/fnU0j6b48uJlZk4LnpvChuuRWl9elOeQ9eHv7 LbpgrEs2iFBQGbhM2qVlLwTkytdYJJJB X-Google-Smtp-Source: AKy350Z1fmzK0t2OO1umIzWGyIIYFW1aiJwUGycfTRFekupLlMMrC1Sq3MEFuedFCxOxcWVydFRLyqR7NIIN X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:144f:e890:2b29:48d9]) (user=irogers job=sendgmr) by 2002:a81:ac02:0:b0:552:e74d:318e with SMTP id k2-20020a81ac02000000b00552e74d318emr9685857ywh.7.1682492496302; Wed, 26 Apr 2023 00:01:36 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:14 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-5-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 04/40] perf vendor events intel: Add icelakex metric constraints From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Previously these constraints were disabled as they contained topdown events. Since: https://lore.kernel.org/all/20230312021543.3060328-9-irogers@google.com/ the topdown events are correctly grouped even if no group exists. This change was created by PR: https://github.com/intel/perfmon/pull/71 Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/icelakex/icx-metrics.json | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json b/too= ls/perf/pmu-events/arch/x86/icelakex/icx-metrics.json index 0f9b174dfc22..76e60e3f9d31 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json @@ -276,6 +276,7 @@ }, { "BriefDescription": "This metric represents overall arithmetic flo= ating-point (FP) operations fraction the CPU has executed (retired)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_gr= oup", "MetricName": "tma_fp_arith", @@ -378,6 +379,7 @@ }, { "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_m= ispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_= misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * tma_info_slots / B= R_MISP_RETIRED.ALL_BRANCHES", "MetricGroup": "Bad;BrMispredicts;tma_issueBM", "MetricName": "tma_info_branch_misprediction_cost", @@ -423,6 +425,7 @@ }, { "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization = if tma_core_bound < tma_ports_utilization else 1) if tma_info_smt_2t_utiliz= ation > 0.5 else 0)", "MetricGroup": "Cor;SMT", "MetricName": "tma_info_core_bound_likely", @@ -475,6 +478,7 @@ }, { "BriefDescription": "Total pipeline cost of DSB (uop cache) misses= - subset of the Instruction_Fetch_BW Bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_= branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + = tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tm= a_mite))", "MetricGroup": "DSBmiss;Fed;tma_issueFB", "MetricName": "tma_info_dsb_misses", @@ -556,6 +560,7 @@ }, { "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma= _mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icach= e_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_big_cod= e", "MetricGroup": "Fed;FetchBW;Frontend", "MetricName": "tma_info_instruction_fetch_bw", @@ -940,6 +945,7 @@ }, { "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_me= mory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + t= ma_pmm_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k= _aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_load= s + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound = + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtl= b_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_stor= e_latency + tma_streaming_stores)))", "MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB", "MetricName": "tma_info_memory_data_tlbs", @@ -948,6 +954,7 @@ }, { "BriefDescription": "Total pipeline cost of Memory Latency related= bottlenecks (external memory and off-core caches)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dra= m_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_= store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + = tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound= + tma_pmm_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_= accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_b= ound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_p= mm_bound + tma_store_bound))", "MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat", "MetricName": "tma_info_memory_latency", @@ -956,6 +963,7 @@ }, { "BriefDescription": "Total pipeline cost of Branch Misprediction r= elated bottlenecks", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency *= tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_i= cache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", "MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM", "MetricName": "tma_info_mispredictions", @@ -1019,6 +1027,7 @@ }, { "BriefDescription": "Average number of Uops retired in cycles wher= e at least one uop has retired.", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_retiring * tma_info_slots / cpu@UOPS_RETIRED.SL= OTS\\,cmask\\=3D1@", "MetricGroup": "Pipeline;Ret", "MetricName": "tma_info_retire" @@ -1219,6 +1228,7 @@ }, { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring memory operations -- uops for memory load or store a= ccesses.", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_= RETIRED.ANY", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", "MetricName": "tma_memory_operations", @@ -1289,6 +1299,7 @@ }, { "BriefDescription": "This metric represents the remaining light uo= ps fraction the CPU has executed - remaining means not covered by other sib= ling nodes", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_m= emory_operations + tma_branch_instructions + tma_nop_instructions))", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", "MetricName": "tma_other_light_ops", --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6561C77B60 for ; Wed, 26 Apr 2023 07:02:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239734AbjDZHCq (ORCPT ); Wed, 26 Apr 2023 03:02:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239593AbjDZHCM (ORCPT ); Wed, 26 Apr 2023 03:02:12 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03ECC30FC for ; Wed, 26 Apr 2023 00:01:45 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-b99f3aee8e0so9366988276.0 for ; Wed, 26 Apr 2023 00:01:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1682492504; x=1685084504; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:from:to:cc:subject:date :message-id:reply-to; bh=3oz1fmpkpm3RUrN17QxJtTgNn0g0BbgzDfSM7rwD4x4=; b=Mqcr4rzTMRWJM6UwmC16qVVHm54K15S4XnXeR385wxZs191JHGeyXqhGnQbEQWE9u5 U0GN/9rdBwnHcyjT+72UGFOfTnOo3smZW5jhINe+7AhGUOTeMr1+nLJTMtIydf3tl3NL Csc62A3qETlRt2dP0ViRJsVK7WJQy2+2ZJMQvpc5wIAZwfeTFysCe5ucYDucFq3HNQBG SL6RWFuBNgC0etVn/iA6K5nKWNSR8JoUXSqqP0nxZCxppidhGufNarwCe0GcmIv4UHL6 a3CMtyiOWUvBqfHNalO03O2bHAYtAQ8/sU8zhIRA56LL1kcG1gErm5gV3yJ3G4JkQxni DOWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682492504; x=1685084504; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=3oz1fmpkpm3RUrN17QxJtTgNn0g0BbgzDfSM7rwD4x4=; b=RXn7Zdh+evIrkgcI6W6ZaDkHf1KY6fke2fdJcXzQ+/HvcTXTPL+ZhtYNzI3mBihxBM r6xLl2mgu8QRtKAWNcgQcd3TeBUQEOF7wyRhJbUGnJNDZ4BlttDi4+r5Oagfbkm5oUC5 hj6eyplfBoq3LChvY69wpn/On06ksbp8BGOGrpbttvgHRHHjkP9Ft1+VDYYisd9gsuFq z2vO5EuCXKz2Zi5Vy0wDuP1w4zOJMono6ZDaw9HEP7bA9Ht3QF9K95XS1knxkkltxA+H U+ioSnOJmrpMLAI/UwHdhFGo5fKpz9qEFU0hn+z3puiA0D1v05sGUa0xRZMWFB7D7JK0 kcfw== X-Gm-Message-State: AC+VfDy2Z7lGgfKObEAXdgoUPRFYHQB+FOVaO6Qh9y1V1nxkjQwnGra6 rfUViNGsZryFym3WuXf9pkaWrI6+B1TT X-Google-Smtp-Source: ACHHUZ78Slf+AOLbwHBKSMORsBnBqBGteKH8pOgfzQqbde7NdiyK9yqHJ8/s9Tavs8eqhVvgEJ69r9V05WDF X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:144f:e890:2b29:48d9]) (user=irogers job=sendgmr) by 2002:a25:b190:0:b0:b8f:5474:2f33 with SMTP id h16-20020a25b190000000b00b8f54742f33mr963068ybj.5.1682492504110; Wed, 26 Apr 2023 00:01:44 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:15 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-6-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 05/40] perf vendor events intel: Add sapphirerapids metric constraints From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Previously these constraints were disabled as they contained topdown events. Since: https://lore.kernel.org/all/20230312021543.3060328-9-irogers@google.com/ the topdown events are correctly grouped even if no group exists. This change was created by PR: https://github.com/intel/perfmon/pull/71 Signed-off-by: Ian Rogers --- .../arch/x86/sapphirerapids/spr-metrics.json | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json= b/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json index 126300b7ae77..527d40dde003 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json @@ -284,6 +284,7 @@ }, { "BriefDescription": "This metric represents overall arithmetic flo= ating-point (FP) operations fraction the CPU has executed (retired)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector + tma_f= p_amx", "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_gr= oup", "MetricName": "tma_fp_arith", @@ -404,6 +405,7 @@ }, { "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_m= ispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_= misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * tma_info_slots / B= R_MISP_RETIRED.ALL_BRANCHES", "MetricGroup": "Bad;BrMispredicts;tma_issueBM", "MetricName": "tma_info_branch_misprediction_cost", @@ -449,6 +451,7 @@ }, { "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization = if tma_core_bound < tma_ports_utilization else 1) if tma_info_smt_2t_utiliz= ation > 0.5 else 0)", "MetricGroup": "Cor;SMT", "MetricName": "tma_info_core_bound_likely", @@ -501,6 +504,7 @@ }, { "BriefDescription": "Total pipeline cost of DSB (uop cache) misses= - subset of the Instruction_Fetch_BW Bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_= branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + = tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tm= a_mite))", "MetricGroup": "DSBmiss;Fed;tma_issueFB", "MetricName": "tma_info_dsb_misses", @@ -582,6 +586,7 @@ }, { "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma= _mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icach= e_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_big_cod= e", "MetricGroup": "Fed;FetchBW;Frontend", "MetricName": "tma_info_instruction_fetch_bw", @@ -990,6 +995,7 @@ }, { "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_me= mory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + t= ma_pmm_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_dt= lb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_= blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + t= ma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtl= b_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_st= reaming_stores)))", "MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB", "MetricName": "tma_info_memory_data_tlbs", @@ -998,6 +1004,7 @@ }, { "BriefDescription": "Total pipeline cost of Memory Latency related= bottlenecks (external memory and off-core caches)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dra= m_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_= store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + = tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound= + tma_pmm_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_= accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_b= ound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_p= mm_bound + tma_store_bound))", "MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat", "MetricName": "tma_info_memory_latency", @@ -1006,6 +1013,7 @@ }, { "BriefDescription": "Total pipeline cost of Branch Misprediction r= elated bottlenecks", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency *= tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_i= cache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", "MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM", "MetricName": "tma_info_mispredictions", @@ -1046,6 +1054,7 @@ }, { "BriefDescription": "Average number of Uops retired in cycles wher= e at least one uop has retired.", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_retiring * tma_info_slots / cpu@UOPS_RETIRED.SL= OTS\\,cmask\\=3D1@", "MetricGroup": "Pipeline;Ret", "MetricName": "tma_info_retire" @@ -1317,6 +1326,7 @@ }, { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring memory operations -- uops for memory load or store a= ccesses.", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_light_operations * MEM_UOP_RETIRED.ANY / (tma_r= etiring * tma_info_slots)", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", "MetricName": "tma_memory_operations", @@ -1388,6 +1398,7 @@ }, { "BriefDescription": "This metric represents the remaining light uo= ps fraction the CPU has executed - remaining means not covered by other sib= ling nodes", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_i= nt_operations + tma_memory_operations + tma_fused_instructions + tma_non_fu= sed_branches + tma_nop_instructions))", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", "MetricName": "tma_other_light_ops", --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 596A8C77B60 for ; Wed, 26 Apr 2023 07:03:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239781AbjDZHDA (ORCPT ); Wed, 26 Apr 2023 03:03:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40236 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239737AbjDZHCV (ORCPT ); Wed, 26 Apr 2023 03:02:21 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AFC6F4214 for ; Wed, 26 Apr 2023 00:01:53 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-b8f4c437ce5so11495546276.3 for ; Wed, 26 Apr 2023 00:01:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1682492513; x=1685084513; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:from:to:cc:subject:date :message-id:reply-to; bh=HKRXjgqbYIqcrQXTW2urd+62tTNfVoWhxwwe/l1W4zU=; b=BQxyfn11M/2bPMIUzaGIhi8OabHP6kgfi3nIu2lrCumQw7DU02534mLLTz2waQlu2J iZ2tYuWfC9Yr93gK5BEuLt42eamkBJKW0o1kGtryRG+RBNjH8hCaot56l9fdjnfANlye R4DzFOypCGsyunoCERfBU/LJHEfl2ftL7BX8QuZxvNvVWMPQxZbqR1GoIM2gOnfIunBI JNWNdvU6ctvY7ijkSpOExGYt66eqm0Znb4xTbXYSGIXG8I7XUGH8kC3lGHzaJ62L9vO7 TCBMF1h7naEv0TmFW9zlMvlM8h0bNBTN2MWJKkmvytSUE6CI9donzJHy6xdqt8EqrkIT Z2xw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682492513; x=1685084513; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=HKRXjgqbYIqcrQXTW2urd+62tTNfVoWhxwwe/l1W4zU=; b=k86Ed6eAKZ1jLsmSq+BF5O1pXkAfIEYsg6sQIyNtXjrV/UntH79hI7373qOxokSdtT XkgUKlAwAE9rL4k5zgjFXNV/Eu9/2IyxfhP3sh8pDgFXV8NeYxOnAbnYkdkoU7bk/r3y FK+cmbu555rJkksg1nQfWCp4edB6EW8sS+ep1MidILI6qUqhZCG9PfB/fqrmstcuGAt6 Ja8CFWG/S68Pc+9TDEoJNYWxhYgA4o2+ih6UEeMw3xwxHCgUoVt82VG4PbWyn4z3IC4L nZEWLLoWmlQwO7y4SgHy6BBtatYL3yxm5hUTNI+d1WmwN3l7R0hr/cL7YcGoIL9i+ci9 w+Kg== X-Gm-Message-State: AAQBX9caDUzh+x84h072riHV43PRRSo3DYxKxpvJl1EaZk+6xU1WQFV8 TA4n2h6NSHsuydunQWF7GJYsKLYTklIm X-Google-Smtp-Source: AKy350b1gDSBoiBY+hL5hlPE9qqc3BUaSRKUwMvmkbqtY0qAPaL/7wGpiu1Ng+xUY/S5kmtYLPf63SQCEnjY X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:144f:e890:2b29:48d9]) (user=irogers job=sendgmr) by 2002:a25:d796:0:b0:b90:3342:9154 with SMTP id o144-20020a25d796000000b00b9033429154mr7314263ybg.3.1682492512836; Wed, 26 Apr 2023 00:01:52 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:16 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-7-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 06/40] perf vendor events intel: Add tigerlake metric constraints From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Previously these constraints were disabled as they contained topdown events. Since: https://lore.kernel.org/all/20230312021543.3060328-9-irogers@google.com/ the topdown events are correctly grouped even if no group exists. This change was created by PR: https://github.com/intel/perfmon/pull/71 Signed-off-by: Ian Rogers --- .../pmu-events/arch/x86/tigerlake/tgl-metrics.json | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json b/to= ols/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json index 4c80d6be6cf1..6ac4a9e5d013 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json @@ -305,6 +305,7 @@ }, { "BriefDescription": "This metric represents overall arithmetic flo= ating-point (FP) operations fraction the CPU has executed (retired)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_gr= oup", "MetricName": "tma_fp_arith", @@ -407,6 +408,7 @@ }, { "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_m= ispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_= misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * tma_info_slots / B= R_MISP_RETIRED.ALL_BRANCHES", "MetricGroup": "Bad;BrMispredicts;tma_issueBM", "MetricName": "tma_info_branch_misprediction_cost", @@ -452,6 +454,7 @@ }, { "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization = if tma_core_bound < tma_ports_utilization else 1) if tma_info_smt_2t_utiliz= ation > 0.5 else 0)", "MetricGroup": "Cor;SMT", "MetricName": "tma_info_core_bound_likely", @@ -504,6 +507,7 @@ }, { "BriefDescription": "Total pipeline cost of DSB (uop cache) misses= - subset of the Instruction_Fetch_BW Bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_= branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + = tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tm= a_lsd + tma_mite))", "MetricGroup": "DSBmiss;Fed;tma_issueFB", "MetricName": "tma_info_dsb_misses", @@ -585,6 +589,7 @@ }, { "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma= _mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icach= e_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_big_cod= e", "MetricGroup": "Fed;FetchBW;Frontend", "MetricName": "tma_info_instruction_fetch_bw", @@ -949,6 +954,7 @@ }, { "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_me= mory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + t= ma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_= dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fw= d_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound += tma_l3_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_= false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores= )))", "MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB", "MetricName": "tma_info_memory_data_tlbs", @@ -957,6 +963,7 @@ }, { "BriefDescription": "Total pipeline cost of Memory Latency related= bottlenecks (external memory and off-core caches)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dra= m_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (= tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (= tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bou= nd) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tm= a_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_= bound + tma_l2_bound + tma_l3_bound + tma_store_bound))", "MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat", "MetricName": "tma_info_memory_latency", @@ -965,6 +972,7 @@ }, { "BriefDescription": "Total pipeline cost of Branch Misprediction r= elated bottlenecks", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency *= tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_i= cache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", "MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM", "MetricName": "tma_info_mispredictions", @@ -1016,6 +1024,7 @@ }, { "BriefDescription": "Average number of Uops retired in cycles wher= e at least one uop has retired.", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_retiring * tma_info_slots / cpu@UOPS_RETIRED.SL= OTS\\,cmask\\=3D1@", "MetricGroup": "Pipeline;Ret", "MetricName": "tma_info_retire" @@ -1210,6 +1219,7 @@ }, { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring memory operations -- uops for memory load or store a= ccesses.", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_= RETIRED.ANY", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", "MetricName": "tma_memory_operations", @@ -1280,6 +1290,7 @@ }, { "BriefDescription": "This metric represents the remaining light uo= ps fraction the CPU has executed - remaining means not covered by other sib= ling nodes", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_m= emory_operations + tma_branch_instructions + tma_nop_instructions))", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", "MetricName": "tma_other_light_ops", --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6657AC77B78 for ; Wed, 26 Apr 2023 07:02:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239753AbjDZHC4 (ORCPT ); Wed, 26 Apr 2023 03:02:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40106 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239751AbjDZHCZ (ORCPT ); Wed, 26 Apr 2023 03:02:25 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE13C4233 for ; Wed, 26 Apr 2023 00:02:00 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-b9229dd8c62so7505395276.0 for ; Wed, 26 Apr 2023 00:02:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1682492520; x=1685084520; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=hiBqu+eAww97O/97VLe65d9bhhVAzSpreWJRIJD1hF8=; b=qCPTKPAkdd6ZDSLxXMEWiEVWcpRIA0sE7KzQdiC4ar3/yxSYEfLe7V8tr7EOFED32y kG/PqUXqo7he3VlQ6BqiG5yZxyjRHGYRAjOK4Ipa5hfQ4djJJy7NlI2D/n3Wrj05b9JY ImcEXQs9e90GKrGkRN5cxuOF/vP42NOre5fwKDTfwWQ1jS37sh7S4tdET/EPXDhKg+b6 pAyCDWvfXJB6X7GrrthEucOOJUgtSJRI53ExcTivYx8gFV1W8W0IuJcJbXFUy4P53kFu mLVFMmeEa+vjK2Ovw/pFufBsKIan4i6Rf9jHbvwGg0ENsovNtjyAcuX2eCEx8Ia9FAhd a2ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682492520; x=1685084520; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=hiBqu+eAww97O/97VLe65d9bhhVAzSpreWJRIJD1hF8=; b=YH2axu7G5YaNGTzii3+nl84EF5+gTkFRTj1SxQcAJ8oqTzTqJu9J4ZncRuNzThlHeF o+wJqthSA/MSUTk3VblwwK9XxVW6f6fogJv8opNlBsHhJiMOW8E2VIqF9XbYGqJvcJUJ tPlks0VVQQlIw70lNRCkMzS5+p5pY5LIp2UJP2jOUIJSyFwL/D6Goqs9tSS60Wdjr0hZ UFnRCsTRdrgFu0CGcrFUPz4LoAiU6eldOHN+4XVKuXC9tHHu4/3KgLhMCvTOpGVtIxhL fVEEOWOTUcZU2xA8Kjfd1sDGkcxcDeyZe9aDmJzSZYN/vaUJCQ87RrKbJNIc9A9rla/J GGLg== X-Gm-Message-State: AC+VfDzHvCbHdWRVpXC6aUlkCMA985KWBFcVjY32pGxf44HN6BLTxIH/ TD9yLf+FTxy/H6FwREGE9SvB0GzLO03O X-Google-Smtp-Source: ACHHUZ7XboWPDRNvVt+K/ZmYBPeDghLrO9PAzCKwPDUwIqHVeFa+nhpDM6XBmwmgStp9qdPYGid/1Slk4xdN X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:144f:e890:2b29:48d9]) (user=irogers job=sendgmr) by 2002:a25:dfd4:0:b0:b99:a54e:a61 with SMTP id w203-20020a25dfd4000000b00b99a54e0a61mr5606896ybg.1.1682492520044; Wed, 26 Apr 2023 00:02:00 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:17 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-8-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 07/40] perf stat: Avoid segv on counter->name From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Switch to use evsel__name that doesn't return NULL for hardware and similar events. Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- tools/perf/util/stat-display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/util/stat-display.c b/tools/perf/util/stat-display.c index 6b46bbb3d322..71dd6cb83918 100644 --- a/tools/perf/util/stat-display.c +++ b/tools/perf/util/stat-display.c @@ -747,7 +747,7 @@ static void uniquify_event_name(struct evsel *counter) int ret =3D 0; =20 if (counter->uniquified_name || counter->use_config_name || - !counter->pmu_name || !strncmp(counter->name, counter->pmu_name, + !counter->pmu_name || !strncmp(evsel__name(counter), counter->pmu_nam= e, strlen(counter->pmu_name))) return; =20 --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8669BC7618E for ; Wed, 26 Apr 2023 07:03:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239775AbjDZHDh (ORCPT ); Wed, 26 Apr 2023 03:03:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40320 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239745AbjDZHCx (ORCPT ); Wed, 26 Apr 2023 03:02:53 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B93BC2 for ; Wed, 26 Apr 2023 00:02:12 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-b9963a72fd9so8135747276.0 for ; Wed, 26 Apr 2023 00:02:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1682492527; x=1685084527; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=Hq0rkxZ+nzigWeul/fQuTIxJ14+0rSKTHQhzwukpkHY=; b=Wz5+bOP4poXGvDFuRQ90lq8R1aluz/0G9u+ErkTJ0ioEr+nlJ9oiliW4mYtD65TY/t FFtpm/W7NfDKodNa84YATE7RvBKry00RZczZK0vScGvW+vJgUBCxPzBM3sql/EN3l16z sW5FeGp0tFflf2OLSmv7noYWqd15zuQeH4aQpGU994RD4idq3f6jWApPMm5F1snGRL4f vVXYRzhXPwnd0D4yW3hOy3y4/pLkmxmDaBtK4LvLx4RpLN0lNXcFBtFRKoeQvNSmtwgq jaJ3tyHymdm2H/zcV3VMqI9igrXxPnkX2m9/MzKJ1DPlacL2KhDS9M4sw3jvSt4aLi5T wTNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682492527; x=1685084527; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Hq0rkxZ+nzigWeul/fQuTIxJ14+0rSKTHQhzwukpkHY=; b=bfnNUFkFg3wSzKiI+iOH/jcQzZ3+71qF+MlByqgtewM+Cs7kfKRyUmsmTNjyidwTgA ee7oMflbgDrTP1p8S4IXJAFFUvt//DB9hXTr0zhTMY7zTJJOamAnsEJ67NHvNAYVQYnu bs5LNbIIODR5oleWqzksUf0MVCem4cmttTZ2GT9Ueqm+ugrNIyGoxnw55lISaUwR6+JI ZcUxbYw0YF059msDYfYHqccWpEM8qdwBIcxhRomSzo8HGoE3CvVhBr4C0VZS0oIeJUHV sbC9AgefpGGr9N0dGUzoNHjjPax3Sva91TjD3eSYS7fCN/qwEa4b6NjUQFscUX52v8a5 UW0w== X-Gm-Message-State: AC+VfDzKpQXqECMCbqbIb1iRv7Vm2dq71CyhiHUe98GpFRRXtitGSZ68 xsFzEnIDowdSf3Ie9JvxgSeClebjsTR6 X-Google-Smtp-Source: ACHHUZ5v2Ejn/Bj7HpudP7hkJxO2DT5BN+Vz8IjHKYpG17aSw7aVvJaQGRzoc10Rx9irrgVmqKdcxB3v9KOM X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:144f:e890:2b29:48d9]) (user=irogers job=sendgmr) by 2002:a25:d091:0:b0:b99:b753:342d with SMTP id h139-20020a25d091000000b00b99b753342dmr5249850ybg.7.1682492526946; Wed, 26 Apr 2023 00:02:06 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:18 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-9-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 08/40] perf test: Test more sysfs events From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Parse events for all PMUs, and not just cpu, in test "Parsing of all PMU events from sysfs". Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/tests/parse-events.c | 103 +++++++++++++++++--------------- 1 file changed, 55 insertions(+), 48 deletions(-) diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index 8068cfd89b84..385bbbc4a409 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -7,6 +7,7 @@ #include "debug.h" #include "pmu.h" #include "pmu-hybrid.h" +#include "pmus.h" #include #include #include "fncache.h" @@ -2225,49 +2226,24 @@ static int test_pmu(void) =20 static int test__pmu_events(struct test_suite *test __maybe_unused, int su= btest __maybe_unused) { - struct stat st; - char path[PATH_MAX]; - struct dirent *ent; - DIR *dir; - int ret; - - if (!test_pmu()) - return TEST_SKIP; - - snprintf(path, PATH_MAX, "%s/bus/event_source/devices/cpu/events/", - sysfs__mountpoint()); - - ret =3D stat(path, &st); - if (ret) { - pr_debug("omitting PMU cpu events tests: %s\n", path); - return TEST_OK; - } + struct perf_pmu *pmu; + int ret =3D TEST_OK; =20 - dir =3D opendir(path); - if (!dir) { - pr_debug("can't open pmu event dir: %s\n", path); - return TEST_FAIL; - } + perf_pmus__for_each_pmu(pmu) { + struct stat st; + char path[PATH_MAX]; + struct dirent *ent; + DIR *dir; + int err; =20 - ret =3D TEST_OK; - while ((ent =3D readdir(dir))) { - struct evlist_test e =3D { .name =3D NULL, }; - char name[2 * NAME_MAX + 1 + 12 + 3]; - int test_ret; + snprintf(path, PATH_MAX, "%s/bus/event_source/devices/%s/events/", + sysfs__mountpoint(), pmu->name); =20 - /* Names containing . are special and cannot be used directly */ - if (strchr(ent->d_name, '.')) + err =3D stat(path, &st); + if (err) { + pr_debug("skipping PMU %s events tests: %s\n", pmu->name, path); + ret =3D combine_test_results(ret, TEST_SKIP); continue; - - snprintf(name, sizeof(name), "cpu/event=3D%s/u", ent->d_name); - - e.name =3D name; - e.check =3D test__checkevent_pmu_events; - - test_ret =3D test_event(&e); - if (test_ret !=3D TEST_OK) { - pr_debug("Test PMU event failed for '%s'", name); - ret =3D combine_test_results(ret, test_ret); } /* * Names containing '-' are recognized as prefixes and suffixes @@ -2282,17 +2258,48 @@ static int test__pmu_events(struct test_suite *test= __maybe_unused, int subtest if (strchr(ent->d_name, '-')) continue; =20 - snprintf(name, sizeof(name), "%s:u,cpu/event=3D%s/u", ent->d_name, ent->= d_name); - e.name =3D name; - e.check =3D test__checkevent_pmu_events_mix; - test_ret =3D test_event(&e); - if (test_ret !=3D TEST_OK) { - pr_debug("Test PMU event failed for '%s'", name); - ret =3D combine_test_results(ret, test_ret); + dir =3D opendir(path); + if (!dir) { + pr_debug("can't open pmu event dir: %s\n", path); + ret =3D combine_test_results(ret, TEST_SKIP); + continue; } - } =20 - closedir(dir); + while ((ent =3D readdir(dir))) { + struct evlist_test e =3D { .name =3D NULL, }; + char name[2 * NAME_MAX + 1 + 12 + 3]; + int test_ret; + + /* Names containing . are special and cannot be used directly */ + if (strchr(ent->d_name, '.')) + continue; + + snprintf(name, sizeof(name), "%s/event=3D%s/u", pmu->name, ent->d_name); + + e.name =3D name; + e.check =3D test__checkevent_pmu_events; + + test_ret =3D test_event(&e); + if (test_ret !=3D TEST_OK) { + pr_debug("Test PMU event failed for '%s'", name); + ret =3D combine_test_results(ret, test_ret); + } + + if (!is_pmu_core(pmu->name)) + continue; + + snprintf(name, sizeof(name), "%s:u,%s/event=3D%s/u", ent->d_name, pmu->= name, ent->d_name); + e.name =3D name; + e.check =3D test__checkevent_pmu_events_mix; + test_ret =3D test_event(&e); + if (test_ret !=3D TEST_OK) { + pr_debug("Test PMU event failed for '%s'", name); + ret =3D combine_test_results(ret, test_ret); + } + } + + closedir(dir); + } return ret; } =20 --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02C91C7618E for ; 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Wed, 26 Apr 2023 00:02:14 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:19 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-10-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 09/40] perf test: Use valid for PMU tests From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rather than skip all tests in test__events_pmu if PMU cpu isn't present, use the per-test valid test. This allows the running of software PMU tests on hybrid and arm systems. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/tests/parse-events.c | 27 +++++++++------------------ 1 file changed, 9 insertions(+), 18 deletions(-) diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index 385bbbc4a409..08d6b8a3015d 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -1430,6 +1430,11 @@ static int test__checkevent_config_cache(struct evli= st *evlist) return TEST_OK; } =20 +static bool test__pmu_cpu_valid(void) +{ + return !!perf_pmu__find("cpu"); +} + static bool test__intel_pt_valid(void) { return !!perf_pmu__find("intel_pt"); @@ -1979,21 +1984,25 @@ static const struct evlist_test test__events[] =3D { static const struct evlist_test test__events_pmu[] =3D { { .name =3D "cpu/config=3D10,config1,config2=3D3,period=3D1000/u", + .valid =3D test__pmu_cpu_valid, .check =3D test__checkevent_pmu, /* 0 */ }, { .name =3D "cpu/config=3D1,name=3Dkrava/u,cpu/config=3D2/u", + .valid =3D test__pmu_cpu_valid, .check =3D test__checkevent_pmu_name, /* 1 */ }, { .name =3D "cpu/config=3D1,call-graph=3Dfp,time,period=3D100000/,cpu/con= fig=3D2,call-graph=3Dno,time=3D0,period=3D2000/", + .valid =3D test__pmu_cpu_valid, .check =3D test__checkevent_pmu_partial_time_callgraph, /* 2 */ }, { .name =3D "cpu/name=3D'COMPLEX_CYCLES_NAME:orig=3Dcycles,desc=3Dchip-cl= ock-ticks',period=3D0x1,event=3D0x2/ukp", + .valid =3D test__pmu_cpu_valid, .check =3D test__checkevent_complex_name, /* 3 */ }, @@ -2209,21 +2218,6 @@ static int test__terms2(struct test_suite *test __ma= ybe_unused, int subtest __ma return test_terms(test__terms, ARRAY_SIZE(test__terms)); } =20 -static int test_pmu(void) -{ - struct stat st; - char path[PATH_MAX]; - int ret; - - snprintf(path, PATH_MAX, "%s/bus/event_source/devices/cpu/format/", - sysfs__mountpoint()); - - ret =3D stat(path, &st); - if (ret) - pr_debug("omitting PMU cpu tests\n"); - return !ret; -} - static int test__pmu_events(struct test_suite *test __maybe_unused, int su= btest __maybe_unused) { struct perf_pmu *pmu; @@ -2305,9 +2299,6 @@ static int test__pmu_events(struct test_suite *test _= _maybe_unused, int subtest =20 static int test__pmu_events2(struct test_suite *test __maybe_unused, int s= ubtest __maybe_unused) { - if (!test_pmu()) - return TEST_SKIP; - return test_events(test__events_pmu, ARRAY_SIZE(test__events_pmu)); } =20 --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2473CC77B78 for ; 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Wed, 26 Apr 2023 00:02:21 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:20 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-11-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 10/40] perf test: Mask config then test From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add helper to test the config of an evsel. Mask the config so that high-bits containing the PMU type, which isn't constant for hybrid, are ignored. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/tests/parse-events.c | 183 +++++++++++++------------------- 1 file changed, 75 insertions(+), 108 deletions(-) diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index 08d6b8a3015d..fa016afbc250 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -21,6 +21,11 @@ #define PERF_TP_SAMPLE_TYPE (PERF_SAMPLE_RAW | PERF_SAMPLE_TIME | \ PERF_SAMPLE_CPU | PERF_SAMPLE_PERIOD) =20 +static bool test_config(const struct evsel *evsel, __u64 expected_config) +{ + return (evsel->core.attr.config & PERF_HW_EVENT_MASK) =3D=3D expected_con= fig; +} + #ifdef HAVE_LIBTRACEEVENT =20 #if defined(__s390x__) @@ -87,7 +92,7 @@ static int test__checkevent_raw(struct evlist *evlist) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 0x1a =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); return TEST_OK; } =20 @@ -97,7 +102,7 @@ static int test__checkevent_numeric(struct evlist *evlis= t) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", 1 =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 1 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 1)); return TEST_OK; } =20 @@ -107,8 +112,7 @@ static int test__checkevent_symbolic_name(struct evlist= *evlist) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_INSTRUCTIONS =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_INSTRUCT= IONS)); return TEST_OK; } =20 @@ -118,8 +122,7 @@ static int test__checkevent_symbolic_name_config(struct= evlist *evlist) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CPU_CYCLES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); /* * The period value gets configured within evlist__config, * while this test executes only parse events method. @@ -139,8 +142,7 @@ static int test__checkevent_symbolic_alias(struct evlis= t *evlist) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_SOFTWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_SW_PAGE_FAULTS =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_SW_PAGE_FAU= LTS)); return TEST_OK; } =20 @@ -150,7 +152,7 @@ static int test__checkevent_genhw(struct evlist *evlist) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HW_CACHE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", (1 << 16) =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 1 << 16)); return TEST_OK; } =20 @@ -160,7 +162,7 @@ static int test__checkevent_breakpoint(struct evlist *e= vlist) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_BREAKPOINT =3D=3D evsel->core.att= r.type); - TEST_ASSERT_VAL("wrong config", 0 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0)); TEST_ASSERT_VAL("wrong bp_type", (HW_BREAKPOINT_R | HW_BREAKPOINT_W) =3D= =3D evsel->core.attr.bp_type); TEST_ASSERT_VAL("wrong bp_len", HW_BREAKPOINT_LEN_4 =3D=3D @@ -174,7 +176,7 @@ static int test__checkevent_breakpoint_x(struct evlist = *evlist) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_BREAKPOINT =3D=3D evsel->core.att= r.type); - TEST_ASSERT_VAL("wrong config", 0 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0)); TEST_ASSERT_VAL("wrong bp_type", HW_BREAKPOINT_X =3D=3D evsel->core.attr.bp_type); TEST_ASSERT_VAL("wrong bp_len", sizeof(long) =3D=3D evsel->core.attr.bp_l= en); @@ -188,7 +190,7 @@ static int test__checkevent_breakpoint_r(struct evlist = *evlist) TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_BREAKPOINT =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 0 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0)); TEST_ASSERT_VAL("wrong bp_type", HW_BREAKPOINT_R =3D=3D evsel->core.attr.bp_type); TEST_ASSERT_VAL("wrong bp_len", @@ -203,7 +205,7 @@ static int test__checkevent_breakpoint_w(struct evlist = *evlist) TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_BREAKPOINT =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 0 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0)); TEST_ASSERT_VAL("wrong bp_type", HW_BREAKPOINT_W =3D=3D evsel->core.attr.bp_type); TEST_ASSERT_VAL("wrong bp_len", @@ -218,7 +220,7 @@ static int test__checkevent_breakpoint_rw(struct evlist= *evlist) TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_BREAKPOINT =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 0 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0)); TEST_ASSERT_VAL("wrong bp_type", (HW_BREAKPOINT_R|HW_BREAKPOINT_W) =3D=3D evsel->core.attr.bp_type); TEST_ASSERT_VAL("wrong bp_len", @@ -447,7 +449,7 @@ static int test__checkevent_pmu(struct evlist *evlist) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 10 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 10)); TEST_ASSERT_VAL("wrong config1", 1 =3D=3D evsel->core.attr.config1); TEST_ASSERT_VAL("wrong config2", 3 =3D=3D evsel->core.attr.config2); TEST_ASSERT_VAL("wrong config3", 0 =3D=3D evsel->core.attr.config3); @@ -469,7 +471,7 @@ static int test__checkevent_list(struct evlist *evlist) =20 /* r1 */ TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 1 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 1)); TEST_ASSERT_VAL("wrong config1", 0 =3D=3D evsel->core.attr.config1); TEST_ASSERT_VAL("wrong config2", 0 =3D=3D evsel->core.attr.config2); TEST_ASSERT_VAL("wrong config3", 0 =3D=3D evsel->core.attr.config3); @@ -492,7 +494,7 @@ static int test__checkevent_list(struct evlist *evlist) /* 1:1:hp */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", 1 =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 1 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 1)); TEST_ASSERT_VAL("wrong exclude_user", evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -509,14 +511,14 @@ static int test__checkevent_pmu_name(struct evlist *e= vlist) /* cpu/config=3D1,name=3Dkrava/u */ TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 1 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 1)); TEST_ASSERT_VAL("wrong name", !strcmp(evsel__name(evsel), "krava")); =20 /* cpu/config=3D2/u" */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 2 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 2)); TEST_ASSERT_VAL("wrong name", !strcmp(evsel__name(evsel), "cpu/config=3D2/u")); =20 @@ -530,7 +532,7 @@ static int test__checkevent_pmu_partial_time_callgraph(= struct evlist *evlist) /* cpu/config=3D1,call-graph=3Dfp,time,period=3D100000/ */ TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 1 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 1)); /* * The period, time and callgraph value gets configured within evlist__co= nfig, * while this test executes only parse events method. @@ -542,7 +544,7 @@ static int test__checkevent_pmu_partial_time_callgraph(= struct evlist *evlist) /* cpu/config=3D2,call-graph=3Dno,time=3D0,period=3D2000/ */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 2 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 2)); /* * The period, time and callgraph value gets configured within evlist__co= nfig, * while this test executes only parse events method. @@ -694,8 +696,7 @@ static int test__group1(struct evlist *evlist) /* instructions:k */ evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_INSTRUCTIONS =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_INSTRUCT= IONS)); TEST_ASSERT_VAL("wrong exclude_user", evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -710,8 +711,7 @@ static int test__group1(struct evlist *evlist) /* cycles:upp */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CPU_CYCLES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -736,8 +736,7 @@ static int test__group2(struct evlist *evlist) /* faults + :ku modifier */ evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong type", PERF_TYPE_SOFTWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_SW_PAGE_FAULTS =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_SW_PAGE_FAU= LTS)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -752,8 +751,7 @@ static int test__group2(struct evlist *evlist) /* cache-references + :u modifier */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CACHE_REFERENCES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CACHE_RE= FERENCES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -767,8 +765,7 @@ static int test__group2(struct evlist *evlist) /* cycles:k */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CPU_CYCLES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong exclude_user", evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -811,8 +808,7 @@ static int test__group3(struct evlist *evlist __maybe_u= nused) /* group1 cycles:kppp */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CPU_CYCLES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong exclude_user", evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -828,8 +824,7 @@ static int test__group3(struct evlist *evlist __maybe_u= nused) /* group2 cycles + G modifier */ evsel =3D leader =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CPU_CYCLES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -846,7 +841,7 @@ static int test__group3(struct evlist *evlist __maybe_u= nused) /* group2 1:3 + G modifier */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", 1 =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 3 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 3)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -860,8 +855,7 @@ static int test__group3(struct evlist *evlist __maybe_u= nused) /* instructions:u */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_INSTRUCTIONS =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_INSTRUCT= IONS)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -885,8 +879,7 @@ static int test__group4(struct evlist *evlist __maybe_u= nused) /* cycles:u + p */ evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CPU_CYCLES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -903,8 +896,7 @@ static int test__group4(struct evlist *evlist __maybe_u= nused) /* instructions:kp + p */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_INSTRUCTIONS =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_INSTRUCT= IONS)); TEST_ASSERT_VAL("wrong exclude_user", evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -929,8 +921,7 @@ static int test__group5(struct evlist *evlist __maybe_u= nused) /* cycles + G */ evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CPU_CYCLES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -946,8 +937,7 @@ static int test__group5(struct evlist *evlist __maybe_u= nused) /* instructions + G */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_INSTRUCTIONS =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_INSTRUCT= IONS)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -961,8 +951,7 @@ static int test__group5(struct evlist *evlist __maybe_u= nused) /* cycles:G */ evsel =3D leader =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CPU_CYCLES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -978,8 +967,7 @@ static int test__group5(struct evlist *evlist __maybe_u= nused) /* instructions:G */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_INSTRUCTIONS =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_INSTRUCT= IONS)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -992,8 +980,7 @@ static int test__group5(struct evlist *evlist __maybe_u= nused) /* cycles */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CPU_CYCLES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -1015,8 +1002,7 @@ static int test__group_gh1(struct evlist *evlist) /* cycles + :H group modifier */ evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CPU_CYCLES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -1031,8 +1017,7 @@ static int test__group_gh1(struct evlist *evlist) /* cache-misses:G + :H group modifier */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CACHE_MISSES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CACHE_MI= SSES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -1055,8 +1040,7 @@ static int test__group_gh2(struct evlist *evlist) /* cycles + :G group modifier */ evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CPU_CYCLES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -1071,8 +1055,7 @@ static int test__group_gh2(struct evlist *evlist) /* cache-misses:H + :G group modifier */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CACHE_MISSES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CACHE_MI= SSES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -1095,8 +1078,7 @@ static int test__group_gh3(struct evlist *evlist) /* cycles:G + :u group modifier */ evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CPU_CYCLES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -1111,8 +1093,7 @@ static int test__group_gh3(struct evlist *evlist) /* cache-misses:H + :u group modifier */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CACHE_MISSES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CACHE_MI= SSES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -1135,8 +1116,7 @@ static int test__group_gh4(struct evlist *evlist) /* cycles:G + :uG group modifier */ evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CPU_CYCLES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -1151,8 +1131,7 @@ static int test__group_gh4(struct evlist *evlist) /* cache-misses:H + :uG group modifier */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CACHE_MISSES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CACHE_MI= SSES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -1174,8 +1153,7 @@ static int test__leader_sample1(struct evlist *evlist) /* cycles - sampling group leader */ evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CPU_CYCLES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -1189,8 +1167,7 @@ static int test__leader_sample1(struct evlist *evlist) /* cache-misses - not sampling */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CACHE_MISSES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CACHE_MI= SSES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -1203,8 +1180,7 @@ static int test__leader_sample1(struct evlist *evlist) /* branch-misses - not sampling */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_BRANCH_MISSES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_BRANCH_M= ISSES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -1227,8 +1203,7 @@ static int test__leader_sample2(struct evlist *evlist= __maybe_unused) /* instructions - sampling group leader */ evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_INSTRUCTIONS =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_INSTRUCT= IONS)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -1242,8 +1217,7 @@ static int test__leader_sample2(struct evlist *evlist= __maybe_unused) /* branch-misses - not sampling */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_BRANCH_MISSES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_BRANCH_M= ISSES)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); @@ -1279,8 +1253,7 @@ static int test__pinned_group(struct evlist *evlist) /* cycles - group leader */ evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CPU_CYCLES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong group name", !evsel->group_name); TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); TEST_ASSERT_VAL("wrong pinned", evsel->core.attr.pinned); @@ -1288,14 +1261,12 @@ static int test__pinned_group(struct evlist *evlist) /* cache-misses - can not be pinned, but will go on with the leader */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CACHE_MISSES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CACHE_MI= SSES)); TEST_ASSERT_VAL("wrong pinned", !evsel->core.attr.pinned); =20 /* branch-misses - ditto */ evsel =3D evsel__next(evsel); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_BRANCH_MISSES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_BRANCH_M= ISSES)); TEST_ASSERT_VAL("wrong pinned", !evsel->core.attr.pinned); =20 return TEST_OK; @@ -1323,8 +1294,7 @@ static int test__exclusive_group(struct evlist *evlis= t) /* cycles - group leader */ evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CPU_CYCLES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong group name", !evsel->group_name); TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); TEST_ASSERT_VAL("wrong exclusive", evsel->core.attr.exclusive); @@ -1332,14 +1302,12 @@ static int test__exclusive_group(struct evlist *evl= ist) /* cache-misses - can not be pinned, but will go on with the leader */ evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_CACHE_MISSES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CACHE_MI= SSES)); TEST_ASSERT_VAL("wrong exclusive", !evsel->core.attr.exclusive); =20 /* branch-misses - ditto */ evsel =3D evsel__next(evsel); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_HW_BRANCH_MISSES =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_BRANCH_M= ISSES)); TEST_ASSERT_VAL("wrong exclusive", !evsel->core.attr.exclusive); =20 return TEST_OK; @@ -1350,7 +1318,7 @@ static int test__checkevent_breakpoint_len(struct evl= ist *evlist) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_BREAKPOINT =3D=3D evsel->core.att= r.type); - TEST_ASSERT_VAL("wrong config", 0 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0)); TEST_ASSERT_VAL("wrong bp_type", (HW_BREAKPOINT_R | HW_BREAKPOINT_W) =3D= =3D evsel->core.attr.bp_type); TEST_ASSERT_VAL("wrong bp_len", HW_BREAKPOINT_LEN_1 =3D=3D @@ -1365,7 +1333,7 @@ static int test__checkevent_breakpoint_len_w(struct e= vlist *evlist) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_BREAKPOINT =3D=3D evsel->core.att= r.type); - TEST_ASSERT_VAL("wrong config", 0 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0)); TEST_ASSERT_VAL("wrong bp_type", HW_BREAKPOINT_W =3D=3D evsel->core.attr.bp_type); TEST_ASSERT_VAL("wrong bp_len", HW_BREAKPOINT_LEN_2 =3D=3D @@ -1393,8 +1361,7 @@ static int test__checkevent_precise_max_modifier(stru= ct evlist *evlist) =20 TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_SOFTWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", - PERF_COUNT_SW_TASK_CLOCK =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_SW_TASK_CLO= CK)); return TEST_OK; } =20 @@ -1462,7 +1429,7 @@ static int test__checkevent_raw_pmu(struct evlist *ev= list) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_SOFTWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", 0x1a =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); return TEST_OK; } =20 @@ -1471,7 +1438,7 @@ static int test__sym_event_slash(struct evlist *evlis= t) struct evsel *evsel =3D evlist__first(evlist); =20 TEST_ASSERT_VAL("wrong type", evsel->core.attr.type =3D=3D PERF_TYPE_HARD= WARE); - TEST_ASSERT_VAL("wrong config", evsel->core.attr.config =3D=3D PERF_COUNT= _HW_CPU_CYCLES); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); return TEST_OK; } @@ -1481,7 +1448,7 @@ static int test__sym_event_dc(struct evlist *evlist) struct evsel *evsel =3D evlist__first(evlist); =20 TEST_ASSERT_VAL("wrong type", evsel->core.attr.type =3D=3D PERF_TYPE_HARD= WARE); - TEST_ASSERT_VAL("wrong config", evsel->core.attr.config =3D=3D PERF_COUNT= _HW_CPU_CYCLES); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); TEST_ASSERT_VAL("wrong exclude_user", evsel->core.attr.exclude_user); return TEST_OK; } @@ -1548,7 +1515,7 @@ static int test__hybrid_hw_event_with_pmu(struct evli= st *evlist) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 0x3c =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); return TEST_OK; } =20 @@ -1559,12 +1526,12 @@ static int test__hybrid_hw_group_event(struct evlis= t *evlist) evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 0x3c =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); =20 evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 0xc0 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0xc0)); TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); return TEST_OK; } @@ -1580,7 +1547,7 @@ static int test__hybrid_sw_hw_group_event(struct evli= st *evlist) =20 evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 0x3c =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); return TEST_OK; } @@ -1592,7 +1559,7 @@ static int test__hybrid_hw_sw_group_event(struct evli= st *evlist) evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 0x3c =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); =20 evsel =3D evsel__next(evsel); @@ -1608,14 +1575,14 @@ static int test__hybrid_group_modifier1(struct evli= st *evlist) evsel =3D leader =3D evlist__first(evlist); TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 0x3c =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); TEST_ASSERT_VAL("wrong exclude_user", evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); =20 evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 0xc0 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0xc0)); TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); @@ -1629,17 +1596,17 @@ static int test__hybrid_raw1(struct evlist *evlist) if (!perf_pmu__hybrid_mounted("cpu_atom")) { TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entr= ies); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type= ); - TEST_ASSERT_VAL("wrong config", 0x1a =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); return TEST_OK; } =20 TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 0x1a =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); =20 /* The type of second event is randome value */ evsel =3D evsel__next(evsel); - TEST_ASSERT_VAL("wrong config", 0x1a =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); return TEST_OK; } =20 @@ -1649,7 +1616,7 @@ static int test__hybrid_raw2(struct evlist *evlist) =20 TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", 0x1a =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); return TEST_OK; } =20 --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60F75C7618E for ; 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Wed, 26 Apr 2023 00:02:29 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:21 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-12-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 11/40] perf test: Test more with config_cache From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" test__checkevent_config_cache checks the parsing of "L1-dcache-misses/name=3Dcachepmu/". Don't just check that the name is set correctly, also validate the rest of the perf_event_attr for L1-dcache-misses. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/tests/parse-events.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index fa016afbc250..177464793aa8 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -1394,7 +1394,7 @@ static int test__checkevent_config_cache(struct evlis= t *evlist) struct evsel *evsel =3D evlist__first(evlist); =20 TEST_ASSERT_VAL("wrong name setting", evsel__name_is(evsel, "cachepmu")); - return TEST_OK; + return test__checkevent_genhw(evlist); } =20 static bool test__pmu_cpu_valid(void) --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C40DC7618E for ; Wed, 26 Apr 2023 07:04:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239815AbjDZHER (ORCPT ); Wed, 26 Apr 2023 03:04:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40118 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239769AbjDZHDe (ORCPT ); Wed, 26 Apr 2023 03:03:34 -0400 Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E23EC3581 for ; Wed, 26 Apr 2023 00:02:44 -0700 (PDT) Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-5529a6f9f28so101470707b3.2 for ; Wed, 26 Apr 2023 00:02:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1682492557; x=1685084557; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=pGMhDh/Xxfc/617r/znj1e9S4uhjiiI/jhf4ibmGn/I=; b=FhKZ0DbW98MwDW0YYRBsJErMz6DD3KZB3q5XqWRRfggSzXjVsDbhf1nBN17cgMT4bj cpMm9pfQsbCSWHdFa+1SzDjDuMaiWZjrYLDHpkDJNeRaTdnF2HB9S956VcP/iEJ8+o3R KA23U2jsY/mZlYdg4AJhxyF/2zOAzV9vUUAVoK2QzhcjPT+qhhofQh0DxcJsePhv5bcx MMtqxDVJIwhctmaofnNPxZMOJOOOl0o0gP7fsKw2nUXXW8jseH05+zKAKWXGeX433JpL 0L3MydqE9IAuyp4Muf6R+jq/OuuTqmNjy3IIjKrC9UCHWfiNTgl8gYbOK4yjB4NMWuX4 FIKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682492557; x=1685084557; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=pGMhDh/Xxfc/617r/znj1e9S4uhjiiI/jhf4ibmGn/I=; b=DuA+3GztQOrscXsTUMrP2Gfxoewv8G3/qvXtQLfi3QrNXTR25oGX4d7NmToLVD8hMb OmvCQwq136DiGhvW0yTjaK0Te0qh7xchObgbYITOl/U9ICwKDnw/SpcRVewp8xTDuHy+ bN+f/EgVKMt1OJh9VOv48G9LUeDQZDa+IMZUHVKeu311fOygjAoQTJL4+s39VMuRl74Q pX2EHqIzirce7WkcPB7QVHJ37CWgp81QlujwMhDfEm92kPaqcUcIpagSApRZXGYAntCt V4uVRt3+60ptwpYN67UfuvsFBxKVtGrNTOr6Fb8lW/mRzmcOx3WUXyJzLOPvot42m0iS 4v3Q== X-Gm-Message-State: AAQBX9dg6wu2aFGfMGnqSSikwsdDW1n2wTimqG1vUtpbsERo4mp3mueJ 74Llqpiu5n2o7dg7Jn0/YZ4WxgYKPuPj X-Google-Smtp-Source: AKy350bakCIOKOTTUH+ySM6QN5fHzmW7rOWqtxS5zVWWvQEvHYfEyG9m9mkU8RLrIUjIpMZbllarcMAar391 X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:144f:e890:2b29:48d9]) (user=irogers job=sendgmr) by 2002:a81:4425:0:b0:552:d924:a304 with SMTP id r37-20020a814425000000b00552d924a304mr9106383ywa.4.1682492557276; Wed, 26 Apr 2023 00:02:37 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:22 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-13-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 12/40] perf test: Roundtrip name, don't assume 1 event per name From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Opening hardware names and a legacy cache event on a hybrid PMU opens it on each PMU. Parsing and checking indexes fails, as the parsed index is double the expected. Avoid checking the index by just comparing the names immediately after the parse. This change removes hard coded hybrid logic and removes assumptions about the expansion of an event. On hybrid the PMUs may or may not support an event and so using a distance isn't a consistent solution. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/tests/evsel-roundtrip-name.c | 119 ++++++++++-------------- 1 file changed, 49 insertions(+), 70 deletions(-) diff --git a/tools/perf/tests/evsel-roundtrip-name.c b/tools/perf/tests/evs= el-roundtrip-name.c index e94fed901992..15ff86f9da0b 100644 --- a/tools/perf/tests/evsel-roundtrip-name.c +++ b/tools/perf/tests/evsel-roundtrip-name.c @@ -4,114 +4,93 @@ #include "parse-events.h" #include "tests.h" #include "debug.h" -#include "pmu.h" -#include "pmu-hybrid.h" -#include #include =20 static int perf_evsel__roundtrip_cache_name_test(void) { - char name[128]; - int type, op, err =3D 0, ret =3D 0, i, idx; - struct evsel *evsel; - struct evlist *evlist =3D evlist__new(); + int ret =3D TEST_OK; =20 - if (evlist =3D=3D NULL) - return -ENOMEM; - - for (type =3D 0; type < PERF_COUNT_HW_CACHE_MAX; type++) { - for (op =3D 0; op < PERF_COUNT_HW_CACHE_OP_MAX; op++) { + for (int type =3D 0; type < PERF_COUNT_HW_CACHE_MAX; type++) { + for (int op =3D 0; op < PERF_COUNT_HW_CACHE_OP_MAX; op++) { /* skip invalid cache type */ if (!evsel__is_cache_op_valid(type, op)) continue; =20 - for (i =3D 0; i < PERF_COUNT_HW_CACHE_RESULT_MAX; i++) { - __evsel__hw_cache_type_op_res_name(type, op, i, name, sizeof(name)); - err =3D parse_event(evlist, name); - if (err) - ret =3D err; - } - } - } - - idx =3D 0; - evsel =3D evlist__first(evlist); + for (int res =3D 0; res < PERF_COUNT_HW_CACHE_RESULT_MAX; res++) { + char name[128]; + struct evlist *evlist =3D evlist__new(); + struct evsel *evsel; + int err; =20 - for (type =3D 0; type < PERF_COUNT_HW_CACHE_MAX; type++) { - for (op =3D 0; op < PERF_COUNT_HW_CACHE_OP_MAX; op++) { - /* skip invalid cache type */ - if (!evsel__is_cache_op_valid(type, op)) - continue; + if (evlist =3D=3D NULL) { + pr_debug("Failed to alloc evlist"); + return TEST_FAIL; + } + __evsel__hw_cache_type_op_res_name(type, op, res, + name, sizeof(name)); =20 - for (i =3D 0; i < PERF_COUNT_HW_CACHE_RESULT_MAX; i++) { - __evsel__hw_cache_type_op_res_name(type, op, i, name, sizeof(name)); - if (evsel->core.idx !=3D idx) + err =3D parse_event(evlist, name); + if (err) { + pr_debug("Failure to parse cache event '%s' possibly as PMUs don't su= pport it", + name); + evlist__delete(evlist); continue; - - ++idx; - - if (strcmp(evsel__name(evsel), name)) { - pr_debug("%s !=3D %s\n", evsel__name(evsel), name); - ret =3D -1; } - - evsel =3D evsel__next(evsel); + evlist__for_each_entry(evlist, evsel) { + if (strcmp(evsel__name(evsel), name)) { + pr_debug("%s !=3D %s\n", evsel__name(evsel), name); + ret =3D TEST_FAIL; + } + } + evlist__delete(evlist); } } } - - evlist__delete(evlist); return ret; } =20 -static int __perf_evsel__name_array_test(const char *const names[], int nr= _names, - int distance) +static int perf_evsel__name_array_test(const char *const names[], int nr_n= ames) { - int i, err; - struct evsel *evsel; - struct evlist *evlist =3D evlist__new(); + int ret =3D TEST_OK; =20 - if (evlist =3D=3D NULL) - return -ENOMEM; + for (int i =3D 0; i < nr_names; ++i) { + struct evlist *evlist =3D evlist__new(); + struct evsel *evsel; + int err; =20 - for (i =3D 0; i < nr_names; ++i) { + if (evlist =3D=3D NULL) { + pr_debug("Failed to alloc evlist"); + return TEST_FAIL; + } err =3D parse_event(evlist, names[i]); if (err) { pr_debug("failed to parse event '%s', err %d\n", names[i], err); - goto out_delete_evlist; + evlist__delete(evlist); + ret =3D TEST_FAIL; + continue; } - } - - err =3D 0; - evlist__for_each_entry(evlist, evsel) { - if (strcmp(evsel__name(evsel), names[evsel->core.idx / distance])) { - --err; - pr_debug("%s !=3D %s\n", evsel__name(evsel), names[evsel->core.idx / di= stance]); + evlist__for_each_entry(evlist, evsel) { + if (strcmp(evsel__name(evsel), names[i])) { + pr_debug("%s !=3D %s\n", evsel__name(evsel), names[i]); + ret =3D TEST_FAIL; + } } + evlist__delete(evlist); } - -out_delete_evlist: - evlist__delete(evlist); - return err; + return ret; } =20 -#define perf_evsel__name_array_test(names, distance) \ - __perf_evsel__name_array_test(names, ARRAY_SIZE(names), distance) - static int test__perf_evsel__roundtrip_name_test(struct test_suite *test _= _maybe_unused, int subtest __maybe_unused) { - int err =3D 0, ret =3D 0; - - if (perf_pmu__has_hybrid() && perf_pmu__hybrid_mounted("cpu_atom")) - return perf_evsel__name_array_test(evsel__hw_names, 2); + int err =3D 0, ret =3D TEST_OK; =20 - err =3D perf_evsel__name_array_test(evsel__hw_names, 1); + err =3D perf_evsel__name_array_test(evsel__hw_names, PERF_COUNT_HW_MAX); if (err) ret =3D err; =20 - err =3D __perf_evsel__name_array_test(evsel__sw_names, PERF_COUNT_SW_DUMM= Y + 1, 1); + err =3D perf_evsel__name_array_test(evsel__sw_names, PERF_COUNT_SW_DUMMY = + 1); if (err) ret =3D err; =20 --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D783DC7618E for ; Wed, 26 Apr 2023 07:04:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239710AbjDZHEV (ORCPT ); Wed, 26 Apr 2023 03:04:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40128 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239808AbjDZHDg (ORCPT ); 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Wed, 26 Apr 2023 00:02:45 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:23 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-14-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 13/40] perf parse-events: Set attr.type to PMU type early From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Set attr.type to PMU type early so that later terms can override the value. Setting the value in perf_pmu__config means that earlier steps, like config_term_pmu, can override the value. Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- tools/perf/util/parse-events.c | 2 +- tools/perf/util/pmu.c | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index d71019dcd614..4ba01577618e 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -1492,9 +1492,9 @@ int parse_events_add_pmu(struct parse_events_state *p= arse_state, } else { memset(&attr, 0, sizeof(attr)); } + attr.type =3D pmu->type; =20 if (!head_config) { - attr.type =3D pmu->type; evsel =3D __add_event(list, &parse_state->idx, &attr, /*init_attr=3D*/true, /*name=3D*/NULL, /*metric_id=3D*/NULL, pmu, diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index ad209c88a124..cb33d869f1ed 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -1398,7 +1398,6 @@ int perf_pmu__config(struct perf_pmu *pmu, struct per= f_event_attr *attr, { bool zero =3D !!pmu->default_config; =20 - attr->type =3D pmu->type; return perf_pmu__config_terms(pmu->name, &pmu->format, attr, head_terms, zero, err); } --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5DAFEC77B60 for ; Wed, 26 Apr 2023 07:04:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239719AbjDZHEZ (ORCPT ); Wed, 26 Apr 2023 03:04:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40168 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239816AbjDZHDu (ORCPT ); Wed, 26 Apr 2023 03:03:50 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9051B2118 for ; Wed, 26 Apr 2023 00:02:54 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-b8f32cc8c31so11548913276.2 for ; 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Wed, 26 Apr 2023 00:02:52 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:24 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-15-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 14/40] perf print-events: Avoid unnecessary strlist From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The strlist in print_hwcache_events holds the event names as they are generated, and then it is iterated and printed. This is unnecessary and each event can just be printed as it is processed. Rename the variable i to res, to be more intention revealing and consistent with other code. Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- tools/perf/util/print-events.c | 60 ++++++++++++++++++---------------- 1 file changed, 31 insertions(+), 29 deletions(-) diff --git a/tools/perf/util/print-events.c b/tools/perf/util/print-events.c index 386b1ab0b60e..93bbb868d400 100644 --- a/tools/perf/util/print-events.c +++ b/tools/perf/util/print-events.c @@ -226,58 +226,60 @@ void print_sdt_events(const struct print_callbacks *p= rint_cb, void *print_state) =20 int print_hwcache_events(const struct print_callbacks *print_cb, void *pri= nt_state) { - struct strlist *evt_name_list =3D strlist__new(NULL, NULL); - struct str_node *nd; + const char *event_type_descriptor =3D event_type_descriptors[PERF_TYPE_HW= _CACHE]; =20 - if (!evt_name_list) { - pr_debug("Failed to allocate new strlist for hwcache events\n"); - return -ENOMEM; - } for (int type =3D 0; type < PERF_COUNT_HW_CACHE_MAX; type++) { for (int op =3D 0; op < PERF_COUNT_HW_CACHE_OP_MAX; op++) { /* skip invalid cache type */ if (!evsel__is_cache_op_valid(type, op)) continue; =20 - for (int i =3D 0; i < PERF_COUNT_HW_CACHE_RESULT_MAX; i++) { + for (int res =3D 0; res < PERF_COUNT_HW_CACHE_RESULT_MAX; res++) { struct perf_pmu *pmu =3D NULL; char name[64]; =20 - __evsel__hw_cache_type_op_res_name(type, op, i, name, sizeof(name)); + __evsel__hw_cache_type_op_res_name(type, op, res, + name, sizeof(name)); if (!perf_pmu__has_hybrid()) { if (is_event_supported(PERF_TYPE_HW_CACHE, - type | (op << 8) | (i << 16))) - strlist__add(evt_name_list, name); + type | (op << 8) | (res << 16))) { + print_cb->print_event(print_state, + "cache", + /*pmu_name=3D*/NULL, + name, + /*event_alias=3D*/NULL, + /*scale_unit=3D*/NULL, + /*deprecated=3D*/false, + event_type_descriptor, + /*desc=3D*/NULL, + /*long_desc=3D*/NULL, + /*encoding_desc=3D*/NULL); + } continue; } perf_pmu__for_each_hybrid_pmu(pmu) { if (is_event_supported(PERF_TYPE_HW_CACHE, - type | (op << 8) | (i << 16) | + type | (op << 8) | (res << 16) | ((__u64)pmu->type << PERF_PMU_TYPE_SHIFT))) { char new_name[128]; - snprintf(new_name, sizeof(new_name), - "%s/%s/", pmu->name, name); - strlist__add(evt_name_list, new_name); + snprintf(new_name, sizeof(new_name), + "%s/%s/", pmu->name, name); + print_cb->print_event(print_state, + "cache", + pmu->name, + name, + new_name, + /*scale_unit=3D*/NULL, + /*deprecated=3D*/false, + event_type_descriptor, + /*desc=3D*/NULL, + /*long_desc=3D*/NULL, + /*encoding_desc=3D*/NULL); } } } } } - - strlist__for_each_entry(nd, evt_name_list) { - print_cb->print_event(print_state, - "cache", - /*pmu_name=3D*/NULL, - nd->s, - /*event_alias=3D*/NULL, - /*scale_unit=3D*/NULL, - /*deprecated=3D*/false, - event_type_descriptors[PERF_TYPE_HW_CACHE], - /*desc=3D*/NULL, - /*long_desc=3D*/NULL, - /*encoding_desc=3D*/NULL); - } - strlist__delete(evt_name_list); return 0; } =20 --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73DFCC77B78 for ; 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Wed, 26 Apr 2023 00:02:59 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:25 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-16-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 15/40] perf parse-events: Avoid scanning PMUs before parsing From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The event parser needs to handle two special cases: 1) legacy events like L1-dcache-load-miss. These event names don't appear in json or sysfs, and lookup tables are used for the config value. 2) raw events where 'r0xead' is the same as 'read' unless the PMU has an event called 'read' in which case the event has priority. The previous parser to handle these cases would scan all PMUs for components of event names. These components would then be used to classify in the lexer whether the token should be part of a legacy event, a raw event or an event. The grammar would handle legacy event tokens or recombining the tokens back into a regular event name. The code wasn't PMU specific and had issues around events like AMD's branch-brs that would fail to parse as it expects brs to be a suffix on a legacy event style name: $ perf stat -e branch-brs true event syntax error: 'branch-brs' \___ parser error This change removes processing all PMUs by using the lexer in the form of a regular expression matcher. The lexer will return the token for the longest matched sequence of characters, and in the event of a tie the first. The legacy events are a fixed number of regular expressions, and by matching these before a name token its possible to generate an accurate legacy event token with everything else matching as a name. Because of the lexer change the handling of hyphens in the grammar can be removed as hyphens just become a part of the name. To handle raw events and terms the parser is changed to defer trying to evaluate whether something is a raw event until the PMU is known in the grammar. Once the PMU is known, the events of the PMU can be scanned for the 'read' style problem. A new term type is added for these raw terms, used to enable deferring the evaluation. While this change is large, it has stats of: 170 insertions(+), 436 deletions(-) the bulk of the change is deleting the old approach. It isn't possible to break apart the code added due to the dependencies on how the parts of the parsing work. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/tests/parse-events.c | 24 +-- tools/perf/tests/pmu-events.c | 9 - tools/perf/util/parse-events.c | 329 ++++++++++---------------------- tools/perf/util/parse-events.h | 16 +- tools/perf/util/parse-events.l | 85 +-------- tools/perf/util/parse-events.y | 143 +++++--------- 6 files changed, 170 insertions(+), 436 deletions(-) diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index 177464793aa8..6eadb8a47dbf 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -664,11 +664,11 @@ static int test__checkterms_simple(struct list_head *= terms) */ term =3D list_entry(term->list.next, struct parse_events_term, list); TEST_ASSERT_VAL("wrong type term", - term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_USER); + term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_RAW); TEST_ASSERT_VAL("wrong type val", - term->type_val =3D=3D PARSE_EVENTS__TERM_TYPE_NUM); - TEST_ASSERT_VAL("wrong val", term->val.num =3D=3D 1); - TEST_ASSERT_VAL("wrong config", !strcmp(term->config, "read")); + term->type_val =3D=3D PARSE_EVENTS__TERM_TYPE_STR); + TEST_ASSERT_VAL("wrong val", !strcmp(term->val.str, "read")); + TEST_ASSERT_VAL("wrong config", !strcmp(term->config, "raw")); =20 /* * r0xead @@ -678,11 +678,11 @@ static int test__checkterms_simple(struct list_head *= terms) */ term =3D list_entry(term->list.next, struct parse_events_term, list); TEST_ASSERT_VAL("wrong type term", - term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_CONFIG); + term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_RAW); TEST_ASSERT_VAL("wrong type val", - term->type_val =3D=3D PARSE_EVENTS__TERM_TYPE_NUM); - TEST_ASSERT_VAL("wrong val", term->val.num =3D=3D 0xead); - TEST_ASSERT_VAL("wrong config", !strcmp(term->config, "config")); + term->type_val =3D=3D PARSE_EVENTS__TERM_TYPE_STR); + TEST_ASSERT_VAL("wrong val", !strcmp(term->val.str, "r0xead")); + TEST_ASSERT_VAL("wrong config", !strcmp(term->config, "raw")); return TEST_OK; } =20 @@ -2090,7 +2090,6 @@ static int test_event_fake_pmu(const char *str) return -ENOMEM; =20 parse_events_error__init(&err); - perf_pmu__test_parse_init(); ret =3D __parse_events(evlist, str, &err, &perf_pmu__fake, /*warn_if_reor= dered=3D*/true); if (ret) { pr_debug("failed to parse event '%s', err %d, str '%s'\n", @@ -2144,13 +2143,6 @@ static int test_term(const struct terms_test *t) =20 INIT_LIST_HEAD(&terms); =20 - /* - * The perf_pmu__test_parse_init prepares perf_pmu_events_list - * which gets freed in parse_events_terms. - */ - if (perf_pmu__test_parse_init()) - return -1; - ret =3D parse_events_terms(&terms, t->str); if (ret) { pr_debug("failed to parse terms '%s', err %d\n", diff --git a/tools/perf/tests/pmu-events.c b/tools/perf/tests/pmu-events.c index 1dff863b9711..a2cde61b1c77 100644 --- a/tools/perf/tests/pmu-events.c +++ b/tools/perf/tests/pmu-events.c @@ -776,15 +776,6 @@ static int check_parse_id(const char *id, struct parse= _events_error *error, for (cur =3D strchr(dup, '@') ; cur; cur =3D strchr(++cur, '@')) *cur =3D '/'; =20 - if (fake_pmu) { - /* - * Every call to __parse_events will try to initialize the PMU - * state from sysfs and then clean it up at the end. Reset the - * PMU events to the test state so that we don't pick up - * erroneous prefixes and suffixes. - */ - perf_pmu__test_parse_init(); - } ret =3D __parse_events(evlist, dup, error, fake_pmu, /*warn_if_reordered= =3D*/true); free(dup); =20 diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index 4ba01577618e..e416e653cf74 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -34,11 +34,6 @@ =20 #define MAX_NAME_LEN 100 =20 -struct perf_pmu_event_symbol { - char *symbol; - enum perf_pmu_event_symbol_type type; -}; - #ifdef PARSER_DEBUG extern int parse_events_debug; #endif @@ -49,15 +44,6 @@ static int parse_events__with_hybrid_pmu(struct parse_ev= ents_state *parse_state, const char *str, char *pmu_name, struct list_head *list); =20 -static struct perf_pmu_event_symbol *perf_pmu_events_list; -/* - * The variable indicates the number of supported pmu event symbols. - * 0 means not initialized and ready to init - * -1 means failed to init, don't try anymore - * >0 is the number of supported pmu event symbols - */ -static int perf_pmu_events_list_num; - struct event_symbol event_symbols_hw[PERF_COUNT_HW_MAX] =3D { [PERF_COUNT_HW_CPU_CYCLES] =3D { .symbol =3D "cpu-cycles", @@ -236,6 +222,57 @@ static char *get_config_name(struct list_head *head_te= rms) return get_config_str(head_terms, PARSE_EVENTS__TERM_TYPE_NAME); } =20 +/** + * fix_raw - For each raw term see if there is an event (aka alias) in pmu= that + * matches the raw's string value. If the string value matches an + * event then change the term to be an event, if not then change= it to + * be a config term. For example, "read" may be an event of the = PMU or + * a raw hex encoding of 0xead. The fix-up is done late so the P= MU of + * the event can be determined and we don't need to scan all PMUs + * ahead-of-time. + * @config_terms: the list of terms that may contain a raw term. + * @pmu: the PMU to scan for events from. + */ +static void fix_raw(struct list_head *config_terms, struct perf_pmu *pmu) +{ + struct parse_events_term *term; + + list_for_each_entry(term, config_terms, list) { + struct perf_pmu_alias *alias; + bool matched =3D false; + + if (term->type_term !=3D PARSE_EVENTS__TERM_TYPE_RAW) + continue; + + list_for_each_entry(alias, &pmu->aliases, list) { + if (!strcmp(alias->name, term->val.str)) { + free(term->config); + term->config =3D term->val.str; + term->type_val =3D PARSE_EVENTS__TERM_TYPE_NUM; + term->type_term =3D PARSE_EVENTS__TERM_TYPE_USER; + term->val.num =3D 1; + term->no_value =3D true; + matched =3D true; + break; + } + } + if (!matched) { + u64 num; + + free(term->config); + term->config=3Dstrdup("config"); + errno =3D 0; + num =3D strtoull(term->val.str + 1, NULL, 16); + assert(errno =3D=3D 0); + free(term->val.str); + term->type_val =3D PARSE_EVENTS__TERM_TYPE_NUM; + term->type_term =3D PARSE_EVENTS__TERM_TYPE_CONFIG; + term->val.num =3D num; + term->no_value =3D false; + } + } +} + static struct evsel * __add_event(struct list_head *list, int *idx, struct perf_event_attr *attr, @@ -328,18 +365,27 @@ static int add_event_tool(struct list_head *list, int= *idx, return 0; } =20 -static int parse_aliases(char *str, const char *const names[][EVSEL__MAX_A= LIASES], int size) +/** + * parse_aliases - search names for entries beginning or equalling str ign= oring + * case. If mutliple entries in names match str then the l= ongest + * is chosen. + * @str: The needle to look for. + * @names: The haystack to search. + * @size: The size of the haystack. + * @longest: Out argument giving the length of the matching entry. + */ +static int parse_aliases(const char *str, const char *const names[][EVSEL_= _MAX_ALIASES], int size, + int *longest) { - int i, j; - int n, longest =3D -1; + *longest =3D -1; + for (int i =3D 0; i < size; i++) { + for (int j =3D 0; j < EVSEL__MAX_ALIASES && names[i][j]; j++) { + int n =3D strlen(names[i][j]); =20 - for (i =3D 0; i < size; i++) { - for (j =3D 0; j < EVSEL__MAX_ALIASES && names[i][j]; j++) { - n =3D strlen(names[i][j]); - if (n > longest && !strncasecmp(str, names[i][j], n)) - longest =3D n; + if (n > *longest && !strncasecmp(str, names[i][j], n)) + *longest =3D n; } - if (longest > 0) + if (*longest > 0) return i; } =20 @@ -357,52 +403,58 @@ static int config_attr(struct perf_event_attr *attr, struct parse_events_error *err, config_term_func_t config_term); =20 -int parse_events_add_cache(struct list_head *list, int *idx, - char *type, char *op_result1, char *op_result2, +int parse_events_add_cache(struct list_head *list, int *idx, const char *n= ame, struct parse_events_error *err, struct list_head *head_config, struct parse_events_state *parse_state) { struct perf_event_attr attr; LIST_HEAD(config_terms); - char name[MAX_NAME_LEN]; const char *config_name, *metric_id; int cache_type =3D -1, cache_op =3D -1, cache_result =3D -1; - char *op_result[2] =3D { op_result1, op_result2 }; - int i, n, ret; + int ret, len; + const char *name_end =3D &name[strlen(name) + 1]; bool hybrid; + const char *str =3D name; =20 /* - * No fallback - if we cannot get a clear cache type - * then bail out: + * Search str for the legacy cache event name composed of 1, 2 or 3 + * hyphen separated sections. The first section is the cache type while + * the others are the optional op and optional result. To make life hard + * the names in the table also contain hyphens and the longest name + * should always be selected. */ - cache_type =3D parse_aliases(type, evsel__hw_cache, PERF_COUNT_HW_CACHE_M= AX); + cache_type =3D parse_aliases(str, evsel__hw_cache, PERF_COUNT_HW_CACHE_MA= X, &len); if (cache_type =3D=3D -1) return -EINVAL; + str +=3D len + 1; =20 config_name =3D get_config_name(head_config); - n =3D snprintf(name, MAX_NAME_LEN, "%s", type); - - for (i =3D 0; (i < 2) && (op_result[i]); i++) { - char *str =3D op_result[i]; - - n +=3D snprintf(name + n, MAX_NAME_LEN - n, "-%s", str); - - if (cache_op =3D=3D -1) { + if (str < name_end) { + cache_op =3D parse_aliases(str, evsel__hw_cache_op, + PERF_COUNT_HW_CACHE_OP_MAX, &len); + if (cache_op >=3D 0) { + if (!evsel__is_cache_op_valid(cache_type, cache_op)) + return -EINVAL; + str +=3D len + 1; + } else { + cache_result =3D parse_aliases(str, evsel__hw_cache_result, + PERF_COUNT_HW_CACHE_RESULT_MAX, &len); + if (cache_result >=3D 0) + str +=3D len + 1; + } + } + if (str < name_end) { + if (cache_op < 0) { cache_op =3D parse_aliases(str, evsel__hw_cache_op, - PERF_COUNT_HW_CACHE_OP_MAX); + PERF_COUNT_HW_CACHE_OP_MAX, &len); if (cache_op >=3D 0) { if (!evsel__is_cache_op_valid(cache_type, cache_op)) return -EINVAL; - continue; } - } - - if (cache_result =3D=3D -1) { + } else if (cache_result < 0) { cache_result =3D parse_aliases(str, evsel__hw_cache_result, - PERF_COUNT_HW_CACHE_RESULT_MAX); - if (cache_result >=3D 0) - continue; + PERF_COUNT_HW_CACHE_RESULT_MAX, &len); } } =20 @@ -968,6 +1020,7 @@ static const char *config_term_names[__PARSE_EVENTS__T= ERM_TYPE_NR] =3D { [PARSE_EVENTS__TERM_TYPE_AUX_OUTPUT] =3D "aux-output", [PARSE_EVENTS__TERM_TYPE_AUX_SAMPLE_SIZE] =3D "aux-sample-size", [PARSE_EVENTS__TERM_TYPE_METRIC_ID] =3D "metric-id", + [PARSE_EVENTS__TERM_TYPE_RAW] =3D "raw", }; =20 static bool config_term_shrinked; @@ -1089,6 +1142,9 @@ do { \ case PARSE_EVENTS__TERM_TYPE_METRIC_ID: CHECK_TYPE_VAL(STR); break; + case PARSE_EVENTS__TERM_TYPE_RAW: + CHECK_TYPE_VAL(STR); + break; case PARSE_EVENTS__TERM_TYPE_MAX_STACK: CHECK_TYPE_VAL(NUM); break; @@ -1485,6 +1541,8 @@ int parse_events_add_pmu(struct parse_events_state *p= arse_state, parse_events_error__handle(err, 0, err_str, NULL); return -EINVAL; } + if (head_config) + fix_raw(head_config, pmu); =20 if (pmu->default_config) { memcpy(&attr, pmu->default_config, @@ -1875,180 +1933,6 @@ int parse_events_name(struct list_head *list, const= char *name) return 0; } =20 -static int -comp_pmu(const void *p1, const void *p2) -{ - struct perf_pmu_event_symbol *pmu1 =3D (struct perf_pmu_event_symbol *) p= 1; - struct perf_pmu_event_symbol *pmu2 =3D (struct perf_pmu_event_symbol *) p= 2; - - return strcasecmp(pmu1->symbol, pmu2->symbol); -} - -static void perf_pmu__parse_cleanup(void) -{ - if (perf_pmu_events_list_num > 0) { - struct perf_pmu_event_symbol *p; - int i; - - for (i =3D 0; i < perf_pmu_events_list_num; i++) { - p =3D perf_pmu_events_list + i; - zfree(&p->symbol); - } - zfree(&perf_pmu_events_list); - perf_pmu_events_list_num =3D 0; - } -} - -#define SET_SYMBOL(str, stype) \ -do { \ - p->symbol =3D str; \ - if (!p->symbol) \ - goto err; \ - p->type =3D stype; \ -} while (0) - -/* - * Read the pmu events list from sysfs - * Save it into perf_pmu_events_list - */ -static void perf_pmu__parse_init(void) -{ - - struct perf_pmu *pmu =3D NULL; - struct perf_pmu_alias *alias; - int len =3D 0; - - pmu =3D NULL; - while ((pmu =3D perf_pmu__scan(pmu)) !=3D NULL) { - list_for_each_entry(alias, &pmu->aliases, list) { - char *tmp =3D strchr(alias->name, '-'); - - if (tmp) { - char *tmp2 =3D NULL; - - tmp2 =3D strchr(tmp + 1, '-'); - len++; - if (tmp2) - len++; - } - - len++; - } - } - - if (len =3D=3D 0) { - perf_pmu_events_list_num =3D -1; - return; - } - perf_pmu_events_list =3D malloc(sizeof(struct perf_pmu_event_symbol) * le= n); - if (!perf_pmu_events_list) - return; - perf_pmu_events_list_num =3D len; - - len =3D 0; - pmu =3D NULL; - while ((pmu =3D perf_pmu__scan(pmu)) !=3D NULL) { - list_for_each_entry(alias, &pmu->aliases, list) { - struct perf_pmu_event_symbol *p =3D perf_pmu_events_list + len; - char *tmp =3D strchr(alias->name, '-'); - char *tmp2 =3D NULL; - - if (tmp) - tmp2 =3D strchr(tmp + 1, '-'); - if (tmp2) { - SET_SYMBOL(strndup(alias->name, tmp - alias->name), - PMU_EVENT_SYMBOL_PREFIX); - p++; - tmp++; - SET_SYMBOL(strndup(tmp, tmp2 - tmp), PMU_EVENT_SYMBOL_SUFFIX); - p++; - SET_SYMBOL(strdup(++tmp2), PMU_EVENT_SYMBOL_SUFFIX2); - len +=3D 3; - } else if (tmp) { - SET_SYMBOL(strndup(alias->name, tmp - alias->name), - PMU_EVENT_SYMBOL_PREFIX); - p++; - SET_SYMBOL(strdup(++tmp), PMU_EVENT_SYMBOL_SUFFIX); - len +=3D 2; - } else { - SET_SYMBOL(strdup(alias->name), PMU_EVENT_SYMBOL); - len++; - } - } - } - qsort(perf_pmu_events_list, len, - sizeof(struct perf_pmu_event_symbol), comp_pmu); - - return; -err: - perf_pmu__parse_cleanup(); -} - -/* - * This function injects special term in - * perf_pmu_events_list so the test code - * can check on this functionality. - */ -int perf_pmu__test_parse_init(void) -{ - struct perf_pmu_event_symbol *list, *tmp, symbols[] =3D { - {(char *)"read", PMU_EVENT_SYMBOL}, - {(char *)"event", PMU_EVENT_SYMBOL_PREFIX}, - {(char *)"two", PMU_EVENT_SYMBOL_SUFFIX}, - {(char *)"hyphen", PMU_EVENT_SYMBOL_SUFFIX}, - {(char *)"hyph", PMU_EVENT_SYMBOL_SUFFIX2}, - }; - unsigned long i, j; - - tmp =3D list =3D malloc(sizeof(*list) * ARRAY_SIZE(symbols)); - if (!list) - return -ENOMEM; - - for (i =3D 0; i < ARRAY_SIZE(symbols); i++, tmp++) { - tmp->type =3D symbols[i].type; - tmp->symbol =3D strdup(symbols[i].symbol); - if (!tmp->symbol) - goto err_free; - } - - perf_pmu_events_list =3D list; - perf_pmu_events_list_num =3D ARRAY_SIZE(symbols); - - qsort(perf_pmu_events_list, ARRAY_SIZE(symbols), - sizeof(struct perf_pmu_event_symbol), comp_pmu); - return 0; - -err_free: - for (j =3D 0, tmp =3D list; j < i; j++, tmp++) - zfree(&tmp->symbol); - free(list); - return -ENOMEM; -} - -enum perf_pmu_event_symbol_type -perf_pmu__parse_check(const char *name) -{ - struct perf_pmu_event_symbol p, *r; - - /* scan kernel pmu events from sysfs if needed */ - if (perf_pmu_events_list_num =3D=3D 0) - perf_pmu__parse_init(); - /* - * name "cpu" could be prefix of cpu-cycles or cpu// events. - * cpu-cycles has been handled by hardcode. - * So it must be cpu// events, not kernel pmu event. - */ - if ((perf_pmu_events_list_num <=3D 0) || !strcmp(name, "cpu")) - return PMU_EVENT_SYMBOL_ERR; - - p.symbol =3D strdup(name); - r =3D bsearch(&p, perf_pmu_events_list, - (size_t) perf_pmu_events_list_num, - sizeof(struct perf_pmu_event_symbol), comp_pmu); - zfree(&p.symbol); - return r ? r->type : PMU_EVENT_SYMBOL_ERR; -} - static int parse_events__scanner(const char *str, struct parse_events_state *parse_state) { @@ -2086,7 +1970,6 @@ int parse_events_terms(struct list_head *terms, const= char *str) int ret; =20 ret =3D parse_events__scanner(str, &parse_state); - perf_pmu__parse_cleanup(); =20 if (!ret) { list_splice(parse_state.terms, terms); @@ -2111,7 +1994,6 @@ static int parse_events__with_hybrid_pmu(struct parse= _events_state *parse_state, int ret; =20 ret =3D parse_events__scanner(str, &ps); - perf_pmu__parse_cleanup(); =20 if (!ret) { if (!list_empty(&ps.list)) { @@ -2267,7 +2149,6 @@ int __parse_events(struct evlist *evlist, const char = *str, int ret; =20 ret =3D parse_events__scanner(str, &parse_state); - perf_pmu__parse_cleanup(); =20 if (!ret && list_empty(&parse_state.list)) { WARN_ONCE(true, "WARNING: event parser found nothing\n"); diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index 86ad4438a2aa..f638542c8638 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -41,14 +41,6 @@ int parse_events_terms(struct list_head *terms, const ch= ar *str); int parse_filter(const struct option *opt, const char *str, int unset); int exclude_perf(const struct option *opt, const char *arg, int unset); =20 -enum perf_pmu_event_symbol_type { - PMU_EVENT_SYMBOL_ERR, /* not a PMU EVENT */ - PMU_EVENT_SYMBOL, /* normal style PMU event */ - PMU_EVENT_SYMBOL_PREFIX, /* prefix of pre-suf style event */ - PMU_EVENT_SYMBOL_SUFFIX, /* suffix of pre-suf style event */ - PMU_EVENT_SYMBOL_SUFFIX2, /* suffix of pre-suf2 style event */ -}; - enum { PARSE_EVENTS__TERM_TYPE_NUM, PARSE_EVENTS__TERM_TYPE_STR, @@ -78,6 +70,7 @@ enum { PARSE_EVENTS__TERM_TYPE_AUX_OUTPUT, PARSE_EVENTS__TERM_TYPE_AUX_SAMPLE_SIZE, PARSE_EVENTS__TERM_TYPE_METRIC_ID, + PARSE_EVENTS__TERM_TYPE_RAW, __PARSE_EVENTS__TERM_TYPE_NR, }; =20 @@ -174,8 +167,7 @@ int parse_events_add_numeric(struct parse_events_state = *parse_state, int parse_events_add_tool(struct parse_events_state *parse_state, struct list_head *list, int tool_event); -int parse_events_add_cache(struct list_head *list, int *idx, - char *type, char *op_result1, char *op_result2, +int parse_events_add_cache(struct list_head *list, int *idx, const char *n= ame, struct parse_events_error *error, struct list_head *head_config, struct parse_events_state *parse_state); @@ -198,8 +190,6 @@ int parse_events_multi_pmu_add(struct parse_events_stat= e *parse_state, int parse_events_copy_term_list(struct list_head *old, struct list_head **new); =20 -enum perf_pmu_event_symbol_type -perf_pmu__parse_check(const char *name); void parse_events__set_leader(char *name, struct list_head *list); void parse_events_update_lists(struct list_head *list_event, struct list_head *list_all); @@ -241,8 +231,6 @@ static inline bool is_sdt_event(char *str __maybe_unuse= d) } #endif /* HAVE_LIBELF_SUPPORT */ =20 -int perf_pmu__test_parse_init(void); - struct evsel *parse_events__add_event_hybrid(struct list_head *list, int *= idx, struct perf_event_attr *attr, const char *name, diff --git a/tools/perf/util/parse-events.l b/tools/perf/util/parse-events.l index 51fe0a9fb3de..4b35c099189a 100644 --- a/tools/perf/util/parse-events.l +++ b/tools/perf/util/parse-events.l @@ -63,17 +63,6 @@ static int str(yyscan_t scanner, int token) return token; } =20 -static int raw(yyscan_t scanner) -{ - YYSTYPE *yylval =3D parse_events_get_lval(scanner); - char *text =3D parse_events_get_text(scanner); - - if (perf_pmu__parse_check(text) =3D=3D PMU_EVENT_SYMBOL) - return str(scanner, PE_NAME); - - return __value(yylval, text + 1, 16, PE_RAW); -} - static bool isbpf_suffix(char *text) { int len =3D strlen(text); @@ -131,35 +120,6 @@ do { \ yyless(0); \ } while (0) =20 -static int pmu_str_check(yyscan_t scanner, struct parse_events_state *pars= e_state) -{ - YYSTYPE *yylval =3D parse_events_get_lval(scanner); - char *text =3D parse_events_get_text(scanner); - - yylval->str =3D strdup(text); - - /* - * If we're not testing then parse check determines the PMU event type - * which if it isn't a PMU returns PE_NAME. When testing the result of - * parse check can't be trusted so we return PE_PMU_EVENT_FAKE unless - * an '!' is present in which case the text can't be a PMU name. - */ - switch (perf_pmu__parse_check(text)) { - case PMU_EVENT_SYMBOL_PREFIX: - return PE_PMU_EVENT_PRE; - case PMU_EVENT_SYMBOL_SUFFIX: - return PE_PMU_EVENT_SUF; - case PMU_EVENT_SYMBOL_SUFFIX2: - return PE_PMU_EVENT_SUF2; - case PMU_EVENT_SYMBOL: - return parse_state->fake_pmu - ? PE_PMU_EVENT_FAKE : PE_KERNEL_PMU_EVENT; - default: - return parse_state->fake_pmu && !strchr(text,'!') - ? PE_PMU_EVENT_FAKE : PE_NAME; - } -} - static int sym(yyscan_t scanner, int type, int config) { YYSTYPE *yylval =3D parse_events_get_lval(scanner); @@ -211,13 +171,15 @@ bpf_source [^,{}]+\.c[a-zA-Z0-9._]* num_dec [0-9]+ num_hex 0x[a-fA-F0-9]+ num_raw_hex [a-fA-F0-9]+ -name [a-zA-Z_*?\[\]][a-zA-Z0-9_*?.\[\]!]* +name [a-zA-Z_*?\[\]][a-zA-Z0-9_*?.\[\]!\-]* name_tag [\'][a-zA-Z_*?\[\]][a-zA-Z0-9_*?\-,\.\[\]:=3D]*[\'] name_minus [a-zA-Z_*?][a-zA-Z0-9\-_*?.:]* drv_cfg_term [a-zA-Z0-9_\.]+(=3D[a-zA-Z0-9_*?\.:]+)? /* If you add a modifier you need to update check_modifier() */ modifier_event [ukhpPGHSDIWeb]+ modifier_bp [rwx]{1,3} +lc_type (L1-dcache|l1-d|l1d|L1-data|L1-icache|l1-i|l1i|L1-instruction|LLC= |L2|dTLB|d-tlb|Data-TLB|iTLB|i-tlb|Instruction-TLB|branch|branches|bpu|btb|= bpc|node) +lc_op_result (load|loads|read|store|stores|write|prefetch|prefetches|specu= lative-read|speculative-load|refs|Reference|ops|access|misses|miss) =20 %% =20 @@ -303,8 +265,8 @@ percore { return term(yyscanner, PARSE_EVENTS__TERM_T= YPE_PERCORE); } aux-output { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_AUX_OUTPUT); } aux-sample-size { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_AUX_SAMP= LE_SIZE); } metric-id { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_METRIC_ID); } -r{num_raw_hex} { return raw(yyscanner); } -r0x{num_raw_hex} { return raw(yyscanner); } +r{num_raw_hex} { return str(yyscanner, PE_RAW); } +r0x{num_raw_hex} { return str(yyscanner, PE_RAW); } , { return ','; } "/" { BEGIN(INITIAL); return '/'; } {name_minus} { return str(yyscanner, PE_NAME); } @@ -359,47 +321,20 @@ system_time { return tool(yyscanner, PERF_TOOL_S= YSTEM_TIME); } bpf-output { return sym(yyscanner, PERF_TYPE_SOFTWARE, PERF_COUNT_SW_B= PF_OUTPUT); } cgroup-switches { return sym(yyscanner, PERF_TYPE_SOFTWARE, PERF_COUNT= _SW_CGROUP_SWITCHES); } =20 - /* - * We have to handle the kernel PMU event cycles-ct/cycles-t/mem-loads/me= m-stores separately. - * Because the prefix cycles is mixed up with cpu-cycles. - * loads and stores are mixed up with cache event - */ -cycles-ct | -cycles-t | -mem-loads | -mem-loads-aux | -mem-stores | -topdown-[a-z-]+ | -tx-capacity-[a-z-]+ | -el-capacity-[a-z-]+ { return str(yyscanner, PE_KERNEL_PMU_EVENT); } - -L1-dcache|l1-d|l1d|L1-data | -L1-icache|l1-i|l1i|L1-instruction | -LLC|L2 | -dTLB|d-tlb|Data-TLB | -iTLB|i-tlb|Instruction-TLB | -branch|branches|bpu|btb|bpc | -node { return str(yyscanner, PE_NAME_CACHE_TYPE); } - -load|loads|read | -store|stores|write | -prefetch|prefetches | -speculative-read|speculative-load | -refs|Reference|ops|access | -misses|miss { return str(yyscanner, PE_NAME_CACHE_OP_RESULT); } - +{lc_type} { return str(yyscanner, PE_LEGACY_CACHE); } +{lc_type}-{lc_op_result} { return str(yyscanner, PE_LEGACY_CACHE); } +{lc_type}-{lc_op_result}-{lc_op_result} { return str(yyscanner, PE_LEGACY_= CACHE); } mem: { BEGIN(mem); return PE_PREFIX_MEM; } -r{num_raw_hex} { return raw(yyscanner); } +r{num_raw_hex} { return str(yyscanner, PE_RAW); } {num_dec} { return value(yyscanner, 10); } {num_hex} { return value(yyscanner, 16); } =20 {modifier_event} { return str(yyscanner, PE_MODIFIER_EVENT); } {bpf_object} { if (!isbpf(yyscanner)) { USER_REJECT }; return str(yyscann= er, PE_BPF_OBJECT); } {bpf_source} { if (!isbpf(yyscanner)) { USER_REJECT }; return str(yyscann= er, PE_BPF_SOURCE); } -{name} { return pmu_str_check(yyscanner, _parse_state); } +{name} { return str(yyscanner, PE_NAME); } {name_tag} { return str(yyscanner, PE_NAME); } "/" { BEGIN(config); return '/'; } -- { return '-'; } , { BEGIN(event); return ','; } : { return ':'; } "{" { BEGIN(event); return '{'; } diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y index 4488443e506e..e7072b5601c5 100644 --- a/tools/perf/util/parse-events.y +++ b/tools/perf/util/parse-events.y @@ -8,6 +8,7 @@ =20 #define YYDEBUG 1 =20 +#include #include #include #include @@ -52,36 +53,35 @@ static void free_list_evsel(struct list_head* list_evse= l) %} =20 %token PE_START_EVENTS PE_START_TERMS -%token PE_VALUE PE_VALUE_SYM_HW PE_VALUE_SYM_SW PE_RAW PE_TERM +%token PE_VALUE PE_VALUE_SYM_HW PE_VALUE_SYM_SW PE_TERM %token PE_VALUE_SYM_TOOL %token PE_EVENT_NAME -%token PE_NAME +%token PE_RAW PE_NAME %token PE_BPF_OBJECT PE_BPF_SOURCE %token PE_MODIFIER_EVENT PE_MODIFIER_BP -%token PE_NAME_CACHE_TYPE PE_NAME_CACHE_OP_RESULT +%token PE_LEGACY_CACHE %token PE_PREFIX_MEM PE_PREFIX_RAW PE_PREFIX_GROUP %token PE_ERROR -%token PE_PMU_EVENT_PRE PE_PMU_EVENT_SUF PE_PMU_EVENT_SUF2 PE_KERNEL_PMU_E= VENT PE_PMU_EVENT_FAKE +%token PE_KERNEL_PMU_EVENT PE_PMU_EVENT_FAKE %token PE_ARRAY_ALL PE_ARRAY_RANGE %token PE_DRV_CFG_TERM %type PE_VALUE %type PE_VALUE_SYM_HW %type PE_VALUE_SYM_SW %type PE_VALUE_SYM_TOOL -%type PE_RAW %type PE_TERM %type value_sym +%type PE_RAW %type PE_NAME %type PE_BPF_OBJECT %type PE_BPF_SOURCE -%type PE_NAME_CACHE_TYPE -%type PE_NAME_CACHE_OP_RESULT +%type PE_LEGACY_CACHE %type PE_MODIFIER_EVENT %type PE_MODIFIER_BP %type PE_EVENT_NAME -%type PE_PMU_EVENT_PRE PE_PMU_EVENT_SUF PE_PMU_EVENT_SUF2 PE_KERNEL_= PMU_EVENT PE_PMU_EVENT_FAKE +%type PE_KERNEL_PMU_EVENT PE_PMU_EVENT_FAKE %type PE_DRV_CFG_TERM -%type event_pmu_name +%type name_or_raw %destructor { free ($$); } %type event_term %destructor { parse_events_term__delete ($$); } @@ -273,11 +273,8 @@ event_def: event_pmu | event_legacy_raw sep_dc | event_bpf_file =20 -event_pmu_name: -PE_NAME | PE_PMU_EVENT_PRE - event_pmu: -event_pmu_name opt_pmu_config +PE_NAME opt_pmu_config { struct parse_events_state *parse_state =3D _parse_state; struct parse_events_error *error =3D parse_state->error; @@ -303,10 +300,12 @@ event_pmu_name opt_pmu_config list =3D alloc_list(); if (!list) CLEANUP_YYABORT; + /* Attempt to add to list assuming $1 is a PMU name. */ if (parse_events_add_pmu(_parse_state, list, $1, $2, /*auto_merge_stats= =3D*/false)) { struct perf_pmu *pmu =3D NULL; int ok =3D 0; =20 + /* Failure to add, try wildcard expansion of $1 as a PMU name. */ if (asprintf(&pattern, "%s*", $1) < 0) CLEANUP_YYABORT; =20 @@ -329,6 +328,12 @@ event_pmu_name opt_pmu_config } } =20 + if (!ok) { + /* Failure to add, assume $1 is an event name. */ + zfree(&list); + ok =3D !parse_events_multi_pmu_add(_parse_state, $1, $2, &list); + $2 =3D NULL; + } if (!ok) CLEANUP_YYABORT; } @@ -352,41 +357,27 @@ PE_KERNEL_PMU_EVENT sep_dc $$ =3D list; } | -PE_KERNEL_PMU_EVENT opt_pmu_config +PE_NAME sep_dc { struct list_head *list; int err; =20 - /* frees $2 */ - err =3D parse_events_multi_pmu_add(_parse_state, $1, $2, &list); + err =3D parse_events_multi_pmu_add(_parse_state, $1, NULL, &list); free($1); if (err < 0) YYABORT; $$ =3D list; } | -PE_PMU_EVENT_PRE '-' PE_PMU_EVENT_SUF '-' PE_PMU_EVENT_SUF2 sep_dc -{ - struct list_head *list; - char pmu_name[128]; - snprintf(pmu_name, sizeof(pmu_name), "%s-%s-%s", $1, $3, $5); - free($1); - free($3); - free($5); - if (parse_events_multi_pmu_add(_parse_state, pmu_name, NULL, &list) < 0) - YYABORT; - $$ =3D list; -} -| -PE_PMU_EVENT_PRE '-' PE_PMU_EVENT_SUF sep_dc +PE_KERNEL_PMU_EVENT opt_pmu_config { struct list_head *list; - char pmu_name[128]; + int err; =20 - snprintf(pmu_name, sizeof(pmu_name), "%s-%s", $1, $3); + /* frees $2 */ + err =3D parse_events_multi_pmu_add(_parse_state, $1, $2, &list); free($1); - free($3); - if (parse_events_multi_pmu_add(_parse_state, pmu_name, NULL, &list) < 0) + if (err < 0) YYABORT; $$ =3D list; } @@ -476,7 +467,7 @@ PE_VALUE_SYM_TOOL sep_slash_slash_dc } =20 event_legacy_cache: -PE_NAME_CACHE_TYPE '-' PE_NAME_CACHE_OP_RESULT '-' PE_NAME_CACHE_OP_RESULT= opt_event_config +PE_LEGACY_CACHE opt_event_config { struct parse_events_state *parse_state =3D _parse_state; struct parse_events_error *error =3D parse_state->error; @@ -485,51 +476,8 @@ PE_NAME_CACHE_TYPE '-' PE_NAME_CACHE_OP_RESULT '-' PE_= NAME_CACHE_OP_RESULT opt_e =20 list =3D alloc_list(); ABORT_ON(!list); - err =3D parse_events_add_cache(list, &parse_state->idx, $1, $3, $5, error= , $6, - parse_state); - parse_events_terms__delete($6); - free($1); - free($3); - free($5); - if (err) { - free_list_evsel(list); - YYABORT; - } - $$ =3D list; -} -| -PE_NAME_CACHE_TYPE '-' PE_NAME_CACHE_OP_RESULT opt_event_config -{ - struct parse_events_state *parse_state =3D _parse_state; - struct parse_events_error *error =3D parse_state->error; - struct list_head *list; - int err; + err =3D parse_events_add_cache(list, &parse_state->idx, $1, error, $2, pa= rse_state); =20 - list =3D alloc_list(); - ABORT_ON(!list); - err =3D parse_events_add_cache(list, &parse_state->idx, $1, $3, NULL, err= or, $4, - parse_state); - parse_events_terms__delete($4); - free($1); - free($3); - if (err) { - free_list_evsel(list); - YYABORT; - } - $$ =3D list; -} -| -PE_NAME_CACHE_TYPE opt_event_config -{ - struct parse_events_state *parse_state =3D _parse_state; - struct parse_events_error *error =3D parse_state->error; - struct list_head *list; - int err; - - list =3D alloc_list(); - ABORT_ON(!list); - err =3D parse_events_add_cache(list, &parse_state->idx, $1, NULL, NULL, e= rror, $2, - parse_state); parse_events_terms__delete($2); free($1); if (err) { @@ -633,17 +581,6 @@ tracepoint_name opt_event_config } =20 tracepoint_name: -PE_NAME '-' PE_NAME ':' PE_NAME -{ - struct tracepoint_name tracepoint; - - ABORT_ON(asprintf(&tracepoint.sys, "%s-%s", $1, $3) < 0); - tracepoint.event =3D $5; - free($1); - free($3); - $$ =3D tracepoint; -} -| PE_NAME ':' PE_NAME { struct tracepoint_name tracepoint =3D {$1, $3}; @@ -673,10 +610,15 @@ PE_RAW opt_event_config { struct list_head *list; int err; + u64 num; =20 list =3D alloc_list(); ABORT_ON(!list); - err =3D parse_events_add_numeric(_parse_state, list, PERF_TYPE_RAW, $1, $= 2); + errno =3D 0; + num =3D strtoull($1 + 1, NULL, 16); + ABORT_ON(errno); + free($1); + err =3D parse_events_add_numeric(_parse_state, list, PERF_TYPE_RAW, num, = $2); parse_events_terms__delete($2); if (err) { free(list); @@ -781,17 +723,22 @@ event_term $$ =3D head; } =20 +name_or_raw: PE_RAW | PE_NAME + event_term: PE_RAW { struct parse_events_term *term; =20 - ABORT_ON(parse_events_term__num(&term, PARSE_EVENTS__TERM_TYPE_CONFIG, - NULL, $1, false, &@1, NULL)); + if (parse_events_term__str(&term, PARSE_EVENTS__TERM_TYPE_RAW, + strdup("raw"), $1, &@1, &@1)) { + free($1); + YYABORT; + } $$ =3D term; } | -PE_NAME '=3D' PE_NAME +name_or_raw '=3D' PE_NAME { struct parse_events_term *term; =20 @@ -804,7 +751,7 @@ PE_NAME '=3D' PE_NAME $$ =3D term; } | -PE_NAME '=3D' PE_VALUE +name_or_raw '=3D' PE_VALUE { struct parse_events_term *term; =20 @@ -816,7 +763,7 @@ PE_NAME '=3D' PE_VALUE $$ =3D term; } | -PE_NAME '=3D' PE_VALUE_SYM_HW +name_or_raw '=3D' PE_VALUE_SYM_HW { struct parse_events_term *term; int config =3D $3 & 255; @@ -876,7 +823,7 @@ PE_TERM $$ =3D term; } | -PE_NAME array '=3D' PE_NAME +name_or_raw array '=3D' PE_NAME { struct parse_events_term *term; =20 @@ -891,7 +838,7 @@ PE_NAME array '=3D' PE_NAME $$ =3D term; } | -PE_NAME array '=3D' PE_VALUE +name_or_raw array '=3D' PE_VALUE { struct parse_events_term *term; =20 --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C571FC77B60 for ; Wed, 26 Apr 2023 07:04:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239793AbjDZHEs (ORCPT ); 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Wed, 26 Apr 2023 00:03:06 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:26 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-17-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 16/40] perf test: Validate events with hyphens in From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rewritten event parsing can handle event names that contain components of legacy events. Signed-off-by: Ian Rogers Tested-by: Kan Liang --- tools/perf/tests/parse-events.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index 6eadb8a47dbf..cb976765b8b0 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -2198,18 +2198,6 @@ static int test__pmu_events(struct test_suite *test = __maybe_unused, int subtest ret =3D combine_test_results(ret, TEST_SKIP); continue; } - /* - * Names containing '-' are recognized as prefixes and suffixes - * due to '-' being a legacy PMU separator. This fails when the - * prefix or suffix collides with an existing legacy token. For - * example, branch-brs has a prefix (branch) that collides with - * a PE_NAME_CACHE_TYPE token causing a parse error as a suffix - * isn't expected after this. As event names in the config - * slashes are allowed a '-' in the name we check this works - * above. - */ - if (strchr(ent->d_name, '-')) - continue; =20 dir =3D opendir(path); if (!dir) { --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E35C7C77B7C for ; Wed, 26 Apr 2023 07:05:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239707AbjDZHFG (ORCPT ); Wed, 26 Apr 2023 03:05:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39610 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239825AbjDZHEd (ORCPT ); Wed, 26 Apr 2023 03:04:33 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A55F444B6 for ; Wed, 26 Apr 2023 00:03:28 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-b8f6d2ac543so12895980276.2 for ; Wed, 26 Apr 2023 00:03:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1682492595; x=1685084595; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=Y7D6E0hATCK7e1RhJ0eODuZwXaDaxrE5gp17wu1kd6s=; b=z8cQGxheu+DMJewQ2FHIqzYoSrvavrXIpAjOk3OS7CyyD3f40naRFY2J1LOvx6/Olu 72ly0G9EqB3PLNEOq9FCvlTDcUJ1R/fkMYCLRPrsDqLYoYAH6BTKJZDvtMCGJCxG23E4 i0P+JuxZLXbDZKD0cgCL2LbTfUUZYkZ82sG2JJhTnjvfpNKCif6FcazANU7z9eGrr/x0 JBMIq2XeXcEgbZNj7zX6vLJP2ifBUyjAFmTmv0SyFhxb9tpR5+OjrH2+uPPoqvTGGxu9 Z1c2vJFlZJWZIgPY3TXADvtWEUC0fy/87G4P5rxESEzNkwoqXNczxtk54CE/wBuNdVOQ T0ZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682492595; x=1685084595; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Y7D6E0hATCK7e1RhJ0eODuZwXaDaxrE5gp17wu1kd6s=; b=To1V71jwWuu4x3KCgAM7Qrb+6eG7t/SlsWcfdRdEav/kQu5xPPvOmPLBk5pv9Id+ri 84V7O82o7sblEpSssDGpvNDNqgYkb/8N8LeoOzGig1CuBoDPyzljNNnFL8Nb5TbT+/Y6 vLAIWZ1UsUyDBQk2aU3wpuzgmu0M2mjyfpI6Ov0EY7hlPBzjFajYqc8Tc5MnFaNuP6Ll pE5LOITeeSAaBjzYubxAxd2CLkZVs2fuA0RY7QQ0LilAJf1Kp4UdYROmvN5Gfv5IWqoK hP/7BRcb5N+mDIk7FbckZ0/ApiWOLFAHCzkczLFcMlAvb0Grx4b277Si+1XMiE1UNoAy FA5g== X-Gm-Message-State: AAQBX9cF6EJoYNGxtoR+7cPFQ/BznQXcXq79eBztxDeKk8L/sNWoKKBV TrtrpmnEkidnwhmUj3GCvxMjGb4hrCuX X-Google-Smtp-Source: AKy350YtpEvrzaryAHEe/JisXIZbzPVDfFCJVa5KR2OxwYn1BzMw2cjE2nzRtyRLahgdZcGyF5nTI7nMHMkl X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:144f:e890:2b29:48d9]) (user=irogers job=sendgmr) by 2002:a25:d0c7:0:b0:b97:2ecf:ff6d with SMTP id h190-20020a25d0c7000000b00b972ecfff6dmr11079097ybg.5.1682492595218; Wed, 26 Apr 2023 00:03:15 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:27 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-18-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 17/40] perf evsel: Modify group pmu name for software events From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If we have a group of {cycles,faults} then we need the faults software event to appear to be on the same PMU as cycles so that we don't split the group in parse_events__sort_events_and_fix_groups. This case is relatively easy as cycles is the leader and will have a PMU name. In the reverse case, {faults,cycles} we still need faults to appear to have the PMU name of cycles but the old behavior is just to return "cpu". For hybrid this fails as cycles will be on "cpu_core" or "cpu_atom", causing faults to be split into a different group. Change the behavior for software events so that the whole group is searched for the named PMU. Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- tools/perf/util/evsel.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c index 1cd04b5998d2..63522322e118 100644 --- a/tools/perf/util/evsel.c +++ b/tools/perf/util/evsel.c @@ -829,23 +829,26 @@ bool evsel__name_is(struct evsel *evsel, const char *= name) =20 const char *evsel__group_pmu_name(const struct evsel *evsel) { - const struct evsel *leader; + struct evsel *leader, *pos; =20 /* If the pmu_name is set use it. pmu_name isn't set for CPU and software= events. */ if (evsel->pmu_name) return evsel->pmu_name; /* * Software events may be in a group with other uncore PMU events. Use - * the pmu_name of the group leader to avoid breaking the software event - * out of the group. + * the pmu_name of the first non-software event to avoid breaking the + * software event out of the group. * * Aux event leaders, like intel_pt, expect a group with events from * other PMUs, so substitute the AUX event's PMU in this case. */ leader =3D evsel__leader(evsel); - if ((evsel->core.attr.type =3D=3D PERF_TYPE_SOFTWARE || evsel__is_aux_eve= nt(leader)) && - leader->pmu_name) { - return leader->pmu_name; + if (evsel->core.attr.type =3D=3D PERF_TYPE_SOFTWARE || evsel__is_aux_even= t(leader)) { + /* Starting with the leader, find the first event with a named PMU. */ + for_each_group_evsel(pos, leader) { + if (pos->pmu_name) + return pos->pmu_name; + } } =20 return "cpu"; --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD187C7618E for ; Wed, 26 Apr 2023 07:05:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239699AbjDZHFJ (ORCPT ); Wed, 26 Apr 2023 03:05:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40104 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239800AbjDZHEl (ORCPT ); Wed, 26 Apr 2023 03:04:41 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BCFE04686 for ; Wed, 26 Apr 2023 00:03:33 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-b8f324b3ef8so7383594276.0 for ; Wed, 26 Apr 2023 00:03:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1682492602; x=1685084602; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=RjuboGAp9ru4SnSIW5FLSn0mUR/AY3DyroHqTIHNwEU=; b=sBlg/i3eLnD4UQIvD1Ots6pX3JAgdWb2iZdiPnk+L9cXtOGQp7d7cKUzdVgaigpQCd Ld821gQkXe21anWpF0Jv26BsUPJmUJaFBgPgX3/M4FfoMZC2kfuCJK5fNFzdDbEjywiR D+WmY/WIuPlPjHCkwuRguKolpF4pggT+qEIYEcmwD8YISDR8ioElgGxlpphh3kyqJQ17 atamyWXOfkICffnapgXxTEB45wNeMy3vLzqBgaZuyHDTjtPR0Qu1ZPvaO1CFDAnP6CdK msw96QpC2dN0luIR+BNrwZKksWnO6kJmkPR4wPeanEhPOSnxXJTokMvPx947IBF2ltPy UbQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682492602; x=1685084602; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=RjuboGAp9ru4SnSIW5FLSn0mUR/AY3DyroHqTIHNwEU=; b=Jbu5mAsgimKJyssbpXGFae45F+5wAZnmBSucs743wrM4GeiRAHRR95KftgK/fbgfXn tQAIkFptZLTFFlmb1z1VujS/pfCeqmC2DRtjUWfZGB1ixvHjVs3KxMdfIQ6Ji2ufyG/2 HOux+Phk3HSlpttz0/9jhuQMWCm2lq+kn1N30hp2bHH8vkm3ahTtTtTfjMNNZ0O5iDIT T3fVV5zcLWi2EyFxpJohmNnHmIglOvuj51+mLpDUYIPfuxx1HXvhFDqNwLcKg3T+TMrF L6BmCPjktAHj82el7Nc+y0zeO+hGoStXv0jd9c8KcP60RtKZ/60MnV3tO9ORdtgqo2fa N/5g== X-Gm-Message-State: AAQBX9fx/oOP9ufrJTGvOG6XnMlwxcyDxIYFNAOAKjNL+NZMuj31q0TJ RD99qTlO3lcMmRmL/eZQ7tnWPQT+D5Vg X-Google-Smtp-Source: AKy350ZKCF6AWWNH8UHj0BVpfzJLYnJboM0AtbYgLh9kcD2AuzMqHmjbv/4m/FvGcFtSXkhq6k+ud7nyztf3 X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:144f:e890:2b29:48d9]) (user=irogers job=sendgmr) by 2002:a25:7452:0:b0:b92:2c78:1481 with SMTP id p79-20020a257452000000b00b922c781481mr11283377ybc.12.1682492602305; Wed, 26 Apr 2023 00:03:22 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:28 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-19-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 18/40] perf test: Move x86 hybrid tests to arch/x86 From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The tests use x86 hybrid specific PMUs. Signed-off-by: Ian Rogers --- tools/perf/arch/x86/include/arch-tests.h | 1 + tools/perf/arch/x86/tests/Build | 1 + tools/perf/arch/x86/tests/arch-tests.c | 10 + tools/perf/arch/x86/tests/hybrid.c | 277 +++++++++++++++++++++++ tools/perf/tests/parse-events.c | 181 --------------- 5 files changed, 289 insertions(+), 181 deletions(-) create mode 100644 tools/perf/arch/x86/tests/hybrid.c diff --git a/tools/perf/arch/x86/include/arch-tests.h b/tools/perf/arch/x86= /include/arch-tests.h index 902e9ea9b99e..33d39c1d3e64 100644 --- a/tools/perf/arch/x86/include/arch-tests.h +++ b/tools/perf/arch/x86/include/arch-tests.h @@ -11,6 +11,7 @@ int test__intel_pt_pkt_decoder(struct test_suite *test, i= nt subtest); int test__intel_pt_hybrid_compat(struct test_suite *test, int subtest); int test__bp_modify(struct test_suite *test, int subtest); int test__x86_sample_parsing(struct test_suite *test, int subtest); +int test__hybrid(struct test_suite *test, int subtest); =20 extern struct test_suite *arch_tests[]; =20 diff --git a/tools/perf/arch/x86/tests/Build b/tools/perf/arch/x86/tests/Bu= ild index 6f4e8636c3bf..08cc8b9c931e 100644 --- a/tools/perf/arch/x86/tests/Build +++ b/tools/perf/arch/x86/tests/Build @@ -3,5 +3,6 @@ perf-$(CONFIG_DWARF_UNWIND) +=3D dwarf-unwind.o =20 perf-y +=3D arch-tests.o perf-y +=3D sample-parsing.o +perf-y +=3D hybrid.o perf-$(CONFIG_AUXTRACE) +=3D insn-x86.o intel-pt-test.o perf-$(CONFIG_X86_64) +=3D bp-modify.o diff --git a/tools/perf/arch/x86/tests/arch-tests.c b/tools/perf/arch/x86/t= ests/arch-tests.c index aae6ea0fe52b..147ad0638bbb 100644 --- a/tools/perf/arch/x86/tests/arch-tests.c +++ b/tools/perf/arch/x86/tests/arch-tests.c @@ -22,6 +22,15 @@ struct test_suite suite__intel_pt =3D { DEFINE_SUITE("x86 bp modify", bp_modify); #endif DEFINE_SUITE("x86 Sample parsing", x86_sample_parsing); +static struct test_case hybrid_tests[] =3D { + TEST_CASE_REASON("x86 hybrid event parsing", hybrid, "not hybrid"), + { .name =3D NULL, } +}; + +struct test_suite suite__hybrid =3D { + .desc =3D "x86 hybrid", + .test_cases =3D hybrid_tests, +}; =20 struct test_suite *arch_tests[] =3D { #ifdef HAVE_DWARF_UNWIND_SUPPORT @@ -35,5 +44,6 @@ struct test_suite *arch_tests[] =3D { &suite__bp_modify, #endif &suite__x86_sample_parsing, + &suite__hybrid, NULL, }; diff --git a/tools/perf/arch/x86/tests/hybrid.c b/tools/perf/arch/x86/tests= /hybrid.c new file mode 100644 index 000000000000..0f99cfd116ee --- /dev/null +++ b/tools/perf/arch/x86/tests/hybrid.c @@ -0,0 +1,277 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "arch-tests.h" +#include "debug.h" +#include "evlist.h" +#include "evsel.h" +#include "pmu-hybrid.h" +#include "tests/tests.h" + +static bool test_config(const struct evsel *evsel, __u64 expected_config) +{ + return (evsel->core.attr.config & PERF_HW_EVENT_MASK) =3D=3D expected_con= fig; +} + +static int test__hybrid_hw_event_with_pmu(struct evlist *evlist) +{ + struct evsel *evsel =3D evlist__first(evlist); + + TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); + return TEST_OK; +} + +static int test__hybrid_hw_group_event(struct evlist *evlist) +{ + struct evsel *evsel, *leader; + + evsel =3D leader =3D evlist__first(evlist); + TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); + TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); + + evsel =3D evsel__next(evsel); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0xc0)); + TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); + return TEST_OK; +} + +static int test__hybrid_sw_hw_group_event(struct evlist *evlist) +{ + struct evsel *evsel, *leader; + + evsel =3D leader =3D evlist__first(evlist); + TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_SOFTWARE =3D=3D evsel->core.attr.= type); + TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); + + evsel =3D evsel__next(evsel); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); + TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); + return TEST_OK; +} + +static int test__hybrid_hw_sw_group_event(struct evlist *evlist) +{ + struct evsel *evsel, *leader; + + evsel =3D leader =3D evlist__first(evlist); + TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); + TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); + + evsel =3D evsel__next(evsel); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_SOFTWARE =3D=3D evsel->core.attr.= type); + TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); + return TEST_OK; +} + +static int test__hybrid_group_modifier1(struct evlist *evlist) +{ + struct evsel *evsel, *leader; + + evsel =3D leader =3D evlist__first(evlist); + TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); + TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); + TEST_ASSERT_VAL("wrong exclude_user", evsel->core.attr.exclude_user); + TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); + + evsel =3D evsel__next(evsel); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0xc0)); + TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); + TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); + TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); + return TEST_OK; +} + +static int test__hybrid_raw1(struct evlist *evlist) +{ + struct evsel *evsel =3D evlist__first(evlist); + + if (!perf_pmu__hybrid_mounted("cpu_atom")) { + TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entr= ies); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type= ); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); + return TEST_OK; + } + + TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); + + /* The type of second event is randome value */ + evsel =3D evsel__next(evsel); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); + return TEST_OK; +} + +static int test__hybrid_raw2(struct evlist *evlist) +{ + struct evsel *evsel =3D evlist__first(evlist); + + TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); + TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); + return TEST_OK; +} + +static int test__hybrid_cache_event(struct evlist *evlist) +{ + struct evsel *evsel =3D evlist__first(evlist); + + TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_HW_CACHE =3D=3D evsel->core.attr.= type); + TEST_ASSERT_VAL("wrong config", 0x2 =3D=3D (evsel->core.attr.config & 0xf= fffffff)); + return TEST_OK; +} + +static int test__checkevent_pmu(struct evlist *evlist) +{ + + struct evsel *evsel =3D evlist__first(evlist); + + TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); + TEST_ASSERT_VAL("wrong config", 10 =3D=3D evsel->core.attr.config); + TEST_ASSERT_VAL("wrong config1", 1 =3D=3D evsel->core.attr.config1); + TEST_ASSERT_VAL("wrong config2", 3 =3D=3D evsel->core.attr.config2); + TEST_ASSERT_VAL("wrong config3", 0 =3D=3D evsel->core.attr.config3); + /* + * The period value gets configured within evlist__config, + * while this test executes only parse events method. + */ + TEST_ASSERT_VAL("wrong period", 0 =3D=3D evsel->core.attr.sample_peri= od); + + return TEST_OK; +} + +struct evlist_test { + const char *name; + bool (*valid)(void); + int (*check)(struct evlist *evlist); +}; + +static const struct evlist_test test__hybrid_events[] =3D { + { + .name =3D "cpu_core/cpu-cycles/", + .check =3D test__hybrid_hw_event_with_pmu, + /* 0 */ + }, + { + .name =3D "{cpu_core/cpu-cycles/,cpu_core/instructions/}", + .check =3D test__hybrid_hw_group_event, + /* 1 */ + }, + { + .name =3D "{cpu-clock,cpu_core/cpu-cycles/}", + .check =3D test__hybrid_sw_hw_group_event, + /* 2 */ + }, + { + .name =3D "{cpu_core/cpu-cycles/,cpu-clock}", + .check =3D test__hybrid_hw_sw_group_event, + /* 3 */ + }, + { + .name =3D "{cpu_core/cpu-cycles/k,cpu_core/instructions/u}", + .check =3D test__hybrid_group_modifier1, + /* 4 */ + }, + { + .name =3D "r1a", + .check =3D test__hybrid_raw1, + /* 5 */ + }, + { + .name =3D "cpu_core/r1a/", + .check =3D test__hybrid_raw2, + /* 6 */ + }, + { + .name =3D "cpu_core/config=3D10,config1,config2=3D3,period=3D1000/u", + .check =3D test__checkevent_pmu, + /* 7 */ + }, + { + .name =3D "cpu_core/LLC-loads/", + .check =3D test__hybrid_cache_event, + /* 8 */ + }, +}; + +static int test_event(const struct evlist_test *e) +{ + struct parse_events_error err; + struct evlist *evlist; + int ret; + + if (e->valid && !e->valid()) { + pr_debug("... SKIP\n"); + return TEST_OK; + } + + evlist =3D evlist__new(); + if (evlist =3D=3D NULL) { + pr_err("Failed allocation"); + return TEST_FAIL; + } + parse_events_error__init(&err); + ret =3D parse_events(evlist, e->name, &err); + if (ret) { + pr_debug("failed to parse event '%s', err %d, str '%s'\n", + e->name, ret, err.str); + parse_events_error__print(&err, e->name); + ret =3D TEST_FAIL; + if (strstr(err.str, "can't access trace events")) + ret =3D TEST_SKIP; + } else { + ret =3D e->check(evlist); + } + parse_events_error__exit(&err); + evlist__delete(evlist); + + return ret; +} + +static int combine_test_results(int existing, int latest) +{ + if (existing =3D=3D TEST_FAIL) + return TEST_FAIL; + if (existing =3D=3D TEST_SKIP) + return latest =3D=3D TEST_OK ? TEST_SKIP : latest; + return latest; +} + +static int test_events(const struct evlist_test *events, int cnt) +{ + int ret =3D TEST_OK; + + for (int i =3D 0; i < cnt; i++) { + const struct evlist_test *e =3D &events[i]; + int test_ret; + + pr_debug("running test %d '%s'\n", i, e->name); + test_ret =3D test_event(e); + if (test_ret !=3D TEST_OK) { + pr_debug("Event test failure: test %d '%s'", i, e->name); + ret =3D combine_test_results(ret, test_ret); + } + } + + return ret; +} + +int test__hybrid(struct test_suite *test __maybe_unused, int subtest __may= be_unused) +{ + if (!perf_pmu__has_hybrid()) + return TEST_SKIP; + + return test_events(test__hybrid_events, ARRAY_SIZE(test__hybrid_events)); +} diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index cb976765b8b0..15fec7f01315 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -6,7 +6,6 @@ #include "tests.h" #include "debug.h" #include "pmu.h" -#include "pmu-hybrid.h" #include "pmus.h" #include #include @@ -1509,127 +1508,6 @@ static int test__all_tracepoints(struct evlist *evl= ist) } #endif /* HAVE_LIBTRACEVENT */ =20 -static int test__hybrid_hw_event_with_pmu(struct evlist *evlist) -{ - struct evsel *evsel =3D evlist__first(evlist); - - TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); - return TEST_OK; -} - -static int test__hybrid_hw_group_event(struct evlist *evlist) -{ - struct evsel *evsel, *leader; - - evsel =3D leader =3D evlist__first(evlist); - TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); - TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); - - evsel =3D evsel__next(evsel); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0xc0)); - TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); - return TEST_OK; -} - -static int test__hybrid_sw_hw_group_event(struct evlist *evlist) -{ - struct evsel *evsel, *leader; - - evsel =3D leader =3D evlist__first(evlist); - TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_SOFTWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); - - evsel =3D evsel__next(evsel); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); - TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); - return TEST_OK; -} - -static int test__hybrid_hw_sw_group_event(struct evlist *evlist) -{ - struct evsel *evsel, *leader; - - evsel =3D leader =3D evlist__first(evlist); - TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); - TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); - - evsel =3D evsel__next(evsel); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_SOFTWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); - return TEST_OK; -} - -static int test__hybrid_group_modifier1(struct evlist *evlist) -{ - struct evsel *evsel, *leader; - - evsel =3D leader =3D evlist__first(evlist); - TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x3c)); - TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); - TEST_ASSERT_VAL("wrong exclude_user", evsel->core.attr.exclude_user); - TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); - - evsel =3D evsel__next(evsel); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0xc0)); - TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); - TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); - TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); - return TEST_OK; -} - -static int test__hybrid_raw1(struct evlist *evlist) -{ - struct evsel *evsel =3D evlist__first(evlist); - - if (!perf_pmu__hybrid_mounted("cpu_atom")) { - TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entr= ies); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type= ); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); - return TEST_OK; - } - - TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); - - /* The type of second event is randome value */ - evsel =3D evsel__next(evsel); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); - return TEST_OK; -} - -static int test__hybrid_raw2(struct evlist *evlist) -{ - struct evsel *evsel =3D evlist__first(evlist); - - TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); - return TEST_OK; -} - -static int test__hybrid_cache_event(struct evlist *evlist) -{ - struct evsel *evsel =3D evlist__first(evlist); - - TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_HW_CACHE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", 0x2 =3D=3D (evsel->core.attr.config & 0xf= fffffff)); - return TEST_OK; -} - struct evlist_test { const char *name; bool (*valid)(void); @@ -1997,54 +1875,6 @@ static const struct terms_test test__terms[] =3D { }, }; =20 -static const struct evlist_test test__hybrid_events[] =3D { - { - .name =3D "cpu_core/cpu-cycles/", - .check =3D test__hybrid_hw_event_with_pmu, - /* 0 */ - }, - { - .name =3D "{cpu_core/cpu-cycles/,cpu_core/instructions/}", - .check =3D test__hybrid_hw_group_event, - /* 1 */ - }, - { - .name =3D "{cpu-clock,cpu_core/cpu-cycles/}", - .check =3D test__hybrid_sw_hw_group_event, - /* 2 */ - }, - { - .name =3D "{cpu_core/cpu-cycles/,cpu-clock}", - .check =3D test__hybrid_hw_sw_group_event, - /* 3 */ - }, - { - .name =3D "{cpu_core/cpu-cycles/k,cpu_core/instructions/u}", - .check =3D test__hybrid_group_modifier1, - /* 4 */ - }, - { - .name =3D "r1a", - .check =3D test__hybrid_raw1, - /* 5 */ - }, - { - .name =3D "cpu_core/r1a/", - .check =3D test__hybrid_raw2, - /* 6 */ - }, - { - .name =3D "cpu_core/config=3D10,config1,config2=3D3,period=3D1000/u", - .check =3D test__checkevent_pmu, - /* 7 */ - }, - { - .name =3D "cpu_core/LLC-loads/", - .check =3D test__hybrid_cache_event, - /* 8 */ - }, -}; - static int test_event(const struct evlist_test *e) { struct parse_events_error err; @@ -2307,14 +2137,6 @@ static bool test_alias(char **event, char **alias) return false; } =20 -static int test__hybrid(struct test_suite *test __maybe_unused, int subtes= t __maybe_unused) -{ - if (!perf_pmu__has_hybrid()) - return TEST_SKIP; - - return test_events(test__hybrid_events, ARRAY_SIZE(test__hybrid_events)); -} - static int test__checkevent_pmu_events_alias(struct evlist *evlist) { struct evsel *evsel1 =3D evlist__first(evlist); @@ -2378,9 +2200,6 @@ static struct test_case tests__parse_events[] =3D { TEST_CASE_REASON("Test event parsing", events2, "permissions"), - TEST_CASE_REASON("Test parsing of \"hybrid\" CPU events", - hybrid, - "not hybrid"), TEST_CASE_REASON("Parsing of all PMU events from sysfs", pmu_events, "permissions"), --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D0DDC77B78 for ; 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Wed, 26 Apr 2023 00:03:33 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:29 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-20-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 19/40] perf test x86 hybrid: Don't assume evlist order From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Switch to a loop rather than depend on evlist order for raw events test. Signed-off-by: Ian Rogers --- tools/perf/arch/x86/tests/hybrid.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/tools/perf/arch/x86/tests/hybrid.c b/tools/perf/arch/x86/tests= /hybrid.c index 0f99cfd116ee..66486335652f 100644 --- a/tools/perf/arch/x86/tests/hybrid.c +++ b/tools/perf/arch/x86/tests/hybrid.c @@ -11,6 +11,11 @@ static bool test_config(const struct evsel *evsel, __u64= expected_config) return (evsel->core.attr.config & PERF_HW_EVENT_MASK) =3D=3D expected_con= fig; } =20 +static bool test_perf_config(const struct perf_evsel *evsel, __u64 expecte= d_config) +{ + return (evsel->attr.config & PERF_HW_EVENT_MASK) =3D=3D expected_config; +} + static int test__hybrid_hw_event_with_pmu(struct evlist *evlist) { struct evsel *evsel =3D evlist__first(evlist); @@ -93,22 +98,15 @@ static int test__hybrid_group_modifier1(struct evlist *= evlist) =20 static int test__hybrid_raw1(struct evlist *evlist) { - struct evsel *evsel =3D evlist__first(evlist); + struct perf_evsel *evsel; =20 - if (!perf_pmu__hybrid_mounted("cpu_atom")) { - TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entr= ies); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type= ); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); - return TEST_OK; - } + perf_evlist__for_each_evsel(&evlist->core, evsel) { + struct perf_pmu *pmu =3D perf_pmu__find_by_type(evsel->attr.type); =20 - TEST_ASSERT_VAL("wrong number of entries", 2 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); - - /* The type of second event is randome value */ - evsel =3D evsel__next(evsel); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); + TEST_ASSERT_VAL("missing pmu", pmu); + TEST_ASSERT_VAL("unexpected pmu", !strncmp(pmu->name, "cpu_", 4)); + TEST_ASSERT_VAL("wrong config", test_perf_config(evsel, 0x1a)); + } return TEST_OK; } =20 --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7AD3DC7618E for ; Wed, 26 Apr 2023 07:05:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239872AbjDZHF3 (ORCPT ); Wed, 26 Apr 2023 03:05:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39274 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239874AbjDZHEy (ORCPT ); Wed, 26 Apr 2023 03:04:54 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AAB7746B1 for ; Wed, 26 Apr 2023 00:03:46 -0700 (PDT) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-55605fd3e19so108467637b3.1 for ; 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Wed, 26 Apr 2023 00:03:40 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:30 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-21-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 20/40] perf parse-events: Support PMUs for legacy cache events From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allow a legacy cache event to be both, for example, "L1-dcache-load-miss" and "cpu/L1-dcache-load-miss/" by introducing a new legacy cache term type. The term type is processed in config_term_pmu, setting both the type in perf_event_attr and the config. The code to determine the config is factored out of parse_events_add_cache and shared. If the PMU doesn't support legacy events, currently just core/hybrid PMUs do, then the term is treated like a PE_NAME term - as before. If only terms are being parsed, such as for perf_pmu__new_alias, then the PE_LEGACY_CACHE token is always parsed as PE_NAME. Signed-off-by: Ian Rogers --- tools/perf/tests/parse-events.c | 18 +++++++++ tools/perf/util/parse-events.c | 70 ++++++++++++++++++++++----------- tools/perf/util/parse-events.h | 3 ++ tools/perf/util/parse-events.l | 9 ++++- tools/perf/util/parse-events.y | 14 ++++++- tools/perf/util/pmu.c | 5 +++ tools/perf/util/pmu.h | 1 + 7 files changed, 96 insertions(+), 24 deletions(-) diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index 15fec7f01315..6aea51e33dc0 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -1861,6 +1861,24 @@ static const struct evlist_test test__events_pmu[] = =3D { .check =3D test__checkevent_raw_pmu, /* 5 */ }, + { + .name =3D "cpu/L1-dcache-load-miss/", + .valid =3D test__pmu_cpu_valid, + .check =3D test__checkevent_genhw, + /* 6 */ + }, + { + .name =3D "cpu/L1-dcache-load-miss/kp", + .valid =3D test__pmu_cpu_valid, + .check =3D test__checkevent_genhw_modifier, + /* 7 */ + }, + { + .name =3D "cpu/L1-dcache-misses,name=3Dcachepmu/", + .valid =3D test__pmu_cpu_valid, + .check =3D test__checkevent_config_cache, + /* 8 */ + }, }; =20 struct terms_test { diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index e416e653cf74..9b2d7b6572c2 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -403,33 +403,27 @@ static int config_attr(struct perf_event_attr *attr, struct parse_events_error *err, config_term_func_t config_term); =20 -int parse_events_add_cache(struct list_head *list, int *idx, const char *n= ame, - struct parse_events_error *err, - struct list_head *head_config, - struct parse_events_state *parse_state) +/** + * parse_events__decode_legacy_cache - Search name for the legacy cache ev= ent + * name composed of 1, 2 or 3 hyphen + * separated sections. The first secti= on is + * the cache type while the others are= the + * optional op and optional result. To= make + * life hard the names in the table al= so + * contain hyphens and the longest name + * should always be selected. + */ +static int parse_events__decode_legacy_cache(const char *name, int pmu_typ= e, __u64 *config) { - struct perf_event_attr attr; - LIST_HEAD(config_terms); - const char *config_name, *metric_id; - int cache_type =3D -1, cache_op =3D -1, cache_result =3D -1; - int ret, len; + int len, cache_type =3D -1, cache_op =3D -1, cache_result =3D -1; const char *name_end =3D &name[strlen(name) + 1]; - bool hybrid; const char *str =3D name; =20 - /* - * Search str for the legacy cache event name composed of 1, 2 or 3 - * hyphen separated sections. The first section is the cache type while - * the others are the optional op and optional result. To make life hard - * the names in the table also contain hyphens and the longest name - * should always be selected. - */ cache_type =3D parse_aliases(str, evsel__hw_cache, PERF_COUNT_HW_CACHE_MA= X, &len); if (cache_type =3D=3D -1) return -EINVAL; str +=3D len + 1; =20 - config_name =3D get_config_name(head_config); if (str < name_end) { cache_op =3D parse_aliases(str, evsel__hw_cache_op, PERF_COUNT_HW_CACHE_OP_MAX, &len); @@ -470,9 +464,28 @@ int parse_events_add_cache(struct list_head *list, int= *idx, const char *name, if (cache_result =3D=3D -1) cache_result =3D PERF_COUNT_HW_CACHE_RESULT_ACCESS; =20 + *config =3D ((__u64)pmu_type << PERF_PMU_TYPE_SHIFT) | + cache_type | (cache_op << 8) | (cache_result << 16); + return 0; +} + +int parse_events_add_cache(struct list_head *list, int *idx, const char *n= ame, + struct parse_events_error *err, + struct list_head *head_config, + struct parse_events_state *parse_state) +{ + struct perf_event_attr attr; + LIST_HEAD(config_terms); + const char *config_name, *metric_id; + int ret; + bool hybrid; + + memset(&attr, 0, sizeof(attr)); - attr.config =3D cache_type | (cache_op << 8) | (cache_result << 16); attr.type =3D PERF_TYPE_HW_CACHE; + ret =3D parse_events__decode_legacy_cache(name, /*pmu_type=3D*/0, &attr.c= onfig); + if (ret) + return ret; =20 if (head_config) { if (config_attr(&attr, head_config, err, @@ -483,6 +496,7 @@ int parse_events_add_cache(struct list_head *list, int = *idx, const char *name, return -ENOMEM; } =20 + config_name =3D get_config_name(head_config); metric_id =3D get_config_metric_id(head_config); ret =3D parse_events__add_cache_hybrid(list, idx, &attr, config_name ? : name, @@ -1021,6 +1035,7 @@ static const char *config_term_names[__PARSE_EVENTS__= TERM_TYPE_NR] =3D { [PARSE_EVENTS__TERM_TYPE_AUX_SAMPLE_SIZE] =3D "aux-sample-size", [PARSE_EVENTS__TERM_TYPE_METRIC_ID] =3D "metric-id", [PARSE_EVENTS__TERM_TYPE_RAW] =3D "raw", + [PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE] =3D "legacy-cache", }; =20 static bool config_term_shrinked; @@ -1198,15 +1213,25 @@ static int config_term_pmu(struct perf_event_attr *= attr, struct parse_events_term *term, struct parse_events_error *err) { + if (term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE) { + const struct perf_pmu *pmu =3D perf_pmu__find_by_type(attr->type); + + if (perf_pmu__supports_legacy_cache(pmu)) { + attr->type =3D PERF_TYPE_HW_CACHE; + return parse_events__decode_legacy_cache(term->config, pmu->type, + &attr->config); + } else + term->type_term =3D PARSE_EVENTS__TERM_TYPE_USER; + } if (term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_USER || - term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_DRV_CFG) + term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_DRV_CFG) { /* * Always succeed for sysfs terms, as we dont know * at this point what type they need to have. */ return 0; - else - return config_term_common(attr, term, err); + } + return config_term_common(attr, term, err); } =20 #ifdef HAVE_LIBTRACEEVENT @@ -2145,6 +2170,7 @@ int __parse_events(struct evlist *evlist, const char = *str, .evlist =3D evlist, .stoken =3D PE_START_EVENTS, .fake_pmu =3D fake_pmu, + .match_legacy_cache_terms =3D true, }; int ret; =20 diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index f638542c8638..5acb62c2e00a 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -71,6 +71,7 @@ enum { PARSE_EVENTS__TERM_TYPE_AUX_SAMPLE_SIZE, PARSE_EVENTS__TERM_TYPE_METRIC_ID, PARSE_EVENTS__TERM_TYPE_RAW, + PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE, __PARSE_EVENTS__TERM_TYPE_NR, }; =20 @@ -122,6 +123,8 @@ struct parse_events_state { int stoken; struct perf_pmu *fake_pmu; char *hybrid_pmu_name; + /* Should PE_LEGACY_NAME tokens be generated for config terms? */ + bool match_legacy_cache_terms; bool wild_card_pmus; }; =20 diff --git a/tools/perf/util/parse-events.l b/tools/perf/util/parse-events.l index 4b35c099189a..abe0ce681d29 100644 --- a/tools/perf/util/parse-events.l +++ b/tools/perf/util/parse-events.l @@ -63,6 +63,11 @@ static int str(yyscan_t scanner, int token) return token; } =20 +static int lc_str(yyscan_t scanner, const struct parse_events_state *state) +{ + return str(scanner, state->match_legacy_cache_terms ? PE_LEGACY_CACHE : P= E_NAME); +} + static bool isbpf_suffix(char *text) { int len =3D strlen(text); @@ -185,7 +190,6 @@ lc_op_result (load|loads|read|store|stores|write|prefet= ch|prefetches|speculative =20 %{ struct parse_events_state *_parse_state =3D parse_events_get_extra(yyscan= ner); - { int start_token =3D _parse_state->stoken; =20 @@ -269,6 +273,9 @@ r{num_raw_hex} { return str(yyscanner, PE_RAW); } r0x{num_raw_hex} { return str(yyscanner, PE_RAW); } , { return ','; } "/" { BEGIN(INITIAL); return '/'; } +{lc_type} { return lc_str(yyscanner, _parse_state); } +{lc_type}-{lc_op_result} { return lc_str(yyscanner, _parse_state); } +{lc_type}-{lc_op_result}-{lc_op_result} { return lc_str(yyscanner, _parse_= state); } {name_minus} { return str(yyscanner, PE_NAME); } \[all\] { return PE_ARRAY_ALL; } "[" { BEGIN(array); return '['; } diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y index e7072b5601c5..f84fa1b132b3 100644 --- a/tools/perf/util/parse-events.y +++ b/tools/perf/util/parse-events.y @@ -723,7 +723,7 @@ event_term $$ =3D head; } =20 -name_or_raw: PE_RAW | PE_NAME +name_or_raw: PE_RAW | PE_NAME | PE_LEGACY_CACHE =20 event_term: PE_RAW @@ -775,6 +775,18 @@ name_or_raw '=3D' PE_VALUE_SYM_HW $$ =3D term; } | +PE_LEGACY_CACHE +{ + struct parse_events_term *term; + + if (parse_events_term__num(&term, PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE, + $1, 1, true, &@1, NULL)) { + free($1); + YYABORT; + } + $$ =3D term; +} +| PE_NAME { struct parse_events_term *term; diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index cb33d869f1ed..63071d876190 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -1650,6 +1650,11 @@ bool is_pmu_core(const char *name) return !strcmp(name, "cpu") || is_arm_pmu_core(name); } =20 +bool perf_pmu__supports_legacy_cache(const struct perf_pmu *pmu) +{ + return is_pmu_core(pmu->name) || perf_pmu__is_hybrid(pmu->name); +} + static bool pmu_alias_is_duplicate(struct sevent *alias_a, struct sevent *alias_b) { diff --git a/tools/perf/util/pmu.h b/tools/perf/util/pmu.h index b9a02dedd473..05702bc4bcf8 100644 --- a/tools/perf/util/pmu.h +++ b/tools/perf/util/pmu.h @@ -220,6 +220,7 @@ void perf_pmu__del_formats(struct list_head *formats); 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charset="utf-8" It is inconsistent that "perf stat -e instructions-retired" wildcard opens on all PMUs while legacy cache events like "perf stat -e L1-dcache-load-miss" do not. A behavior introduced by hybrid is that a legacy cache event like L1-dcache-load-miss should wildcard open on all hybrid PMUs. A call to is_event_supported is necessary for each PMU, a failure of which results in the event not being added. Rather than special case that logic, move it into the main legacy cache event case and attempt to open legacy cache events on all PMUs. Signed-off-by: Ian Rogers --- tools/perf/util/parse-events-hybrid.c | 33 ------------- tools/perf/util/parse-events-hybrid.h | 7 --- tools/perf/util/parse-events.c | 70 ++++++++++++++------------- tools/perf/util/parse-events.h | 3 +- tools/perf/util/parse-events.y | 2 +- 5 files changed, 39 insertions(+), 76 deletions(-) diff --git a/tools/perf/util/parse-events-hybrid.c b/tools/perf/util/parse-= events-hybrid.c index 7c9f9150bad5..d2c0be051d46 100644 --- a/tools/perf/util/parse-events-hybrid.c +++ b/tools/perf/util/parse-events-hybrid.c @@ -179,36 +179,3 @@ int parse_events__add_numeric_hybrid(struct parse_even= ts_state *parse_state, return add_raw_hybrid(parse_state, list, attr, name, metric_id, config_terms); } - -int parse_events__add_cache_hybrid(struct list_head *list, int *idx, - struct perf_event_attr *attr, - const char *name, - const char *metric_id, - struct list_head *config_terms, - bool *hybrid, - struct parse_events_state *parse_state) -{ - struct perf_pmu *pmu; - int ret; - - *hybrid =3D false; - if (!perf_pmu__has_hybrid()) - return 0; - - *hybrid =3D true; - perf_pmu__for_each_hybrid_pmu(pmu) { - LIST_HEAD(terms); - - if (pmu_cmp(parse_state, pmu)) - continue; - - copy_config_terms(&terms, config_terms); - ret =3D create_event_hybrid(PERF_TYPE_HW_CACHE, idx, list, - attr, name, metric_id, &terms, pmu); - free_config_terms(&terms); - if (ret) - return ret; - } - - return 0; -} diff --git a/tools/perf/util/parse-events-hybrid.h b/tools/perf/util/parse-= events-hybrid.h index cbc05fec02a2..bc2966e73897 100644 --- a/tools/perf/util/parse-events-hybrid.h +++ b/tools/perf/util/parse-events-hybrid.h @@ -15,11 +15,4 @@ int parse_events__add_numeric_hybrid(struct parse_events= _state *parse_state, struct list_head *config_terms, bool *hybrid); =20 -int parse_events__add_cache_hybrid(struct list_head *list, int *idx, - struct perf_event_attr *attr, - const char *name, const char *metric_id, - struct list_head *config_terms, - bool *hybrid, - struct parse_events_state *parse_state); - #endif /* __PERF_PARSE_EVENTS_HYBRID_H */ diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index 9b2d7b6572c2..e007b2bc1ab4 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -471,46 +471,50 @@ static int parse_events__decode_legacy_cache(const ch= ar *name, int pmu_type, __u =20 int parse_events_add_cache(struct list_head *list, int *idx, const char *n= ame, struct parse_events_error *err, - struct list_head *head_config, - struct parse_events_state *parse_state) + struct list_head *head_config) { - struct perf_event_attr attr; - LIST_HEAD(config_terms); - const char *config_name, *metric_id; - int ret; - bool hybrid; + struct perf_pmu *pmu =3D NULL; + bool found_supported =3D false; + const char *config_name =3D get_config_name(head_config); + const char *metric_id =3D get_config_metric_id(head_config); =20 + while ((pmu =3D perf_pmu__scan(pmu)) !=3D NULL) { + LIST_HEAD(config_terms); + struct perf_event_attr attr; + int ret; =20 - memset(&attr, 0, sizeof(attr)); - attr.type =3D PERF_TYPE_HW_CACHE; - ret =3D parse_events__decode_legacy_cache(name, /*pmu_type=3D*/0, &attr.c= onfig); - if (ret) - return ret; + /* + * Skip uncore PMUs for performance. Software PMUs can open + * PERF_TYPE_HW_CACHE, so skip. + */ + if (pmu->is_uncore || pmu->type =3D=3D PERF_TYPE_SOFTWARE) + continue; =20 - if (head_config) { - if (config_attr(&attr, head_config, err, - config_term_common)) - return -EINVAL; + memset(&attr, 0, sizeof(attr)); + attr.type =3D PERF_TYPE_HW_CACHE; =20 - if (get_config_terms(head_config, &config_terms)) - return -ENOMEM; - } + ret =3D parse_events__decode_legacy_cache(name, pmu->type, &attr.config); + if (ret) + return ret; =20 - config_name =3D get_config_name(head_config); - metric_id =3D get_config_metric_id(head_config); - ret =3D parse_events__add_cache_hybrid(list, idx, &attr, - config_name ? : name, - metric_id, - &config_terms, - &hybrid, parse_state); - if (hybrid) - goto out_free_terms; + if (!is_event_supported(PERF_TYPE_HW_CACHE, attr.config)) + continue; =20 - ret =3D add_event(list, idx, &attr, config_name ? : name, metric_id, - &config_terms); -out_free_terms: - free_config_terms(&config_terms); - return ret; + found_supported =3D true; + + if (head_config) { + if (config_attr(&attr, head_config, err, + config_term_common)) + return -EINVAL; + + if (get_config_terms(head_config, &config_terms)) + return -ENOMEM; + } + + ret =3D add_event(list, idx, &attr, config_name ? : name, metric_id, &co= nfig_terms); + free_config_terms(&config_terms); + } + return found_supported ? 0: -EINVAL; } =20 #ifdef HAVE_LIBTRACEEVENT diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index 5acb62c2e00a..0c26303f7f63 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -172,8 +172,7 @@ int parse_events_add_tool(struct parse_events_state *pa= rse_state, int tool_event); int parse_events_add_cache(struct list_head *list, int *idx, const char *n= ame, struct parse_events_error *error, - struct list_head *head_config, - struct parse_events_state *parse_state); + struct list_head *head_config); int parse_events_add_breakpoint(struct list_head *list, int *idx, u64 addr, char *type, u64 len); int parse_events_add_pmu(struct parse_events_state *parse_state, diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y index f84fa1b132b3..cc7528558845 100644 --- a/tools/perf/util/parse-events.y +++ b/tools/perf/util/parse-events.y @@ -476,7 +476,7 @@ PE_LEGACY_CACHE opt_event_config =20 list =3D alloc_list(); ABORT_ON(!list); - err =3D parse_events_add_cache(list, &parse_state->idx, $1, error, $2, pa= rse_state); + err =3D parse_events_add_cache(list, &parse_state->idx, $1, error, $2); =20 parse_events_terms__delete($2); free($1); --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31C54C7618E for ; Wed, 26 Apr 2023 07:05:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239832AbjDZHFz (ORCPT ); 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Wed, 26 Apr 2023 00:03:59 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:32 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-23-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 22/40] perf print-events: Print legacy cache events for each PMU From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Mirroring parse_events_add_cache, list the legacy name alongside its alias with the PMU. Remove the now unnecessary hybrid logic. Signed-off-by: Ian Rogers --- tools/perf/util/parse-events.c | 2 +- tools/perf/util/parse-events.h | 1 + tools/perf/util/print-events.c | 85 ++++++++++++++++------------------ 3 files changed, 41 insertions(+), 47 deletions(-) diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index e007b2bc1ab4..ae421a5c9ddd 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -413,7 +413,7 @@ static int config_attr(struct perf_event_attr *attr, * contain hyphens and the longest name * should always be selected. */ -static int parse_events__decode_legacy_cache(const char *name, int pmu_typ= e, __u64 *config) +int parse_events__decode_legacy_cache(const char *name, int pmu_type, __u6= 4 *config) { int len, cache_type =3D -1, cache_op =3D -1, cache_result =3D -1; const char *name_end =3D &name[strlen(name) + 1]; diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index 0c26303f7f63..4e49be290209 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -173,6 +173,7 @@ int parse_events_add_tool(struct parse_events_state *pa= rse_state, int parse_events_add_cache(struct list_head *list, int *idx, const char *n= ame, struct parse_events_error *error, struct list_head *head_config); +int parse_events__decode_legacy_cache(const char *name, int pmu_type, __u6= 4 *config); int parse_events_add_breakpoint(struct list_head *list, int *idx, u64 addr, char *type, u64 len); int parse_events_add_pmu(struct parse_events_state *parse_state, diff --git a/tools/perf/util/print-events.c b/tools/perf/util/print-events.c index 93bbb868d400..d416c5484cd5 100644 --- a/tools/perf/util/print-events.c +++ b/tools/perf/util/print-events.c @@ -226,56 +226,49 @@ void print_sdt_events(const struct print_callbacks *p= rint_cb, void *print_state) =20 int print_hwcache_events(const struct print_callbacks *print_cb, void *pri= nt_state) { + struct perf_pmu *pmu =3D NULL; const char *event_type_descriptor =3D event_type_descriptors[PERF_TYPE_HW= _CACHE]; =20 - for (int type =3D 0; type < PERF_COUNT_HW_CACHE_MAX; type++) { - for (int op =3D 0; op < PERF_COUNT_HW_CACHE_OP_MAX; op++) { - /* skip invalid cache type */ - if (!evsel__is_cache_op_valid(type, op)) - continue; + while ((pmu =3D perf_pmu__scan(pmu)) !=3D NULL) { + /* + * Skip uncore PMUs for performance. Software PMUs can open + * PERF_TYPE_HW_CACHE, so skip. + */ + if (pmu->is_uncore || pmu->type =3D=3D PERF_TYPE_SOFTWARE) + continue; =20 - for (int res =3D 0; res < PERF_COUNT_HW_CACHE_RESULT_MAX; res++) { - struct perf_pmu *pmu =3D NULL; - char name[64]; - - __evsel__hw_cache_type_op_res_name(type, op, res, - name, sizeof(name)); - if (!perf_pmu__has_hybrid()) { - if (is_event_supported(PERF_TYPE_HW_CACHE, - type | (op << 8) | (res << 16))) { - print_cb->print_event(print_state, - "cache", - /*pmu_name=3D*/NULL, - name, - /*event_alias=3D*/NULL, - /*scale_unit=3D*/NULL, - /*deprecated=3D*/false, - event_type_descriptor, - /*desc=3D*/NULL, - /*long_desc=3D*/NULL, - /*encoding_desc=3D*/NULL); - } + for (int type =3D 0; type < PERF_COUNT_HW_CACHE_MAX; type++) { + for (int op =3D 0; op < PERF_COUNT_HW_CACHE_OP_MAX; op++) { + /* skip invalid cache type */ + if (!evsel__is_cache_op_valid(type, op)) continue; - } - perf_pmu__for_each_hybrid_pmu(pmu) { - if (is_event_supported(PERF_TYPE_HW_CACHE, - type | (op << 8) | (res << 16) | - ((__u64)pmu->type << PERF_PMU_TYPE_SHIFT))) { - char new_name[128]; - snprintf(new_name, sizeof(new_name), - "%s/%s/", pmu->name, name); - print_cb->print_event(print_state, - "cache", - pmu->name, - name, - new_name, - /*scale_unit=3D*/NULL, - /*deprecated=3D*/false, - event_type_descriptor, - /*desc=3D*/NULL, - /*long_desc=3D*/NULL, - /*encoding_desc=3D*/NULL); - } + + for (int res =3D 0; res < PERF_COUNT_HW_CACHE_RESULT_MAX; res++) { + char name[64]; + char alias_name[128]; + __u64 config; + int ret; + + __evsel__hw_cache_type_op_res_name(type, op, res, + name, sizeof(name)); + + ret =3D parse_events__decode_legacy_cache(name, pmu->type, + &config); + if (ret || !is_event_supported(PERF_TYPE_HW_CACHE, config)) + continue; + snprintf(alias_name, sizeof(alias_name), "%s/%s/", + pmu->name, name); + print_cb->print_event(print_state, + "cache", + pmu->name, + name, + alias_name, + /*scale_unit=3D*/NULL, + /*deprecated=3D*/false, + event_type_descriptor, + /*desc=3D*/NULL, + /*long_desc=3D*/NULL, + /*encoding_desc=3D*/NULL); } } } --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:40 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27B54C77B60 for ; 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Wed, 26 Apr 2023 00:04:09 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:33 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-24-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 23/40] perf parse-events: Support wildcards on raw events From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Legacy raw events like r1a open as PERF_TYPE_RAW on non-hybrid systems and on each hybrid PMU on hybrid systems. Rather than iterate hybrid PMUs add a perf_pmu__supports_wildcard_numeric function that says when a numeric event should be opened upon it. If the parsed event specifies the type of the PMU then don't wildcard match PMUs, use the specified PMU type. Signed-off-by: Ian Rogers --- tools/perf/util/parse-events.c | 43 ++++++++++++++++++++++++---------- tools/perf/util/parse-events.h | 3 ++- tools/perf/util/parse-events.y | 13 ++++++---- tools/perf/util/pmu.c | 5 ++++ tools/perf/util/pmu.h | 1 + 5 files changed, 47 insertions(+), 18 deletions(-) diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index ae421a5c9ddd..12b312935353 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -25,7 +25,6 @@ #include "util/parse-branch-options.h" #include "util/evsel_config.h" #include "util/event.h" -#include "util/parse-events-hybrid.h" #include "util/pmu-hybrid.h" #include "util/bpf-filter.h" #include "util/util.h" @@ -1449,15 +1448,14 @@ int parse_events_add_tracepoint(struct list_head *l= ist, int *idx, #endif } =20 -int parse_events_add_numeric(struct parse_events_state *parse_state, - struct list_head *list, - u32 type, u64 config, - struct list_head *head_config) +static int __parse_events_add_numeric(struct parse_events_state *parse_sta= te, + struct list_head *list, + u32 type, u64 config, + struct list_head *head_config) { struct perf_event_attr attr; LIST_HEAD(config_terms); const char *name, *metric_id; - bool hybrid; int ret; =20 memset(&attr, 0, sizeof(attr)); @@ -1475,19 +1473,38 @@ int parse_events_add_numeric(struct parse_events_st= ate *parse_state, =20 name =3D get_config_name(head_config); metric_id =3D get_config_metric_id(head_config); - ret =3D parse_events__add_numeric_hybrid(parse_state, list, &attr, - name, metric_id, - &config_terms, &hybrid); - if (hybrid) - goto out_free_terms; - ret =3D add_event(list, &parse_state->idx, &attr, name, metric_id, &config_terms); -out_free_terms: free_config_terms(&config_terms); return ret; } =20 +int parse_events_add_numeric(struct parse_events_state *parse_state, + struct list_head *list, + u32 type, u64 config, + struct list_head *head_config, + bool wildcard) +{ + struct perf_pmu *pmu =3D NULL; + bool found_supported =3D false; + + if (!wildcard) + return __parse_events_add_numeric(parse_state, list, type, config, head_= config); + + while ((pmu =3D perf_pmu__scan(pmu)) !=3D NULL) { + int ret; + + if (!perf_pmu__supports_wildcard_numeric(pmu)) + continue; + + found_supported =3D true; + ret =3D __parse_events_add_numeric(parse_state, list, pmu->type, config,= head_config); + if (ret) + return ret; + } + return found_supported ? 0 : -EINVAL; +} + int parse_events_add_tool(struct parse_events_state *parse_state, struct list_head *list, int tool_event) diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index 4e49be290209..831cd1ff4702 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -166,7 +166,8 @@ int parse_events_load_bpf_obj(struct parse_events_state= *parse_state, int parse_events_add_numeric(struct parse_events_state *parse_state, struct list_head *list, u32 type, u64 config, - struct list_head *head_config); + struct list_head *head_config, + bool wildcard); int parse_events_add_tool(struct parse_events_state *parse_state, struct list_head *list, int tool_event); diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y index cc7528558845..5055a29a448f 100644 --- a/tools/perf/util/parse-events.y +++ b/tools/perf/util/parse-events.y @@ -435,7 +435,8 @@ value_sym '/' event_config '/' =20 list =3D alloc_list(); ABORT_ON(!list); - err =3D parse_events_add_numeric(_parse_state, list, type, config, $3); + err =3D parse_events_add_numeric(_parse_state, list, type, config, $3, + /*wildcard=3D*/false); parse_events_terms__delete($3); if (err) { free_list_evsel(list); @@ -452,7 +453,9 @@ value_sym sep_slash_slash_dc =20 list =3D alloc_list(); ABORT_ON(!list); - ABORT_ON(parse_events_add_numeric(_parse_state, list, type, config, NULL)= ); + ABORT_ON(parse_events_add_numeric(_parse_state, list, type, config, + /*head_config=3D*/NULL, + /*wildcard=3D*/false)); $$ =3D list; } | @@ -596,7 +599,8 @@ PE_VALUE ':' PE_VALUE opt_event_config =20 list =3D alloc_list(); ABORT_ON(!list); - err =3D parse_events_add_numeric(_parse_state, list, (u32)$1, $3, $4); + err =3D parse_events_add_numeric(_parse_state, list, (u32)$1, $3, $4, + /*wildcard=3D*/false); parse_events_terms__delete($4); if (err) { free(list); @@ -618,7 +622,8 @@ PE_RAW opt_event_config num =3D strtoull($1 + 1, NULL, 16); ABORT_ON(errno); free($1); - err =3D parse_events_add_numeric(_parse_state, list, PERF_TYPE_RAW, num, = $2); + err =3D parse_events_add_numeric(_parse_state, list, PERF_TYPE_RAW, num, = $2, + /*wildcard=3D*/true); parse_events_terms__delete($2); if (err) { free(list); diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index 63071d876190..cd4247a379d4 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -1655,6 +1655,11 @@ bool perf_pmu__supports_legacy_cache(const struct pe= rf_pmu *pmu) return is_pmu_core(pmu->name) || perf_pmu__is_hybrid(pmu->name); } =20 +bool perf_pmu__supports_wildcard_numeric(const struct perf_pmu *pmu) +{ + return is_pmu_core(pmu->name) || perf_pmu__is_hybrid(pmu->name); +} + static bool pmu_alias_is_duplicate(struct sevent *alias_a, struct sevent *alias_b) { diff --git a/tools/perf/util/pmu.h b/tools/perf/util/pmu.h index 05702bc4bcf8..5a19536a5449 100644 --- a/tools/perf/util/pmu.h +++ b/tools/perf/util/pmu.h @@ -221,6 +221,7 @@ struct perf_pmu *perf_pmu__scan(struct perf_pmu *pmu); =20 bool is_pmu_core(const char *name); bool perf_pmu__supports_legacy_cache(const struct perf_pmu *pmu); +bool perf_pmu__supports_wildcard_numeric(const struct perf_pmu *pmu); void print_pmu_events(const struct print_callbacks *print_cb, void *print_= state); bool pmu_have_event(const char *pname, const char *name); =20 --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:40 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E14F9C77B60 for ; Wed, 26 Apr 2023 07:06:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239860AbjDZHGZ (ORCPT ); Wed, 26 Apr 2023 03:06:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40196 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239843AbjDZHF4 (ORCPT ); Wed, 26 Apr 2023 03:05:56 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2052E422C for ; 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charset="utf-8" The event parser no longer needs to recurse in case of a legacy cache event in a PMU, the necessary wild card logic has moved to perf_pmu__supports_legacy_cache and perf_pmu__supports_wildcard_numeric. Signed-off-by: Ian Rogers --- tools/perf/util/Build | 1 - tools/perf/util/parse-events-hybrid.c | 181 -------------------------- tools/perf/util/parse-events-hybrid.h | 18 --- tools/perf/util/parse-events.c | 74 ----------- tools/perf/util/parse-events.h | 8 -- 5 files changed, 282 deletions(-) delete mode 100644 tools/perf/util/parse-events-hybrid.c delete mode 100644 tools/perf/util/parse-events-hybrid.h diff --git a/tools/perf/util/Build b/tools/perf/util/Build index bd18fe5f2719..c146736ead19 100644 --- a/tools/perf/util/Build +++ b/tools/perf/util/Build @@ -24,7 +24,6 @@ perf-y +=3D llvm-utils.o perf-y +=3D mmap.o perf-y +=3D memswap.o perf-y +=3D parse-events.o -perf-y +=3D parse-events-hybrid.o perf-y +=3D print-events.o perf-y +=3D tracepoint.o perf-y +=3D perf_regs.o diff --git a/tools/perf/util/parse-events-hybrid.c b/tools/perf/util/parse-= events-hybrid.c deleted file mode 100644 index d2c0be051d46..000000000000 --- a/tools/perf/util/parse-events-hybrid.c +++ /dev/null @@ -1,181 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include -#include -#include -#include "evlist.h" -#include "evsel.h" -#include "parse-events.h" -#include "parse-events-hybrid.h" -#include "debug.h" -#include "pmu.h" -#include "pmu-hybrid.h" -#include "perf.h" - -static void config_hybrid_attr(struct perf_event_attr *attr, - int type, int pmu_type) -{ - /* - * attr.config layout for type PERF_TYPE_HARDWARE and - * PERF_TYPE_HW_CACHE - * - * PERF_TYPE_HARDWARE: 0xEEEEEEEE000000AA - * AA: hardware event ID - * EEEEEEEE: PMU type ID - * PERF_TYPE_HW_CACHE: 0xEEEEEEEE00DDCCBB - * BB: hardware cache ID - * CC: hardware cache op ID - * DD: hardware cache op result ID - * EEEEEEEE: PMU type ID - * If the PMU type ID is 0, the PERF_TYPE_RAW will be applied. - */ - attr->type =3D type; - attr->config =3D (attr->config & PERF_HW_EVENT_MASK) | - ((__u64)pmu_type << PERF_PMU_TYPE_SHIFT); -} - -static int create_event_hybrid(__u32 config_type, int *idx, - struct list_head *list, - struct perf_event_attr *attr, const char *name, - const char *metric_id, - struct list_head *config_terms, - struct perf_pmu *pmu) -{ - struct evsel *evsel; - __u32 type =3D attr->type; - __u64 config =3D attr->config; - - config_hybrid_attr(attr, config_type, pmu->type); - - /* - * Some hybrid hardware cache events are only available on one CPU - * PMU. For example, the 'L1-dcache-load-misses' is only available - * on cpu_core, while the 'L1-icache-loads' is only available on - * cpu_atom. We need to remove "not supported" hybrid cache events. - */ - if (attr->type =3D=3D PERF_TYPE_HW_CACHE - && !is_event_supported(attr->type, attr->config)) - return 0; - - evsel =3D parse_events__add_event_hybrid(list, idx, attr, name, metric_id, - pmu, config_terms); - if (evsel) { - evsel->pmu_name =3D strdup(pmu->name); - if (!evsel->pmu_name) - return -ENOMEM; - } else - return -ENOMEM; - attr->type =3D type; - attr->config =3D config; - return 0; -} - -static int pmu_cmp(struct parse_events_state *parse_state, - struct perf_pmu *pmu) -{ - if (parse_state->evlist && parse_state->evlist->hybrid_pmu_name) - return strcmp(parse_state->evlist->hybrid_pmu_name, pmu->name); - - if (parse_state->hybrid_pmu_name) - return strcmp(parse_state->hybrid_pmu_name, pmu->name); - - return 0; -} - -static int add_hw_hybrid(struct parse_events_state *parse_state, - struct list_head *list, struct perf_event_attr *attr, - const char *name, const char *metric_id, - struct list_head *config_terms) -{ - struct perf_pmu *pmu; - int ret; - - perf_pmu__for_each_hybrid_pmu(pmu) { - LIST_HEAD(terms); - - if (pmu_cmp(parse_state, pmu)) - continue; - - copy_config_terms(&terms, config_terms); - ret =3D create_event_hybrid(PERF_TYPE_HARDWARE, - &parse_state->idx, list, attr, name, - metric_id, &terms, pmu); - free_config_terms(&terms); - if (ret) - return ret; - } - - return 0; -} - -static int create_raw_event_hybrid(int *idx, struct list_head *list, - struct perf_event_attr *attr, - const char *name, - const char *metric_id, - struct list_head *config_terms, - struct perf_pmu *pmu) -{ - struct evsel *evsel; - - attr->type =3D pmu->type; - evsel =3D parse_events__add_event_hybrid(list, idx, attr, name, metric_id, - pmu, config_terms); - if (evsel) - evsel->pmu_name =3D strdup(pmu->name); - else - return -ENOMEM; - - return 0; -} - -static int add_raw_hybrid(struct parse_events_state *parse_state, - struct list_head *list, struct perf_event_attr *attr, - const char *name, const char *metric_id, - struct list_head *config_terms) -{ - struct perf_pmu *pmu; - int ret; - - perf_pmu__for_each_hybrid_pmu(pmu) { - LIST_HEAD(terms); - - if (pmu_cmp(parse_state, pmu)) - continue; - - copy_config_terms(&terms, config_terms); - ret =3D create_raw_event_hybrid(&parse_state->idx, list, attr, - name, metric_id, &terms, pmu); - free_config_terms(&terms); - if (ret) - return ret; - } - - return 0; -} - -int parse_events__add_numeric_hybrid(struct parse_events_state *parse_stat= e, - struct list_head *list, - struct perf_event_attr *attr, - const char *name, const char *metric_id, - struct list_head *config_terms, - bool *hybrid) -{ - *hybrid =3D false; - if (attr->type =3D=3D PERF_TYPE_SOFTWARE) - return 0; - - if (!perf_pmu__has_hybrid()) - return 0; - - *hybrid =3D true; - if (attr->type !=3D PERF_TYPE_RAW) { - return add_hw_hybrid(parse_state, list, attr, name, metric_id, - config_terms); - } - - return add_raw_hybrid(parse_state, list, attr, name, metric_id, - config_terms); -} diff --git a/tools/perf/util/parse-events-hybrid.h b/tools/perf/util/parse-= events-hybrid.h deleted file mode 100644 index bc2966e73897..000000000000 --- a/tools/perf/util/parse-events-hybrid.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __PERF_PARSE_EVENTS_HYBRID_H -#define __PERF_PARSE_EVENTS_HYBRID_H - -#include -#include -#include -#include -#include - -int parse_events__add_numeric_hybrid(struct parse_events_state *parse_stat= e, - struct list_head *list, - struct perf_event_attr *attr, - const char *name, const char *metric_id, - struct list_head *config_terms, - bool *hybrid); - -#endif /* __PERF_PARSE_EVENTS_HYBRID_H */ diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index 12b312935353..fad0dd4b86b2 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -25,7 +25,6 @@ #include "util/parse-branch-options.h" #include "util/evsel_config.h" #include "util/event.h" -#include "util/pmu-hybrid.h" #include "util/bpf-filter.h" #include "util/util.h" #include "tracepoint.h" @@ -39,9 +38,6 @@ extern int parse_events_debug; int parse_events_parse(void *parse_state, void *scanner); static int get_config_terms(struct list_head *head_config, struct list_head *head_terms __maybe_unused); -static int parse_events__with_hybrid_pmu(struct parse_events_state *parse_= state, - const char *str, char *pmu_name, - struct list_head *list); =20 struct event_symbol event_symbols_hw[PERF_COUNT_HW_MAX] =3D { [PERF_COUNT_HW_CPU_CYCLES] =3D { @@ -1524,33 +1520,6 @@ static bool config_term_percore(struct list_head *co= nfig_terms) return false; } =20 -static int parse_events__inside_hybrid_pmu(struct parse_events_state *pars= e_state, - struct list_head *list, char *name, - struct list_head *head_config) -{ - struct parse_events_term *term; - int ret =3D -1; - - if (parse_state->fake_pmu || !head_config || list_empty(head_config) || - !perf_pmu__is_hybrid(name)) { - return -1; - } - - /* - * More than one term in list. - */ - if (head_config->next && head_config->next->next !=3D head_config) - return -1; - - term =3D list_first_entry(head_config, struct parse_events_term, list); - if (term && term->config && strcmp(term->config, "event")) { - ret =3D parse_events__with_hybrid_pmu(parse_state, term->config, - name, list); - } - - return ret; -} - int parse_events_add_pmu(struct parse_events_state *parse_state, struct list_head *list, char *name, struct list_head *head_config, @@ -1645,11 +1614,6 @@ int parse_events_add_pmu(struct parse_events_state *= parse_state, if (pmu->default_config && get_config_chgs(pmu, head_config, &config_term= s)) return -ENOMEM; =20 - if (!parse_events__inside_hybrid_pmu(parse_state, list, name, - head_config)) { - return 0; - } - if (!parse_state->fake_pmu && perf_pmu__config(pmu, &attr, head_config, p= arse_state->error)) { free_config_terms(&config_terms); return -EINVAL; @@ -2027,32 +1991,6 @@ int parse_events_terms(struct list_head *terms, cons= t char *str) return ret; } =20 -static int parse_events__with_hybrid_pmu(struct parse_events_state *parse_= state, - const char *str, char *pmu_name, - struct list_head *list) -{ - struct parse_events_state ps =3D { - .list =3D LIST_HEAD_INIT(ps.list), - .stoken =3D PE_START_EVENTS, - .hybrid_pmu_name =3D pmu_name, - .idx =3D parse_state->idx, - }; - int ret; - - ret =3D parse_events__scanner(str, &ps); - - if (!ret) { - if (!list_empty(&ps.list)) { - list_splice(&ps.list, list); - parse_state->idx =3D ps.idx; - return 0; - } else - return -1; - } - - return ret; -} - __weak int arch_evlist__cmp(const struct evsel *lhs, const struct evsel *r= hs) { /* Order by insertion index. */ @@ -2776,15 +2714,3 @@ char *parse_events_formats_error_string(char *additi= onal_terms) fail: return NULL; } - -struct evsel *parse_events__add_event_hybrid(struct list_head *list, int *= idx, - struct perf_event_attr *attr, - const char *name, - const char *metric_id, - struct perf_pmu *pmu, - struct list_head *config_terms) -{ - return __add_event(list, idx, attr, /*init_attr=3D*/true, name, metric_id, - pmu, config_terms, /*auto_merge_stats=3D*/false, - /*cpu_list=3D*/NULL); -} diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index 831cd1ff4702..77b8f7efdb94 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -122,7 +122,6 @@ struct parse_events_state { struct list_head *terms; int stoken; struct perf_pmu *fake_pmu; - char *hybrid_pmu_name; /* Should PE_LEGACY_NAME tokens be generated for config terms? */ bool match_legacy_cache_terms; bool wild_card_pmus; @@ -235,11 +234,4 @@ static inline bool is_sdt_event(char *str __maybe_unus= ed) } #endif /* HAVE_LIBELF_SUPPORT */ =20 -struct evsel *parse_events__add_event_hybrid(struct list_head *list, int *= idx, - struct perf_event_attr *attr, - const char *name, - const char *metric_id, - struct perf_pmu *pmu, - struct list_head *config_terms); - #endif /* __PERF_PARSE_EVENTS_H */ --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:40 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D90B2C77B78 for ; Wed, 26 Apr 2023 07:06:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239917AbjDZHGl (ORCPT ); Wed, 26 Apr 2023 03:06:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40264 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239877AbjDZHGG (ORCPT ); Wed, 26 Apr 2023 03:06:06 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 372AC49C5 for ; Wed, 26 Apr 2023 00:04:50 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-b92309d84c1so33258364276.1 for ; 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Wed, 26 Apr 2023 00:04:31 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:35 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-26-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 25/40] perf parse-events: Minor type safety cleanup From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use the typed parse_state rather than void* _parse_state when available. Signed-off-by: Ian Rogers --- tools/perf/util/parse-events.y | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y index 5055a29a448f..e709508b1d6e 100644 --- a/tools/perf/util/parse-events.y +++ b/tools/perf/util/parse-events.y @@ -301,7 +301,7 @@ PE_NAME opt_pmu_config if (!list) CLEANUP_YYABORT; /* Attempt to add to list assuming $1 is a PMU name. */ - if (parse_events_add_pmu(_parse_state, list, $1, $2, /*auto_merge_stats= =3D*/false)) { + if (parse_events_add_pmu(parse_state, list, $1, $2, /*auto_merge_stats=3D= */false)) { struct perf_pmu *pmu =3D NULL; int ok =3D 0; =20 @@ -319,7 +319,7 @@ PE_NAME opt_pmu_config !perf_pmu__match(pattern, pmu->alias_name, $1)) { if (parse_events_copy_term_list(orig_terms, &terms)) CLEANUP_YYABORT; - if (!parse_events_add_pmu(_parse_state, list, pmu->name, terms, + if (!parse_events_add_pmu(parse_state, list, pmu->name, terms, /*auto_merge_stats=3D*/true)) { ok++; parse_state->wild_card_pmus =3D true; @@ -331,7 +331,7 @@ PE_NAME opt_pmu_config if (!ok) { /* Failure to add, assume $1 is an event name. */ zfree(&list); - ok =3D !parse_events_multi_pmu_add(_parse_state, $1, $2, &list); + ok =3D !parse_events_multi_pmu_add(parse_state, $1, $2, &list); $2 =3D NULL; } if (!ok) --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:40 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D0FDC77B78 for ; Wed, 26 Apr 2023 07:06:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239563AbjDZHGs (ORCPT ); Wed, 26 Apr 2023 03:06:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40118 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239903AbjDZHGK (ORCPT ); Wed, 26 Apr 2023 03:06:10 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D306B3AAD for ; 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charset="utf-8" To support the cputype argument added to "perf stat" for hybrid it is necessary to filter events during wildcard matching. Add a scanner argument for the filter and checking it when wildcard matching. Signed-off-by: Ian Rogers --- tools/perf/builtin-record.c | 13 +++++++-- tools/perf/builtin-stat.c | 10 +++++-- tools/perf/builtin-top.c | 5 +++- tools/perf/builtin-trace.c | 5 +++- tools/perf/tests/parse-events.c | 3 +- tools/perf/tests/pmu-events.c | 3 +- tools/perf/util/evlist.h | 1 - tools/perf/util/metricgroup.c | 4 +-- tools/perf/util/parse-events.c | 51 ++++++++++++++++++++++++--------- tools/perf/util/parse-events.h | 21 ++++++++++---- tools/perf/util/parse-events.y | 6 ++-- 11 files changed, 90 insertions(+), 32 deletions(-) diff --git a/tools/perf/builtin-record.c b/tools/perf/builtin-record.c index 7b7e74a56346..7e4490dfc0b5 100644 --- a/tools/perf/builtin-record.c +++ b/tools/perf/builtin-record.c @@ -3335,6 +3335,14 @@ const char record_callchain_help[] =3D CALLCHAIN_REC= ORD_HELP =20 static bool dry_run; =20 +static struct parse_events_option_args parse_events_option_args =3D { + .evlistp =3D &record.evlist, +}; + +static struct parse_events_option_args switch_output_parse_events_option_a= rgs =3D { + .evlistp =3D &record.sb_evlist, +}; + /* * XXX Will stay a global variable till we fix builtin-script.c to stop me= ssing * with it and switch to use the library functions in perf_evlist that came @@ -3343,7 +3351,7 @@ static bool dry_run; * using pipes, etc. */ static struct option __record_options[] =3D { - OPT_CALLBACK('e', "event", &record.evlist, "event", + OPT_CALLBACK('e', "event", &parse_events_option_args, "event", "event selector. use 'perf list' to list available events", parse_events_option), OPT_CALLBACK(0, "filter", &record.evlist, "filter", @@ -3496,7 +3504,8 @@ static struct option __record_options[] =3D { &record.switch_output.set, "signal or size[BKMG] or time[smhd]", "Switch output when receiving SIGUSR2 (signal) or cross a size or tim= e threshold", "signal"), - OPT_CALLBACK_SET(0, "switch-output-event", &record.sb_evlist, &record.swi= tch_output_event_set, "switch output event", + OPT_CALLBACK_SET(0, "switch-output-event", &switch_output_parse_events_op= tion_args, + &record.switch_output_event_set, "switch output event", "switch output event selector. use 'perf list' to list available event= s", parse_events_option_new_evlist), OPT_INTEGER(0, "switch-max-files", &record.switch_output.num_files, diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index eb34f5418ad3..46210fa3f14b 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -101,6 +101,10 @@ static void print_counters(struct timespec *ts, int argc, const char **arg= v); =20 static struct evlist *evsel_list; +static struct parse_events_option_args parse_events_option_args =3D { + .evlistp =3D &evsel_list, +}; + static bool all_counters_use_bpf =3D true; =20 static struct target target =3D { @@ -1096,8 +1100,8 @@ static int parse_hybrid_type(const struct option *opt, return -1; } =20 - evlist->hybrid_pmu_name =3D perf_pmu__hybrid_type_to_pmu(str); - if (!evlist->hybrid_pmu_name) { + parse_events_option_args.pmu_filter =3D perf_pmu__hybrid_type_to_pmu(str); + if (!parse_events_option_args.pmu_filter) { fprintf(stderr, "--cputype %s is not supported!\n", str); return -1; } @@ -1108,7 +1112,7 @@ static int parse_hybrid_type(const struct option *opt, static struct option stat_options[] =3D { OPT_BOOLEAN('T', "transaction", &transaction_run, "hardware transaction statistics"), - OPT_CALLBACK('e', "event", &evsel_list, "event", + OPT_CALLBACK('e', "event", &parse_events_option_args, "event", "event selector. use 'perf list' to list available events", parse_events_option), OPT_CALLBACK(0, "filter", &evsel_list, "filter", diff --git a/tools/perf/builtin-top.c b/tools/perf/builtin-top.c index eb5740154bc0..48ee49e95c5e 100644 --- a/tools/perf/builtin-top.c +++ b/tools/perf/builtin-top.c @@ -1440,12 +1440,15 @@ int cmd_top(int argc, const char **argv) .max_stack =3D sysctl__max_stack(), .nr_threads_synthesize =3D UINT_MAX, }; + struct parse_events_option_args parse_events_option_args =3D { + .evlistp =3D &top.evlist, + }; bool branch_call_mode =3D false; struct record_opts *opts =3D &top.record_opts; struct target *target =3D &opts->target; const char *disassembler_style =3D NULL, *objdump_path =3D NULL, *addr2li= ne_path =3D NULL; const struct option options[] =3D { - OPT_CALLBACK('e', "event", &top.evlist, "event", + OPT_CALLBACK('e', "event", &parse_events_option_args, "event", "event selector. use 'perf list' to list available events", parse_events_option), OPT_U64('c', "count", &opts->user_interval, "event period to sample"), diff --git a/tools/perf/builtin-trace.c b/tools/perf/builtin-trace.c index 8ee3a45c3c54..b49d3abb1203 100644 --- a/tools/perf/builtin-trace.c +++ b/tools/perf/builtin-trace.c @@ -4591,8 +4591,11 @@ static int trace__parse_events_option(const struct o= ption *opt, const char *str, err =3D 0; =20 if (lists[0]) { + struct parse_events_option_args parse_events_option_args =3D { + .evlistp =3D &trace->evlist, + }; struct option o =3D { - .value =3D &trace->evlist, + .value =3D &parse_events_option_args, }; err =3D parse_events_option(&o, lists[0], 0); } diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index 6aea51e33dc0..0b8ec9b1034f 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -1938,7 +1938,8 @@ static int test_event_fake_pmu(const char *str) return -ENOMEM; =20 parse_events_error__init(&err); - ret =3D __parse_events(evlist, str, &err, &perf_pmu__fake, /*warn_if_reor= dered=3D*/true); + ret =3D __parse_events(evlist, str, /*pmu_filter=3D*/NULL, &err, + &perf_pmu__fake, /*warn_if_reordered=3D*/true); if (ret) { pr_debug("failed to parse event '%s', err %d, str '%s'\n", str, ret, err.str); diff --git a/tools/perf/tests/pmu-events.c b/tools/perf/tests/pmu-events.c index a2cde61b1c77..734004f1a37d 100644 --- a/tools/perf/tests/pmu-events.c +++ b/tools/perf/tests/pmu-events.c @@ -776,7 +776,8 @@ static int check_parse_id(const char *id, struct parse_= events_error *error, for (cur =3D strchr(dup, '@') ; cur; cur =3D strchr(++cur, '@')) *cur =3D '/'; =20 - ret =3D __parse_events(evlist, dup, error, fake_pmu, /*warn_if_reordered= =3D*/true); + ret =3D __parse_events(evlist, dup, /*pmu_filter=3D*/NULL, error, fake_pm= u, + /*warn_if_reordered=3D*/true); free(dup); =20 evlist__delete(evlist); diff --git a/tools/perf/util/evlist.h b/tools/perf/util/evlist.h index 46cf402add93..e7e5540cc970 100644 --- a/tools/perf/util/evlist.h +++ b/tools/perf/util/evlist.h @@ -67,7 +67,6 @@ struct evlist { struct evsel *selected; struct events_stats stats; struct perf_env *env; - const char *hybrid_pmu_name; void (*trace_event_sample_raw)(struct evlist *evlist, union perf_event *event, struct perf_sample *sample); diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index 4b9a16291b96..46fc31cff124 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -1441,8 +1441,8 @@ static int parse_ids(bool metric_no_merge, struct per= f_pmu *fake_pmu, } pr_debug("Parsing metric events '%s'\n", events.buf); parse_events_error__init(&parse_error); - ret =3D __parse_events(parsed_evlist, events.buf, &parse_error, fake_pmu, - /*warn_if_reordered=3D*/false); + ret =3D __parse_events(parsed_evlist, events.buf, /*pmu_filter=3D*/NULL, + &parse_error, fake_pmu, /*warn_if_reordered=3D*/false); if (ret) { parse_events_error__print(&parse_error, events.buf); goto err_out; diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index fad0dd4b86b2..29fa84c4cdd4 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -464,8 +464,24 @@ int parse_events__decode_legacy_cache(const char *name= , int pmu_type, __u64 *con return 0; } =20 +/** + * parse_events__filter_pmu - returns false if a wildcard PMU should be + * considered, true if it should be filtered. + */ +bool parse_events__filter_pmu(const struct parse_events_state *parse_state, + const struct perf_pmu *pmu) +{ + if (parse_state->pmu_filter =3D=3D NULL) + return false; + + if (pmu->name =3D=3D NULL) + return true; + + return strcmp(parse_state->pmu_filter, pmu->name) !=3D 0; +} + int parse_events_add_cache(struct list_head *list, int *idx, const char *n= ame, - struct parse_events_error *err, + struct parse_events_state *parse_state, struct list_head *head_config) { struct perf_pmu *pmu =3D NULL; @@ -485,6 +501,9 @@ int parse_events_add_cache(struct list_head *list, int = *idx, const char *name, if (pmu->is_uncore || pmu->type =3D=3D PERF_TYPE_SOFTWARE) continue; =20 + if (parse_events__filter_pmu(parse_state, pmu)) + continue; + memset(&attr, 0, sizeof(attr)); attr.type =3D PERF_TYPE_HW_CACHE; =20 @@ -498,8 +517,7 @@ int parse_events_add_cache(struct list_head *list, int = *idx, const char *name, found_supported =3D true; =20 if (head_config) { - if (config_attr(&attr, head_config, err, - config_term_common)) + if (config_attr(&attr, head_config, parse_state->error, config_term_com= mon)) return -EINVAL; =20 if (get_config_terms(head_config, &config_terms)) @@ -1493,6 +1511,9 @@ int parse_events_add_numeric(struct parse_events_stat= e *parse_state, if (!perf_pmu__supports_wildcard_numeric(pmu)) continue; =20 + if (parse_events__filter_pmu(parse_state, pmu)) + continue; + found_supported =3D true; ret =3D __parse_events_add_numeric(parse_state, list, pmu->type, config,= head_config); if (ret) @@ -1686,6 +1707,9 @@ int parse_events_multi_pmu_add(struct parse_events_st= ate *parse_state, while ((pmu =3D perf_pmu__scan(pmu)) !=3D NULL) { struct perf_pmu_alias *alias; =20 + if (parse_events__filter_pmu(parse_state, pmu)) + continue; + list_for_each_entry(alias, &pmu->aliases, list) { if (!strcasecmp(alias->name, str)) { parse_events_copy_term_list(head, &orig_head); @@ -2118,7 +2142,7 @@ static bool parse_events__sort_events_and_fix_groups(= struct list_head *list) return idx_changed || num_leaders !=3D orig_num_leaders; } =20 -int __parse_events(struct evlist *evlist, const char *str, +int __parse_events(struct evlist *evlist, const char *str, const char *pmu= _filter, struct parse_events_error *err, struct perf_pmu *fake_pmu, bool warn_if_reordered) { @@ -2129,6 +2153,7 @@ int __parse_events(struct evlist *evlist, const char = *str, .evlist =3D evlist, .stoken =3D PE_START_EVENTS, .fake_pmu =3D fake_pmu, + .pmu_filter =3D pmu_filter, .match_legacy_cache_terms =3D true, }; int ret; @@ -2310,12 +2335,13 @@ void parse_events_error__print(struct parse_events_= error *err, int parse_events_option(const struct option *opt, const char *str, int unset __maybe_unused) { - struct evlist *evlist =3D *(struct evlist **)opt->value; + struct parse_events_option_args *args =3D opt->value; struct parse_events_error err; int ret; =20 parse_events_error__init(&err); - ret =3D parse_events(evlist, str, &err); + ret =3D __parse_events(*args->evlistp, str, args->pmu_filter, &err, + /*fake_pmu=3D*/NULL, /*warn_if_reordered=3D*/true); =20 if (ret) { parse_events_error__print(&err, str); @@ -2328,22 +2354,21 @@ int parse_events_option(const struct option *opt, c= onst char *str, =20 int parse_events_option_new_evlist(const struct option *opt, const char *s= tr, int unset) { - struct evlist **evlistp =3D opt->value; + struct parse_events_option_args *args =3D opt->value; int ret; =20 - if (*evlistp =3D=3D NULL) { - *evlistp =3D evlist__new(); + if (*args->evlistp =3D=3D NULL) { + *args->evlistp =3D evlist__new(); =20 - if (*evlistp =3D=3D NULL) { + if (*args->evlistp =3D=3D NULL) { fprintf(stderr, "Not enough memory to create evlist\n"); return -1; } } - ret =3D parse_events_option(opt, str, unset); if (ret) { - evlist__delete(*evlistp); - *evlistp =3D NULL; + evlist__delete(*args->evlistp); + *args->evlistp =3D NULL; } =20 return ret; diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index 77b8f7efdb94..d4cbda6e946a 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -22,17 +22,24 @@ bool is_event_supported(u8 type, u64 config); =20 const char *event_type(int type); =20 +/* Arguments encoded in opt->value. */ +struct parse_events_option_args { + struct evlist **evlistp; + const char *pmu_filter; +}; int parse_events_option(const struct option *opt, const char *str, int uns= et); int parse_events_option_new_evlist(const struct option *opt, const char *s= tr, int unset); -__attribute__((nonnull(1, 2, 3))) -int __parse_events(struct evlist *evlist, const char *str, struct parse_ev= ents_error *error, - struct perf_pmu *fake_pmu, bool warn_if_reordered); +__attribute__((nonnull(1, 2, 4))) +int __parse_events(struct evlist *evlist, const char *str, const char *pmu= _filter, + struct parse_events_error *error, struct perf_pmu *fake_pmu, + bool warn_if_reordered); =20 __attribute__((nonnull(1, 2, 3))) static inline int parse_events(struct evlist *evlist, const char *str, struct parse_events_error *err) { - return __parse_events(evlist, str, err, /*fake_pmu=3D*/NULL, /*warn_if_re= ordered=3D*/true); + return __parse_events(evlist, str, /*pmu_filter=3D*/NULL, err, /*fake_pmu= =3D*/NULL, + /*warn_if_reordered=3D*/true); } =20 int parse_event(struct evlist *evlist, const char *str); @@ -122,11 +129,15 @@ struct parse_events_state { struct list_head *terms; int stoken; struct perf_pmu *fake_pmu; + /* If non-null, when wildcard matching only match the given PMU. */ + const char *pmu_filter; /* Should PE_LEGACY_NAME tokens be generated for config terms? */ bool match_legacy_cache_terms; bool wild_card_pmus; }; =20 +bool parse_events__filter_pmu(const struct parse_events_state *parse_state, + const struct perf_pmu *pmu); void parse_events__shrink_config_terms(void); int parse_events__is_hardcoded_term(struct parse_events_term *term); int parse_events_term__num(struct parse_events_term **term, @@ -171,7 +182,7 @@ int parse_events_add_tool(struct parse_events_state *pa= rse_state, struct list_head *list, int tool_event); int parse_events_add_cache(struct list_head *list, int *idx, const char *n= ame, - struct parse_events_error *error, + struct parse_events_state *parse_state, struct list_head *head_config); int parse_events__decode_legacy_cache(const char *name, int pmu_type, __u6= 4 *config); int parse_events_add_breakpoint(struct list_head *list, int *idx, diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y index e709508b1d6e..c95877cbd6cf 100644 --- a/tools/perf/util/parse-events.y +++ b/tools/perf/util/parse-events.y @@ -312,6 +312,9 @@ PE_NAME opt_pmu_config while ((pmu =3D perf_pmu__scan(pmu)) !=3D NULL) { char *name =3D pmu->name; =20 + if (parse_events__filter_pmu(parse_state, pmu)) + continue; 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Wed, 26 Apr 2023 00:04:48 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:37 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-28-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 27/40] perf stat: Make cputype filter generic From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rather than limit the --cputype argument for "perf list" and "perf stat" to hybrid PMUs of just cpu_atom and cpu_core, allow any PMU. Note, that if cpu_atom isn't mounted but a filter of cpu_atom is requested, then this will now fail. As such a filter would never succeed, no events can come from that unmounted PMU, then this behavior could never have been useful and failing is clearer. Signed-off-by: Ian Rogers --- tools/perf/builtin-list.c | 19 +++++++++++-------- tools/perf/builtin-stat.c | 12 +++++++----- tools/perf/util/pmu-hybrid.c | 20 -------------------- tools/perf/util/pmu-hybrid.h | 1 - tools/perf/util/pmus.c | 25 ++++++++++++++++++++++++- tools/perf/util/pmus.h | 3 +++ 6 files changed, 45 insertions(+), 35 deletions(-) diff --git a/tools/perf/builtin-list.c b/tools/perf/builtin-list.c index 1f5dbd5f0ba4..1b48cf214b6e 100644 --- a/tools/perf/builtin-list.c +++ b/tools/perf/builtin-list.c @@ -11,8 +11,8 @@ #include "builtin.h" =20 #include "util/print-events.h" +#include "util/pmus.h" #include "util/pmu.h" -#include "util/pmu-hybrid.h" #include "util/debug.h" #include "util/metricgroup.h" #include "util/string2.h" @@ -429,7 +429,7 @@ int cmd_list(int argc, const char **argv) .print_event =3D default_print_event, .print_metric =3D default_print_metric, }; - const char *hybrid_name =3D NULL; + const char *cputype =3D NULL; const char *unit_name =3D NULL; bool json =3D false; struct option list_options[] =3D { @@ -443,8 +443,8 @@ int cmd_list(int argc, const char **argv) "Print information on the perf event names and expressions used int= ernally by events."), OPT_BOOLEAN(0, "deprecated", &default_ps.deprecated, "Print deprecated events."), - OPT_STRING(0, "cputype", &hybrid_name, "hybrid cpu type", - "Limit PMU or metric printing to the given hybrid PMU (e.g. core or = atom)."), + OPT_STRING(0, "cputype", &cputype, "cpu type", + "Limit PMU or metric printing to the given PMU (e.g. cpu, core or at= om)."), OPT_STRING(0, "unit", &unit_name, "PMU name", "Limit PMU or metric printing to the specified PMU."), OPT_INCR(0, "debug", &verbose, @@ -484,10 +484,13 @@ int cmd_list(int argc, const char **argv) assert(default_ps.visited_metrics); if (unit_name) default_ps.pmu_glob =3D strdup(unit_name); - else if (hybrid_name) { - default_ps.pmu_glob =3D perf_pmu__hybrid_type_to_pmu(hybrid_name); - if (!default_ps.pmu_glob) - pr_warning("WARNING: hybrid cputype is not supported!\n"); + else if (cputype) { + const struct perf_pmu *pmu =3D perf_pmus__pmu_for_pmu_filter(cputype); + + if (!pmu) + pr_warning("WARNING: cputype is not supported!\n"); + + default_ps.pmu_glob =3D pmu->name; } } print_cb.print_start(ps); diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index 46210fa3f14b..e2119ffd08de 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -44,6 +44,7 @@ #include "util/cgroup.h" #include #include "util/parse-events.h" +#include "util/pmus.h" #include "util/pmu.h" #include "util/event.h" #include "util/evlist.h" @@ -69,7 +70,6 @@ #include "util/pfm.h" #include "util/bpf_counter.h" #include "util/iostat.h" -#include "util/pmu-hybrid.h" #include "util/util.h" #include "asm/bug.h" =20 @@ -1089,10 +1089,11 @@ static int parse_stat_cgroups(const struct option *= opt, return parse_cgroups(opt, str, unset); } =20 -static int parse_hybrid_type(const struct option *opt, +static int parse_cputype(const struct option *opt, const char *str, int unset __maybe_unused) { + const struct perf_pmu *pmu; struct evlist *evlist =3D *(struct evlist **)opt->value; =20 if (!list_empty(&evlist->core.entries)) { @@ -1100,11 +1101,12 @@ static int parse_hybrid_type(const struct option *o= pt, return -1; } =20 - parse_events_option_args.pmu_filter =3D perf_pmu__hybrid_type_to_pmu(str); - if (!parse_events_option_args.pmu_filter) { + pmu =3D perf_pmus__pmu_for_pmu_filter(str); + if (!pmu) { fprintf(stderr, "--cputype %s is not supported!\n", str); return -1; } + parse_events_option_args.pmu_filter =3D pmu->name; =20 return 0; } @@ -1230,7 +1232,7 @@ static struct option stat_options[] =3D { OPT_CALLBACK(0, "cputype", &evsel_list, "hybrid cpu type", "Only enable events on applying cpu with this type " "for hybrid platform (e.g. core or atom)", - parse_hybrid_type), + parse_cputype), #ifdef HAVE_LIBPFM OPT_CALLBACK(0, "pfm-events", &evsel_list, "event", "libpfm4 event selector. use 'perf list' to list available events", diff --git a/tools/perf/util/pmu-hybrid.c b/tools/perf/util/pmu-hybrid.c index 38628805a952..bc4cb0738c35 100644 --- a/tools/perf/util/pmu-hybrid.c +++ b/tools/perf/util/pmu-hybrid.c @@ -50,23 +50,3 @@ bool perf_pmu__is_hybrid(const char *name) { return perf_pmu__find_hybrid_pmu(name) !=3D NULL; } - -char *perf_pmu__hybrid_type_to_pmu(const char *type) -{ - char *pmu_name =3D NULL; - - if (asprintf(&pmu_name, "cpu_%s", type) < 0) - return NULL; - - if (perf_pmu__is_hybrid(pmu_name)) - return pmu_name; - - /* - * pmu may be not scanned, check the sysfs. - */ - if (perf_pmu__hybrid_mounted(pmu_name)) - return pmu_name; - - free(pmu_name); - return NULL; -} diff --git a/tools/perf/util/pmu-hybrid.h b/tools/perf/util/pmu-hybrid.h index 2b186c26a43e..206b94931531 100644 --- a/tools/perf/util/pmu-hybrid.h +++ b/tools/perf/util/pmu-hybrid.h @@ -17,7 +17,6 @@ bool perf_pmu__hybrid_mounted(const char *name); =20 struct perf_pmu *perf_pmu__find_hybrid_pmu(const char *name); bool perf_pmu__is_hybrid(const char *name); -char *perf_pmu__hybrid_type_to_pmu(const char *type); =20 static inline int perf_pmu__hybrid_pmu_num(void) { diff --git a/tools/perf/util/pmus.c b/tools/perf/util/pmus.c index 7f3b93c4d229..140e11f00b29 100644 --- a/tools/perf/util/pmus.c +++ b/tools/perf/util/pmus.c @@ -1,5 +1,28 @@ // SPDX-License-Identifier: GPL-2.0 #include -#include +#include +#include "pmus.h" +#include "pmu.h" =20 LIST_HEAD(pmus); + +const struct perf_pmu *perf_pmus__pmu_for_pmu_filter(const char *str) +{ + struct perf_pmu *pmu =3D NULL; + + while ((pmu =3D perf_pmu__scan(pmu)) !=3D NULL) { + if (!strcmp(pmu->name, str)) + return pmu; + /* Ignore "uncore_" prefix. */ + if (!strncmp(pmu->name, "uncore_", 7)) { + if (!strcmp(pmu->name + 7, str)) + return pmu; + } + /* Ignore "cpu_" prefix on Intel hybrid PMUs. */ + if (!strncmp(pmu->name, "cpu_", 4)) { + if (!strcmp(pmu->name + 4, str)) + return pmu; + } + } + return NULL; +} diff --git a/tools/perf/util/pmus.h b/tools/perf/util/pmus.h index 5ec12007eb5c..d475e2960c10 100644 --- a/tools/perf/util/pmus.h +++ b/tools/perf/util/pmus.h @@ -3,7 +3,10 @@ #define __PMUS_H =20 extern struct list_head pmus; +struct perf_pmu; =20 #define perf_pmus__for_each_pmu(pmu) list_for_each_entry(pmu, &pmus, list) =20 +const struct perf_pmu *perf_pmus__pmu_for_pmu_filter(const char *str); + #endif /* __PMUS_H */ --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:40 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06E63C77B60 for ; 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Wed, 26 Apr 2023 00:04:56 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:38 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-29-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 28/40] perf test: Add cputype testing to perf stat From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Check a bogus PMU fails and that a known PMU succeeds. Limit to PMUs known cpu, cpu_atom and armv8_pmuv3_0 ones. Signed-off-by: Ian Rogers --- tools/perf/tests/shell/stat.sh | 44 ++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/tools/perf/tests/shell/stat.sh b/tools/perf/tests/shell/stat.sh index 2c1d3f704995..fe1283ca39d1 100755 --- a/tools/perf/tests/shell/stat.sh +++ b/tools/perf/tests/shell/stat.sh @@ -91,9 +91,53 @@ test_topdown_weak_groups() { echo "Topdown weak groups test [Success]" } =20 +test_cputype() { + # Test --cputype argument. + echo "cputype test" + + # Bogus PMU should fail. + if perf stat --cputype=3D"123" -e instructions true > /dev/null 2>&1 + then + echo "cputype test [Bogus PMU didn't fail]" + err=3D1 + return + fi + + # Find a known PMU for cputype. + pmu=3D"" + for i in cpu cpu_atom armv8_pmuv3_0 + do + if test -d "/sys/devices/$i" + then + pmu=3D"$i" + break + fi + if perf stat -e "$i/instructions/" true > /dev/null 2>&1 + then + pmu=3D"$i" + break + fi + done + if test "x$pmu" =3D "x" + then + echo "cputype test [Skipped known PMU not found]" + return + fi + + # Test running with cputype produces output. + if ! perf stat --cputype=3D"$pmu" -e instructions true 2>&1 | grep -E -q= "instructions" + then + echo "cputype test [Failed count missed with given filter]" + err=3D1 + return + fi + echo "cputype test [Success]" +} + test_default_stat test_stat_record_report test_stat_repeat_weak_groups test_topdown_groups test_topdown_weak_groups +test_cputype exit $err --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:40 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0867C77B7C for ; Wed, 26 Apr 2023 07:07:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239637AbjDZHHR (ORCPT ); Wed, 26 Apr 2023 03:07:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40246 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239499AbjDZHG1 (ORCPT ); Wed, 26 Apr 2023 03:06:27 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 11EF344A4 for ; Wed, 26 Apr 2023 00:05:18 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-b92309d84c1so33260967276.1 for ; Wed, 26 Apr 2023 00:05:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1682492704; x=1685084704; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=/DyyFJ8rDDuRlbHILxuq/n1XyL8kZC4XVBz7gkkjj0g=; b=yD7jcbQ7BtJ9heAatlDomgW6pBoRf4c4a9IxQn1R9HmjAX+cV5hEbzt2ooIiX933nq C44kx9wOeM9NxV2mVcIewNEqf/cx42oRK4BX4A8b6LrOh1eteLLhyImuR0QVuOG2lAmz U9Cs04OMS8eN0amzclZoRNgD4Sqx9d9RCP6ZGFp8Joj7r86drbAkz5p8OW7G2nTHASb+ cZt4nUOEV3icNO8QusxaknZtcQAzHLzF/ialPZ0NgqYGjRKtMTl/v+r0PNo1rOA+09Tn L68Pm6MOh03BFa6Yxlj6vMt1IrSCxQm1Z6nnWlpPHd3vNPiSedEHLWKCSjcVJCZhLw1o tSvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682492704; x=1685084704; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=/DyyFJ8rDDuRlbHILxuq/n1XyL8kZC4XVBz7gkkjj0g=; b=iavb/efj8a2Zy7b37JYVCkZujfE50ruRdOVdBGDxWbvMqPcVBQY2mA2qBuexpvzaJ2 df7va47HOIiTsRBtWn0sKRO8+95Ihd8nhdlYrSfPRjXv1OCBZv/SYJc802GW4r4vofEb qEre4wI6neJ30C7gcrb/JvlBUoxLvARPS3hV4U5C8Q68MFbqv+/WaMuXV+e8I4y5EUnW BaUFUgl/vCQ6CeeiDwqt2a4Tocnecnd1nFvP5ClWrj0aQ85dDsr5eFM5ewKDs0AnRUQf NF/SPnn+f2FXYQYC7T6+1xJw8YSrwa1W0PxOJ5jEFj0A6xVtGmXkgxAqaPTOJ1WeABZ/ V75g== X-Gm-Message-State: AC+VfDwM2Lr52J1i0zKpjVaA78TQGOZwk8f80zQo0Z6Z85zp9tJ4SRXV qsr3kluOmtyuCOG8osndktSFfOCpdf0Z X-Google-Smtp-Source: ACHHUZ6y5R6hIPDBP9JQr5OofgHsoDW8CGyVPTublNJFdV0I29Qxn3zeHGmzR+1HVeBLii4tKNgr1yqBc9xY X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:144f:e890:2b29:48d9]) (user=irogers job=sendgmr) by 2002:a81:ad0e:0:b0:54f:bf72:7fa6 with SMTP id l14-20020a81ad0e000000b0054fbf727fa6mr1003155ywh.0.1682492703869; Wed, 26 Apr 2023 00:05:03 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:39 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-30-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 29/40] perf test: Fix parse-events tests for >1 core PMU From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove assumptions of just 1 core PMU. Signed-off-by: Ian Rogers --- tools/perf/tests/parse-events.c | 179 +++++++++++++++++++------------- 1 file changed, 106 insertions(+), 73 deletions(-) diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index 0b8ec9b1034f..a0cd50e18ebc 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -25,6 +25,11 @@ static bool test_config(const struct evsel *evsel, __u64= expected_config) return (evsel->core.attr.config & PERF_HW_EVENT_MASK) =3D=3D expected_con= fig; } =20 +static bool test_perf_config(const struct perf_evsel *evsel, __u64 expecte= d_config) +{ + return (evsel->attr.config & PERF_HW_EVENT_MASK) =3D=3D expected_config; +} + #ifdef HAVE_LIBTRACEEVENT =20 #if defined(__s390x__) @@ -87,11 +92,27 @@ static int test__checkevent_tracepoint_multi(struct evl= ist *evlist) =20 static int test__checkevent_raw(struct evlist *evlist) { - struct evsel *evsel =3D evlist__first(evlist); + struct perf_evsel *evsel; + bool raw_type_match =3D false; =20 - TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 0x1a)); + TEST_ASSERT_VAL("wrong number of entries", 0 !=3D evlist->core.nr_entries= ); + + perf_evlist__for_each_evsel(&evlist->core, evsel) { + struct perf_pmu *pmu; + bool type_matched =3D false; + + TEST_ASSERT_VAL("wrong config", test_perf_config(evsel, 0x1a)); + perf_pmus__for_each_pmu(pmu) { + if (pmu->type =3D=3D evsel->attr.type) { + TEST_ASSERT_VAL("PMU type expected once", !type_matched); + type_matched =3D true; + if (pmu->type =3D=3D PERF_TYPE_RAW) + raw_type_match =3D true; + } + } + TEST_ASSERT_VAL("No PMU found for type", type_matched); + } + TEST_ASSERT_VAL("Raw PMU not matched", raw_type_match); return TEST_OK; } =20 @@ -107,31 +128,35 @@ static int test__checkevent_numeric(struct evlist *ev= list) =20 static int test__checkevent_symbolic_name(struct evlist *evlist) { - struct evsel *evsel =3D evlist__first(evlist); + struct perf_evsel *evsel; =20 - TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_INSTRUCT= IONS)); + TEST_ASSERT_VAL("wrong number of entries", 0 !=3D evlist->core.nr_entries= ); + + perf_evlist__for_each_evsel(&evlist->core, evsel) { + TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->attr.type= ); + TEST_ASSERT_VAL("wrong config", + test_perf_config(evsel, PERF_COUNT_HW_INSTRUCTIONS)); + } return TEST_OK; } =20 static int test__checkevent_symbolic_name_config(struct evlist *evlist) { - struct evsel *evsel =3D evlist__first(evlist); + struct perf_evsel *evsel; =20 - TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); - /* - * The period value gets configured within evlist__config, - * while this test executes only parse events method. - */ - TEST_ASSERT_VAL("wrong period", - 0 =3D=3D evsel->core.attr.sample_period); - TEST_ASSERT_VAL("wrong config1", - 0 =3D=3D evsel->core.attr.config1); - TEST_ASSERT_VAL("wrong config2", - 1 =3D=3D evsel->core.attr.config2); + TEST_ASSERT_VAL("wrong number of entries", 0 !=3D evlist->core.nr_entries= ); + + perf_evlist__for_each_evsel(&evlist->core, evsel) { + TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE =3D=3D evsel->attr.type= ); + TEST_ASSERT_VAL("wrong config", test_perf_config(evsel, PERF_COUNT_HW_CP= U_CYCLES)); + /* + * The period value gets configured within evlist__config, + * while this test executes only parse events method. + */ + TEST_ASSERT_VAL("wrong period", 0 =3D=3D evsel->attr.sample_period); + TEST_ASSERT_VAL("wrong config1", 0 =3D=3D evsel->attr.config1); + TEST_ASSERT_VAL("wrong config2", 1 =3D=3D evsel->attr.config2); + } return TEST_OK; } =20 @@ -147,11 +172,14 @@ static int test__checkevent_symbolic_alias(struct evl= ist *evlist) =20 static int test__checkevent_genhw(struct evlist *evlist) { - struct evsel *evsel =3D evlist__first(evlist); + struct perf_evsel *evsel; =20 - TEST_ASSERT_VAL("wrong number of entries", 1 =3D=3D evlist->core.nr_entri= es); - TEST_ASSERT_VAL("wrong type", PERF_TYPE_HW_CACHE =3D=3D evsel->core.attr.= type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 1 << 16)); + TEST_ASSERT_VAL("wrong number of entries", 0 !=3D evlist->core.nr_entries= ); + + perf_evlist__for_each_entry(&evlist->core, evsel) { + TEST_ASSERT_VAL("wrong type", PERF_TYPE_HW_CACHE =3D=3D evsel->attr.type= ); + TEST_ASSERT_VAL("wrong config", test_perf_config(evsel, 1 << 16)); + } return TEST_OK; } =20 @@ -243,17 +271,15 @@ static int test__checkevent_tracepoint_modifier(struc= t evlist *evlist) static int test__checkevent_tracepoint_multi_modifier(struct evlist *evlist) { - struct evsel *evsel; + struct perf_evsel *evsel; =20 TEST_ASSERT_VAL("wrong number of entries", evlist->core.nr_entries > 1); =20 - evlist__for_each_entry(evlist, evsel) { - TEST_ASSERT_VAL("wrong exclude_user", - !evsel->core.attr.exclude_user); - TEST_ASSERT_VAL("wrong exclude_kernel", - evsel->core.attr.exclude_kernel); - TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); - TEST_ASSERT_VAL("wrong precise_ip", !evsel->core.attr.precise_ip); + perf_evlist__for_each_entry(&evlist->core, evsel) { + TEST_ASSERT_VAL("wrong exclude_user", !evsel->attr.exclude_user); + TEST_ASSERT_VAL("wrong exclude_kernel", evsel->attr.exclude_kernel); + TEST_ASSERT_VAL("wrong exclude_hv", evsel->attr.exclude_hv); + TEST_ASSERT_VAL("wrong precise_ip", !evsel->attr.precise_ip); } =20 return test__checkevent_tracepoint_multi(evlist); @@ -262,25 +288,27 @@ test__checkevent_tracepoint_multi_modifier(struct evl= ist *evlist) =20 static int test__checkevent_raw_modifier(struct evlist *evlist) { - struct evsel *evsel =3D evlist__first(evlist); - - TEST_ASSERT_VAL("wrong exclude_user", evsel->core.attr.exclude_user); - TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); - TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); - TEST_ASSERT_VAL("wrong precise_ip", evsel->core.attr.precise_ip); + struct perf_evsel *evsel; =20 + perf_evlist__for_each_entry(&evlist->core, evsel) { + TEST_ASSERT_VAL("wrong exclude_user", evsel->attr.exclude_user); + TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->attr.exclude_kernel); + TEST_ASSERT_VAL("wrong exclude_hv", evsel->attr.exclude_hv); + TEST_ASSERT_VAL("wrong precise_ip", evsel->attr.precise_ip); + } return test__checkevent_raw(evlist); } =20 static int test__checkevent_numeric_modifier(struct evlist *evlist) { - struct evsel *evsel =3D evlist__first(evlist); - - TEST_ASSERT_VAL("wrong exclude_user", evsel->core.attr.exclude_user); - TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); - TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); - TEST_ASSERT_VAL("wrong precise_ip", evsel->core.attr.precise_ip); + struct perf_evsel *evsel; =20 + perf_evlist__for_each_entry(&evlist->core, evsel) { + TEST_ASSERT_VAL("wrong exclude_user", evsel->attr.exclude_user); + TEST_ASSERT_VAL("wrong exclude_kernel", evsel->attr.exclude_kernel); + TEST_ASSERT_VAL("wrong exclude_hv", !evsel->attr.exclude_hv); + TEST_ASSERT_VAL("wrong precise_ip", evsel->attr.precise_ip); + } return test__checkevent_numeric(evlist); } =20 @@ -298,21 +326,23 @@ static int test__checkevent_symbolic_name_modifier(st= ruct evlist *evlist) =20 static int test__checkevent_exclude_host_modifier(struct evlist *evlist) { - struct evsel *evsel =3D evlist__first(evlist); - - TEST_ASSERT_VAL("wrong exclude guest", !evsel->core.attr.exclude_guest); - TEST_ASSERT_VAL("wrong exclude host", evsel->core.attr.exclude_host); + struct perf_evsel *evsel; =20 + perf_evlist__for_each_entry(&evlist->core, evsel) { + TEST_ASSERT_VAL("wrong exclude guest", !evsel->attr.exclude_guest); + TEST_ASSERT_VAL("wrong exclude host", evsel->attr.exclude_host); + } return test__checkevent_symbolic_name(evlist); } =20 static int test__checkevent_exclude_guest_modifier(struct evlist *evlist) { - struct evsel *evsel =3D evlist__first(evlist); - - TEST_ASSERT_VAL("wrong exclude guest", evsel->core.attr.exclude_guest); - TEST_ASSERT_VAL("wrong exclude host", !evsel->core.attr.exclude_host); - + struct perf_evsel *evsel; +=20 + perf_evlist__for_each_entry(&evlist->core, evsel) { + TEST_ASSERT_VAL("wrong exclude guest", evsel->attr.exclude_guest); + TEST_ASSERT_VAL("wrong exclude host", !evsel->attr.exclude_host); + } return test__checkevent_symbolic_name(evlist); } =20 @@ -330,13 +360,14 @@ static int test__checkevent_symbolic_alias_modifier(s= truct evlist *evlist) =20 static int test__checkevent_genhw_modifier(struct evlist *evlist) { - struct evsel *evsel =3D evlist__first(evlist); - - TEST_ASSERT_VAL("wrong exclude_user", evsel->core.attr.exclude_user); - TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); - TEST_ASSERT_VAL("wrong exclude_hv", evsel->core.attr.exclude_hv); - TEST_ASSERT_VAL("wrong precise_ip", evsel->core.attr.precise_ip); + struct perf_evsel *evsel; =20 + perf_evlist__for_each_entry(&evlist->core, evsel) { + TEST_ASSERT_VAL("wrong exclude_user", evsel->attr.exclude_user); + TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->attr.exclude_kernel); + TEST_ASSERT_VAL("wrong exclude_hv", evsel->attr.exclude_hv); + TEST_ASSERT_VAL("wrong precise_ip", evsel->attr.precise_ip); + } return test__checkevent_genhw(evlist); } =20 @@ -466,21 +497,23 @@ static int test__checkevent_list(struct evlist *evlis= t) { struct evsel *evsel =3D evlist__first(evlist); =20 - TEST_ASSERT_VAL("wrong number of entries", 3 =3D=3D evlist->core.nr_entri= es); + TEST_ASSERT_VAL("wrong number of entries", 3 <=3D evlist->core.nr_entries= ); =20 /* r1 */ - TEST_ASSERT_VAL("wrong type", PERF_TYPE_RAW =3D=3D evsel->core.attr.type); - TEST_ASSERT_VAL("wrong config", test_config(evsel, 1)); - TEST_ASSERT_VAL("wrong config1", 0 =3D=3D evsel->core.attr.config1); - TEST_ASSERT_VAL("wrong config2", 0 =3D=3D evsel->core.attr.config2); - TEST_ASSERT_VAL("wrong config3", 0 =3D=3D evsel->core.attr.config3); - TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); - TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); - TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); - TEST_ASSERT_VAL("wrong precise_ip", !evsel->core.attr.precise_ip); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_TRACEPOINT !=3D evsel->core.attr.= type); + while (PERF_TYPE_TRACEPOINT !=3D evsel->core.attr.type) { + TEST_ASSERT_VAL("wrong config", test_config(evsel, 1)); + TEST_ASSERT_VAL("wrong config1", 0 =3D=3D evsel->core.attr.config1); + TEST_ASSERT_VAL("wrong config2", 0 =3D=3D evsel->core.attr.config2); + TEST_ASSERT_VAL("wrong config3", 0 =3D=3D evsel->core.attr.config3); + TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); + TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel= ); + TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); + TEST_ASSERT_VAL("wrong precise_ip", !evsel->core.attr.precise_ip); + evsel =3D evsel__next(evsel); + } =20 /* syscalls:sys_enter_openat:k */ - evsel =3D evsel__next(evsel); TEST_ASSERT_VAL("wrong type", PERF_TYPE_TRACEPOINT =3D=3D evsel->core.att= r.type); TEST_ASSERT_VAL("wrong sample_type", PERF_TP_SAMPLE_TYPE =3D=3D evsel->core.attr.sample_type); @@ -1916,7 +1949,7 @@ static int test_event(const struct evlist_test *e) e->name, ret, err.str); parse_events_error__print(&err, e->name); ret =3D TEST_FAIL; - if (strstr(err.str, "can't access trace events")) + if (err.str && strstr(err.str, "can't access trace events")) ret =3D TEST_SKIP; } else { ret =3D e->check(evlist); --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:40 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05988C77B60 for ; Wed, 26 Apr 2023 07:07:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239589AbjDZHHg (ORCPT ); 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Wed, 26 Apr 2023 00:05:11 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:40 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-31-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 30/40] perf parse-events: Support hardware events as terms From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" An event like "cpu/instructions/" typically parses due to there being a sysfs event called instructions. On hybrid recursive parsing means that the hardware event is encoded in the attribute, with the PMU being placed in the high bits of the config: ''' $ perf stat -vv -e 'cpu_core/cycles/' true ... ------------------------------------------------------------ perf_event_attr: size 136 config 0x400000000 sample_type IDENTIFIER read_format TOTAL_TIME_ENABLED|TOTAL_TIME_RUNNING disabled 1 inherit 1 enable_on_exec 1 exclude_guest 1 ------------------------------------------------------------ ''' Make this behavior the default by adding a new term type and token for hardware events. The token gathers both the numeric config and the parsed name, so that if the token appears like "cycles/name=3Dcycles/" then the token can be handled like a name. The numeric value isn't sufficient to distinguish say "cpu-cycles" from "cycles". Extend the parse-events test so that all current non-PMU hardware parsing tests, also test with the PMU cpu - more than half the change. Signed-off-by: Ian Rogers --- tools/perf/tests/parse-events.c | 126 ++++++++++++++++++++++++++++++++ tools/perf/util/parse-events.c | 37 +++------- tools/perf/util/parse-events.h | 3 +- tools/perf/util/parse-events.l | 20 +++++ tools/perf/util/parse-events.y | 34 +++++++-- 5 files changed, 187 insertions(+), 33 deletions(-) diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index a0cd50e18ebc..4c21bef882ff 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -1912,6 +1912,132 @@ static const struct evlist_test test__events_pmu[] = =3D { .check =3D test__checkevent_config_cache, /* 8 */ }, + { + .name =3D "cpu/instructions/", + .valid =3D test__pmu_cpu_valid, + .check =3D test__checkevent_symbolic_name, + /* 9 */ + }, + { + .name =3D "cpu/cycles,period=3D100000,config2/", + .valid =3D test__pmu_cpu_valid, + .check =3D test__checkevent_symbolic_name_config, + /* 0 */ + }, + { + .name =3D "cpu/instructions/h", + .valid =3D test__pmu_cpu_valid, + .check =3D test__checkevent_symbolic_name_modifier, + /* 1 */ + }, + { + .name =3D "cpu/instructions/G", + .valid =3D test__pmu_cpu_valid, + .check =3D test__checkevent_exclude_host_modifier, + /* 2 */ + }, + { + .name =3D "cpu/instructions/H", + .valid =3D test__pmu_cpu_valid, + .check =3D test__checkevent_exclude_guest_modifier, + /* 3 */ + }, + { + .name =3D "{cpu/instructions/k,cpu/cycles/upp}", + .valid =3D test__pmu_cpu_valid, + .check =3D test__group1, + /* 4 */ + }, + { + .name =3D "{cpu/cycles/u,cpu/instructions/kp}:p", + .valid =3D test__pmu_cpu_valid, + .check =3D test__group4, + /* 5 */ + }, + { + .name =3D "{cpu/cycles/,cpu/cache-misses/G}:H", + .valid =3D test__pmu_cpu_valid, + .check =3D test__group_gh1, + /* 6 */ + }, + { + .name =3D "{cpu/cycles/,cpu/cache-misses/H}:G", + .valid =3D test__pmu_cpu_valid, + .check =3D test__group_gh2, + /* 7 */ + }, + { + .name =3D "{cpu/cycles/G,cpu/cache-misses/H}:u", + .valid =3D test__pmu_cpu_valid, + .check =3D test__group_gh3, + /* 8 */ + }, + { + .name =3D "{cpu/cycles/G,cpu/cache-misses/H}:uG", + .valid =3D test__pmu_cpu_valid, + .check =3D test__group_gh4, + /* 9 */ + }, + { + .name =3D "{cpu/cycles/,cpu/cache-misses/,cpu/branch-misses/}:S", + .valid =3D test__pmu_cpu_valid, + .check =3D test__leader_sample1, + /* 0 */ + }, + { + .name =3D "{cpu/instructions/,cpu/branch-misses/}:Su", + .valid =3D test__pmu_cpu_valid, + .check =3D test__leader_sample2, + /* 1 */ + }, + { + .name =3D "cpu/instructions/uDp", + .valid =3D test__pmu_cpu_valid, + .check =3D test__checkevent_pinned_modifier, + /* 2 */ + }, + { + .name =3D "{cpu/cycles/,cpu/cache-misses/,cpu/branch-misses/}:D", + .valid =3D test__pmu_cpu_valid, + .check =3D test__pinned_group, + /* 3 */ + }, + { + .name =3D "cpu/instructions/I", + .valid =3D test__pmu_cpu_valid, + .check =3D test__checkevent_exclude_idle_modifier, + /* 4 */ + }, + { + .name =3D "cpu/instructions/kIG", + .valid =3D test__pmu_cpu_valid, + .check =3D test__checkevent_exclude_idle_modifier_1, + /* 5 */ + }, + { + .name =3D "cpu/cycles/u", + .valid =3D test__pmu_cpu_valid, + .check =3D test__sym_event_slash, + /* 6 */ + }, + { + .name =3D "cpu/cycles/k", + .valid =3D test__pmu_cpu_valid, + .check =3D test__sym_event_dc, + /* 7 */ + }, + { + .name =3D "cpu/instructions/uep", + .valid =3D test__pmu_cpu_valid, + .check =3D test__checkevent_exclusive_modifier, + /* 8 */ + }, + { + .name =3D "{cpu/cycles/,cpu/cache-misses/,cpu/branch-misses/}:e", + .valid =3D test__pmu_cpu_valid, + .check =3D test__exclusive_group, + /* 9 */ + }, }; =20 struct terms_test { diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index 29fa84c4cdd4..27c179323b6d 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -1053,6 +1053,7 @@ static const char *config_term_names[__PARSE_EVENTS__= TERM_TYPE_NR] =3D { [PARSE_EVENTS__TERM_TYPE_METRIC_ID] =3D "metric-id", [PARSE_EVENTS__TERM_TYPE_RAW] =3D "raw", [PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE] =3D "legacy-cache", + [PARSE_EVENTS__TERM_TYPE_HARDWARE] =3D "hardware", }; =20 static bool config_term_shrinked; @@ -1240,6 +1241,17 @@ static int config_term_pmu(struct perf_event_attr *a= ttr, } else term->type_term =3D PARSE_EVENTS__TERM_TYPE_USER; } + if (term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_HARDWARE) { + const struct perf_pmu *pmu =3D perf_pmu__find_by_type(attr->type); + + if (!pmu) { + pr_debug("Failed to find PMU for type %d", attr->type); + return -EINVAL; + } + attr->type =3D PERF_TYPE_HARDWARE; + attr->config =3D ((__u64)pmu->type << PERF_PMU_TYPE_SHIFT) | term->val.n= um; + return 0; + } if (term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_USER || term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_DRV_CFG) { /* @@ -2566,31 +2578,6 @@ int parse_events_term__str(struct parse_events_term = **term, return new_term(term, &temp, str, 0); } =20 -int parse_events_term__sym_hw(struct parse_events_term **term, - char *config, unsigned idx) -{ - struct event_symbol *sym; - char *str; - struct parse_events_term temp =3D { - .type_val =3D PARSE_EVENTS__TERM_TYPE_STR, - .type_term =3D PARSE_EVENTS__TERM_TYPE_USER, - .config =3D config, - }; - - if (!temp.config) { - temp.config =3D strdup("event"); - if (!temp.config) - return -ENOMEM; - } - BUG_ON(idx >=3D PERF_COUNT_HW_MAX); - sym =3D &event_symbols_hw[idx]; - - str =3D strdup(sym->symbol); - if (!str) - return -ENOMEM; - return new_term(term, &temp, str, 0); -} - int parse_events_term__clone(struct parse_events_term **new, struct parse_events_term *term) { diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index d4cbda6e946a..7fe80b416143 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -79,6 +79,7 @@ enum { PARSE_EVENTS__TERM_TYPE_METRIC_ID, PARSE_EVENTS__TERM_TYPE_RAW, PARSE_EVENTS__TERM_TYPE_LEGACY_CACHE, + PARSE_EVENTS__TERM_TYPE_HARDWARE, __PARSE_EVENTS__TERM_TYPE_NR, }; =20 @@ -147,8 +148,6 @@ int parse_events_term__num(struct parse_events_term **t= erm, int parse_events_term__str(struct parse_events_term **term, int type_term, char *config, char *str, void *loc_term, void *loc_val); -int parse_events_term__sym_hw(struct parse_events_term **term, - char *config, unsigned idx); int parse_events_term__clone(struct parse_events_term **new, struct parse_events_term *term); void parse_events_term__delete(struct parse_events_term *term); diff --git a/tools/perf/util/parse-events.l b/tools/perf/util/parse-events.l index abe0ce681d29..6deb70c25984 100644 --- a/tools/perf/util/parse-events.l +++ b/tools/perf/util/parse-events.l @@ -149,6 +149,16 @@ static int term(yyscan_t scanner, int type) return PE_TERM; } =20 +static int hw_term(yyscan_t scanner, int config) +{ + YYSTYPE *yylval =3D parse_events_get_lval(scanner); + char *text =3D parse_events_get_text(scanner); + + yylval->hardware_term.str =3D strdup(text); + yylval->hardware_term.num =3D PERF_TYPE_HARDWARE + config; + return PE_TERM_HW; +} + #define YY_USER_ACTION \ do { \ yylloc->last_column =3D yylloc->first_column; \ @@ -269,6 +279,16 @@ percore { return term(yyscanner, PARSE_EVENTS__TERM_= TYPE_PERCORE); } aux-output { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_AUX_OUTPUT); } aux-sample-size { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_AUX_SAMP= LE_SIZE); } metric-id { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_METRIC_ID); } +cpu-cycles|cycles { return hw_term(yyscanner, PERF_COUNT_HW_CPU_CYCLES)= ; } +stalled-cycles-frontend|idle-cycles-frontend { return hw_term(yyscanner, P= ERF_COUNT_HW_STALLED_CYCLES_FRONTEND); } +stalled-cycles-backend|idle-cycles-backend { return hw_term(yyscanner, PER= F_COUNT_HW_STALLED_CYCLES_BACKEND); } +instructions { return hw_term(yyscanner, PERF_COUNT_HW_INSTRUCTIONS); } +cache-references { return hw_term(yyscanner, PERF_COUNT_HW_CACHE_REFERE= NCES); } +cache-misses { return hw_term(yyscanner, PERF_COUNT_HW_CACHE_MISSES); } +branch-instructions|branches { return hw_term(yyscanner, PERF_COUNT_HW_B= RANCH_INSTRUCTIONS); } +branch-misses { return hw_term(yyscanner, PERF_COUNT_HW_BRANCH_MISSES)= ; } +bus-cycles { return hw_term(yyscanner, PERF_COUNT_HW_BUS_CYCLES); } +ref-cycles { return hw_term(yyscanner, PERF_COUNT_HW_REF_CPU_CYCLES); } r{num_raw_hex} { return str(yyscanner, PE_RAW); } r0x{num_raw_hex} { return str(yyscanner, PE_RAW); } , { return ','; } diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y index c95877cbd6cf..819a5123fd77 100644 --- a/tools/perf/util/parse-events.y +++ b/tools/perf/util/parse-events.y @@ -65,6 +65,7 @@ static void free_list_evsel(struct list_head* list_evsel) %token PE_KERNEL_PMU_EVENT PE_PMU_EVENT_FAKE %token PE_ARRAY_ALL PE_ARRAY_RANGE %token PE_DRV_CFG_TERM +%token PE_TERM_HW %type PE_VALUE %type PE_VALUE_SYM_HW %type PE_VALUE_SYM_SW @@ -112,6 +113,8 @@ static void free_list_evsel(struct list_head* list_evse= l) %type array_term %type array_terms %destructor { free ($$.ranges); } +%type PE_TERM_HW +%destructor { free ($$.str); } =20 %union { @@ -125,6 +128,10 @@ static void free_list_evsel(struct list_head* list_evs= el) char *event; } tracepoint_name; struct parse_events_array array; + struct hardware_term { + char *str; + u64 num; + } hardware_term; } %% =20 @@ -770,13 +777,14 @@ name_or_raw '=3D' PE_VALUE $$ =3D term; } | -name_or_raw '=3D' PE_VALUE_SYM_HW +name_or_raw '=3D' PE_TERM_HW { struct parse_events_term *term; - int config =3D $3 & 255; =20 - if (parse_events_term__sym_hw(&term, $1, config)) { + if (parse_events_term__str(&term, PARSE_EVENTS__TERM_TYPE_USER, + $1, $3.str, &@1, &@3)) { free($1); + free($3.str); YYABORT; } $$ =3D term; @@ -806,12 +814,15 @@ PE_NAME $$ =3D term; } | -PE_VALUE_SYM_HW +PE_TERM_HW { struct parse_events_term *term; - int config =3D $1 & 255; =20 - ABORT_ON(parse_events_term__sym_hw(&term, NULL, config)); + if (parse_events_term__num(&term, PARSE_EVENTS__TERM_TYPE_HARDWARE, + $1.str, $1.num & 255, false, &@1, NULL)) { + free($1.str); + YYABORT; + } $$ =3D term; } | @@ -826,6 +837,17 @@ PE_TERM '=3D' PE_NAME $$ =3D term; } | +PE_TERM '=3D' PE_TERM_HW +{ + struct parse_events_term *term; + + if (parse_events_term__str(&term, (int)$1, NULL, $3.str, &@1, &@3)) { + free($3.str); + YYABORT; + } + $$ =3D term; +} +| PE_TERM '=3D' PE_VALUE { struct parse_events_term *term; --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:40 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90300C7618E for ; Wed, 26 Apr 2023 07:07:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239804AbjDZHHj (ORCPT ); Wed, 26 Apr 2023 03:07:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239903AbjDZHHB (ORCPT ); Wed, 26 Apr 2023 03:07:01 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BAEE249D4 for ; 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bh=hpUWqNL0tOEngg8yuOrwHuZx1oPdLKlDkdLSWdUpIbg=; b=PKbciE8STjk/QOhLC046+A/bMfQN5il1RJgcPMezT4Vbi9+1SrKQDjUsXlxWETGg+L VwDd+qirvTAoNGsJVnMi1ZoAeegUcJUldJDpifjCP7mmnk0NQgks+gB4nMuuelnn8xBS goigm5woS6xgXve/xpgD0C8ATExPU+LZR0Ti+8YfPsV9XKidYMJVBLJhmGVQQFDprGn8 0f/gsrOot2KP9lTWiUKolYwo4oepaBdwtz0zWLGI27JjmngGF7R/OHqrSBT6S7QMq/OY XpVLSFyoJTFJ0BE7v1fw4HmAgQI1wIbn7I2EdbdQU8LCoNgWqi8ODzkELxVZAr5zH89h 7C2w== X-Gm-Message-State: AC+VfDyIsRAHoYBakmUxm3Hapwl4ck7xLiVMxArbDjGjd/OauZMXw+6X zWdfBYH5G6COYTwR1gxyj2izlHHXfuW1 X-Google-Smtp-Source: ACHHUZ65Ydc2KtN7BWaC/ktnakyD7s40B2e42pMLpiPw3w+MRMRsBxzYMRNaXC4/qxOnDGXQtCDs+HCM1Gdc X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:144f:e890:2b29:48d9]) (user=irogers job=sendgmr) by 2002:a81:25c1:0:b0:556:aa28:f9c5 with SMTP id l184-20020a8125c1000000b00556aa28f9c5mr944980ywl.2.1682492719959; Wed, 26 Apr 2023 00:05:19 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:41 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-32-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 31/40] perf parse-events: Avoid error when assigning a term From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Avoid the parser error: ''' $ perf stat -e 'cycles/name=3Dname/' true event syntax error: 'cycles/name=3Dname/' \___ parser error ''' by turning the term back to a string if it is on the right. Add PMU and generic parsing tests. Signed-off-by: Ian Rogers --- tools/perf/tests/parse-events.c | 21 +++++++++++++++++++++ tools/perf/util/parse-events.c | 9 +++++++++ tools/perf/util/parse-events.h | 3 +++ tools/perf/util/parse-events.y | 8 ++++++++ 4 files changed, 41 insertions(+) diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index 4c21bef882ff..06042f450ece 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -1485,6 +1485,16 @@ static int test__sym_event_dc(struct evlist *evlist) return TEST_OK; } =20 +static int test__term_equal_term(struct evlist *evlist) +{ + struct evsel *evsel =3D evlist__first(evlist); + + TEST_ASSERT_VAL("wrong type", evsel->core.attr.type =3D=3D PERF_TYPE_HARD= WARE); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); + TEST_ASSERT_VAL("wrong name setting", strcmp(evsel->name, "name") =3D=3D = 0); + return TEST_OK; +} + #ifdef HAVE_LIBTRACEEVENT static int count_tracepoints(void) { @@ -1857,6 +1867,11 @@ static const struct evlist_test test__events[] =3D { .check =3D test__exclusive_group, /* 7 */ }, + { + .name =3D "cycles/name=3Dname/", + .check =3D test__term_equal_term, + /* 8 */ + }, }; =20 static const struct evlist_test test__events_pmu[] =3D { @@ -2038,6 +2053,12 @@ static const struct evlist_test test__events_pmu[] = =3D { .check =3D test__exclusive_group, /* 9 */ }, + { + .name =3D "cpu/cycles,name=3Dname/", + .valid =3D test__pmu_cpu_valid, + .check =3D test__term_equal_term, + /* 0 */ + }, }; =20 struct terms_test { diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index 27c179323b6d..98e424257278 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -2578,6 +2578,15 @@ int parse_events_term__str(struct parse_events_term = **term, return new_term(term, &temp, str, 0); } =20 +int parse_events_term__term(struct parse_events_term **term, + int term_lhs, int term_rhs, + void *loc_term, void *loc_val) +{ + return parse_events_term__str(term, term_lhs, NULL, + strdup(config_term_names[term_rhs]), + loc_term, loc_val); +} + int parse_events_term__clone(struct parse_events_term **new, struct parse_events_term *term) { diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index 7fe80b416143..2a8cafe0ee8f 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -148,6 +148,9 @@ int parse_events_term__num(struct parse_events_term **t= erm, int parse_events_term__str(struct parse_events_term **term, int type_term, char *config, char *str, void *loc_term, void *loc_val); +int parse_events_term__term(struct parse_events_term **term, + int term_lhs, int term_rhs, + void *loc_term, void *loc_val); int parse_events_term__clone(struct parse_events_term **new, struct parse_events_term *term); void parse_events_term__delete(struct parse_events_term *term); diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y index 819a5123fd77..0aaebc57748e 100644 --- a/tools/perf/util/parse-events.y +++ b/tools/perf/util/parse-events.y @@ -848,6 +848,14 @@ PE_TERM '=3D' PE_TERM_HW $$ =3D term; } | +PE_TERM '=3D' PE_TERM +{ + struct parse_events_term *term; + + ABORT_ON(parse_events_term__term(&term, (int)$1, (int)$3, &@1, &@3)); + $$ =3D term; +} +| PE_TERM '=3D' PE_VALUE { struct parse_events_term *term; --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:40 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 217F5C77B60 for ; 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Wed, 26 Apr 2023 00:05:27 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:42 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-33-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 32/40] perf parse-events: Avoid error when assigning a legacy cache term From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Avoid the parser error: ''' $ perf stat -e 'cycles/name=3Dl1d/' true event syntax error: 'cycles/name=3Dl1d/' \___ parser error ''' by combining the name and legacy cache cases in the parser. Signed-off-by: Ian Rogers --- tools/perf/tests/parse-events.c | 21 +++++++++++++++++++++ tools/perf/util/parse-events.y | 10 ++++++---- 2 files changed, 27 insertions(+), 4 deletions(-) diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index 06042f450ece..c44f0ffa51c5 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -1495,6 +1495,16 @@ static int test__term_equal_term(struct evlist *evli= st) return TEST_OK; } =20 +static int test__term_equal_legacy(struct evlist *evlist) +{ + struct evsel *evsel =3D evlist__first(evlist); + + TEST_ASSERT_VAL("wrong type", evsel->core.attr.type =3D=3D PERF_TYPE_HARD= WARE); + TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_HW_CPU_CYCL= ES)); + TEST_ASSERT_VAL("wrong name setting", strcmp(evsel->name, "l1d") =3D=3D 0= ); + return TEST_OK; +} + #ifdef HAVE_LIBTRACEEVENT static int count_tracepoints(void) { @@ -1872,6 +1882,11 @@ static const struct evlist_test test__events[] =3D { .check =3D test__term_equal_term, /* 8 */ }, + { + .name =3D "cycles/name=3Dl1d/", + .check =3D test__term_equal_legacy, + /* 9 */ + }, }; =20 static const struct evlist_test test__events_pmu[] =3D { @@ -2059,6 +2074,12 @@ static const struct evlist_test test__events_pmu[] = =3D { .check =3D test__term_equal_term, /* 0 */ }, + { + .name =3D "cpu/cycles,name=3Dl1d/", + .valid =3D test__pmu_cpu_valid, + .check =3D test__term_equal_legacy, + /* 1 */ + }, }; =20 struct terms_test { diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y index 0aaebc57748e..f4ee03b5976b 100644 --- a/tools/perf/util/parse-events.y +++ b/tools/perf/util/parse-events.y @@ -82,7 +82,7 @@ static void free_list_evsel(struct list_head* list_evsel) %type PE_EVENT_NAME %type PE_KERNEL_PMU_EVENT PE_PMU_EVENT_FAKE %type PE_DRV_CFG_TERM -%type name_or_raw +%type name_or_raw name_or_legacy %destructor { free ($$); } %type event_term %destructor { parse_events_term__delete ($$); } @@ -739,6 +739,8 @@ event_term =20 name_or_raw: PE_RAW | PE_NAME | PE_LEGACY_CACHE =20 +name_or_legacy: PE_NAME | PE_LEGACY_CACHE + event_term: PE_RAW { @@ -752,7 +754,7 @@ PE_RAW $$ =3D term; } | -name_or_raw '=3D' PE_NAME +name_or_raw '=3D' name_or_legacy { struct parse_events_term *term; =20 @@ -826,7 +828,7 @@ PE_TERM_HW $$ =3D term; } | -PE_TERM '=3D' PE_NAME +PE_TERM '=3D' name_or_legacy { struct parse_events_term *term; =20 @@ -872,7 +874,7 @@ PE_TERM $$ =3D term; } | -name_or_raw array '=3D' PE_NAME +name_or_raw array '=3D' name_or_legacy { struct parse_events_term *term; =20 --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:40 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94D4DC77B60 for ; Wed, 26 Apr 2023 07:07:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239942AbjDZHH4 (ORCPT ); Wed, 26 Apr 2023 03:07:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45888 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239914AbjDZHHP (ORCPT ); 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Wed, 26 Apr 2023 00:05:36 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:43 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-34-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 33/40] perf parse-events: Don't auto merge hybrid wildcard events From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Bring back the behavior of not auto-merging hybrid events by delegating to a test in pmu. Signed-off-by: Ian Rogers --- tools/perf/util/parse-events.c | 5 ++++- tools/perf/util/parse-events.y | 4 +++- tools/perf/util/pmu.c | 5 +++++ tools/perf/util/pmu.h | 1 + 4 files changed, 13 insertions(+), 2 deletions(-) diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index 98e424257278..b62dcc51b22f 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -1718,16 +1718,19 @@ int parse_events_multi_pmu_add(struct parse_events_= state *parse_state, =20 while ((pmu =3D perf_pmu__scan(pmu)) !=3D NULL) { struct perf_pmu_alias *alias; + bool auto_merge_stats; =20 if (parse_events__filter_pmu(parse_state, pmu)) continue; =20 + auto_merge_stats =3D perf_pmu__auto_merge_stats(pmu); + list_for_each_entry(alias, &pmu->aliases, list) { if (!strcasecmp(alias->name, str)) { parse_events_copy_term_list(head, &orig_head); if (!parse_events_add_pmu(parse_state, list, pmu->name, orig_head, - /*auto_merge_stats=3D*/true)) { + auto_merge_stats)) { pr_debug("%s -> %s/%s/\n", str, pmu->name, alias->str); ok++; diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y index f4ee03b5976b..4e1f5de35be8 100644 --- a/tools/perf/util/parse-events.y +++ b/tools/perf/util/parse-events.y @@ -327,10 +327,12 @@ PE_NAME opt_pmu_config name +=3D 7; if (!perf_pmu__match(pattern, name, $1) || !perf_pmu__match(pattern, pmu->alias_name, $1)) { + bool auto_merge_stats =3D perf_pmu__auto_merge_stats(pmu); + if (parse_events_copy_term_list(orig_terms, &terms)) CLEANUP_YYABORT; if (!parse_events_add_pmu(parse_state, list, pmu->name, terms, - /*auto_merge_stats=3D*/true)) { + auto_merge_stats)) { ok++; parse_state->wild_card_pmus =3D true; } diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index cd4247a379d4..f4f0afbc391c 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -1660,6 +1660,11 @@ bool perf_pmu__supports_wildcard_numeric(const struc= t perf_pmu *pmu) return is_pmu_core(pmu->name) || perf_pmu__is_hybrid(pmu->name); } =20 +bool perf_pmu__auto_merge_stats(const struct perf_pmu *pmu) +{ + return !perf_pmu__is_hybrid(pmu->name); +} + static bool pmu_alias_is_duplicate(struct sevent *alias_a, struct sevent *alias_b) { diff --git a/tools/perf/util/pmu.h b/tools/perf/util/pmu.h index 5a19536a5449..0e0cb6283594 100644 --- a/tools/perf/util/pmu.h +++ b/tools/perf/util/pmu.h @@ -222,6 +222,7 @@ struct perf_pmu *perf_pmu__scan(struct perf_pmu *pmu); bool is_pmu_core(const char *name); bool perf_pmu__supports_legacy_cache(const struct perf_pmu *pmu); bool perf_pmu__supports_wildcard_numeric(const struct perf_pmu *pmu); +bool perf_pmu__auto_merge_stats(const struct perf_pmu *pmu); void print_pmu_events(const struct print_callbacks *print_cb, void *print_= state); bool pmu_have_event(const char *pname, const char *name); =20 --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:40 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DAEDEC7618E for ; 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Wed, 26 Apr 2023 00:05:43 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:44 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-35-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 34/40] perf parse-events: Don't reorder atom cpu events From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On hybrid systems the topdown events don't share a fixed counter on the atom core, so they don't require the sorting the perf metric supporting PMUs do. Signed-off-by: Ian Rogers --- tools/perf/arch/x86/util/evlist.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/perf/arch/x86/util/evlist.c b/tools/perf/arch/x86/util/e= vlist.c index d4193479a364..1b6065841fb0 100644 --- a/tools/perf/arch/x86/util/evlist.c +++ b/tools/perf/arch/x86/util/evlist.c @@ -6,6 +6,7 @@ #include "util/event.h" #include "util/pmu-hybrid.h" #include "topdown.h" +#include "evsel.h" =20 static int ___evlist__add_default_attrs(struct evlist *evlist, struct perf_event_attr *attrs, @@ -67,8 +68,7 @@ int arch_evlist__add_default_attrs(struct evlist *evlist, =20 int arch_evlist__cmp(const struct evsel *lhs, const struct evsel *rhs) { - if (topdown_sys_has_perf_metrics() && - (!lhs->pmu_name || !strncmp(lhs->pmu_name, "cpu", 3))) { + if (topdown_sys_has_perf_metrics() && evsel__sys_has_perf_metrics(lhs)) { /* Ensure the topdown slots comes first. */ if (strcasestr(lhs->name, "slots")) return -1; --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:40 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B102C7618E for ; Wed, 26 Apr 2023 07:08:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239855AbjDZHIR (ORCPT ); Wed, 26 Apr 2023 03:08:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239449AbjDZHHt (ORCPT ); Wed, 26 Apr 2023 03:07:49 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7253A4C04 for ; Wed, 26 Apr 2023 00:06:08 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-b99f3aee8e0so9387254276.0 for ; Wed, 26 Apr 2023 00:06:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1682492750; x=1685084750; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=Q5tgiBAgTcpLZ/xGkkqluwwTTaJgssStvWVHfd5SvpU=; b=PglZOsjG/RR4WLB3wZ64AvXLJMR9qLYqZG1WiV3O++lfDLpc8n/h8JmukWUVeSpUCQ SPBHNdluX6/dSfE+Z/CjndMF7VdGz6A6be284nHvOQRYcuXyaxLnB4M3XWIaSCmfeNJ2 TCRO/yzhK8j/S7rykFKZteiXByh81f1Io6CkCWiLMmOHRUKKfvCWFvVqLbOMmh9rtxD3 WcU0lE2gXNbalc7oid79hEXnr5WeLkhNmjnZImMrXy/A9cWIywkxCcfI1/hJB92quW8w FqRE0l2GrT3VAGEfgf03RsuBF7dyqa62TAfiJvlZ8tIm/tTMXY0JzqxkM1RxKtamHYoN Z93w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682492750; x=1685084750; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Q5tgiBAgTcpLZ/xGkkqluwwTTaJgssStvWVHfd5SvpU=; b=eYsUeU81STQZoBpNdQ2SFEkjKm4EshmnVNpaq0w2v4dCsCs1SPIRSAkBqDrGx7D67S c/pWt7Fl++3uxQZ6uXlntTUauSp3lt/sGEwsRmDyq6sxZ2N6ruYkXV2PQiI7aqdeNJfi BDXo0r1rESiicCrt1AeV/MC0urRT6IEhW5ogunA+tzzgQdmaG/eTAH/6w9H8Q8IUr76Z dM5XEllmGj3EOhoxBJ9yGPnTY/Hdby9s5H0X1XHa8A75cVPPdUs/0nHFO2xZqTN/HLB4 jrn8eRQsUWWp7kcBeKe8Dsu+huIDdWoLud19+z9qp6tBKXlx4msOTU9VYLRRD5RrNKk2 RMEw== X-Gm-Message-State: AC+VfDwkGyY3hHCOeY6YZQXGO1V4jDgEeZv/TIn6R8ldlRXDUBjWHimZ M2IVbx+qkD5El8A63r5iLu7YVqL/3iUK X-Google-Smtp-Source: ACHHUZ7OtP4D2TSMVUsrJv3S233Sncn/vp51KC1XltPGHOjCWtewvV0bf4XlL1SfFA78jtVGjDJPRnH9q21Y X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:144f:e890:2b29:48d9]) (user=irogers job=sendgmr) by 2002:a05:690c:2f82:b0:54f:e2ca:3085 with SMTP id ew2-20020a05690c2f8200b0054fe2ca3085mr942919ywb.1.1682492750509; Wed, 26 Apr 2023 00:05:50 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:45 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-36-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 35/40] perf metrics: Be PMU specific for referenced metrics. From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Hybrid systems may define the same metric for different PMUs, this can cause confusion of events. To avoid this make the referenced metric searchs PMU specific, matching that in the table. Signed-off-by: Ian Rogers --- tools/perf/builtin-stat.c | 6 +- tools/perf/pmu-events/jevents.py | 4 +- tools/perf/pmu-events/pmu-events.h | 1 + tools/perf/util/metricgroup.c | 97 +++++++++++++++++++++--------- tools/perf/util/metricgroup.h | 2 +- 5 files changed, 75 insertions(+), 35 deletions(-) diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index e2119ffd08de..5dbdf001028b 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -1794,7 +1794,7 @@ static int add_default_attributes(void) * will use this approach. To determine transaction support * on an architecture test for such a metric name. */ - if (!metricgroup__has_metric("transaction")) { + if (!metricgroup__has_metric("all", "transaction")) { pr_err("Missing transaction metrics"); return -1; } @@ -1823,7 +1823,7 @@ static int add_default_attributes(void) smi_reset =3D true; } =20 - if (!metricgroup__has_metric("smi")) { + if (!metricgroup__has_metric("all", "smi")) { pr_err("Missing smi metrics"); return -1; } @@ -1898,7 +1898,7 @@ static int add_default_attributes(void) * Add TopdownL1 metrics if they exist. To minimize * multiplexing, don't request threshold computation. */ - if (metricgroup__has_metric("TopdownL1")) { + if (metricgroup__has_metric("all", "TopdownL1")) { struct evlist *metric_evlist =3D evlist__new(); struct evsel *metric_evsel; =20 diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jeven= ts.py index ca99b9cfe4ad..bbcaafaf7c25 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -51,8 +51,8 @@ _json_event_attributes =3D [ =20 # Attributes that are in pmu_metric rather than pmu_event. _json_metric_attributes =3D [ - 'metric_name', 'metric_group', 'metric_expr', 'metric_threshold', 'des= c', - 'long_desc', 'unit', 'compat', 'aggr_mode', 'event_grouping' + 'pmu', 'metric_name', 'metric_group', 'metric_expr', 'metric_threshold= ', + 'desc', 'long_desc', 'unit', 'compat', 'aggr_mode', 'event_grouping' ] # Attributes that are bools or enum int values, encoded as '0', '1',... _json_enum_attributes =3D ['aggr_mode', 'deprecated', 'event_grouping', 'p= erpkg'] diff --git a/tools/perf/pmu-events/pmu-events.h b/tools/perf/pmu-events/pmu= -events.h index b7dff8f1021f..1dd8f35a2483 100644 --- a/tools/perf/pmu-events/pmu-events.h +++ b/tools/perf/pmu-events/pmu-events.h @@ -51,6 +51,7 @@ struct pmu_event { }; =20 struct pmu_metric { + const char *pmu; const char *metric_name; const char *metric_group; const char *metric_expr; diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index 46fc31cff124..39fbdb5bab1f 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -123,6 +123,7 @@ struct metric { * within the expression. */ struct expr_parse_ctx *pctx; + const char *pmu; /** The name of the metric such as "IPC". */ const char *metric_name; /** Modifier on the metric such as "u" or NULL for none. */ @@ -216,6 +217,7 @@ static struct metric *metric__new(const struct pmu_metr= ic *pm, if (!m->pctx) goto out_err; =20 + m->pmu =3D pm->pmu ?: "cpu"; m->metric_name =3D pm->metric_name; m->modifier =3D NULL; if (modifier) { @@ -259,11 +261,12 @@ static bool contains_metric_id(struct evsel **metric_= events, int num_events, /** * setup_metric_events - Find a group of events in metric_evlist that corr= espond * to the IDs from a parsed metric expression. + * @pmu: The PMU for the IDs. * @ids: the metric IDs to match. * @metric_evlist: the list of perf events. * @out_metric_events: holds the created metric events array. */ -static int setup_metric_events(struct hashmap *ids, +static int setup_metric_events(const char *pmu, struct hashmap *ids, struct evlist *metric_evlist, struct evsel ***out_metric_events) { @@ -271,6 +274,7 @@ static int setup_metric_events(struct hashmap *ids, const char *metric_id; struct evsel *ev; size_t ids_size, matched_events, i; + bool all_pmus =3D !strcmp(pmu, "all"); =20 *out_metric_events =3D NULL; ids_size =3D hashmap__size(ids); @@ -283,6 +287,8 @@ static int setup_metric_events(struct hashmap *ids, evlist__for_each_entry(metric_evlist, ev) { struct expr_id_data *val_ptr; =20 + if (!all_pmus && strcmp(ev->pmu_name, pmu)) + continue; /* * Check for duplicate events with the same name. For * example, uncore_imc/cas_count_read/ will turn into 6 @@ -355,8 +361,13 @@ static bool match_metric(const char *n, const char *li= st) return false; } =20 -static bool match_pm_metric(const struct pmu_metric *pm, const char *metri= c) +static bool match_pm_metric(const struct pmu_metric *pm, const char *pmu, = const char *metric) { + const char *pm_pmu =3D pm->pmu ?: "cpu"; + + if (strcmp(pmu, "all") && strcmp(pm_pmu, pmu)) + return false; + return match_metric(pm->metric_group, metric) || match_metric(pm->metric_name, metric); } @@ -766,6 +777,7 @@ struct visited_metric { =20 struct metricgroup_add_iter_data { struct list_head *metric_list; + const char *pmu; const char *metric_name; const char *modifier; int *ret; @@ -779,7 +791,8 @@ struct metricgroup_add_iter_data { const struct pmu_metrics_table *table; }; =20 -static bool metricgroup__find_metric(const char *metric, +static bool metricgroup__find_metric(const char *pmu, + const char *metric, const struct pmu_metrics_table *table, struct pmu_metric *pm); =20 @@ -798,6 +811,7 @@ static int add_metric(struct list_head *metric_list, * resolve_metric - Locate metrics within the root metric and recursively = add * references to them. * @metric_list: The list the metric is added to. + * @pmu: The PMU name to resolve metrics on, or "all" for all PMUs. * @modifier: if non-null event modifiers like "u". * @metric_no_group: Should events written to events be grouped "{}" or * global. Grouping is the default but due to multiplexi= ng the @@ -813,6 +827,7 @@ static int add_metric(struct list_head *metric_list, * architecture perf is running upon. */ static int resolve_metric(struct list_head *metric_list, + const char *pmu, const char *modifier, bool metric_no_group, bool metric_no_threshold, @@ -842,7 +857,7 @@ static int resolve_metric(struct list_head *metric_list, hashmap__for_each_entry(root_metric->pctx->ids, cur, bkt) { struct pmu_metric pm; =20 - if (metricgroup__find_metric(cur->pkey, table, &pm)) { + if (metricgroup__find_metric(pmu, cur->pkey, table, &pm)) { pending =3D realloc(pending, (pending_cnt + 1) * sizeof(struct to_resolve)); if (!pending) @@ -993,9 +1008,12 @@ static int __add_metric(struct list_head *metric_list, } if (!ret) { /* Resolve referenced metrics. */ - ret =3D resolve_metric(metric_list, modifier, metric_no_group, + const char *pmu =3D pm->pmu ?: "cpu"; + + ret =3D resolve_metric(metric_list, pmu, modifier, metric_no_group, metric_no_threshold, user_requested_cpu_list, - system_wide, root_metric, &visited_node, table); + system_wide, root_metric, &visited_node, + table); } if (ret) { if (is_root) @@ -1008,6 +1026,7 @@ static int __add_metric(struct list_head *metric_list, } =20 struct metricgroup__find_metric_data { + const char *pmu; const char *metric; struct pmu_metric *pm; }; @@ -1017,6 +1036,10 @@ static int metricgroup__find_metric_callback(const s= truct pmu_metric *pm, void *vdata) { struct metricgroup__find_metric_data *data =3D vdata; + const char *pm_pmu =3D pm->pmu ?: "cpu"; + + if (strcmp(data->pmu, "all") && strcmp(pm_pmu, data->pmu)) + return 0; =20 if (!match_metric(pm->metric_name, data->metric)) return 0; @@ -1025,11 +1048,13 @@ static int metricgroup__find_metric_callback(const = struct pmu_metric *pm, return 1; } =20 -static bool metricgroup__find_metric(const char *metric, +static bool metricgroup__find_metric(const char *pmu, + const char *metric, const struct pmu_metrics_table *table, struct pmu_metric *pm) { struct metricgroup__find_metric_data data =3D { + .pmu =3D pmu, .metric =3D metric, .pm =3D pm, }; @@ -1083,7 +1108,7 @@ static int metricgroup__add_metric_sys_event_iter(con= st struct pmu_metric *pm, struct metricgroup_add_iter_data *d =3D data; int ret; =20 - if (!match_pm_metric(pm, d->metric_name)) + if (!match_pm_metric(pm, d->pmu, d->metric_name)) return 0; =20 ret =3D add_metric(d->metric_list, pm, d->modifier, d->metric_no_group, @@ -1128,6 +1153,7 @@ static int metric_list_cmp(void *priv __maybe_unused,= const struct list_head *l, =20 struct metricgroup__add_metric_data { struct list_head *list; + const char *pmu; const char *metric_name; const char *modifier; const char *user_requested_cpu_list; @@ -1144,10 +1170,7 @@ static int metricgroup__add_metric_callback(const st= ruct pmu_metric *pm, struct metricgroup__add_metric_data *data =3D vdata; int ret =3D 0; =20 - if (pm->metric_expr && - (match_metric(pm->metric_group, data->metric_name) || - match_metric(pm->metric_name, data->metric_name))) { - + if (pm->metric_expr && match_pm_metric(pm, data->pmu, data->metric_name))= { data->has_match =3D true; ret =3D add_metric(data->list, pm, data->modifier, data->metric_no_group, data->metric_no_threshold, data->user_requested_cpu_list, @@ -1159,6 +1182,7 @@ static int metricgroup__add_metric_callback(const str= uct pmu_metric *pm, =20 /** * metricgroup__add_metric - Find and add a metric, or a metric group. + * @pmu: The PMU name to search for metrics on, or "all" for all PMUs. * @metric_name: The name of the metric or metric group. For example, "IPC" * could be the name of a metric and "TopDownL1" the name of= a * metric group. @@ -1172,7 +1196,7 @@ static int metricgroup__add_metric_callback(const str= uct pmu_metric *pm, * @table: The table that is searched for metrics, most commonly the table= for the * architecture perf is running upon. */ -static int metricgroup__add_metric(const char *metric_name, const char *mo= difier, +static int metricgroup__add_metric(const char *pmu, const char *metric_nam= e, const char *modifier, bool metric_no_group, bool metric_no_threshold, const char *user_requested_cpu_list, bool system_wide, @@ -1186,6 +1210,7 @@ static int metricgroup__add_metric(const char *metric= _name, const char *modifier { struct metricgroup__add_metric_data data =3D { .list =3D &list, + .pmu =3D pmu, .metric_name =3D metric_name, .modifier =3D modifier, .metric_no_group =3D metric_no_group, @@ -1210,6 +1235,7 @@ static int metricgroup__add_metric(const char *metric= _name, const char *modifier .fn =3D metricgroup__add_metric_sys_event_iter, .data =3D (void *) &(struct metricgroup_add_iter_data) { .metric_list =3D &list, + .pmu =3D pmu, .metric_name =3D metric_name, .modifier =3D modifier, .metric_no_group =3D metric_no_group, @@ -1239,6 +1265,7 @@ static int metricgroup__add_metric(const char *metric= _name, const char *modifier /** * metricgroup__add_metric_list - Find and add metrics, or metric groups, * specified in a list. + * @pmu: A pmu to restrict the metrics to, or "all" for all PMUS. * @list: the list of metrics or metric groups. For example, "IPC,CPI,TopD= ownL1" * would match the IPC and CPI metrics, and TopDownL1 would match a= ll * the metrics in the TopDownL1 group. @@ -1251,7 +1278,8 @@ static int metricgroup__add_metric(const char *metric= _name, const char *modifier * @table: The table that is searched for metrics, most commonly the table= for the * architecture perf is running upon. */ -static int metricgroup__add_metric_list(const char *list, bool metric_no_g= roup, +static int metricgroup__add_metric_list(const char *pmu, const char *list, + bool metric_no_group, bool metric_no_threshold, const char *user_requested_cpu_list, bool system_wide, struct list_head *metric_list, @@ -1270,7 +1298,7 @@ static int metricgroup__add_metric_list(const char *l= ist, bool metric_no_group, if (modifier) *modifier++ =3D '\0'; =20 - ret =3D metricgroup__add_metric(metric_name, modifier, + ret =3D metricgroup__add_metric(pmu, metric_name, modifier, metric_no_group, metric_no_threshold, user_requested_cpu_list, system_wide, metric_list, table); @@ -1460,7 +1488,8 @@ static int parse_ids(bool metric_no_merge, struct per= f_pmu *fake_pmu, return ret; } =20 -static int parse_groups(struct evlist *perf_evlist, const char *str, +static int parse_groups(struct evlist *perf_evlist, + const char *pmu, const char *str, bool metric_no_group, bool metric_no_merge, bool metric_no_threshold, @@ -1478,7 +1507,7 @@ static int parse_groups(struct evlist *perf_evlist, c= onst char *str, =20 if (metric_events_list->nr_entries =3D=3D 0) metricgroup__rblist_init(metric_events_list); - ret =3D metricgroup__add_metric_list(str, metric_no_group, metric_no_thre= shold, + ret =3D metricgroup__add_metric_list(pmu, str, metric_no_group, metric_no= _threshold, user_requested_cpu_list, system_wide, &metric_list, table); if (ret) @@ -1535,6 +1564,11 @@ static int parse_groups(struct evlist *perf_evlist, = const char *str, strcmp(m->modifier, n->modifier))) continue; =20 + if ((!m->pmu && n->pmu) || + (m->pmu && !n->pmu) || + (m->pmu && n->pmu && strcmp(m->pmu, n->pmu))) + continue; + if (expr__subset_of_ids(n->pctx, m->pctx)) { pr_debug("Events in '%s' fully contained within '%s'\n", m->metric_name, n->metric_name); @@ -1552,7 +1586,8 @@ static int parse_groups(struct evlist *perf_evlist, c= onst char *str, =20 metric_evlist =3D m->evlist; } - ret =3D setup_metric_events(m->pctx->ids, metric_evlist, &metric_events); + ret =3D setup_metric_events(fake_pmu ? "all" : m->pmu, m->pctx->ids, + metric_evlist, &metric_events); if (ret) { pr_debug("Cannot resolve IDs for %s: %s\n", m->metric_name, m->metric_expr); @@ -1623,7 +1658,7 @@ int metricgroup__parse_groups(struct evlist *perf_evl= ist, if (!table) return -EINVAL; =20 - return parse_groups(perf_evlist, str, metric_no_group, metric_no_merge, + return parse_groups(perf_evlist, "all", str, metric_no_group, metric_no_m= erge, metric_no_threshold, user_requested_cpu_list, system_wide, /*fake_pmu=3D*/NULL, metric_events, table); } @@ -1633,7 +1668,7 @@ int metricgroup__parse_groups_test(struct evlist *evl= ist, const char *str, struct rblist *metric_events) { - return parse_groups(evlist, str, + return parse_groups(evlist, "all", str, /*metric_no_group=3D*/false, /*metric_no_merge=3D*/false, /*metric_no_threshold=3D*/false, @@ -1642,28 +1677,32 @@ int metricgroup__parse_groups_test(struct evlist *e= vlist, &perf_pmu__fake, metric_events, table); } =20 +struct metricgroup__has_metric_data { + const char *pmu; + const char *metric; +}; static int metricgroup__has_metric_callback(const struct pmu_metric *pm, const struct pmu_metrics_table *table __maybe_unused, void *vdata) { - const char *metric =3D vdata; - - if (match_metric(pm->metric_name, metric) || - match_metric(pm->metric_group, metric)) - return 1; + struct metricgroup__has_metric_data *data =3D vdata; =20 - return 0; + return match_pm_metric(pm, data->pmu, data->metric) ? 1 : 0; } =20 -bool metricgroup__has_metric(const char *metric) +bool metricgroup__has_metric(const char *pmu, const char *metric) { const struct pmu_metrics_table *table =3D pmu_metrics_table__find(); + struct metricgroup__has_metric_data data =3D { + .pmu =3D pmu, + .metric =3D metric, + }; =20 if (!table) return false; =20 - return pmu_metrics_table_for_each_metric(table, metricgroup__has_metric_c= allback, - (void *)metric) ? true : false; + return pmu_metrics_table_for_each_metric(table, metricgroup__has_metric_c= allback, &data) + ? true : false; } =20 static int metricgroup__topdown_max_level_callback(const struct pmu_metric= *pm, diff --git a/tools/perf/util/metricgroup.h b/tools/perf/util/metricgroup.h index 77472e35705e..08e9b9e953ec 100644 --- a/tools/perf/util/metricgroup.h +++ b/tools/perf/util/metricgroup.h @@ -80,7 +80,7 @@ int metricgroup__parse_groups_test(struct evlist *evlist, struct rblist *metric_events); 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Wed, 26 Apr 2023 00:06:00 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:46 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-37-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 36/40] perf metric: Json flag to not group events if gathering a metric group From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some metric groups have metrics that don't have fully overlapping events, meaning that the group's events become unique event groups that may need to multiplex with each other. This can be particularly unfortunate when the groups wouldn't need to multiplex because there are sufficient hardware counters. Add a flag so that if recording a metric group then the metrics within the group needn't use groups for their events. The flag is added to Intel TopdownL1 and TopdownL2 metrics. Signed-off-by: Ian Rogers --- .../arch/x86/alderlake/adl-metrics.json | 26 +++++++++++++++++++ .../arch/x86/alderlaken/adln-metrics.json | 14 ++++++++++ .../arch/x86/broadwell/bdw-metrics.json | 12 +++++++++ .../arch/x86/broadwellde/bdwde-metrics.json | 12 +++++++++ .../arch/x86/broadwellx/bdx-metrics.json | 12 +++++++++ .../arch/x86/cascadelakex/clx-metrics.json | 12 +++++++++ .../arch/x86/haswell/hsw-metrics.json | 12 +++++++++ .../arch/x86/haswellx/hsx-metrics.json | 12 +++++++++ .../arch/x86/icelake/icl-metrics.json | 12 +++++++++ .../arch/x86/icelakex/icx-metrics.json | 12 +++++++++ .../arch/x86/ivybridge/ivb-metrics.json | 12 +++++++++ .../arch/x86/ivytown/ivt-metrics.json | 12 +++++++++ .../arch/x86/jaketown/jkt-metrics.json | 12 +++++++++ .../arch/x86/sandybridge/snb-metrics.json | 12 +++++++++ .../arch/x86/sapphirerapids/spr-metrics.json | 12 +++++++++ .../arch/x86/skylake/skl-metrics.json | 12 +++++++++ .../arch/x86/skylakex/skx-metrics.json | 12 +++++++++ .../arch/x86/tigerlake/tgl-metrics.json | 12 +++++++++ tools/perf/pmu-events/jevents.py | 4 ++- tools/perf/pmu-events/pmu-events.h | 1 + tools/perf/util/metricgroup.c | 5 +++- 21 files changed, 240 insertions(+), 2 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json b/to= ols/perf/pmu-events/arch/x86/alderlake/adl-metrics.json index d09361dacd4f..4c2a14ea5a1c 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json @@ -133,6 +133,7 @@ "MetricGroup": "TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "Counts the total number of issue slots that= were not consumed by the backend due to backend stalls. Note that uops mu= st be available for consumption in order for this event to count. If a uop= is not available (IQ is empty), this event will not count. The rest of t= hese subevents count backend stalls, in cycles, due to an outstanding reque= st which is memory bound vs core bound. The subevents are not slot based = events and therefore can not be precisely added or subtracted from the Back= end_Bound_Aux subevents which are slot based.", "ScaleUnit": "100%", "Unit": "cpu_atom" @@ -143,6 +144,7 @@ "MetricGroup": "TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound_aux", "MetricThreshold": "tma_backend_bound_aux > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "Counts the total number of issue slots that= were not consumed by the backend due to backend stalls. Note that UOPS mu= st be available for consumption in order for this event to count. If a uop= is not available (IQ is empty), this event will not count. All of these s= ubevents count backend stalls, in slots, due to a resource limitation. Th= ese are not cycle based events and therefore can not be precisely added or = subtracted from the Backend_Bound subevents which are cycle based. These s= ubevents are supplementary to Backend_Bound and can be used to analyze resu= lts from a resource perspective at allocation.", "ScaleUnit": "100%", "Unit": "cpu_atom" @@ -153,6 +155,7 @@ "MetricGroup": "TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "Counts the total number of issue slots that = were not consumed by the backend because allocation is stalled due to a mis= predicted jump or a machine clear. Only issue slots wasted due to fast nuke= s such as memory ordering nukes are counted. Other nukes are not accounted = for. Counts all issue slots blocked during this recovery window including r= elevant microcode flows and while uops are not yet available in the instruc= tion queue (IQ). Also includes the issue slots that were consumed by the ba= ckend but were thrown away because they were younger than the mispredict or= machine clear.", "ScaleUnit": "100%", "Unit": "cpu_atom" @@ -163,6 +166,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", "MetricName": "tma_base", "MetricThreshold": "tma_base > 0.6", + "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%", "Unit": "cpu_atom" }, @@ -182,6 +186,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.05", + "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%", "Unit": "cpu_atom" }, @@ -209,6 +214,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1", + "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%", "Unit": "cpu_atom" }, @@ -255,6 +261,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1", + "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%", "Unit": "cpu_atom" }, @@ -264,6 +271,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.15", + "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%", "Unit": "cpu_atom" }, @@ -291,6 +299,7 @@ "MetricGroup": "TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "ScaleUnit": "100%", "Unit": "cpu_atom" }, @@ -593,6 +602,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.05", + "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%", "Unit": "cpu_atom" }, @@ -611,6 +621,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2", + "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%", "Unit": "cpu_atom" }, @@ -629,6 +640,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", "MetricName": "tma_ms_uops", "MetricThreshold": "tma_ms_uops > 0.05", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "Counts the number of uops that are from the = complex flows issued by the micro-sequencer (MS). This includes uops from = flows due to complex instructions, faults, assists, and inserted flows.", "ScaleUnit": "100%", "Unit": "cpu_atom" @@ -729,6 +741,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_aux_group= ", "MetricName": "tma_resource_bound", "MetricThreshold": "tma_resource_bound > 0.2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "Counts the total number of issue slots that= were not consumed by the backend due to backend stalls. Note that uops mu= st be available for consumption in order for this event to count. If a uop= is not available (IQ is empty), this event will not count.", "ScaleUnit": "100%", "Unit": "cpu_atom" @@ -739,6 +752,7 @@ "MetricGroup": "TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.75", + "MetricgroupNoGroup": "TopdownL1", "ScaleUnit": "100%", "Unit": "cpu_atom" }, @@ -848,6 +862,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", "ScaleUnit": "100%", "Unit": "cpu_core" @@ -858,6 +873,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%", "Unit": "cpu_core" @@ -868,6 +884,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS. Related metrics: = tma_info_branch_misprediction_cost, tma_info_mispredictions, tma_mispredict= s_resteers", "ScaleUnit": "100%", "Unit": "cpu_core" @@ -919,6 +936,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%", "Unit": "cpu_core" @@ -1031,6 +1049,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 6 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", "ScaleUnit": "100%", "Unit": "cpu_core" @@ -1041,6 +1060,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_= 16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", "ScaleUnit": "100%", "Unit": "cpu_core" @@ -1122,6 +1142,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound. Sample with: FRONTE= ND_RETIRED.LATENCY_GE_4_PS", "ScaleUnit": "100%", "Unit": "cpu_core" @@ -1142,6 +1163,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences. Sample with: UOPS_RETIRED.HEA= VY", "ScaleUnit": "100%", "Unit": "cpu_core" @@ -2032,6 +2054,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%", "Unit": "cpu_core" @@ -2091,6 +2114,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sh= aring, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_c= ache", "ScaleUnit": "100%", "Unit": "cpu_core" @@ -2121,6 +2145,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%", "Unit": "cpu_core" @@ -2321,6 +2346,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .SLOTS", "ScaleUnit": "100%", "Unit": "cpu_core" diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json b/= tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json index 1a85d935c733..0402adbf7d92 100644 --- a/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json +++ b/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json @@ -98,6 +98,7 @@ "MetricGroup": "TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "Counts the total number of issue slots that= were not consumed by the backend due to backend stalls. Note that uops mu= st be available for consumption in order for this event to count. If a uop= is not available (IQ is empty), this event will not count. The rest of t= hese subevents count backend stalls, in cycles, due to an outstanding reque= st which is memory bound vs core bound. The subevents are not slot based = events and therefore can not be precisely added or subtracted from the Back= end_Bound_Aux subevents which are slot based.", "ScaleUnit": "100%" }, @@ -107,6 +108,7 @@ "MetricGroup": "TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound_aux", "MetricThreshold": "tma_backend_bound_aux > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "Counts the total number of issue slots that= were not consumed by the backend due to backend stalls. Note that UOPS mu= st be available for consumption in order for this event to count. If a uop= is not available (IQ is empty), this event will not count. All of these s= ubevents count backend stalls, in slots, due to a resource limitation. Th= ese are not cycle based events and therefore can not be precisely added or = subtracted from the Backend_Bound subevents which are cycle based. These s= ubevents are supplementary to Backend_Bound and can be used to analyze resu= lts from a resource perspective at allocation.", "ScaleUnit": "100%" }, @@ -116,6 +118,7 @@ "MetricGroup": "TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "Counts the total number of issue slots that = were not consumed by the backend because allocation is stalled due to a mis= predicted jump or a machine clear. Only issue slots wasted due to fast nuke= s such as memory ordering nukes are counted. Other nukes are not accounted = for. Counts all issue slots blocked during this recovery window including r= elevant microcode flows and while uops are not yet available in the instruc= tion queue (IQ). Also includes the issue slots that were consumed by the ba= ckend but were thrown away because they were younger than the mispredict or= machine clear.", "ScaleUnit": "100%" }, @@ -125,6 +128,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", "MetricName": "tma_base", "MetricThreshold": "tma_base > 0.6", + "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%" }, { @@ -142,6 +146,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.05", + "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%" }, { @@ -166,6 +171,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1", + "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%" }, { @@ -207,6 +213,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1", + "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%" }, { @@ -215,6 +222,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.15", + "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%" }, { @@ -239,6 +247,7 @@ "MetricGroup": "TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "ScaleUnit": "100%" }, { @@ -499,6 +508,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.05", + "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%" }, { @@ -515,6 +525,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2", + "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%" }, { @@ -531,6 +542,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", "MetricName": "tma_ms_uops", "MetricThreshold": "tma_ms_uops > 0.05", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "Counts the number of uops that are from the = complex flows issued by the micro-sequencer (MS). This includes uops from = flows due to complex instructions, faults, assists, and inserted flows.", "ScaleUnit": "100%" }, @@ -620,6 +632,7 @@ "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_aux_group= ", "MetricName": "tma_resource_bound", "MetricThreshold": "tma_resource_bound > 0.2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "Counts the total number of issue slots that= were not consumed by the backend due to backend stalls. Note that uops mu= st be available for consumption in order for this event to count. If a uop= is not available (IQ is empty), this event will not count.", "ScaleUnit": "100%" }, @@ -629,6 +642,7 @@ "MetricGroup": "TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.75", + "MetricgroupNoGroup": "TopdownL1", "ScaleUnit": "100%" }, { diff --git a/tools/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json b/to= ols/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json index 51cf8560a8d3..f9e2316601e1 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json @@ -103,6 +103,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound.", "ScaleUnit": "100%" }, @@ -112,6 +113,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%" }, @@ -122,6 +124,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics:= tma_info_branch_misprediction_cost, tma_mispredicts_resteers", "ScaleUnit": "100%" }, @@ -170,6 +173,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%" }, @@ -263,6 +267,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 4 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Rel= ated metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_iptb, tma_l= cp", "ScaleUnit": "100%" }, @@ -272,6 +277,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", "ScaleUnit": "100%" }, @@ -326,6 +332,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound.", "ScaleUnit": "100%" }, @@ -335,6 +342,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences.", "ScaleUnit": "100%" }, @@ -828,6 +836,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, @@ -858,6 +867,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sh= aring, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_c= ache", "ScaleUnit": "100%" }, @@ -886,6 +896,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%" }, @@ -1048,6 +1059,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .RETIRE_SLOTS", "ScaleUnit": "100%" }, diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json = b/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json index fb57c7382408..e9c46d336a8e 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json @@ -97,6 +97,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", "ScaleUnit": "100%" }, @@ -106,6 +107,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%" }, @@ -116,6 +118,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS. Related metrics: = tma_info_branch_misprediction_cost, tma_mispredicts_resteers", "ScaleUnit": "100%" }, @@ -164,6 +167,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%" }, @@ -248,6 +252,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 4 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_dsb_coverage, tma_info_iptb, tma_lcp", "ScaleUnit": "100%" }, @@ -257,6 +262,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_= 16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", "ScaleUnit": "100%" }, @@ -311,6 +317,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound. Sample with: FRONTE= ND_RETIRED.LATENCY_GE_4_PS", "ScaleUnit": "100%" }, @@ -320,6 +327,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences.", "ScaleUnit": "100%" }, @@ -795,6 +803,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, @@ -825,6 +834,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sh= aring, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_c= ache", "ScaleUnit": "100%" }, @@ -853,6 +863,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%" }, @@ -1013,6 +1024,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .SLOTS", "ScaleUnit": "100%" }, diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json b/t= ools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json index 65ec0c9e55d1..437b9867acb9 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json @@ -103,6 +103,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound.", "ScaleUnit": "100%" }, @@ -112,6 +113,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%" }, @@ -122,6 +124,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics:= tma_info_branch_misprediction_cost, tma_mispredicts_resteers", "ScaleUnit": "100%" }, @@ -170,6 +173,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%" }, @@ -263,6 +267,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 4 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Rel= ated metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_iptb, tma_l= cp", "ScaleUnit": "100%" }, @@ -272,6 +277,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", "ScaleUnit": "100%" }, @@ -326,6 +332,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound.", "ScaleUnit": "100%" }, @@ -335,6 +342,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences.", "ScaleUnit": "100%" }, @@ -829,6 +837,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, @@ -869,6 +878,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sh= aring, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_c= ache", "ScaleUnit": "100%" }, @@ -897,6 +907,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%" }, @@ -1079,6 +1090,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .RETIRE_SLOTS", "ScaleUnit": "100%" }, diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json b= /tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json index 8f7dc72accd0..875c766222e3 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json @@ -101,6 +101,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound.", "ScaleUnit": "100%" }, @@ -110,6 +111,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%" }, @@ -120,6 +122,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics:= tma_info_branch_misprediction_cost, tma_info_mispredictions, tma_mispredic= ts_resteers", "ScaleUnit": "100%" }, @@ -167,6 +170,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%" }, @@ -271,6 +275,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 4 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", "ScaleUnit": "100%" }, @@ -280,6 +285,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_= 16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", "ScaleUnit": "100%" }, @@ -354,6 +360,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound. Sample with: FRONTE= ND_RETIRED.LATENCY_GE_4_PS", "ScaleUnit": "100%" }, @@ -372,6 +379,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences.", "ScaleUnit": "100%" }, @@ -1142,6 +1150,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, @@ -1196,6 +1205,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sh= aring, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_c= ache", "ScaleUnit": "100%" }, @@ -1224,6 +1234,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%" }, @@ -1458,6 +1469,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .RETIRE_SLOTS", "ScaleUnit": "100%" }, diff --git a/tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json b/tool= s/perf/pmu-events/arch/x86/haswell/hsw-metrics.json index 2528418200bb..9570a88d6d1c 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json +++ b/tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json @@ -103,6 +103,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound.", "ScaleUnit": "100%" }, @@ -112,6 +113,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%" }, @@ -122,6 +124,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics:= tma_info_branch_misprediction_cost, tma_mispredicts_resteers", "ScaleUnit": "100%" }, @@ -161,6 +164,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%" }, @@ -254,6 +258,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 4 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Rel= ated metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_iptb, tma_l= cp", "ScaleUnit": "100%" }, @@ -263,6 +268,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", "ScaleUnit": "100%" }, @@ -272,6 +278,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound.", "ScaleUnit": "100%" }, @@ -281,6 +288,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences.", "ScaleUnit": "100%" }, @@ -663,6 +671,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, @@ -693,6 +702,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sh= aring, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_c= ache", "ScaleUnit": "100%" }, @@ -721,6 +731,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%" }, @@ -874,6 +885,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .RETIRE_SLOTS", "ScaleUnit": "100%" }, diff --git a/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json b/too= ls/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json index 11f152c346eb..a522202cf684 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json @@ -103,6 +103,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound.", "ScaleUnit": "100%" }, @@ -112,6 +113,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%" }, @@ -122,6 +124,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics:= tma_info_branch_misprediction_cost, tma_mispredicts_resteers", "ScaleUnit": "100%" }, @@ -161,6 +164,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%" }, @@ -254,6 +258,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 4 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Rel= ated metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_iptb, tma_l= cp", "ScaleUnit": "100%" }, @@ -263,6 +268,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", "ScaleUnit": "100%" }, @@ -272,6 +278,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound.", "ScaleUnit": "100%" }, @@ -281,6 +288,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences.", "ScaleUnit": "100%" }, @@ -664,6 +672,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, @@ -704,6 +713,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sh= aring, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_c= ache", "ScaleUnit": "100%" }, @@ -732,6 +742,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%" }, @@ -905,6 +916,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .RETIRE_SLOTS", "ScaleUnit": "100%" }, diff --git a/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json b/tool= s/perf/pmu-events/arch/x86/icelake/icl-metrics.json index cb58317860ea..ae8a96ec7fa5 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json @@ -115,6 +115,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", "ScaleUnit": "100%" }, @@ -124,6 +125,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%" }, @@ -141,6 +143,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics:= tma_info_branch_misprediction_cost, tma_info_mispredictions, tma_mispredic= ts_resteers", "ScaleUnit": "100%" }, @@ -187,6 +190,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%" }, @@ -288,6 +292,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 5 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", "ScaleUnit": "100%" }, @@ -297,6 +302,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_= 16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", "ScaleUnit": "100%" }, @@ -370,6 +376,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound. Sample with: FRONTE= ND_RETIRED.LATENCY_GE_4_PS", "ScaleUnit": "100%" }, @@ -379,6 +386,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences.", "ScaleUnit": "100%" }, @@ -1120,6 +1128,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, @@ -1173,6 +1182,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sh= aring, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_c= ache", "ScaleUnit": "100%" }, @@ -1200,6 +1210,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%" }, @@ -1371,6 +1382,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .SLOTS", "ScaleUnit": "100%" }, diff --git a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json b/too= ls/perf/pmu-events/arch/x86/icelakex/icx-metrics.json index 76e60e3f9d31..b736fec164d0 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json @@ -80,6 +80,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", "ScaleUnit": "100%" }, @@ -89,6 +90,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%" }, @@ -106,6 +108,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics:= tma_info_branch_misprediction_cost, tma_info_mispredictions, tma_mispredic= ts_resteers", "ScaleUnit": "100%" }, @@ -152,6 +155,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%" }, @@ -253,6 +257,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 5 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", "ScaleUnit": "100%" }, @@ -262,6 +267,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_= 16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", "ScaleUnit": "100%" }, @@ -335,6 +341,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound. Sample with: FRONTE= ND_RETIRED.LATENCY_GE_4_PS", "ScaleUnit": "100%" }, @@ -344,6 +351,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences.", "ScaleUnit": "100%" }, @@ -1143,6 +1151,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, @@ -1196,6 +1205,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sh= aring, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_c= ache", "ScaleUnit": "100%" }, @@ -1223,6 +1233,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%" }, @@ -1421,6 +1432,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .SLOTS", "ScaleUnit": "100%" }, diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json b/to= ols/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json index 5247f69c13b6..11080ccffd51 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json @@ -103,6 +103,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound.", "ScaleUnit": "100%" }, @@ -112,6 +113,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%" }, @@ -122,6 +124,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics:= tma_info_branch_misprediction_cost, tma_mispredicts_resteers", "ScaleUnit": "100%" }, @@ -161,6 +164,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%" }, @@ -254,6 +258,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 4 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Rel= ated metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_iptb, tma_l= cp", "ScaleUnit": "100%" }, @@ -263,6 +268,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", "ScaleUnit": "100%" }, @@ -299,6 +305,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound.", "ScaleUnit": "100%" }, @@ -308,6 +315,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences.", "ScaleUnit": "100%" }, @@ -724,6 +732,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, @@ -754,6 +763,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sh= aring, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_c= ache", "ScaleUnit": "100%" }, @@ -782,6 +792,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%" }, @@ -917,6 +928,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .RETIRE_SLOTS", "ScaleUnit": "100%" }, diff --git a/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json b/tool= s/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json index 89469b10fa30..65a46d659c0a 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json @@ -103,6 +103,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound.", "ScaleUnit": "100%" }, @@ -112,6 +113,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%" }, @@ -122,6 +124,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics:= tma_info_branch_misprediction_cost, tma_mispredicts_resteers", "ScaleUnit": "100%" }, @@ -161,6 +164,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%" }, @@ -254,6 +258,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 4 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Rel= ated metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_iptb, tma_l= cp", "ScaleUnit": "100%" }, @@ -263,6 +268,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", "ScaleUnit": "100%" }, @@ -299,6 +305,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound.", "ScaleUnit": "100%" }, @@ -308,6 +315,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences.", "ScaleUnit": "100%" }, @@ -725,6 +733,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, @@ -765,6 +774,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sh= aring, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_c= ache", "ScaleUnit": "100%" }, @@ -793,6 +803,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%" }, @@ -948,6 +959,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .RETIRE_SLOTS", "ScaleUnit": "100%" }, diff --git a/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json b/too= ls/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json index e8f4e5c01c9f..66a6f657bd6f 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json @@ -76,6 +76,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound.", "ScaleUnit": "100%" }, @@ -85,6 +86,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%" }, @@ -95,6 +97,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics:= tma_info_branch_misprediction_cost, tma_mispredicts_resteers", "ScaleUnit": "100%" }, @@ -114,6 +117,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%" }, @@ -160,6 +164,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 4 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Rel= ated metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_lcp", "ScaleUnit": "100%" }, @@ -169,6 +174,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", "ScaleUnit": "100%" }, @@ -205,6 +211,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound.", "ScaleUnit": "100%" }, @@ -214,6 +221,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences.", "ScaleUnit": "100%" }, @@ -412,6 +420,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, @@ -422,6 +431,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches= , tma_remote_cache", "ScaleUnit": "100%" }, @@ -450,6 +460,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%" }, @@ -487,6 +498,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .RETIRE_SLOTS", "ScaleUnit": "100%" }, diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json b/= tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json index 4a99fe515f4b..4b8bc19392a4 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json @@ -76,6 +76,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound.", "ScaleUnit": "100%" }, @@ -85,6 +86,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%" }, @@ -95,6 +97,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics:= tma_info_branch_misprediction_cost, tma_mispredicts_resteers", "ScaleUnit": "100%" }, @@ -114,6 +117,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%" }, @@ -160,6 +164,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 4 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Rel= ated metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_lcp", "ScaleUnit": "100%" }, @@ -169,6 +174,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", "ScaleUnit": "100%" }, @@ -205,6 +211,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound.", "ScaleUnit": "100%" }, @@ -214,6 +221,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences.", "ScaleUnit": "100%" }, @@ -411,6 +419,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, @@ -421,6 +430,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches= , tma_remote_cache", "ScaleUnit": "100%" }, @@ -449,6 +459,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%" }, @@ -486,6 +497,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .RETIRE_SLOTS", "ScaleUnit": "100%" }, diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json= b/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json index 527d40dde003..4308e2483112 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json @@ -87,6 +87,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", "ScaleUnit": "100%" }, @@ -96,6 +97,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%" }, @@ -105,6 +107,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS. Related metrics: = tma_info_branch_misprediction_cost, tma_info_mispredictions, tma_mispredict= s_resteers", "ScaleUnit": "100%" }, @@ -151,6 +154,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%" }, @@ -252,6 +256,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 6 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", "ScaleUnit": "100%" }, @@ -261,6 +266,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_= 16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", "ScaleUnit": "100%" }, @@ -352,6 +358,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound. Sample with: FRONTE= ND_RETIRED.LATENCY_GE_4_PS", "ScaleUnit": "100%" }, @@ -370,6 +377,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences. Sample with: UOPS_RETIRED.HEA= VY", "ScaleUnit": "100%" }, @@ -1225,6 +1233,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, @@ -1278,6 +1287,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sh= aring, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_c= ache", "ScaleUnit": "100%" }, @@ -1313,6 +1323,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%" }, @@ -1520,6 +1531,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .SLOTS", "ScaleUnit": "100%" }, diff --git a/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json b/tool= s/perf/pmu-events/arch/x86/skylake/skl-metrics.json index a6d212b349f5..21ef6c9be816 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json @@ -101,6 +101,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound.", "ScaleUnit": "100%" }, @@ -110,6 +111,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%" }, @@ -120,6 +122,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics:= tma_info_branch_misprediction_cost, tma_info_mispredictions, tma_mispredic= ts_resteers", "ScaleUnit": "100%" }, @@ -167,6 +170,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%" }, @@ -271,6 +275,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 4 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", "ScaleUnit": "100%" }, @@ -280,6 +285,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_= 16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", "ScaleUnit": "100%" }, @@ -345,6 +351,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound. Sample with: FRONTE= ND_RETIRED.LATENCY_GE_4_PS", "ScaleUnit": "100%" }, @@ -363,6 +370,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences.", "ScaleUnit": "100%" }, @@ -1065,6 +1073,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, @@ -1110,6 +1119,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sh= aring, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_c= ache", "ScaleUnit": "100%" }, @@ -1138,6 +1148,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%" }, @@ -1343,6 +1354,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .RETIRE_SLOTS", "ScaleUnit": "100%" }, diff --git a/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json b/too= ls/perf/pmu-events/arch/x86/skylakex/skx-metrics.json index fa2f7f126a30..eb6f12c0343d 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json @@ -101,6 +101,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound.", "ScaleUnit": "100%" }, @@ -110,6 +111,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%" }, @@ -120,6 +122,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics:= tma_info_branch_misprediction_cost, tma_info_mispredictions, tma_mispredic= ts_resteers", "ScaleUnit": "100%" }, @@ -167,6 +170,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%" }, @@ -271,6 +275,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 4 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", "ScaleUnit": "100%" }, @@ -280,6 +285,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_= 16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", "ScaleUnit": "100%" }, @@ -354,6 +360,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound. Sample with: FRONTE= ND_RETIRED.LATENCY_GE_4_PS", "ScaleUnit": "100%" }, @@ -372,6 +379,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences.", "ScaleUnit": "100%" }, @@ -1123,6 +1131,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, @@ -1177,6 +1186,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sh= aring, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_c= ache", "ScaleUnit": "100%" }, @@ -1205,6 +1215,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%" }, @@ -1429,6 +1440,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .RETIRE_SLOTS", "ScaleUnit": "100%" }, diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json b/to= ols/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json index 6ac4a9e5d013..ae62bacf9f5e 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json @@ -109,6 +109,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", "ScaleUnit": "100%" }, @@ -118,6 +119,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", "ScaleUnit": "100%" }, @@ -135,6 +137,7 @@ "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics:= tma_info_branch_misprediction_cost, tma_info_mispredictions, tma_mispredic= ts_resteers", "ScaleUnit": "100%" }, @@ -181,6 +184,7 @@ "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", "ScaleUnit": "100%" }, @@ -282,6 +286,7 @@ "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group;tma_issueFB", "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound= > 0.15 & tma_info_ipc / 5 > 0.35", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", "ScaleUnit": "100%" }, @@ -291,6 +296,7 @@ "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_= 16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", "ScaleUnit": "100%" }, @@ -364,6 +370,7 @@ "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound. Sample with: FRONTE= ND_RETIRED.LATENCY_GE_4_PS", "ScaleUnit": "100%" }, @@ -373,6 +380,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences.", "ScaleUnit": "100%" }, @@ -1134,6 +1142,7 @@ "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_light_operations", "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized software = running on Intel Core/Xeon products. While this often indicates efficient X= 86 instructions were executed; high value does not necessarily mean better = performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, @@ -1187,6 +1196,7 @@ "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sh= aring, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_c= ache", "ScaleUnit": "100%" }, @@ -1214,6 +1224,7 @@ "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2", "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", "ScaleUnit": "100%" }, @@ -1385,6 +1396,7 @@ "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1", "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .SLOTS", "ScaleUnit": "100%" }, diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jeven= ts.py index bbcaafaf7c25..b18dd2fcbf04 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -52,7 +52,8 @@ _json_event_attributes =3D [ # Attributes that are in pmu_metric rather than pmu_event. _json_metric_attributes =3D [ 'pmu', 'metric_name', 'metric_group', 'metric_expr', 'metric_threshold= ', - 'desc', 'long_desc', 'unit', 'compat', 'aggr_mode', 'event_grouping' + 'desc', 'long_desc', 'unit', 'compat', 'metricgroup_no_group', 'aggr_m= ode', + 'event_grouping' ] # Attributes that are bools or enum int values, encoded as '0', '1',... _json_enum_attributes =3D ['aggr_mode', 'deprecated', 'event_grouping', 'p= erpkg'] @@ -303,6 +304,7 @@ class JsonEvent: self.deprecated =3D jd.get('Deprecated') self.metric_name =3D jd.get('MetricName') self.metric_group =3D jd.get('MetricGroup') + self.metricgroup_no_group =3D jd.get('MetricgroupNoGroup') self.event_grouping =3D convert_metric_constraint(jd.get('MetricConstr= aint')) self.metric_expr =3D None if 'MetricExpr' in jd: diff --git a/tools/perf/pmu-events/pmu-events.h b/tools/perf/pmu-events/pmu= -events.h index 1dd8f35a2483..3549e6971a4d 100644 --- a/tools/perf/pmu-events/pmu-events.h +++ b/tools/perf/pmu-events/pmu-events.h @@ -60,6 +60,7 @@ struct pmu_metric { const char *compat; const char *desc; const char *long_desc; + const char *metricgroup_no_group; enum aggr_mode_class aggr_mode; enum metric_event_groups event_grouping; }; diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index 39fbdb5bab1f..17478eb33bdc 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -1171,8 +1171,11 @@ static int metricgroup__add_metric_callback(const st= ruct pmu_metric *pm, int ret =3D 0; =20 if (pm->metric_expr && match_pm_metric(pm, data->pmu, data->metric_name))= { + bool metric_no_group =3D data->metric_no_group || + match_metric(data->metric_name, pm->metricgroup_no_group); + data->has_match =3D true; - ret =3D add_metric(data->list, pm, data->modifier, data->metric_no_group, + ret =3D add_metric(data->list, pm, data->modifier, metric_no_group, data->metric_no_threshold, data->user_requested_cpu_list, data->system_wide, /*root_metric=3D*/NULL, /*visited_metrics=3D*/NULL, table); --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:40 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5DDBC77B60 for ; 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Wed, 26 Apr 2023 00:06:08 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:47 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-38-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 37/40] perf stat: Command line PMU metric filtering From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Wire up the --cputype value to limit which metrics are parsed. Signed-off-by: Ian Rogers --- tools/perf/builtin-stat.c | 20 ++++++++++++-------- tools/perf/util/metricgroup.c | 3 ++- tools/perf/util/metricgroup.h | 1 + 3 files changed, 15 insertions(+), 9 deletions(-) diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index 5dbdf001028b..67dc69270ae4 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -1783,6 +1783,7 @@ static int add_default_attributes(void) }; =20 struct perf_event_attr default_null_attrs[] =3D {}; + const char *pmu =3D parse_events_option_args.pmu_filter ?: "all"; =20 /* Set attrs if no event is selected and !null_run: */ if (stat_config.null_run) @@ -1794,11 +1795,11 @@ static int add_default_attributes(void) * will use this approach. To determine transaction support * on an architecture test for such a metric name. */ - if (!metricgroup__has_metric("all", "transaction")) { + if (!metricgroup__has_metric(pmu, "transaction")) { pr_err("Missing transaction metrics"); return -1; } - return metricgroup__parse_groups(evsel_list, "transaction", + return metricgroup__parse_groups(evsel_list, pmu, "transaction", stat_config.metric_no_group, stat_config.metric_no_merge, stat_config.metric_no_threshold, @@ -1823,7 +1824,7 @@ static int add_default_attributes(void) smi_reset =3D true; } =20 - if (!metricgroup__has_metric("all", "smi")) { + if (!metricgroup__has_metric(pmu, "smi")) { pr_err("Missing smi metrics"); return -1; } @@ -1831,7 +1832,7 @@ static int add_default_attributes(void) if (!force_metric_only) stat_config.metric_only =3D true; =20 - return metricgroup__parse_groups(evsel_list, "smi", + return metricgroup__parse_groups(evsel_list, pmu, "smi", stat_config.metric_no_group, stat_config.metric_no_merge, stat_config.metric_no_threshold, @@ -1864,7 +1865,8 @@ static int add_default_attributes(void) "Please print the result regularly, e.g. -I1000\n"); } str[8] =3D stat_config.topdown_level + '0'; - if (metricgroup__parse_groups(evsel_list, str, + if (metricgroup__parse_groups(evsel_list, + pmu, str, /*metric_no_group=3D*/false, /*metric_no_merge=3D*/false, /*metric_no_threshold=3D*/true, @@ -1898,14 +1900,14 @@ static int add_default_attributes(void) * Add TopdownL1 metrics if they exist. To minimize * multiplexing, don't request threshold computation. */ - if (metricgroup__has_metric("all", "TopdownL1")) { + if (metricgroup__has_metric(pmu, "TopdownL1")) { struct evlist *metric_evlist =3D evlist__new(); struct evsel *metric_evsel; =20 if (!metric_evlist) return -1; =20 - if (metricgroup__parse_groups(metric_evlist, "TopdownL1", + if (metricgroup__parse_groups(metric_evlist, pmu, "TopdownL1", /*metric_no_group=3D*/false, /*metric_no_merge=3D*/false, /*metric_no_threshold=3D*/true, @@ -2429,7 +2431,9 @@ int cmd_stat(int argc, const char **argv) * knowing the target is system-wide. */ if (metrics) { - metricgroup__parse_groups(evsel_list, metrics, + const char *pmu =3D parse_events_option_args.pmu_filter ?: "all"; + + metricgroup__parse_groups(evsel_list, pmu, metrics, stat_config.metric_no_group, stat_config.metric_no_merge, stat_config.metric_no_threshold, diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index 17478eb33bdc..4245b23d8efe 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -1648,6 +1648,7 @@ static int parse_groups(struct evlist *perf_evlist, } =20 int metricgroup__parse_groups(struct evlist *perf_evlist, + const char *pmu, const char *str, bool metric_no_group, bool metric_no_merge, @@ -1661,7 +1662,7 @@ int metricgroup__parse_groups(struct evlist *perf_evl= ist, if (!table) return -EINVAL; =20 - return parse_groups(perf_evlist, "all", str, metric_no_group, metric_no_m= erge, + return parse_groups(perf_evlist, pmu, str, metric_no_group, metric_no_mer= ge, metric_no_threshold, user_requested_cpu_list, system_wide, /*fake_pmu=3D*/NULL, metric_events, table); } diff --git a/tools/perf/util/metricgroup.h b/tools/perf/util/metricgroup.h index 08e9b9e953ec..bf18274c15df 100644 --- a/tools/perf/util/metricgroup.h +++ b/tools/perf/util/metricgroup.h @@ -67,6 +67,7 @@ struct metric_event *metricgroup__lookup(struct rblist *m= etric_events, struct evsel *evsel, bool create); int metricgroup__parse_groups(struct evlist *perf_evlist, + const char *pmu, const char *str, bool metric_no_group, bool metric_no_merge, --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:40 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7AB31C7618E for ; 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Wed, 26 Apr 2023 00:06:16 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:48 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-39-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 38/40] perf vendor events intel: Correct alderlake metrics From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Fix the metrics tma_memory_bound on alderlake cpu_core and tma_microcode_sequencer on alderlake cpu_atom, where metrics had be rewritten across PMUs. Fix MEM_BOUND_STALLS_AT_RET_CORRECTION which is an aux metric but lacks a hash prefix. Add PMU prefixes for cpu_core/cpu_atom events to avoid wildcard opening the events. Signed-off-by: Ian Rogers --- .../arch/x86/alderlake/adl-metrics.json | 238 +++++++++--------- .../arch/x86/alderlaken/adln-metrics.json | 6 +- 2 files changed, 122 insertions(+), 122 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json b/to= ols/perf/pmu-events/arch/x86/alderlake/adl-metrics.json index 4c2a14ea5a1c..840f6f6fc8c5 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json @@ -151,7 +151,7 @@ }, { "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend because allocation is stalled due to a misp= redicted jump or a machine clear", - "MetricExpr": "(tma_info_slots - (TOPDOWN_FE_BOUND.ALL + TOPDOWN_B= E_BOUND.ALL + TOPDOWN_RETIRING.ALL)) / tma_info_slots", + "MetricExpr": "(tma_info_slots - (cpu_atom@TOPDOWN_FE_BOUND.ALL@ += cpu_atom@TOPDOWN_BE_BOUND.ALL@ + cpu_atom@TOPDOWN_RETIRING.ALL@)) / tma_in= fo_slots", "MetricGroup": "TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", @@ -162,7 +162,7 @@ }, { "BriefDescription": "Counts the number of uops that are not from t= he microsequencer.", - "MetricExpr": "(TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS) / tma_info= _slots", + "MetricExpr": "(cpu_atom@TOPDOWN_RETIRING.ALL@ - cpu_atom@UOPS_RET= IRED.MS@) / tma_info_slots", "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", "MetricName": "tma_base", "MetricThreshold": "tma_base > 0.6", @@ -229,7 +229,7 @@ }, { "BriefDescription": "Counts the number of machine clears relative = to the number of nuke slots due to memory disambiguation.", - "MetricExpr": "tma_nuke * (MACHINE_CLEARS.DISAMBIGUATION / MACHINE= _CLEARS.SLOW)", + "MetricExpr": "tma_nuke * (cpu_atom@MACHINE_CLEARS.DISAMBIGUATION@= / cpu_atom@MACHINE_CLEARS.SLOW@)", "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", "MetricName": "tma_disambiguation", "MetricThreshold": "tma_disambiguation > 0.02", @@ -239,7 +239,7 @@ { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / tma_info_clks - ME= M_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOU= ND_STALLS.LOAD", + "MetricExpr": "cpu_atom@MEM_BOUND_STALLS.LOAD_DRAM_HIT@ / tma_info= _clks - max((cpu_atom@MEM_BOUND_STALLS.LOAD@ - cpu_atom@LD_HEAD.L1_MISS_AT_= RET@) / tma_info_clks, 0) * cpu_atom@MEM_BOUND_STALLS.LOAD_DRAM_HIT@ / cpu_= atom@MEM_BOUND_STALLS.LOAD@", "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_dram_bound", "MetricThreshold": "tma_dram_bound > 0.1", @@ -277,7 +277,7 @@ }, { "BriefDescription": "Counts the number of machine clears relative = to the number of nuke slots due to FP assists.", - "MetricExpr": "tma_nuke * (MACHINE_CLEARS.FP_ASSIST / MACHINE_CLEA= RS.SLOW)", + "MetricExpr": "tma_nuke * (cpu_atom@MACHINE_CLEARS.FP_ASSIST@ / cp= u_atom@MACHINE_CLEARS.SLOW@)", "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", "MetricName": "tma_fp_assist", "MetricThreshold": "tma_fp_assist > 0.02", @@ -314,7 +314,7 @@ }, { "BriefDescription": "Percentage of total non-speculative loads wit= h a address aliasing block", - "MetricExpr": "100 * LD_BLOCKS.4K_ALIAS / MEM_UOPS_RETIRED.ALL_LOA= DS", + "MetricExpr": "100 * cpu_atom@LD_BLOCKS.4K_ALIAS@ / MEM_UOPS_RETIR= ED.ALL_LOADS", "MetricName": "tma_info_address_alias_blocks", "Unit": "cpu_atom" }, @@ -334,14 +334,14 @@ }, { "BriefDescription": "", - "MetricExpr": "CPU_CLK_UNHALTED.CORE", + "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.CORE@", "MetricGroup": " ", "MetricName": "tma_info_clks", "Unit": "cpu_atom" }, { "BriefDescription": "", - "MetricExpr": "CPU_CLK_UNHALTED.CORE_P", + "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.CORE_P@", "MetricGroup": " ", "MetricName": "tma_info_clks_p", "Unit": "cpu_atom" @@ -383,35 +383,35 @@ }, { "BriefDescription": "Percentage of all uops which are FPDiv uops", - "MetricExpr": "100 * UOPS_RETIRED.FPDIV / UOPS_RETIRED.ALL", + "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.FPDIV@ / UOPS_RETIRED.A= LL", "MetricGroup": " ", "MetricName": "tma_info_fpdiv_uop_ratio", "Unit": "cpu_atom" }, { "BriefDescription": "Percentage of all uops which are IDiv uops", - "MetricExpr": "100 * UOPS_RETIRED.IDIV / UOPS_RETIRED.ALL", + "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.IDIV@ / UOPS_RETIRED.AL= L", "MetricGroup": " ", "MetricName": "tma_info_idiv_uop_ratio", "Unit": "cpu_atom" }, { "BriefDescription": "Percent of instruction miss cost that hit in = DRAM", - "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_DRAM_HIT / MEM_BOUND_= STALLS.IFETCH", + "MetricExpr": "100 * cpu_atom@MEM_BOUND_STALLS.IFETCH_DRAM_HIT@ / = cpu_atom@MEM_BOUND_STALLS.IFETCH@", "MetricGroup": " ", "MetricName": "tma_info_inst_miss_cost_dramhit_percent", "Unit": "cpu_atom" }, { "BriefDescription": "Percent of instruction miss cost that hit in = the L2", - "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_L2_HIT / MEM_BOUND_ST= ALLS.IFETCH", + "MetricExpr": "100 * cpu_atom@MEM_BOUND_STALLS.IFETCH_L2_HIT@ / cp= u_atom@MEM_BOUND_STALLS.IFETCH@", "MetricGroup": " ", "MetricName": "tma_info_inst_miss_cost_l2hit_percent", "Unit": "cpu_atom" }, { "BriefDescription": "Percent of instruction miss cost that hit in = the L3", - "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_LLC_HIT / MEM_BOUND_S= TALLS.IFETCH", + "MetricExpr": "100 * cpu_atom@MEM_BOUND_STALLS.IFETCH_LLC_HIT@ / c= pu_atom@MEM_BOUND_STALLS.IFETCH@", "MetricGroup": " ", "MetricName": "tma_info_inst_miss_cost_l3hit_percent", "Unit": "cpu_atom" @@ -439,7 +439,7 @@ }, { "BriefDescription": "Instructions per Far Branch", - "MetricExpr": "INST_RETIRED.ANY / (BR_INST_RETIRED.FAR_BRANCH / 2)= ", + "MetricExpr": "INST_RETIRED.ANY / (cpu_atom@BR_INST_RETIRED.FAR_BR= ANCH@ / 2)", "MetricGroup": " ", "MetricName": "tma_info_ipfarbranch", "Unit": "cpu_atom" @@ -453,7 +453,7 @@ }, { "BriefDescription": "Instructions per retired conditional Branch M= isprediction where the branch was not taken", - "MetricExpr": "INST_RETIRED.ANY / (BR_MISP_RETIRED.COND - BR_MISP_= RETIRED.COND_TAKEN)", + "MetricExpr": "INST_RETIRED.ANY / (cpu_atom@BR_MISP_RETIRED.COND@ = - cpu_atom@BR_MISP_RETIRED.COND_TAKEN@)", "MetricName": "tma_info_ipmisp_cond_ntaken", "Unit": "cpu_atom" }, @@ -498,20 +498,20 @@ }, { "BriefDescription": "Percentage of total non-speculative loads tha= t are splits", - "MetricExpr": "100 * MEM_UOPS_RETIRED.SPLIT_LOADS / MEM_UOPS_RETIR= ED.ALL_LOADS", + "MetricExpr": "100 * cpu_atom@MEM_UOPS_RETIRED.SPLIT_LOADS@ / MEM_= UOPS_RETIRED.ALL_LOADS", "MetricName": "tma_info_load_splits", "Unit": "cpu_atom" }, { "BriefDescription": "load ops retired per 1000 instruction", - "MetricExpr": "1e3 * MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY= ", + "MetricExpr": "1e3 * cpu_atom@MEM_UOPS_RETIRED.ALL_LOADS@ / INST_R= ETIRED.ANY", "MetricGroup": " ", "MetricName": "tma_info_memloadpki", "Unit": "cpu_atom" }, { "BriefDescription": "Percentage of all uops which are ucode ops", - "MetricExpr": "100 * UOPS_RETIRED.MS / UOPS_RETIRED.ALL", + "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.MS@ / UOPS_RETIRED.ALL", "MetricGroup": " ", "MetricName": "tma_info_microcode_uop_ratio", "Unit": "cpu_atom" @@ -525,7 +525,7 @@ }, { "BriefDescription": "Percentage of total non-speculative loads wit= h a store forward or unknown store address block", - "MetricExpr": "100 * LD_BLOCKS.DATA_UNKNOWN / MEM_UOPS_RETIRED.ALL= _LOADS", + "MetricExpr": "100 * cpu_atom@LD_BLOCKS.DATA_UNKNOWN@ / MEM_UOPS_R= ETIRED.ALL_LOADS", "MetricName": "tma_info_store_fwd_blocks", "Unit": "cpu_atom" }, @@ -545,7 +545,7 @@ }, { "BriefDescription": "Percentage of all uops which are x87 uops", - "MetricExpr": "100 * UOPS_RETIRED.X87 / UOPS_RETIRED.ALL", + "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.X87@ / UOPS_RETIRED.ALL= ", "MetricGroup": " ", "MetricName": "tma_info_x87_uop_ratio", "Unit": "cpu_atom" @@ -571,7 +571,7 @@ { "BriefDescription": "Counts the number of cycles a core is stalled= due to a demand load which hit in the L2 Cache.", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / tma_info_clks - MEM_= BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_S= TALLS.LOAD", + "MetricExpr": "cpu_atom@MEM_BOUND_STALLS.LOAD_L2_HIT@ / tma_info_c= lks - max((cpu_atom@MEM_BOUND_STALLS.LOAD@ - cpu_atom@LD_HEAD.L1_MISS_AT_RE= T@) / tma_info_clks, 0) * cpu_atom@MEM_BOUND_STALLS.LOAD_L2_HIT@ / cpu_atom= @MEM_BOUND_STALLS.LOAD@", "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l2_bound", "MetricThreshold": "tma_l2_bound > 0.1", @@ -580,7 +580,7 @@ }, { "BriefDescription": "Counts the number of cycles a core is stalled= due to a demand load which hit in the Last Level Cache (LLC) or other core= with HITE/F/M.", - "MetricExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / tma_info_clks - MEM= _BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND= _STALLS.LOAD", + "MetricExpr": "cpu_atom@MEM_BOUND_STALLS.LOAD_LLC_HIT@ / tma_info_= clks - max((cpu_atom@MEM_BOUND_STALLS.LOAD@ - cpu_atom@LD_HEAD.L1_MISS_AT_R= ET@) / tma_info_clks, 0) * cpu_atom@MEM_BOUND_STALLS.LOAD_LLC_HIT@ / cpu_at= om@MEM_BOUND_STALLS.LOAD@", "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l3_bound", "MetricThreshold": "tma_l3_bound > 0.1", @@ -589,7 +589,7 @@ }, { "BriefDescription": "Counts the number of cycles, relative to the = number of mem_scheduler slots, in which uops are blocked due to load buffer= full", - "MetricExpr": "tma_mem_scheduler * MEM_SCHEDULER_BLOCK.LD_BUF / ME= M_SCHEDULER_BLOCK.ALL", + "MetricExpr": "tma_mem_scheduler * cpu_atom@MEM_SCHEDULER_BLOCK.LD= _BUF@ / MEM_SCHEDULER_BLOCK.ALL", "MetricGroup": "TopdownL4;tma_L4_group;tma_mem_scheduler_group", "MetricName": "tma_ld_buffer", "MetricThreshold": "tma_ld_buffer > 0.05", @@ -617,7 +617,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to stores or loads.", - "MetricExpr": "min(tma_backend_bound, LD_HEAD.ANY_AT_RET / tma_inf= o_clks + tma_store_bound)", + "MetricExpr": "min(cpu_atom@TOPDOWN_BE_BOUND.ALL@ / tma_info_slots= , cpu_atom@LD_HEAD.ANY_AT_RET@ / tma_info_clks + tma_store_bound)", "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2", @@ -627,7 +627,7 @@ }, { "BriefDescription": "Counts the number of machine clears relative = to the number of nuke slots due to memory ordering.", - "MetricExpr": "tma_nuke * (MACHINE_CLEARS.MEMORY_ORDERING / MACHIN= E_CLEARS.SLOW)", + "MetricExpr": "tma_nuke * (cpu_atom@MACHINE_CLEARS.MEMORY_ORDERING= @ / cpu_atom@MACHINE_CLEARS.SLOW@)", "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", "MetricName": "tma_memory_ordering", "MetricThreshold": "tma_memory_ordering > 0.02", @@ -636,7 +636,7 @@ }, { "BriefDescription": "Counts the number of uops that are from the c= omplex flows issued by the micro-sequencer (MS)", - "MetricExpr": "tma_microcode_sequencer", + "MetricExpr": "UOPS_RETIRED.MS / tma_info_slots", "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", "MetricName": "tma_ms_uops", "MetricThreshold": "tma_ms_uops > 0.05", @@ -692,7 +692,7 @@ }, { "BriefDescription": "Counts the number of uops retired excluding m= s and fp div uops.", - "MetricExpr": "(TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS - UOPS_RETI= RED.FPDIV) / tma_info_slots", + "MetricExpr": "(cpu_atom@TOPDOWN_RETIRING.ALL@ - cpu_atom@UOPS_RET= IRED.MS@ - cpu_atom@UOPS_RETIRED.FPDIV@) / tma_info_slots", "MetricGroup": "TopdownL3;tma_L3_group;tma_base_group", "MetricName": "tma_other_ret", "MetricThreshold": "tma_other_ret > 0.3", @@ -701,7 +701,7 @@ }, { "BriefDescription": "Counts the number of machine clears relative = to the number of nuke slots due to page faults.", - "MetricExpr": "tma_nuke * (MACHINE_CLEARS.PAGE_FAULT / MACHINE_CLE= ARS.SLOW)", + "MetricExpr": "tma_nuke * (cpu_atom@MACHINE_CLEARS.PAGE_FAULT@ / c= pu_atom@MACHINE_CLEARS.SLOW@)", "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", "MetricName": "tma_page_fault", "MetricThreshold": "tma_page_fault > 0.02", @@ -758,7 +758,7 @@ }, { "BriefDescription": "Counts the number of cycles, relative to the = number of mem_scheduler slots, in which uops are blocked due to RSV full re= lative", - "MetricExpr": "tma_mem_scheduler * MEM_SCHEDULER_BLOCK.RSV / MEM_S= CHEDULER_BLOCK.ALL", + "MetricExpr": "tma_mem_scheduler * cpu_atom@MEM_SCHEDULER_BLOCK.RS= V@ / MEM_SCHEDULER_BLOCK.ALL", "MetricGroup": "TopdownL4;tma_L4_group;tma_mem_scheduler_group", "MetricName": "tma_rsv", "MetricThreshold": "tma_rsv > 0.05", @@ -776,7 +776,7 @@ }, { "BriefDescription": "Counts the number of machine clears relative = to the number of nuke slots due to SMC.", - "MetricExpr": "tma_nuke * (MACHINE_CLEARS.SMC / MACHINE_CLEARS.SLO= W)", + "MetricExpr": "tma_nuke * (cpu_atom@MACHINE_CLEARS.SMC@ / cpu_atom= @MACHINE_CLEARS.SLOW@)", "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", "MetricName": "tma_smc", "MetricThreshold": "tma_smc > 0.02", @@ -812,7 +812,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to store buffer full.", - "MetricExpr": "tma_mem_scheduler * (MEM_SCHEDULER_BLOCK.ST_BUF / M= EM_SCHEDULER_BLOCK.ALL)", + "MetricExpr": "tma_mem_scheduler * (cpu_atom@MEM_SCHEDULER_BLOCK.S= T_BUF@ / cpu_atom@MEM_SCHEDULER_BLOCK.ALL@)", "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_store_bound", "MetricThreshold": "tma_store_bound > 0.1", @@ -830,7 +830,7 @@ }, { "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution ports for ALU operations.", - "MetricExpr": "(UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + = UOPS_DISPATCHED.PORT_5_11 + UOPS_DISPATCHED.PORT_6) / (5 * tma_info_core_cl= ks)", + "MetricExpr": "(cpu_core@UOPS_DISPATCHED.PORT_0@ + cpu_core@UOPS_D= ISPATCHED.PORT_1@ + cpu_core@UOPS_DISPATCHED.PORT_5_11@ + cpu_core@UOPS_DIS= PATCHED.PORT_6@) / (5 * tma_info_core_clks)", "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group= ", "MetricName": "tma_alu_op_utilization", "MetricThreshold": "tma_alu_op_utilization > 0.6", @@ -849,7 +849,7 @@ }, { "BriefDescription": "This metric estimates fraction of slots the C= PU retired uops as a result of handing SSE to AVX* or AVX* to SSE transitio= n Assists.", - "MetricExpr": "63 * ASSISTS.SSE_AVX_MIX / tma_info_slots", + "MetricExpr": "63 * cpu_core@ASSISTS.SSE_AVX_MIX@ / tma_info_slots= ", "MetricGroup": "HPC;TopdownL5;tma_L5_group;tma_assists_group", "MetricName": "tma_avx_assists", "MetricThreshold": "tma_avx_assists > 0.1", @@ -858,7 +858,7 @@ }, { "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", - "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topd= own\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_inf= o_slots", + "MetricExpr": "cpu_core@topdown\\-be\\-bound@ / (cpu_core@topdown\= \-fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ + cpu_core@topdown\\-retirin= g@ + cpu_core@topdown\\-be\\-bound@) + 0 * tma_info_slots", "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", @@ -880,7 +880,7 @@ }, { "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Branch Misprediction", - "MetricExpr": "topdown\\-br\\-mispredict / (topdown\\-fe\\-bound += topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tm= a_info_slots", + "MetricExpr": "cpu_core@topdown\\-br\\-mispredict@ / (cpu_core@top= down\\-fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ + cpu_core@topdown\\-re= tiring@ + cpu_core@topdown\\-be\\-bound@) + 0 * tma_info_slots", "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", @@ -911,7 +911,7 @@ }, { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Branch Resteers as a result of Machine Clears", - "MetricExpr": "(1 - tma_branch_mispredicts / tma_bad_speculation) = * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_clks", + "MetricExpr": "(1 - tma_branch_mispredicts / tma_bad_speculation) = * cpu_core@INT_MISC.CLEAR_RESTEER_CYCLES@ / tma_info_clks", "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_b= ranch_resteers_group;tma_issueMC", "MetricName": "tma_clears_resteers", "MetricThreshold": "tma_clears_resteers > 0.05 & (tma_branch_reste= ers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", @@ -922,7 +922,7 @@ { "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to contested acces= ses", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "(25 * tma_info_average_frequency * (MEM_LOAD_L3_HIT= _RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DAT= A_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + = 24 * tma_info_average_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 += MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricExpr": "(25 * tma_info_average_frequency * (cpu_core@MEM_LO= AD_L3_HIT_RETIRED.XSNP_FWD@ * (cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT= M@ / (cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM@ + cpu_core@OCR.DEMAND_= DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD@))) + 24 * tma_info_average_frequency * c= pu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS@) * (1 + cpu_core@MEM_LOAD_RETIRE= D.FB_HIT@ / cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / 2) / tma_info_clks", "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_l3_bound_group", "MetricName": "tma_contested_accesses", "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound = > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", @@ -944,7 +944,7 @@ { "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to data-sharing ac= cesses", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "24 * tma_info_average_frequency * (MEM_LOAD_L3_HIT_= RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - OCR.DEMAND_DA= TA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAN= D_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM= _LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricExpr": "24 * tma_info_average_frequency * (cpu_core@MEM_LOA= D_L3_HIT_RETIRED.XSNP_NO_FWD@ + cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD@ = * (1 - cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM@ / (cpu_core@OCR.DEMAN= D_DATA_RD.L3_HIT.SNOOP_HITM@ + cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT= _WITH_FWD@))) * (1 + cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / cpu_core@MEM_LOAD_= RETIRED.L1_MISS@ / 2) / tma_info_clks", "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSync= xn;tma_l3_bound_group", "MetricName": "tma_data_sharing", "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", @@ -975,7 +975,7 @@ { "BriefDescription": "This metric estimates how often the CPU was s= talled on accesses to external memory (DRAM) by loads", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "MEMORY_ACTIVITY.STALLS_L3_MISS / tma_info_clks", + "MetricExpr": "cpu_core@MEMORY_ACTIVITY.STALLS_L3_MISS@ / tma_info= _clks", "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_me= mory_bound_group", "MetricName": "tma_dram_bound", "MetricThreshold": "tma_dram_bound > 0.1 & (tma_memory_bound > 0.2= & tma_backend_bound > 0.2)", @@ -985,7 +985,7 @@ }, { "BriefDescription": "This metric represents Core fraction of cycle= s in which CPU was likely limited due to DSB (decoded uop cache) fetch pipe= line", - "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / tma_info= _core_clks / 2", + "MetricExpr": "(cpu_core@IDQ.DSB_CYCLES_ANY@ - cpu_core@IDQ.DSB_CY= CLES_OK@) / tma_info_core_clks / 2", "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandw= idth_group", "MetricName": "tma_dsb", "MetricThreshold": "tma_dsb > 0.15 & (tma_fetch_bandwidth > 0.1 & = tma_frontend_bound > 0.15 & tma_info_ipc / 6 > 0.35)", @@ -1005,7 +1005,7 @@ }, { "BriefDescription": "This metric roughly estimates the fraction of= cycles where the Data TLB (DTLB) was missed by load accesses", - "MetricExpr": "min(7 * cpu_core@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\= \=3D1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - = MEMORY_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_clks", + "MetricExpr": "min(7 * cpu_core@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\= \=3D1@ + cpu_core@DTLB_LOAD_MISSES.WALK_ACTIVE@, max(cpu_core@CYCLE_ACTIVIT= Y.CYCLES_MEM_ANY@ - cpu_core@MEMORY_ACTIVITY.CYCLES_L1D_MISS@, 0)) / tma_in= fo_clks", "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= l1_bound_group", "MetricName": "tma_dtlb_load", "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (t= ma_memory_bound > 0.2 & tma_backend_bound > 0.2))", @@ -1015,7 +1015,7 @@ }, { "BriefDescription": "This metric roughly estimates the fraction of= cycles spent handling first-level data TLB store misses", - "MetricExpr": "(7 * cpu_core@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\= =3D1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / tma_info_core_clks", + "MetricExpr": "(7 * cpu_core@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\= =3D1@ + cpu_core@DTLB_STORE_MISSES.WALK_ACTIVE@) / tma_info_core_clks", "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= store_bound_group", "MetricName": "tma_dtlb_store", "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", @@ -1025,7 +1025,7 @@ }, { "BriefDescription": "This metric roughly estimates how often CPU w= as handling synchronizations due to False Sharing", - "MetricExpr": "28 * tma_info_average_frequency * OCR.DEMAND_RFO.L3= _HIT.SNOOP_HITM / tma_info_clks", + "MetricExpr": "28 * tma_info_average_frequency * cpu_core@OCR.DEMA= ND_RFO.L3_HIT.SNOOP_HITM@ / tma_info_clks", "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_store_bound_group", "MetricName": "tma_false_sharing", "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > = 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", @@ -1056,7 +1056,7 @@ }, { "BriefDescription": "This metric represents fraction of slots the = CPU was stalled due to Frontend latency issues", - "MetricExpr": "topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + top= down\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.U= OP_DROPPING / tma_info_slots", + "MetricExpr": "cpu_core@topdown\\-fetch\\-lat@ / (cpu_core@topdown= \\-fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ + cpu_core@topdown\\-retiri= ng@ + cpu_core@topdown\\-be\\-bound@) - cpu_core@INT_MISC.UOP_DROPPING@ / t= ma_info_slots", "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend= _bound_group", "MetricName": "tma_fetch_latency", "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", @@ -1088,7 +1088,7 @@ }, { "BriefDescription": "This metric roughly estimates fraction of slo= ts the CPU retired uops as a result of handing Floating Point (FP) Assists", - "MetricExpr": "30 * ASSISTS.FP / tma_info_slots", + "MetricExpr": "30 * cpu_core@ASSISTS.FP@ / tma_info_slots", "MetricGroup": "HPC;TopdownL5;tma_L5_group;tma_assists_group", "MetricName": "tma_fp_assists", "MetricThreshold": "tma_fp_assists > 0.1", @@ -1118,7 +1118,7 @@ }, { "BriefDescription": "This metric approximates arithmetic FP vector= uops fraction the CPU has retired for 128-bit wide vectors", - "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARIT= H_INST_RETIRED.128B_PACKED_SINGLE) / (tma_retiring * tma_info_slots)", + "MetricExpr": "(cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE@= + cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE@) / (tma_retiring * tm= a_info_slots)", "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector= _group;tma_issue2P", "MetricName": "tma_fp_vector_128b", "MetricThreshold": "tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.= 1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", @@ -1128,7 +1128,7 @@ }, { "BriefDescription": "This metric approximates arithmetic FP vector= uops fraction the CPU has retired for 256-bit wide vectors", - "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARIT= H_INST_RETIRED.256B_PACKED_SINGLE) / (tma_retiring * tma_info_slots)", + "MetricExpr": "(cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE@= + cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE@) / (tma_retiring * tm= a_info_slots)", "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector= _group;tma_issue2P", "MetricName": "tma_fp_vector_256b", "MetricThreshold": "tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.= 1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", @@ -1138,7 +1138,7 @@ }, { "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", - "MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topd= own\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UO= P_DROPPING / tma_info_slots", + "MetricExpr": "cpu_core@topdown\\-fe\\-bound@ / (cpu_core@topdown\= \-fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ + cpu_core@topdown\\-retirin= g@ + cpu_core@topdown\\-be\\-bound@) - cpu_core@INT_MISC.UOP_DROPPING@ / tm= a_info_slots", "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", @@ -1149,7 +1149,7 @@ }, { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring fused instructions -- where one uop can represent mu= ltiple contiguous instructions", - "MetricExpr": "tma_light_operations * INST_RETIRED.MACRO_FUSED / (= tma_retiring * tma_info_slots)", + "MetricExpr": "tma_light_operations * cpu_core@INST_RETIRED.MACRO_= FUSED@ / (tma_retiring * tma_info_slots)", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", "MetricName": "tma_fused_instructions", "MetricThreshold": "tma_fused_instructions > 0.1 & tma_light_opera= tions > 0.6", @@ -1159,7 +1159,7 @@ }, { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring heavy-weight operations -- instructions that require= two or more uops or micro-coded sequences", - "MetricExpr": "topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + top= down\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_in= fo_slots", + "MetricExpr": "cpu_core@topdown\\-heavy\\-ops@ / (cpu_core@topdown= \\-fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ + cpu_core@topdown\\-retiri= ng@ + cpu_core@topdown\\-be\\-bound@) + 0 * tma_info_slots", "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_g= roup", "MetricName": "tma_heavy_operations", "MetricThreshold": "tma_heavy_operations > 0.1", @@ -1213,7 +1213,7 @@ }, { "BriefDescription": "Total pipeline cost of branch related instruc= tions (used for program control-flow including function calls)", - "MetricExpr": "100 * ((BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED.= NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * = BR_INST_RETIRED.NEAR_CALL)) / tma_info_slots)", + "MetricExpr": "100 * ((cpu_core@BR_INST_RETIRED.COND@ + 3 * cpu_co= re@BR_INST_RETIRED.NEAR_CALL@ + (cpu_core@BR_INST_RETIRED.NEAR_TAKEN@ - cpu= _core@BR_INST_RETIRED.COND_TAKEN@ - 2 * cpu_core@BR_INST_RETIRED.NEAR_CALL@= )) / tma_info_slots)", "MetricGroup": "Ret;tma_issueBC", "MetricName": "tma_info_branching_overhead", "MetricThreshold": "tma_info_branching_overhead > 10", @@ -1222,21 +1222,21 @@ }, { "BriefDescription": "Fraction of branches that are CALL or RET", - "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_R= ETURN) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricExpr": "(cpu_core@BR_INST_RETIRED.NEAR_CALL@ + cpu_core@BR_= INST_RETIRED.NEAR_RETURN@) / BR_INST_RETIRED.ALL_BRANCHES", "MetricGroup": "Bad;Branches", "MetricName": "tma_info_callret", "Unit": "cpu_core" }, { "BriefDescription": "Per-Logical Processor actual clocks when the = Logical Processor is active.", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD", + "MetricExpr": "cpu_core@CPU_CLK_UNHALTED.THREAD@", "MetricGroup": "Pipeline", "MetricName": "tma_info_clks", "Unit": "cpu_core" }, { "BriefDescription": "STLB (2nd level TLB) code speculative misses = per kilo instruction (misses of any page-size that complete the page walk)", - "MetricExpr": "1e3 * ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY= ", + "MetricExpr": "1e3 * cpu_core@ITLB_MISSES.WALK_COMPLETED@ / INST_R= ETIRED.ANY", "MetricGroup": "Fed;MemoryTLB", "MetricName": "tma_info_code_stlb_mpki", "Unit": "cpu_core" @@ -1266,7 +1266,7 @@ }, { "BriefDescription": "Core actual clocks when any Logical Processor= is active on the Physical Core", - "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED", + "MetricExpr": "cpu_core@CPU_CLK_UNHALTED.DISTRIBUTED@", "MetricGroup": "SMT", "MetricName": "tma_info_core_clks", "Unit": "cpu_core" @@ -1309,7 +1309,7 @@ }, { "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / UOPS_ISSUED.ANY", + "MetricExpr": "IDQ.DSB_UOPS / cpu_core@UOPS_ISSUED.ANY@", "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", "MetricName": "tma_info_dsb_coverage", "MetricThreshold": "tma_info_dsb_coverage < 0.7 & tma_info_ipc / 6= > 0.35", @@ -1350,7 +1350,7 @@ }, { "BriefDescription": "Fill Buffer (FB) hits per kilo instructions f= or retired demand loads (L1D misses that merge into ongoing miss-handling e= ntries)", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", + "MetricExpr": "1e3 * cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / INST_RETI= RED.ANY", "MetricGroup": "CacheMisses;Mem", "MetricName": "tma_info_fb_hpki", "Unit": "cpu_core" @@ -1365,7 +1365,7 @@ { "BriefDescription": "Floating Point Operations Per Cycle", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INS= T_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 = * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PA= CKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / tma_info_cor= e_clks", + "MetricExpr": "(cpu_core@FP_ARITH_INST_RETIRED.SCALAR_SINGLE@ + cp= u_core@FP_ARITH_INST_RETIRED.SCALAR_DOUBLE@ + 2 * cpu_core@FP_ARITH_INST_RE= TIRED.128B_PACKED_DOUBLE@ + 4 * (cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED= _SINGLE@ + cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE@) + 8 * cpu_co= re@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE@) / tma_info_core_clks", "MetricGroup": "Flops;Ret", "MetricName": "tma_info_flopc", "Unit": "cpu_core" @@ -1373,7 +1373,7 @@ { "BriefDescription": "Actual per-core usage of the Floating Point n= on-X87 execution units (regardless of precision or vector-width)", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "(FP_ARITH_DISPATCHED.PORT_0 + FP_ARITH_DISPATCHED.P= ORT_1 + FP_ARITH_DISPATCHED.PORT_5) / (2 * tma_info_core_clks)", + "MetricExpr": "(cpu_core@FP_ARITH_DISPATCHED.PORT_0@ + cpu_core@FP= _ARITH_DISPATCHED.PORT_1@ + cpu_core@FP_ARITH_DISPATCHED.PORT_5@) / (2 * tm= a_info_core_clks)", "MetricGroup": "Cor;Flops;HPC", "MetricName": "tma_info_fp_arith_utilization", "PublicDescription": "Actual per-core usage of the Floating Point = non-X87 execution units (regardless of precision or vector-width). Values >= 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; = [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less commo= n).", @@ -1381,7 +1381,7 @@ }, { "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INS= T_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 = * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PA= CKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / durati= on_time", + "MetricExpr": "(cpu_core@FP_ARITH_INST_RETIRED.SCALAR_SINGLE@ + cp= u_core@FP_ARITH_INST_RETIRED.SCALAR_DOUBLE@ + 2 * cpu_core@FP_ARITH_INST_RE= TIRED.128B_PACKED_DOUBLE@ + 4 * (cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED= _SINGLE@ + cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE@) + 8 * cpu_co= re@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE@) / 1e9 / duration_time", "MetricGroup": "Cor;Flops;HPC", "MetricName": "tma_info_gflops", "PublicDescription": "Giga Floating Point Operations Per Second. A= ggregate across all supported options of: FP precisions, scalar and vector = instructions, vector-width and AMX engine.", @@ -1405,7 +1405,7 @@ }, { "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per-core", - "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_G= E_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", + "MetricExpr": "UOPS_EXECUTED.THREAD / (cpu_core@UOPS_EXECUTED.CORE= _CYCLES_GE_1@ / 2 if #SMT_on else cpu_core@UOPS_EXECUTED.CORE_CYCLES_GE_1@)= ", "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "tma_info_ilp", "Unit": "cpu_core" @@ -1421,7 +1421,7 @@ }, { "BriefDescription": "Total number of retired Instructions", - "MetricExpr": "INST_RETIRED.ANY", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@", "MetricGroup": "Summary;TmaL1;tma_L1_group", "MetricName": "tma_info_instructions", "PublicDescription": "Total number of retired Instructions. Sample= with: INST_RETIRED.PREC_DIST", @@ -1438,7 +1438,7 @@ }, { "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bi= t instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACK= ED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)", + "MetricExpr": "INST_RETIRED.ANY / (cpu_core@FP_ARITH_INST_RETIRED.= 128B_PACKED_DOUBLE@ + cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE@)", "MetricGroup": "Flops;FpVector;InsType", "MetricName": "tma_info_iparith_avx128", "MetricThreshold": "tma_info_iparith_avx128 < 10", @@ -1447,7 +1447,7 @@ }, { "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit i= nstruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACK= ED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", + "MetricExpr": "INST_RETIRED.ANY / (cpu_core@FP_ARITH_INST_RETIRED.= 256B_PACKED_DOUBLE@ + cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE@)", "MetricGroup": "Flops;FpVector;InsType", "MetricName": "tma_info_iparith_avx256", "MetricThreshold": "tma_info_iparith_avx256 < 10", @@ -1514,7 +1514,7 @@ }, { "BriefDescription": "Instructions per Far Branch ( Far Branches ap= ply upon transition from application to operating system, handling interrup= ts, exceptions) [lower number means higher occurrence rate]", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricExpr": "INST_RETIRED.ANY / cpu_core@BR_INST_RETIRED.FAR_BRA= NCH@u", "MetricGroup": "Branches;OS", "MetricName": "tma_info_ipfarbranch", "MetricThreshold": "tma_info_ipfarbranch < 1e6", @@ -1522,7 +1522,7 @@ }, { "BriefDescription": "Instructions per Floating Point (FP) Operatio= n (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SI= NGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B= _PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_I= NST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SIN= GLE)", + "MetricExpr": "INST_RETIRED.ANY / (cpu_core@FP_ARITH_INST_RETIRED.= SCALAR_SINGLE@ + cpu_core@FP_ARITH_INST_RETIRED.SCALAR_DOUBLE@ + 2 * cpu_co= re@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE@ + 4 * (cpu_core@FP_ARITH_INST_= RETIRED.128B_PACKED_SINGLE@ + cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_DO= UBLE@) + 8 * cpu_core@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE@)", "MetricGroup": "Flops;InsType", "MetricName": "tma_info_ipflop", "MetricThreshold": "tma_info_ipflop < 10", @@ -1610,14 +1610,14 @@ }, { "BriefDescription": "Fraction of branches that are unconditional (= direct or indirect) jumps", - "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_= TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricExpr": "(cpu_core@BR_INST_RETIRED.NEAR_TAKEN@ - cpu_core@BR= _INST_RETIRED.COND_TAKEN@ - 2 * cpu_core@BR_INST_RETIRED.NEAR_CALL@) / BR_I= NST_RETIRED.ALL_BRANCHES", "MetricGroup": "Bad;Branches", "MetricName": "tma_info_jump", "Unit": "cpu_core" }, { "BriefDescription": "Cycles Per Instruction for the Operating Syst= em (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / cpu_core@INST_RETIRED= .ANY_P@k", "MetricGroup": "OS", "MetricName": "tma_info_kernel_cpi", "Unit": "cpu_core" @@ -1632,7 +1632,7 @@ }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", + "MetricExpr": "64 * cpu_core@L1D.REPLACEMENT@ / 1e9 / duration_tim= e", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_l1d_cache_fill_bw", "Unit": "cpu_core" @@ -1646,21 +1646,21 @@ }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricExpr": "1e3 * cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / INST_RET= IRED.ANY", "MetricGroup": "CacheMisses;Mem", "MetricName": "tma_info_l1mpki", "Unit": "cpu_core" }, { "BriefDescription": "L1 cache true misses per kilo instruction for= all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.AN= Y", + "MetricExpr": "1e3 * cpu_core@L2_RQSTS.ALL_DEMAND_DATA_RD@ / INST_= RETIRED.ANY", "MetricGroup": "CacheMisses;Mem", "MetricName": "tma_info_l1mpki_load", "Unit": "cpu_core" }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 2 cache [GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", + "MetricExpr": "64 * cpu_core@L2_LINES_IN.ALL@ / 1e9 / duration_tim= e", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_l2_cache_fill_bw", "Unit": "cpu_core" @@ -1674,56 +1674,56 @@ }, { "BriefDescription": "L2 cache hits per kilo instruction for all re= quest types (including speculative)", - "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_= RETIRED.ANY", + "MetricExpr": "1e3 * (cpu_core@L2_RQSTS.REFERENCES@ - cpu_core@L2_= RQSTS.MISS@) / INST_RETIRED.ANY", "MetricGroup": "CacheMisses;Mem", "MetricName": "tma_info_l2hpki_all", "Unit": "cpu_core" }, { "BriefDescription": "L2 cache hits per kilo instruction for all de= mand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.AN= Y", + "MetricExpr": "1e3 * cpu_core@L2_RQSTS.DEMAND_DATA_RD_HIT@ / INST_= RETIRED.ANY", "MetricGroup": "CacheMisses;Mem", "MetricName": "tma_info_l2hpki_load", "Unit": "cpu_core" }, { "BriefDescription": "L2 cache true misses per kilo instruction for= retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricExpr": "1e3 * cpu_core@MEM_LOAD_RETIRED.L2_MISS@ / INST_RET= IRED.ANY", "MetricGroup": "Backend;CacheMisses;Mem", "MetricName": "tma_info_l2mpki", "Unit": "cpu_core" }, { "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instru= ction for all request types (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY", + "MetricExpr": "1e3 * cpu_core@L2_RQSTS.MISS@ / INST_RETIRED.ANY", "MetricGroup": "CacheMisses;Mem;Offcore", "MetricName": "tma_info_l2mpki_all", "Unit": "cpu_core" }, { "BriefDescription": "L2 cache true code cacheline misses per kilo = instruction", - "MetricExpr": "1e3 * FRONTEND_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricExpr": "1e3 * cpu_core@FRONTEND_RETIRED.L2_MISS@ / INST_RET= IRED.ANY", "MetricGroup": "IcMiss", "MetricName": "tma_info_l2mpki_code", "Unit": "cpu_core" }, { "BriefDescription": "L2 cache speculative code cacheline misses pe= r kilo instruction", - "MetricExpr": "1e3 * L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", + "MetricExpr": "1e3 * cpu_core@L2_RQSTS.CODE_RD_MISS@ / INST_RETIRE= D.ANY", "MetricGroup": "IcMiss", "MetricName": "tma_info_l2mpki_code_all", "Unit": "cpu_core" }, { "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instru= ction for all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.A= NY", + "MetricExpr": "1e3 * cpu_core@L2_RQSTS.DEMAND_DATA_RD_MISS@ / INST= _RETIRED.ANY", "MetricGroup": "CacheMisses;Mem", "MetricName": "tma_info_l2mpki_load", "Unit": "cpu_core" }, { "BriefDescription": "Average per-core data access bandwidth to the= L3 cache [GB / sec]", - "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration= _time", + "MetricExpr": "64 * cpu_core@OFFCORE_REQUESTS.ALL_REQUESTS@ / 1e9 = / duration_time", "MetricGroup": "Mem;MemoryBW;Offcore", "MetricName": "tma_info_l3_cache_access_bw", "Unit": "cpu_core" @@ -1737,7 +1737,7 @@ }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", + "MetricExpr": "64 * cpu_core@LONGEST_LAT_CACHE.MISS@ / 1e9 / durat= ion_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_l3_cache_fill_bw", "Unit": "cpu_core" @@ -1751,7 +1751,7 @@ }, { "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", + "MetricExpr": "1e3 * cpu_core@MEM_LOAD_RETIRED.L3_MISS@ / INST_RET= IRED.ANY", "MetricGroup": "CacheMisses;Mem", "MetricName": "tma_info_l3mpki", "Unit": "cpu_core" @@ -1786,14 +1786,14 @@ }, { "BriefDescription": "STLB (2nd level TLB) data load speculative mi= sses per kilo instruction (misses of any page-size that complete the page w= alk)", - "MetricExpr": "1e3 * DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRE= D.ANY", + "MetricExpr": "1e3 * cpu_core@DTLB_LOAD_MISSES.WALK_COMPLETED@ / I= NST_RETIRED.ANY", "MetricGroup": "Mem;MemoryTLB", "MetricName": "tma_info_load_stlb_mpki", "Unit": "cpu_core" }, { "BriefDescription": "Fraction of Uops delivered by the LSD (Loop S= tream Detector; aka Loop Cache)", - "MetricExpr": "LSD.UOPS / UOPS_ISSUED.ANY", + "MetricExpr": "LSD.UOPS / cpu_core@UOPS_ISSUED.ANY@", "MetricGroup": "Fed;LSD", "MetricName": "tma_info_lsd_coverage", "Unit": "cpu_core" @@ -1877,7 +1877,7 @@ }, { "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_P= ENDING + DTLB_STORE_MISSES.WALK_PENDING) / (4 * tma_info_core_clks)", + "MetricExpr": "(cpu_core@ITLB_MISSES.WALK_PENDING@ + cpu_core@DTLB= _LOAD_MISSES.WALK_PENDING@ + cpu_core@DTLB_STORE_MISSES.WALK_PENDING@) / (4= * tma_info_core_clks)", "MetricGroup": "Mem;MemoryTLB", "MetricName": "tma_info_page_walks_utilization", "MetricThreshold": "tma_info_page_walks_utilization > 0.5", @@ -1893,21 +1893,21 @@ }, { "BriefDescription": "Total issue-pipeline slots (per-Physical Core= till ICL; per-Logical Processor ICL onward)", - "MetricExpr": "TOPDOWN.SLOTS", + "MetricExpr": "cpu_core@TOPDOWN.SLOTS@", "MetricGroup": "TmaL1;tma_L1_group", "MetricName": "tma_info_slots", "Unit": "cpu_core" }, { "BriefDescription": "Fraction of Physical Core issue-slots utilize= d by this Logical Processor", - "MetricExpr": "(tma_info_slots / (TOPDOWN.SLOTS / 2) if #SMT_on el= se 1)", + "MetricExpr": "(tma_info_slots / (cpu_core@TOPDOWN.SLOTS@ / 2) if = #SMT_on else 1)", "MetricGroup": "SMT;TmaL1;tma_L1_group", "MetricName": "tma_info_slots_utilization", "Unit": "cpu_core" }, { "BriefDescription": "Fraction of cycles where both hardware Logica= l Processors were active", - "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_U= NHALTED.REF_DISTRIBUTED if #SMT_on else 0)", + "MetricExpr": "(1 - cpu_core@CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE@ /= cpu_core@CPU_CLK_UNHALTED.REF_DISTRIBUTED@ if #SMT_on else 0)", "MetricGroup": "SMT", "MetricName": "tma_info_smt_2t_utilization", "Unit": "cpu_core" @@ -1921,7 +1921,7 @@ }, { "BriefDescription": "STLB (2nd level TLB) data store speculative m= isses per kilo instruction (misses of any page-size that complete the page = walk)", - "MetricExpr": "1e3 * DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIR= ED.ANY", + "MetricExpr": "1e3 * cpu_core@DTLB_STORE_MISSES.WALK_COMPLETED@ / = INST_RETIRED.ANY", "MetricGroup": "Mem;MemoryTLB", "MetricName": "tma_info_store_stlb_mpki", "Unit": "cpu_core" @@ -1969,7 +1969,7 @@ }, { "BriefDescription": "This metric represents 128-bit vector Integer= ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the= CPU has retired", - "MetricExpr": "(INT_VEC_RETIRED.ADD_128 + INT_VEC_RETIRED.VNNI_128= ) / (tma_retiring * tma_info_slots)", + "MetricExpr": "(cpu_core@INT_VEC_RETIRED.ADD_128@ + cpu_core@INT_V= EC_RETIRED.VNNI_128@) / (tma_retiring * tma_info_slots)", "MetricGroup": "Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;= tma_int_operations_group;tma_issue2P", "MetricName": "tma_int_vector_128b", "MetricThreshold": "tma_int_vector_128b > 0.1 & (tma_int_operation= s > 0.1 & tma_light_operations > 0.6)", @@ -1979,7 +1979,7 @@ }, { "BriefDescription": "This metric represents 256-bit vector Integer= ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the= CPU has retired", - "MetricExpr": "(INT_VEC_RETIRED.ADD_256 + INT_VEC_RETIRED.MUL_256 = + INT_VEC_RETIRED.VNNI_256) / (tma_retiring * tma_info_slots)", + "MetricExpr": "(cpu_core@INT_VEC_RETIRED.ADD_256@ + cpu_core@INT_V= EC_RETIRED.MUL_256@ + cpu_core@INT_VEC_RETIRED.VNNI_256@) / (tma_retiring *= tma_info_slots)", "MetricGroup": "Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;= tma_int_operations_group;tma_issue2P", "MetricName": "tma_int_vector_256b", "MetricThreshold": "tma_int_vector_256b > 0.1 & (tma_int_operation= s > 0.1 & tma_light_operations > 0.6)", @@ -1999,7 +1999,7 @@ }, { "BriefDescription": "This metric estimates how often the CPU was s= talled without loads missing the L1 data cache", - "MetricExpr": "max((EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.= STALLS_L1D_MISS) / tma_info_clks, 0)", + "MetricExpr": "max((cpu_core@EXE_ACTIVITY.BOUND_ON_LOADS@ - cpu_co= re@MEMORY_ACTIVITY.STALLS_L1D_MISS@) / tma_info_clks, 0)", "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_= group;tma_issueL1;tma_issueMC;tma_memory_bound_group", "MetricName": "tma_l1_bound", "MetricThreshold": "tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 &= tma_backend_bound > 0.2)", @@ -2010,7 +2010,7 @@ { "BriefDescription": "This metric estimates how often the CPU was s= talled due to L2 cache accesses by loads", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.= STALLS_L2_MISS) / tma_info_clks", + "MetricExpr": "(cpu_core@MEMORY_ACTIVITY.STALLS_L1D_MISS@ - cpu_co= re@MEMORY_ACTIVITY.STALLS_L2_MISS@) / tma_info_clks", "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_= group;tma_memory_bound_group", "MetricName": "tma_l2_bound", "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 = & tma_backend_bound > 0.2)", @@ -2020,7 +2020,7 @@ }, { "BriefDescription": "This metric estimates how often the CPU was s= talled due to loads accesses to L3 cache or contended with a sibling Core", - "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.S= TALLS_L3_MISS) / tma_info_clks", + "MetricExpr": "(cpu_core@MEMORY_ACTIVITY.STALLS_L2_MISS@ - cpu_cor= e@MEMORY_ACTIVITY.STALLS_L3_MISS@) / tma_info_clks", "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_= group;tma_memory_bound_group", "MetricName": "tma_l3_bound", "MetricThreshold": "tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 = & tma_backend_bound > 0.2)", @@ -2030,7 +2030,7 @@ }, { "BriefDescription": "This metric represents fraction of cycles wit= h demand load accesses that hit the L3 cache under unloaded scenarios (poss= ibly L3 latency limited)", - "MetricExpr": "9 * tma_info_average_frequency * MEM_LOAD_RETIRED.L= 3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_= info_clks", + "MetricExpr": "9 * tma_info_average_frequency * cpu_core@MEM_LOAD_= RETIRED.L3_HIT@ * (1 + cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / cpu_core@MEM_LOA= D_RETIRED.L1_MISS@ / 2) / tma_info_clks", "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_= l3_bound_group", "MetricName": "tma_l3_hit_latency", "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.0= 5 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", @@ -2090,7 +2090,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU spent handling cache misses due to lock operations", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS= .ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (10= * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTAN= DING.CYCLES_WITH_DEMAND_RFO))) / tma_info_clks", + "MetricExpr": "(16 * max(0, cpu_core@MEM_INST_RETIRED.LOCK_LOADS@ = - cpu_core@L2_RQSTS.ALL_RFO@) + cpu_core@MEM_INST_RETIRED.LOCK_LOADS@ / cpu= _core@MEM_INST_RETIRED.ALL_STORES@ * (10 * cpu_core@L2_RQSTS.RFO_HIT@ + min= (cpu_core@CPU_CLK_UNHALTED.THREAD@, cpu_core@OFFCORE_REQUESTS_OUTSTANDING.C= YCLES_WITH_DEMAND_RFO@))) / tma_info_clks", "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1= _bound_group", "MetricName": "tma_lock_latency", "MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 &= (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", @@ -2100,7 +2100,7 @@ }, { "BriefDescription": "This metric represents Core fraction of cycle= s in which CPU was likely limited due to LSD (Loop Stream Detector) unit", - "MetricExpr": "(LSD.CYCLES_ACTIVE - LSD.CYCLES_OK) / tma_info_core= _clks / 2", + "MetricExpr": "(cpu_core@LSD.CYCLES_ACTIVE@ - cpu_core@LSD.CYCLES_= OK@) / tma_info_core_clks / 2", "MetricGroup": "FetchBW;LSD;TopdownL3;tma_L3_group;tma_fetch_bandw= idth_group", "MetricName": "tma_lsd", "MetricThreshold": "tma_lsd > 0.15 & (tma_fetch_bandwidth > 0.1 & = tma_frontend_bound > 0.15 & tma_info_ipc / 6 > 0.35)", @@ -2121,7 +2121,7 @@ }, { "BriefDescription": "This metric estimates fraction of cycles wher= e the core's performance was likely hurt due to approaching bandwidth limit= s of external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu_core@OFFCORE_REQUE= STS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=3D4@) / tma_info_clks", + "MetricExpr": "min(cpu_core@CPU_CLK_UNHALTED.THREAD@, cpu_core@OFF= CORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=3D4@) / tma_info_clks", "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_b= ound_group;tma_issueBW", "MetricName": "tma_mem_bandwidth", "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.= 1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", @@ -2131,7 +2131,7 @@ }, { "BriefDescription": "This metric estimates fraction of cycles wher= e the performance was likely hurt due to latency from external memory (DRAM= )", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTST= ANDING.CYCLES_WITH_DATA_RD) / tma_info_clks - tma_mem_bandwidth", + "MetricExpr": "min(cpu_core@CPU_CLK_UNHALTED.THREAD@, cpu_core@OFF= CORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD@) / tma_info_clks - tma_mem_b= andwidth", "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_= bound_group;tma_issueLat", "MetricName": "tma_mem_latency", "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 = & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", @@ -2141,7 +2141,7 @@ }, { "BriefDescription": "This metric represents fraction of slots the = Memory subsystem within the Backend was a bottleneck", - "MetricExpr": "min(tma_backend_bound, LD_HEAD.ANY_AT_RET / tma_inf= o_clks + tma_store_bound)", + "MetricExpr": "cpu_core@topdown\\-mem\\-bound@ / (cpu_core@topdown= \\-fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ + cpu_core@topdown\\-retiri= ng@ + cpu_core@topdown\\-be\\-bound@) + 0 * tma_info_slots", "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_b= ound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", @@ -2152,7 +2152,7 @@ }, { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to LFENCE Instructions.", - "MetricExpr": "13 * MISC2_RETIRED.LFENCE / tma_info_clks", + "MetricExpr": "13 * cpu_core@MISC2_RETIRED.LFENCE@ / tma_info_clks= ", "MetricGroup": "TopdownL6;tma_L6_group;tma_serializing_operation_g= roup", "MetricName": "tma_memory_fence", "MetricThreshold": "tma_memory_fence > 0.05 & (tma_serializing_ope= ration > 0.1 & (tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 = & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))))", @@ -2162,7 +2162,7 @@ { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring memory operations -- uops for memory load or store a= ccesses.", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "tma_light_operations * MEM_UOP_RETIRED.ANY / (tma_r= etiring * tma_info_slots)", + "MetricExpr": "tma_light_operations * cpu_core@MEM_UOP_RETIRED.ANY= @ / (tma_retiring * tma_info_slots)", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", "MetricName": "tma_memory_operations", "MetricThreshold": "tma_memory_operations > 0.1 & tma_light_operat= ions > 0.6", @@ -2181,7 +2181,7 @@ }, { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Branch Resteers as a result of Branch Misprediction= at execution stage", - "MetricExpr": "tma_branch_mispredicts / tma_bad_speculation * INT_= MISC.CLEAR_RESTEER_CYCLES / tma_info_clks", + "MetricExpr": "tma_branch_mispredicts / tma_bad_speculation * cpu_= core@INT_MISC.CLEAR_RESTEER_CYCLES@ / tma_info_clks", "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_b= ranch_resteers_group;tma_issueBM", "MetricName": "tma_mispredicts_resteers", "MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_= resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", @@ -2191,7 +2191,7 @@ }, { "BriefDescription": "This metric represents Core fraction of cycle= s in which CPU was likely limited due to the MITE pipeline (the legacy deco= de pipeline)", - "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / tma_in= fo_core_clks / 2", + "MetricExpr": "(cpu_core@IDQ.MITE_CYCLES_ANY@ - cpu_core@IDQ.MITE_= CYCLES_OK@) / tma_info_core_clks / 2", "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_b= andwidth_group", "MetricName": "tma_mite", "MetricThreshold": "tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & = tma_frontend_bound > 0.15 & tma_info_ipc / 6 > 0.35)", @@ -2201,7 +2201,7 @@ }, { "BriefDescription": "The Mixing_Vectors metric gives the percentag= e of injected blend uops out of all uops issued", - "MetricExpr": "160 * ASSISTS.SSE_AVX_MIX / tma_info_clks", + "MetricExpr": "160 * cpu_core@ASSISTS.SSE_AVX_MIX@ / tma_info_clks= ", "MetricGroup": "TopdownL5;tma_L5_group;tma_issueMV;tma_ports_utili= zed_0_group", "MetricName": "tma_mixing_vectors", "MetricThreshold": "tma_mixing_vectors > 0.05", @@ -2211,7 +2211,7 @@ }, { "BriefDescription": "This metric estimates the fraction of cycles = when the CPU was stalled due to switches of uop delivery to the Microcode S= equencer (MS)", - "MetricExpr": "3 * cpu_core@UOPS_RETIRED.MS\\,cmask\\=3D1\\,edge@ = / (tma_retiring * tma_info_slots / UOPS_ISSUED.ANY) / tma_info_clks", + "MetricExpr": "3 * cpu_core@UOPS_RETIRED.MS\\,cmask\\=3D1\\,edge@ = / (tma_retiring * tma_info_slots / cpu_core@UOPS_ISSUED.ANY@) / tma_info_cl= ks", "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch= _latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO", "MetricName": "tma_ms_switches", "MetricThreshold": "tma_ms_switches > 0.05 & (tma_fetch_latency > = 0.1 & tma_frontend_bound > 0.15)", @@ -2221,7 +2221,7 @@ }, { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring branch instructions that were not fused", - "MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHE= S - INST_RETIRED.MACRO_FUSED) / (tma_retiring * tma_info_slots)", + "MetricExpr": "tma_light_operations * (cpu_core@BR_INST_RETIRED.AL= L_BRANCHES@ - cpu_core@INST_RETIRED.MACRO_FUSED@) / (tma_retiring * tma_inf= o_slots)", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", "MetricName": "tma_non_fused_branches", "MetricThreshold": "tma_non_fused_branches > 0.1 & tma_light_opera= tions > 0.6", @@ -2231,7 +2231,7 @@ }, { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring NOP (no op) instructions", - "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / (tma_reti= ring * tma_info_slots)", + "MetricExpr": "tma_light_operations * cpu_core@INST_RETIRED.NOP@ /= (tma_retiring * tma_info_slots)", "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", "MetricName": "tma_nop_instructions", "MetricThreshold": "tma_nop_instructions > 0.1 & tma_light_operati= ons > 0.6", @@ -2252,7 +2252,7 @@ }, { "BriefDescription": "This metric roughly estimates fraction of slo= ts the CPU retired uops as a result of handing Page Faults", - "MetricExpr": "99 * ASSISTS.PAGE_FAULT / tma_info_slots", + "MetricExpr": "99 * cpu_core@ASSISTS.PAGE_FAULT@ / tma_info_slots", "MetricGroup": "TopdownL5;tma_L5_group;tma_assists_group", "MetricName": "tma_page_faults", "MetricThreshold": "tma_page_faults > 0.05", @@ -2292,7 +2292,7 @@ }, { "BriefDescription": "This metric estimates fraction of cycles the = CPU performance was potentially limited due to Core computation issues (non= divider-related)", - "MetricExpr": "((cpu_core@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=3D0x= 80@ + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVI= TY.BOUND_ON_LOADS) + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu_core@E= XE_ACTIVITY.2_PORTS_UTIL\\,umask\\=3D0xc@)) / tma_info_clks if ARITH.DIV_AC= TIVE < CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS else (EXE_= ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu_core@EXE_ACTIVITY.2_PORTS_UTIL\\= ,umask\\=3D0xc@) / tma_info_clks)", + "MetricExpr": "((cpu_core@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=3D0x= 80@ + tma_serializing_operation * (cpu_core@CYCLE_ACTIVITY.STALLS_TOTAL@ - = cpu_core@EXE_ACTIVITY.BOUND_ON_LOADS@) + (cpu_core@EXE_ACTIVITY.1_PORTS_UTI= L@ + tma_retiring * cpu_core@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=3D0xc@)) /= tma_info_clks if cpu_core@ARITH.DIV_ACTIVE@ < cpu_core@CYCLE_ACTIVITY.STAL= LS_TOTAL@ - cpu_core@EXE_ACTIVITY.BOUND_ON_LOADS@ else (cpu_core@EXE_ACTIVI= TY.1_PORTS_UTIL@ + tma_retiring * cpu_core@EXE_ACTIVITY.2_PORTS_UTIL\\,umas= k\\=3D0xc@) / tma_info_clks)", "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_gr= oup", "MetricName": "tma_ports_utilization", "MetricThreshold": "tma_ports_utilization > 0.15 & (tma_core_bound= > 0.1 & tma_backend_bound > 0.2)", @@ -2302,7 +2302,7 @@ }, { "BriefDescription": "This metric represents fraction of cycles CPU= executed no uops on any execution port (Logical Processor cycles since ICL= , Physical Core cycles otherwise)", - "MetricExpr": "cpu_core@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=3D0x80= @ / tma_info_clks + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTA= L - EXE_ACTIVITY.BOUND_ON_LOADS) / tma_info_clks", + "MetricExpr": "cpu_core@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=3D0x80= @ / tma_info_clks + tma_serializing_operation * (cpu_core@CYCLE_ACTIVITY.ST= ALLS_TOTAL@ - cpu_core@EXE_ACTIVITY.BOUND_ON_LOADS@) / tma_info_clks", "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utiliza= tion_group", "MetricName": "tma_ports_utilized_0", "MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utiliz= ation > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", @@ -2342,7 +2342,7 @@ }, { "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdow= n\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_info_= slots", + "MetricExpr": "cpu_core@topdown\\-retiring@ / (cpu_core@topdown\\-= fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ + cpu_core@topdown\\-retiring@= + cpu_core@topdown\\-be\\-bound@) + 0 * tma_info_slots", "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", @@ -2382,7 +2382,7 @@ }, { "BriefDescription": "This metric estimates fraction of cycles hand= ling memory load split accesses - load that cross 64-byte cache line bounda= ry", - "MetricExpr": "tma_info_load_miss_real_latency * LD_BLOCKS.NO_SR /= tma_info_clks", + "MetricExpr": "tma_info_load_miss_real_latency * cpu_core@LD_BLOCK= S.NO_SR@ / tma_info_clks", "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", "MetricName": "tma_split_loads", "MetricThreshold": "tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & = (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", @@ -2402,7 +2402,7 @@ }, { "BriefDescription": "This metric measures fraction of cycles where= the Super Queue (SQ) was full taking into account all request-types and bo= th hardware SMT threads (Logical Processors)", - "MetricExpr": "(XQ.FULL_CYCLES + L1D_PEND_MISS.L2_STALLS) / tma_in= fo_clks", + "MetricExpr": "(cpu_core@XQ.FULL_CYCLES@ + cpu_core@L1D_PEND_MISS.= L2_STALLS@) / tma_info_clks", "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueB= W;tma_l3_bound_group", "MetricName": "tma_sq_full", "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tm= a_memory_bound > 0.2 & tma_backend_bound > 0.2))", @@ -2422,7 +2422,7 @@ }, { "BriefDescription": "This metric roughly estimates fraction of cyc= les when the memory subsystem had loads blocked since they could not forwar= d data from earlier (in program order) overlapping stores", - "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / tma_info_clks", + "MetricExpr": "13 * cpu_core@LD_BLOCKS.STORE_FORWARD@ / tma_info_c= lks", "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", "MetricName": "tma_store_fwd_blk", "MetricThreshold": "tma_store_fwd_blk > 0.1 & (tma_l1_bound > 0.1 = & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", @@ -2432,7 +2432,7 @@ }, { "BriefDescription": "This metric estimates fraction of cycles the = CPU spent handling L1D store misses", - "MetricExpr": "(MEM_STORE_RETIRED.L2_HIT * 10 * (1 - MEM_INST_RETI= RED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_= LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE= _REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_clks", + "MetricExpr": "(cpu_core@MEM_STORE_RETIRED.L2_HIT@ * 10 * (1 - cpu= _core@MEM_INST_RETIRED.LOCK_LOADS@ / cpu_core@MEM_INST_RETIRED.ALL_STORES@)= + (1 - cpu_core@MEM_INST_RETIRED.LOCK_LOADS@ / cpu_core@MEM_INST_RETIRED.A= LL_STORES@) * min(cpu_core@CPU_CLK_UNHALTED.THREAD@, cpu_core@OFFCORE_REQUE= STS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO@)) / tma_info_clks", "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issue= RFO;tma_issueSL;tma_store_bound_group", "MetricName": "tma_store_latency", "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0= .2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", @@ -2442,7 +2442,7 @@ }, { "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution port for Store operations", - "MetricExpr": "(UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_= 8) / (4 * tma_info_core_clks)", + "MetricExpr": "(cpu_core@UOPS_DISPATCHED.PORT_4_9@ + cpu_core@UOPS= _DISPATCHED.PORT_7_8@) / (4 * tma_info_core_clks)", "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group= ", "MetricName": "tma_store_op_utilization", "MetricThreshold": "tma_store_op_utilization > 0.6", @@ -2470,7 +2470,7 @@ }, { "BriefDescription": "This metric estimates how often CPU was stall= ed due to Streaming store memory accesses; Streaming store optimize out a = read request required by RFO stores", - "MetricExpr": "9 * OCR.STREAMING_WR.ANY_RESPONSE / tma_info_clks", + "MetricExpr": "9 * cpu_core@OCR.STREAMING_WR.ANY_RESPONSE@ / tma_i= nfo_clks", "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueS= mSt;tma_store_bound_group", "MetricName": "tma_streaming_stores", "MetricThreshold": "tma_streaming_stores > 0.2 & (tma_store_bound = > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", @@ -2490,7 +2490,7 @@ }, { "BriefDescription": "This metric serves as an approximation of leg= acy x87 usage", - "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.TH= READ", + "MetricExpr": "tma_retiring * cpu_core@UOPS_EXECUTED.X87@ / UOPS_E= XECUTED.THREAD", "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", "MetricName": "tma_x87_use", "MetricThreshold": "tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_= light_operations > 0.6)", diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json b/= tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json index 0402adbf7d92..f4b3c3883643 100644 --- a/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json +++ b/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json @@ -193,7 +193,7 @@ { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / tma_info_clks - ME= M_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOU= ND_STALLS.LOAD", + "MetricExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / tma_info_clks - ma= x((MEM_BOUND_STALLS.LOAD - LD_HEAD.L1_MISS_AT_RET) / tma_info_clks, 0) * ME= M_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOUND_STALLS.LOAD", "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_dram_bound", "MetricThreshold": "tma_dram_bound > 0.1", @@ -480,7 +480,7 @@ { "BriefDescription": "Counts the number of cycles a core is stalled= due to a demand load which hit in the L2 Cache.", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / tma_info_clks - MEM_= BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_S= TALLS.LOAD", + "MetricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / tma_info_clks - max(= (MEM_BOUND_STALLS.LOAD - LD_HEAD.L1_MISS_AT_RET) / tma_info_clks, 0) * MEM_= BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_STALLS.LOAD", "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l2_bound", "MetricThreshold": "tma_l2_bound > 0.1", @@ -488,7 +488,7 @@ }, { "BriefDescription": "Counts the number of cycles a core is stalled= due to a demand load which hit in the Last Level Cache (LLC) or other core= with HITE/F/M.", - "MetricExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / tma_info_clks - MEM= _BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND= _STALLS.LOAD", + "MetricExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / tma_info_clks - max= ((MEM_BOUND_STALLS.LOAD - LD_HEAD.L1_MISS_AT_RET) / tma_info_clks, 0) * MEM= _BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND_STALLS.LOAD", "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l3_bound", "MetricThreshold": "tma_l3_bound > 0.1", --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:40 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D465C77B60 for ; Wed, 26 Apr 2023 07:13:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239950AbjDZHNr (ORCPT ); Wed, 26 Apr 2023 03:13:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52326 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239624AbjDZHNT (ORCPT ); Wed, 26 Apr 2023 03:13:19 -0400 Received: from mail-yb1-f202.google.com (mail-yb1-f202.google.com [209.85.219.202]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7CAB13C06 for ; Wed, 26 Apr 2023 00:12:37 -0700 (PDT) Received: by mail-yb1-f202.google.com with SMTP id 3f1490d57ef6-b9a25f6aa0eso1478580276.1 for ; Wed, 26 Apr 2023 00:12:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1682492788; x=1685084788; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=6DTTYiMDl8Yj+KSHhgdntFRxS2mVbWmHBiQYwku76Lg=; b=NuU46hM8LqQefH+YUTb3RKzWxAv35JqvJXoIH5cWztwofbicXwg7nad3a6f9YfDNEL rEtUMgkRfEzT1d2Vwg+Atwo1CgX6Ua4BRxM4sfuvrH5Y9uT1uimewphrq8Orj+A/FjhY nh1UFa/id/1xp7od0utvoOYBMMUYApzDoJH9+ckOtTEzj5/ft0UquC6DP/QnX+XH0pd9 o4Zcl2XAEf6GCsalvz9OezYmZJnhUJtgcNIHU3DbIx+CjQ4XLGWHqNW9yhAG1E+KihJO JNhPN/xm0YvM2apAOD79h/cXTF9wIUNgAC/ydIZcOKYxjQPoJj/rSkMZmxxNbZuik0pm ubvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682492788; x=1685084788; h=cc:to:from:subject:references:mime-version:message-id:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=6DTTYiMDl8Yj+KSHhgdntFRxS2mVbWmHBiQYwku76Lg=; b=jT2J2YLXZMY+yHRbdBohE9ldjmRs322LoKqyKqRia4JCpz0Up5SAMbxXLQrAJErHtt goWAfDCrhdgWT76z9DnbEoH89XpU/TAmiN3evZ5UdFK4g/aXTBwdWaaoTD7uMLIjz2Vr F3HB2oux4nIpgK5gnQcGS8LUbvwK7Jj9295y1a3FUcqLrms3j/kcjbv/cc3BHGBQsjR2 ppV5xbBkn7Q47OJEllBHXC2zmzNnGNa2LysBYBXV53mURivMrSeyLEzkL4Rv/BtklqjF 2HJK37GWFzv7PmJGWJkRLagMLvneNn0OvoBH7mjjerSZSCHaDRUgcY+1Wz2giMVWBLXk 4pdw== X-Gm-Message-State: AAQBX9flp2xldzQekS7urm5lDhXYDRylNpZhtFVwn8p3fR4hEAdW3w2W RyYYIZ9CqkFBj0tNvRe0o++d2w4kfqt2 X-Google-Smtp-Source: AKy350Z9EdBOGRby4FVj8/HeMI26okxYHasdc/bUPii0Q+dU/MCrrt49ESbpBWfw59SxjTfBMB0tnZmFnrjf X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:144f:e890:2b29:48d9]) (user=irogers job=sendgmr) by 2002:a25:cf13:0:b0:b92:37f6:faff with SMTP id f19-20020a25cf13000000b00b9237f6faffmr7735741ybg.10.1682492788563; Wed, 26 Apr 2023 00:06:28 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:49 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-40-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 39/40] perf jevents: Don't rewrite metrics across PMUs From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Don't rewrite metrics across PMUs as the result events likely won't be found. Identify metrics with a pair of PMU name and metric name. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/jevents.py | 4 ++-- tools/perf/pmu-events/metric.py | 28 +++++++++++++++++----------- tools/perf/pmu-events/metric_test.py | 6 +++--- 3 files changed, 22 insertions(+), 16 deletions(-) diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jeven= ts.py index b18dd2fcbf04..487ff01baf1b 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -391,11 +391,11 @@ def read_json_events(path: str, topic: str) -> Sequen= ce[JsonEvent]: except BaseException as err: print(f"Exception processing {path}") raise - metrics: list[Tuple[str, metric.Expression]] =3D [] + metrics: list[Tuple[str, str, metric.Expression]] =3D [] for event in events: event.topic =3D topic if event.metric_name and '-' not in event.metric_name: - metrics.append((event.metric_name, event.metric_expr)) + metrics.append((event.pmu, event.metric_name, event.metric_expr)) updates =3D metric.RewriteMetricsInTermsOfOthers(metrics) if updates: for event in events: diff --git a/tools/perf/pmu-events/metric.py b/tools/perf/pmu-events/metric= .py index 8ec0ba884673..af58b74d1644 100644 --- a/tools/perf/pmu-events/metric.py +++ b/tools/perf/pmu-events/metric.py @@ -552,28 +552,34 @@ def ParsePerfJson(orig: str) -> Expression: return _Constify(eval(compile(parsed, orig, 'eval'))) =20 =20 -def RewriteMetricsInTermsOfOthers(metrics: List[Tuple[str, Expression]] - )-> Dict[str, Expression]: +def RewriteMetricsInTermsOfOthers(metrics: List[Tuple[str, str, Expression= ]] + )-> Dict[Tuple[str, str], Expression]: """Shorten metrics by rewriting in terms of others. =20 Args: - metrics (list): pairs of metric names and their expressions. + metrics (list): pmus, metric names and their expressions. Returns: - Dict: mapping from a metric name to a shortened expression. + Dict: mapping from a pmu, metric name pair to a shortened expression. """ - updates: Dict[str, Expression] =3D dict() - for outer_name, outer_expression in metrics: + updates: Dict[Tuple[str, str], Expression] =3D dict() + for outer_pmu, outer_name, outer_expression in metrics: + if outer_pmu is None: + outer_pmu =3D 'cpu' updated =3D outer_expression while True: - for inner_name, inner_expression in metrics: + for inner_pmu, inner_name, inner_expression in metrics: + if inner_pmu is None: + inner_pmu =3D 'cpu' + if inner_pmu.lower() !=3D outer_pmu.lower(): + continue if inner_name.lower() =3D=3D outer_name.lower(): continue - if inner_name in updates: - inner_expression =3D updates[inner_name] + if (inner_pmu, inner_name) in updates: + inner_expression =3D updates[(inner_pmu, inner_name)] updated =3D updated.Substitute(inner_name, inner_expression) if updated.Equals(outer_expression): break - if outer_name in updates and updated.Equals(updates[outer_name]): + if (outer_pmu, outer_name) in updates and updated.Equals(updates[(ou= ter_pmu, outer_name)]): break - updates[outer_name] =3D updated + updates[(outer_pmu, outer_name)] =3D updated return updates diff --git a/tools/perf/pmu-events/metric_test.py b/tools/perf/pmu-events/m= etric_test.py index 40a3c7d8b2bc..ee22ff43ddd7 100755 --- a/tools/perf/pmu-events/metric_test.py +++ b/tools/perf/pmu-events/metric_test.py @@ -158,9 +158,9 @@ class TestMetricExpressions(unittest.TestCase): =20 def test_RewriteMetricsInTermsOfOthers(self): Expression.__eq__ =3D lambda e1, e2: e1.Equals(e2) - before =3D [('m1', ParsePerfJson('a + b + c + d')), - ('m2', ParsePerfJson('a + b + c'))] - after =3D {'m1': ParsePerfJson('m2 + d')} + before =3D [('cpu', 'm1', ParsePerfJson('a + b + c + d')), + ('cpu', 'm2', ParsePerfJson('a + b + c'))] + after =3D {('cpu', 'm1'): ParsePerfJson('m2 + d')} self.assertEqual(RewriteMetricsInTermsOfOthers(before), after) Expression.__eq__ =3D None =20 --=20 2.40.1.495.gc816e09b53d-goog From nobody Thu Dec 18 01:07:40 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B9E9C77B78 for ; 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Wed, 26 Apr 2023 00:06:36 -0700 (PDT) Date: Wed, 26 Apr 2023 00:00:50 -0700 In-Reply-To: <20230426070050.1315519-1-irogers@google.com> Message-Id: <20230426070050.1315519-41-irogers@google.com> Mime-Version: 1.0 References: <20230426070050.1315519-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.495.gc816e09b53d-goog Subject: [PATCH v1 40/40] perf metrics: Be PMU specific in event match From: Ian Rogers To: Arnaldo Carvalho de Melo , Kan Liang , Ahmad Yasin , Peter Zijlstra , Ingo Molnar , Stephane Eranian , Andi Kleen , Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Adrian Hunter , Florian Fischer , Rob Herring , Zhengjun Xing , John Garry , Kajol Jain , Sumanth Korikkar , Thomas Richter , Tiezhu Yang , Ravi Bangoria , Leo Yan , Yang Jihong , James Clark , Suzuki Poulouse , Kang Minchul , Athira Rajeev , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Rogers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Ids/events from a metric are turned into an event string and parsed; setup_metric_events matches the id back to the parsed evsel. With hybrid the same event may exist on both PMUs with the same name and be being used by metrics at the same time. A metric on cpu_core therefore shouldn't match against evsels on cpu_atom, or the metric will compute the wrong value. Make the matching sensitive to the PMU being parsed. Signed-off-by: Ian Rogers --- tools/perf/util/metricgroup.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index 4245b23d8efe..490561f430f2 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -274,7 +274,7 @@ static int setup_metric_events(const char *pmu, struct = hashmap *ids, const char *metric_id; struct evsel *ev; size_t ids_size, matched_events, i; - bool all_pmus =3D !strcmp(pmu, "all"); + bool all_pmus =3D !strcmp(pmu, "all") || !perf_pmu__is_hybrid(pmu); =20 *out_metric_events =3D NULL; ids_size =3D hashmap__size(ids); @@ -287,7 +287,10 @@ static int setup_metric_events(const char *pmu, struct= hashmap *ids, evlist__for_each_entry(metric_evlist, ev) { struct expr_id_data *val_ptr; =20 - if (!all_pmus && strcmp(ev->pmu_name, pmu)) + /* Don't match events for the wrong hybrid PMU. */ + if (!all_pmus && ev->pmu_name && + perf_pmu__is_hybrid(ev->pmu_name) && + strcmp(ev->pmu_name, pmu)) continue; /* * Check for duplicate events with the same name. For @@ -304,6 +307,7 @@ static int setup_metric_events(const char *pmu, struct = hashmap *ids, * about this event. */ if (hashmap__find(ids, metric_id, &val_ptr)) { + pr_debug("Matched metric-id %s to %s\n", metric_id, evsel__name(ev)); metric_events[matched_events++] =3D ev; =20 if (matched_events >=3D ids_size) @@ -1592,7 +1596,7 @@ static int parse_groups(struct evlist *perf_evlist, ret =3D setup_metric_events(fake_pmu ? "all" : m->pmu, m->pctx->ids, metric_evlist, &metric_events); if (ret) { - pr_debug("Cannot resolve IDs for %s: %s\n", + pr_err("Cannot resolve IDs for %s: %s\n", m->metric_name, m->metric_expr); goto out; } --=20 2.40.1.495.gc816e09b53d-goog