From nobody Thu Feb 12 09:01:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C6E6C6FD18 for ; Tue, 25 Apr 2023 13:33:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234099AbjDYNdX (ORCPT ); Tue, 25 Apr 2023 09:33:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59112 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233539AbjDYNdR (ORCPT ); Tue, 25 Apr 2023 09:33:17 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E8FC14470; Tue, 25 Apr 2023 06:32:37 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 33PDWUDZ130322; Tue, 25 Apr 2023 08:32:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1682429550; bh=OhI6iPvELcqsP2Y6gu4QTU0CmmRcgvcgrZOmxdxZUL0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=pD8OVm9uc1pL5lS6Z+cKSvaCql79RboKhku+RUvdqchsZeo30IqGGK7YMULuaioKQ FKNQM2SvbmWegYWnNykWzP8ScR9dG/xL9aF96wf72xCGc0vqZMQdvmQsP0kP/5hKkP TnLsnI5eOZnQxhRz7IDkFzslWYMU0ka7D+Wl1PXE= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 33PDWUB9114481 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 25 Apr 2023 08:32:30 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 25 Apr 2023 08:32:30 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 25 Apr 2023 08:32:30 -0500 Received: from uda0492258.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 33PDWNHI042485; Tue, 25 Apr 2023 08:32:27 -0500 From: Siddharth Vadapalli To: , , , , , , CC: , , , , Subject: [RFC PATCH 1/3] arm64: dts: ti: k3-j784s4-main: Add CPSW9G nodes Date: Tue, 25 Apr 2023 19:02:21 +0530 Message-ID: <20230425133223.4060752-2-s-vadapalli@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230425133223.4060752-1-s-vadapalli@ti.com> References: <20230425133223.4060752-1-s-vadapalli@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" J784S4 SoC has a 9 port Ethernet Switch instance with 8 external ports and 1 host port, referred to as CPSW9G. Add device-tree nodes for CPSW9G and disable it by default. Device-tree overlays will be used to enable it. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 114 +++++++++++++++++++++ 1 file changed, 114 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j784s4-main.dtsi index 7111fe3640d3..cc145840d0c3 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -51,6 +51,13 @@ cpsw1_phy_gmii_sel: phy@4034 { #phy-cells =3D <1>; }; =20 + cpsw0_phy_gmii_sel: phy@4044 { + compatible =3D "ti,j784s4-cpsw9g-phy-gmii-sel"; + ti,qsgmii-main-ports =3D <7>, <7>; + reg =3D <0x4044 0x20>; + #phy-cells =3D <1>; + }; + serdes_ln_ctrl: mux-controller@4080 { compatible =3D "mmio-mux"; reg =3D <0x00004080 0x30>; @@ -955,6 +962,113 @@ cpts@310d0000 { }; }; =20 + main_cpsw0: ethernet@c000000 { + compatible =3D "ti,j784s4-cpswxg-nuss"; + reg =3D <0x00 0xc000000 0x00 0x200000>; + reg-names =3D "cpsw_nuss"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x00 0x00 0x00 0xc000000 0x00 0x200000>; + dma-coherent; + clocks =3D <&k3_clks 64 0>; + clock-names =3D "fck"; + power-domains =3D <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; + + dmas =3D <&main_udmap 0xca00>, + <&main_udmap 0xca01>, + <&main_udmap 0xca02>, + <&main_udmap 0xca03>, + <&main_udmap 0xca04>, + <&main_udmap 0xca05>, + <&main_udmap 0xca06>, + <&main_udmap 0xca07>, + <&main_udmap 0x4a00>; + dma-names =3D "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + status =3D "disabled"; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + main_cpsw0_port1: port@1 { + reg =3D <1>; + label =3D "port1"; + ti,mac-only; + status =3D "disabled"; + }; + + main_cpsw0_port2: port@2 { + reg =3D <2>; + label =3D "port2"; + ti,mac-only; + status =3D "disabled"; + }; + + main_cpsw0_port3: port@3 { + reg =3D <3>; + label =3D "port3"; + ti,mac-only; + status =3D "disabled"; + }; + + main_cpsw0_port4: port@4 { + reg =3D <4>; + label =3D "port4"; + ti,mac-only; + status =3D "disabled"; + }; + + main_cpsw0_port5: port@5 { + reg =3D <5>; + label =3D "port5"; + status =3D "disabled"; + }; + + main_cpsw0_port6: port@6 { + reg =3D <6>; + label =3D "port6"; + status =3D "disabled"; + }; + + main_cpsw0_port7: port@7 { + reg =3D <7>; + label =3D "port7"; + status =3D "disabled"; + }; + + main_cpsw0_port8: port@8 { + reg =3D <8>; + label =3D "port8"; + status =3D "disabled"; + }; + }; + + main_cpsw0_mdio: mdio@f00 { + compatible =3D "ti,cpsw-mdio","ti,davinci_mdio"; + reg =3D <0x00 0xf00 0x00 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&k3_clks 64 0>; + clock-names =3D "fck"; + bus_freq =3D <1000000>; + status =3D "disabled"; + }; + + cpts@3d000 { + compatible =3D "ti,am65-cpts"; + reg =3D <0x00 0x3d000 0x00 0x400>; + clocks =3D <&k3_clks 64 3>; + clock-names =3D "cpts"; + interrupts-extended =3D <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "cpts"; + ti,cpts-ext-ts-inputs =3D <4>; + ti,cpts-periodic-outputs =3D <2>; + }; + }; + main_cpsw1: ethernet@c200000 { compatible =3D "ti,j721e-cpsw-nuss"; reg =3D <0x00 0xc200000 0x00 0x200000>; --=20 2.25.1 From nobody Thu Feb 12 09:01:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58758C6FD18 for ; Tue, 25 Apr 2023 13:33:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234190AbjDYNd1 (ORCPT ); Tue, 25 Apr 2023 09:33:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59472 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234025AbjDYNdU (ORCPT ); Tue, 25 Apr 2023 09:33:20 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 70BCF13FA4; Tue, 25 Apr 2023 06:32:46 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 33PDWZOm045243; Tue, 25 Apr 2023 08:32:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1682429555; bh=N2MePNfVzVxibEIreezgwShBvRJA536Aaebxn8Mr/mA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=rTeMmRq/GMd1iOeAYdiA5RQaLvplHQtz55t7WLKiVL1BKHpzT3OtstxZ/ONbJx2tp LgrU0+NjfFqtxgHrqgZkzFGMeTtx/VPCzNh5j4+TiLYbU9+dAhsVS5AOuhtNYHsruE VUd23EfyNZ14ZrsmpUQP0pCYgT4GyTT2R4imyCLY= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 33PDWZF5014345 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 25 Apr 2023 08:32:35 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 25 Apr 2023 08:32:34 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 25 Apr 2023 08:32:34 -0500 Received: from uda0492258.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 33PDWNHJ042485; Tue, 25 Apr 2023 08:32:31 -0500 From: Siddharth Vadapalli To: , , , , , , CC: , , , , Subject: [RFC PATCH 2/3] arm64: dts: ti: k3-j784s4: Add overlay to enable QSGMII mode with CPSW9G Date: Tue, 25 Apr 2023 19:02:22 +0530 Message-ID: <20230425133223.4060752-3-s-vadapalli@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230425133223.4060752-1-s-vadapalli@ti.com> References: <20230425133223.4060752-1-s-vadapalli@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The J7 Quad Port Add-On Ethernet Card for J784S4 EVM supports QSGMII mode. Use the overlay to configure CPSW9G ports in QSGMII mode with the Add-On Ethernet Card connected to the ENET Expansion 1 slot on the EVM. Add support to reset the PHY from kernel by using gpio-hog and gpio-reset. Add aliases for CPSW9G ports to enable kernel to fetch MAC Addresses directly from U-Boot. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/Makefile | 2 + .../ti/k3-j784s4-evm-quad-port-eth-exp1.dtso | 142 ++++++++++++++++++ 2 files changed, 144 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1= .dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index c83c9d772b81..88c43f1f211b 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -46,6 +46,8 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j721s2-common-proc-board.dtb # Boards with J784s4 SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am69-sk.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm.dtb +dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm-quad-port-eth-exp1.dtbo =20 # Enable support for device-tree overlays DTC_FLAGS_k3-am6548-iot2050-advanced-m2 +=3D -@ +DTC_FLAGS_k3-j784s4-evm +=3D -@ diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso b= /arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso new file mode 100644 index 000000000000..3c1e1b1d495c --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On = Ethernet Card with + * J7AHP board. The Add-On Ethernet Card has to be connected to ENET Expan= sion 1 slot on the + * board. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet1 =3D "/bus@100000/ethernet@c000000/ethernet-ports/port@5"; + ethernet2 =3D "/bus@100000/ethernet@c000000/ethernet-ports/port@6"; + ethernet3 =3D "/bus@100000/ethernet@c000000/ethernet-ports/port@7"; + ethernet4 =3D "/bus@100000/ethernet@c000000/ethernet-ports/port@8"; + }; +}; + +&main_cpsw0 { + status =3D "okay"; +}; + +&main_cpsw0_port5 { + status =3D "okay"; + phy-handle =3D <&cpsw9g_phy1>; + phy-mode =3D "qsgmii"; + mac-address =3D [00 00 00 00 00 00]; + phys =3D <&cpsw0_phy_gmii_sel 5>, <&serdes2_qsgmii_link>; + phy-names =3D "mac", "serdes"; +}; + +&main_cpsw0_port6 { + status =3D "okay"; + phy-handle =3D <&cpsw9g_phy2>; + phy-mode =3D "qsgmii"; + mac-address =3D [00 00 00 00 00 00]; + phys =3D <&cpsw0_phy_gmii_sel 6>, <&serdes2_qsgmii_link>; + phy-names =3D "mac", "serdes"; +}; + +&main_cpsw0_port7 { + status =3D "okay"; + phy-handle =3D <&cpsw9g_phy0>; + phy-mode =3D "qsgmii"; + mac-address =3D [00 00 00 00 00 00]; + phys =3D <&cpsw0_phy_gmii_sel 7>, <&serdes2_qsgmii_link>; + phy-names =3D "mac", "serdes"; +}; + +&main_cpsw0_port8 { + status =3D "okay"; + phy-handle =3D <&cpsw9g_phy3>; + phy-mode =3D "qsgmii"; + mac-address =3D [00 00 00 00 00 00]; + phys =3D <&cpsw0_phy_gmii_sel 8>, <&serdes2_qsgmii_link>; + phy-names =3D "mac", "serdes"; +}; + +&main_cpsw0_mdio { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mdio0_pins_default>; + bus_freq =3D <1000000>; + reset-gpios =3D <&exp2 17 GPIO_ACTIVE_LOW>; + reset-post-delay-us =3D <120000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpsw9g_phy0: ethernet-phy@16 { + reg =3D <16>; + }; + cpsw9g_phy1: ethernet-phy@17 { + reg =3D <17>; + }; + cpsw9g_phy2: ethernet-phy@18 { + reg =3D <18>; + }; + cpsw9g_phy3: ethernet-phy@19 { + reg =3D <19>; + }; +}; + +&exp2 { + /* Power-up ENET1 EXPANDER PHY. */ + qsgmii-line-hog { + gpio-hog; + gpios =3D <16 GPIO_ACTIVE_HIGH>; + output-low; + }; + /* Toggle MUX2 for MDIO lines */ + mux-sel-hog { + gpio-hog; + gpios =3D <13 GPIO_ACTIVE_HIGH>, <14 GPIO_ACTIVE_HIGH>, <15 GPIO_ACTIVE_= HIGH>; + output-high; + }; +}; + +&main_pmx0 { + mdio0_pins_default: mdio0-pins-default { + pinctrl-single,pins =3D < + J784S4_IOPAD(0x05c, PIN_INPUT, 4) /* (AC36) MCASP2_AXR0.MDIO1_MDIO */ + J784S4_IOPAD(0x058, PIN_INPUT, 4) /* (AE37) MCASP2_AFSX.MDIO1_MDC */ + >; + }; +}; + +&serdes_ln_ctrl { + idle-states =3D , , + , , + , , + , , + , , + , ; +}; + +&serdes_wiz2 { + status =3D "okay"; +}; + +&serdes2 { + status =3D "okay"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + serdes2_qsgmii_link: phy@0 { + reg =3D <2>; + cdns,num-lanes =3D <1>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz2 3>; + }; +}; --=20 2.25.1 From nobody Thu Feb 12 09:01:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DEE21C77B61 for ; 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Tue, 25 Apr 2023 08:32:37 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 25 Apr 2023 08:32:37 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Tue, 25 Apr 2023 08:32:37 -0500 Received: from uda0492258.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 33PDWNHK042485; Tue, 25 Apr 2023 08:32:34 -0500 From: Siddharth Vadapalli To: , , , , , , CC: , , , , Subject: [RFC PATCH 3/3] arm64: dts: ti: k3-j784s4: Add overlay for dual port USXGMII mode Date: Tue, 25 Apr 2023 19:02:23 +0530 Message-ID: <20230425133223.4060752-4-s-vadapalli@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230425133223.4060752-1-s-vadapalli@ti.com> References: <20230425133223.4060752-1-s-vadapalli@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The CPSW9G instance of the CPSW Ethernet Switch supports USXGMII mode with MAC Ports 1 and 2 of the instance, which are connected to ENET Expansion 1 and ENET Expansion 2 slots on the EVM respectively, through the Serdes2 instance of the SERDES. Enable CPSW9G MAC Ports 1 and 2 in fixed-link configuration USXGMII mode at 5 Gbps each. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/Makefile | 1 + .../ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso | 72 +++++++++++++++++++ 2 files changed, 73 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.= dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 88c43f1f211b..8ac7507f60ba 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -47,6 +47,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j721s2-common-proc-board.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am69-sk.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm-quad-port-eth-exp1.dtbo +dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm-usxgmii-exp1-exp2.dtbo =20 # Enable support for device-tree overlays DTC_FLAGS_k3-am6548-iot2050-advanced-m2 +=3D -@ diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso b/= arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso new file mode 100644 index 000000000000..90f045a6a9ad --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for CPSW9G in dual port fixed-link USXGMII mode using ENET-1 + * and ENET-2 Expansion slots of J784S4 EVM. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +&main_cpsw0 { + status =3D "okay"; + pinctrl-names =3D "default"; +}; + +&main_cpsw0_port1 { + status =3D "okay"; + phy-mode =3D "usxgmii"; + mac-address =3D [00 00 00 00 00 00]; + phys =3D <&cpsw0_phy_gmii_sel 1>, <&serdes2_usxgmii_link>; + phy-names =3D "mac", "serdes"; + fixed-link { + speed =3D <5000>; + full-duplex; + }; +}; + +&main_cpsw0_port2 { + status =3D "okay"; + phy-mode =3D "usxgmii"; + mac-address =3D [00 00 00 00 00 00]; + phys =3D <&cpsw0_phy_gmii_sel 2>, <&serdes2_usxgmii_link>; + phy-names =3D "mac", "serdes"; + fixed-link { + speed =3D <5000>; + full-duplex; + }; +}; + +&serdes_wiz2 { + status =3D "okay"; + assigned-clock-parents =3D <&k3_clks 406 9>; +}; + +&serdes2 { + status =3D "okay"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + serdes2_usxgmii_link: phy@2 { + reg =3D <2>; + cdns,num-lanes =3D <2>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz2 3>, <&serdes_wiz2 4>; + }; +}; + +&serdes_ln_ctrl { + idle-states =3D , , + , , + , , + , , + , , + , ; +}; --=20 2.25.1