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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id 30-20020a63125e000000b0051b70c8d446sm7644715pgs.73.2023.04.25.03.24.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Apr 2023 03:24:55 -0700 (PDT) From: Jacky Huang To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, jirislaby@kernel.org, tmaimon77@gmail.com, catalin.marinas@arm.com, will@kernel.org Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-serial@vger.kernel.org, arnd@arndb.de, schung@nuvoton.com, mjchen@nuvoton.com, Jacky Huang Subject: [PATCH v8 09/11] reset: Add Nuvoton ma35d1 reset driver support Date: Tue, 25 Apr 2023 10:24:16 +0000 Message-Id: <20230425102418.185783-10-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230425102418.185783-1-ychuang570808@gmail.com> References: <20230425102418.185783-1-ychuang570808@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Jacky Huang This driver supports individual IP reset for ma35d1. The reset control registers is a subset of system control registers. Signed-off-by: Jacky Huang --- drivers/reset/Kconfig | 6 + drivers/reset/Makefile | 1 + drivers/reset/reset-ma35d1.c | 229 +++++++++++++++++++++++++++++++++++ 3 files changed, 236 insertions(+) create mode 100644 drivers/reset/reset-ma35d1.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 2a52c990d4fe..58477c6ca9b8 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -143,6 +143,12 @@ config RESET_NPCM This enables the reset controller driver for Nuvoton NPCM BMC SoCs. =20 +config RESET_NUVOTON_MA35D1 + bool "Nuvton MA35D1 Reset Driver" + default ARCH_NUVOTON || COMPILE_TEST + help + This enables the reset controller driver for Nuvoton MA35D1 SoC. + config RESET_OXNAS bool =20 diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 3e7e5fd633a8..fd52dcf66a99 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_RESET_MCHP_SPARX5) +=3D reset-microchip-spar= x5.o obj-$(CONFIG_RESET_MESON) +=3D reset-meson.o obj-$(CONFIG_RESET_MESON_AUDIO_ARB) +=3D reset-meson-audio-arb.o obj-$(CONFIG_RESET_NPCM) +=3D reset-npcm.o +obj-$(CONFIG_RESET_NUVOTON_MA35D1) +=3D reset-ma35d1.o obj-$(CONFIG_RESET_OXNAS) +=3D reset-oxnas.o obj-$(CONFIG_RESET_PISTACHIO) +=3D reset-pistachio.o obj-$(CONFIG_RESET_POLARFIRE_SOC) +=3D reset-mpfs.o diff --git a/drivers/reset/reset-ma35d1.c b/drivers/reset/reset-ma35d1.c new file mode 100644 index 000000000000..648b380becf7 --- /dev/null +++ b/drivers/reset/reset-ma35d1.c @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Nuvoton Technology Corp. + * Author: Chi-Fang Li + */ + +#include +#include +#include +#include +#include +#include +#include + +struct ma35d1_reset_data { + struct reset_controller_dev rcdev; + struct notifier_block restart_handler; + void __iomem *base; +}; + +static const struct { + u32 reg_ofs; + u32 bit; +} ma35d1_reset_map[] =3D { + [MA35D1_RESET_CHIP] =3D {0x20, 0}, + [MA35D1_RESET_CA35CR0] =3D {0x20, 1}, + [MA35D1_RESET_CA35CR1] =3D {0x20, 2}, + [MA35D1_RESET_CM4] =3D {0x20, 3}, + [MA35D1_RESET_PDMA0] =3D {0x20, 4}, + [MA35D1_RESET_PDMA1] =3D {0x20, 5}, + [MA35D1_RESET_PDMA2] =3D {0x20, 6}, + [MA35D1_RESET_PDMA3] =3D {0x20, 7}, + [MA35D1_RESET_DISP] =3D {0x20, 9}, + [MA35D1_RESET_VCAP0] =3D {0x20, 10}, + [MA35D1_RESET_VCAP1] =3D {0x20, 11}, + [MA35D1_RESET_GFX] =3D {0x20, 12}, + [MA35D1_RESET_VDEC] =3D {0x20, 13}, + [MA35D1_RESET_WHC0] =3D {0x20, 14}, + [MA35D1_RESET_WHC1] =3D {0x20, 15}, + [MA35D1_RESET_GMAC0] =3D {0x20, 16}, + [MA35D1_RESET_GMAC1] =3D {0x20, 17}, + [MA35D1_RESET_HWSEM] =3D {0x20, 18}, + [MA35D1_RESET_EBI] =3D {0x20, 19}, + [MA35D1_RESET_HSUSBH0] =3D {0x20, 20}, + [MA35D1_RESET_HSUSBH1] =3D {0x20, 21}, + [MA35D1_RESET_HSUSBD] =3D {0x20, 22}, + [MA35D1_RESET_USBHL] =3D {0x20, 23}, + [MA35D1_RESET_SDH0] =3D {0x20, 24}, + [MA35D1_RESET_SDH1] =3D {0x20, 25}, + [MA35D1_RESET_NAND] =3D {0x20, 26}, + [MA35D1_RESET_GPIO] =3D {0x20, 27}, + [MA35D1_RESET_MCTLP] =3D {0x20, 28}, + [MA35D1_RESET_MCTLC] =3D {0x20, 29}, + [MA35D1_RESET_DDRPUB] =3D {0x20, 30}, + [MA35D1_RESET_TMR0] =3D {0x24, 2}, + [MA35D1_RESET_TMR1] =3D {0x24, 3}, + [MA35D1_RESET_TMR2] =3D {0x24, 4}, + [MA35D1_RESET_TMR3] =3D {0x24, 5}, + [MA35D1_RESET_I2C0] =3D {0x24, 8}, + [MA35D1_RESET_I2C1] =3D {0x24, 9}, + [MA35D1_RESET_I2C2] =3D {0x24, 10}, + [MA35D1_RESET_I2C3] =3D {0x24, 11}, + [MA35D1_RESET_QSPI0] =3D {0x24, 12}, + [MA35D1_RESET_SPI0] =3D {0x24, 13}, + [MA35D1_RESET_SPI1] =3D {0x24, 14}, + [MA35D1_RESET_SPI2] =3D {0x24, 15}, + [MA35D1_RESET_UART0] =3D {0x24, 16}, + [MA35D1_RESET_UART1] =3D {0x24, 17}, + [MA35D1_RESET_UART2] =3D {0x24, 18}, + [MA35D1_RESET_UART3] =3D {0x24, 19}, + [MA35D1_RESET_UART4] =3D {0x24, 20}, + [MA35D1_RESET_UART5] =3D {0x24, 21}, + [MA35D1_RESET_UART6] =3D {0x24, 22}, + [MA35D1_RESET_UART7] =3D {0x24, 23}, + [MA35D1_RESET_CANFD0] =3D {0x24, 24}, + [MA35D1_RESET_CANFD1] =3D {0x24, 25}, + [MA35D1_RESET_EADC0] =3D {0x24, 28}, + [MA35D1_RESET_I2S0] =3D {0x24, 29}, + [MA35D1_RESET_SC0] =3D {0x28, 0}, + [MA35D1_RESET_SC1] =3D {0x28, 1}, + [MA35D1_RESET_QSPI1] =3D {0x28, 4}, + [MA35D1_RESET_SPI3] =3D {0x28, 6}, + [MA35D1_RESET_EPWM0] =3D {0x28, 16}, + [MA35D1_RESET_EPWM1] =3D {0x28, 17}, + [MA35D1_RESET_QEI0] =3D {0x28, 22}, + [MA35D1_RESET_QEI1] =3D {0x28, 23}, + [MA35D1_RESET_ECAP0] =3D {0x28, 26}, + [MA35D1_RESET_ECAP1] =3D {0x28, 27}, + [MA35D1_RESET_CANFD2] =3D {0x28, 28}, + [MA35D1_RESET_ADC0] =3D {0x28, 31}, + [MA35D1_RESET_TMR4] =3D {0x2C, 0}, + [MA35D1_RESET_TMR5] =3D {0x2C, 1}, + [MA35D1_RESET_TMR6] =3D {0x2C, 2}, + [MA35D1_RESET_TMR7] =3D {0x2C, 3}, + [MA35D1_RESET_TMR8] =3D {0x2C, 4}, + [MA35D1_RESET_TMR9] =3D {0x2C, 5}, + [MA35D1_RESET_TMR10] =3D {0x2C, 6}, + [MA35D1_RESET_TMR11] =3D {0x2C, 7}, + [MA35D1_RESET_UART8] =3D {0x2C, 8}, + [MA35D1_RESET_UART9] =3D {0x2C, 9}, + [MA35D1_RESET_UART10] =3D {0x2C, 10}, + [MA35D1_RESET_UART11] =3D {0x2C, 11}, + [MA35D1_RESET_UART12] =3D {0x2C, 12}, + [MA35D1_RESET_UART13] =3D {0x2C, 13}, + [MA35D1_RESET_UART14] =3D {0x2C, 14}, + [MA35D1_RESET_UART15] =3D {0x2C, 15}, + [MA35D1_RESET_UART16] =3D {0x2C, 16}, + [MA35D1_RESET_I2S1] =3D {0x2C, 17}, + [MA35D1_RESET_I2C4] =3D {0x2C, 18}, + [MA35D1_RESET_I2C5] =3D {0x2C, 19}, + [MA35D1_RESET_EPWM2] =3D {0x2C, 20}, + [MA35D1_RESET_ECAP2] =3D {0x2C, 21}, + [MA35D1_RESET_QEI2] =3D {0x2C, 22}, + [MA35D1_RESET_CANFD3] =3D {0x2C, 23}, + [MA35D1_RESET_KPI] =3D {0x2C, 24}, + [MA35D1_RESET_GIC] =3D {0x2C, 28}, + [MA35D1_RESET_SSMCC] =3D {0x2C, 30}, + [MA35D1_RESET_SSPCC] =3D {0x2C, 31} +}; + +static int ma35d1_restart_handler(struct notifier_block *this, + unsigned long mode, void *cmd) +{ + u32 id =3D MA35D1_RESET_CHIP; + struct ma35d1_reset_data *data =3D container_of(this, + struct ma35d1_reset_data, + restart_handler); + + writel_relaxed(BIT(ma35d1_reset_map[id].bit), + data->base + ma35d1_reset_map[id].reg_ofs); + return 0; +} + +static int ma35d1_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + u32 reg; + struct ma35d1_reset_data *data =3D container_of(rcdev, + struct ma35d1_reset_data, + rcdev); + + reg =3D readl_relaxed(data->base + ma35d1_reset_map[id].reg_ofs); + if (assert) + reg |=3D BIT(ma35d1_reset_map[id].bit); + else + reg &=3D ~(BIT(ma35d1_reset_map[id].bit)); + writel_relaxed(reg, data->base + ma35d1_reset_map[id].reg_ofs); + + return 0; +} + +static int ma35d1_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return ma35d1_reset_update(rcdev, id, true); +} + +static int ma35d1_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return ma35d1_reset_update(rcdev, id, false); +} + +static int ma35d1_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + u32 reg; + struct ma35d1_reset_data *data =3D container_of(rcdev, + struct ma35d1_reset_data, + rcdev); + + reg =3D readl_relaxed(data->base + ma35d1_reset_map[id].reg_ofs); + return !!(reg & BIT(ma35d1_reset_map[id].bit)); +} + +static const struct reset_control_ops ma35d1_reset_ops =3D { + .assert =3D ma35d1_reset_assert, + .deassert =3D ma35d1_reset_deassert, + .status =3D ma35d1_reset_status, +}; + +static const struct of_device_id ma35d1_reset_dt_ids[] =3D { + { .compatible =3D "nuvoton,ma35d1-reset" }, + { }, +}; + +static int ma35d1_reset_probe(struct platform_device *pdev) +{ + int err; + struct device *dev =3D &pdev->dev; + struct resource *res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + struct ma35d1_reset_data *reset_data; + + if (!pdev->dev.of_node) { + dev_err(&pdev->dev, "Device tree node not found\n"); + return -EINVAL; + } + + reset_data =3D devm_kzalloc(dev, sizeof(*reset_data), GFP_KERNEL); + if (!reset_data) + return -ENOMEM; + + reset_data->base =3D devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(reset_data->base)) + return PTR_ERR(reset_data->base); + + reset_data->rcdev.owner =3D THIS_MODULE; + reset_data->rcdev.nr_resets =3D MA35D1_RESET_COUNT; + reset_data->rcdev.ops =3D &ma35d1_reset_ops; + reset_data->rcdev.of_node =3D dev->of_node; + reset_data->restart_handler.notifier_call =3D ma35d1_restart_handler; + reset_data->restart_handler.priority =3D 192; + + err =3D register_restart_handler(&reset_data->restart_handler); + if (err) + dev_warn(&pdev->dev, "failed to register restart handler\n"); + + return devm_reset_controller_register(dev, &reset_data->rcdev); +} + +static struct platform_driver ma35d1_reset_driver =3D { + .probe =3D ma35d1_reset_probe, + .driver =3D { + .name =3D "ma35d1-reset", + .of_match_table =3D ma35d1_reset_dt_ids, + }, +}; + +builtin_platform_driver(ma35d1_reset_driver); --=20 2.34.1