From nobody Thu Feb 12 10:36:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52039C7EE23 for ; Thu, 1 Jun 2023 05:36:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231259AbjFAFgo (ORCPT ); Thu, 1 Jun 2023 01:36:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46330 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229882AbjFAFgj (ORCPT ); Thu, 1 Jun 2023 01:36:39 -0400 Received: from forward103b.mail.yandex.net (forward103b.mail.yandex.net [IPv6:2a02:6b8:c02:900:1:45:d181:d103]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 101F112F; Wed, 31 May 2023 22:36:36 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net [IPv6:2a02:6b8:c14:c83:0:640:84f9:0]) by forward103b.mail.yandex.net (Yandex) with ESMTP id A15E060042; Thu, 1 Jun 2023 08:36:33 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id OaGNfZvWv8c0-Uwdxi0Hz; Thu, 01 Jun 2023 08:36:32 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1685597792; bh=8kmiN/R1jnZXcDguD2owAhWiu+kIyBjHGhxifPM20wM=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=cJvR3aY7GHHIfvFPhS02r1IT+y5RaM6Xpw+xzbeFpQ6nLsGr31K96wW23/vao+Ztf d9WcrTVqo58u2J1KIGf6t1OPlb1JRBmqUYPmkf5/hDrYItW3XGVSkQOCHWkGrX2yVZ 7x2uU20yuhDDKXy9awO3KIOZOXrSwuYL3KjDLZ/k= Authentication-Results: mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij , Hartley Sweeten , Russell King , Lukasz Majewski , Bartosz Golaszewski Cc: Nikita Shubin , Michael Peters , Kris Bahnsen , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [PATCH v1 01/43] gpio: ep93xx: split device in multiple Date: Thu, 1 Jun 2023 08:33:52 +0300 Message-Id: <20230601053546.9574-2-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This prepares ep93xx SOC gpio to convert into device tree driver: - dropped banks and legacy defines - split AB IRQ and make it shared We are relying on IRQ number information A, B ports have single shared IRQ, while F port have dedicated IRQ for each line. Also we had to split single ep93xx platform_device into multiple, one for each port, without this we can't do a full working transition from legacy platform code into device tree capable. All GPIO_LOOKUP were change to match new chip namings. Signed-off-by: Nikita Shubin Reviewed-by: Linus Walleij --- arch/arm/mach-ep93xx/core.c | 121 +++++++++- arch/arm/mach-ep93xx/edb93xx.c | 2 +- arch/arm/mach-ep93xx/ts72xx.c | 4 +- arch/arm/mach-ep93xx/vision_ep9307.c | 10 +- drivers/gpio/gpio-ep93xx.c | 323 ++++++++++----------------- 5 files changed, 236 insertions(+), 224 deletions(-) diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index 71b113976420..d61c1d2a0843 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -35,6 +35,7 @@ #include #include #include +#include =20 #include "hardware.h" #include @@ -139,9 +140,80 @@ EXPORT_SYMBOL_GPL(ep93xx_chip_revision); /************************************************************************* * EP93xx GPIO *************************************************************************/ -static struct resource ep93xx_gpio_resource[] =3D { - DEFINE_RES_MEM(EP93XX_GPIO_PHYS_BASE, 0xcc), +/* port A */ +static struct resource ep93xx_a_gpio_resources[] =3D { + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE, 0x04, "data"), + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x10, 0x04, "dir"), + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x90, 0x1c, "intr"), DEFINE_RES_IRQ(IRQ_EP93XX_GPIO_AB), +}; + +static struct platform_device ep93xx_a_gpio =3D { + .name =3D "gpio-ep93xx", + .id =3D 0, + .num_resources =3D ARRAY_SIZE(ep93xx_a_gpio_resources), + .resource =3D ep93xx_a_gpio_resources, +}; + +/* port B */ +static struct resource ep93xx_b_gpio_resources[] =3D { + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x04, 0x04, "data"), + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x14, 0x04, "dir"), + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0xac, 0x1c, "intr"), + DEFINE_RES_IRQ(IRQ_EP93XX_GPIO_AB), +}; + +static struct platform_device ep93xx_b_gpio =3D { + .name =3D "gpio-ep93xx", + .id =3D 1, + .num_resources =3D ARRAY_SIZE(ep93xx_b_gpio_resources), + .resource =3D ep93xx_b_gpio_resources, +}; + +/* port C */ +static struct resource ep93xx_c_gpio_resources[] =3D { + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x08, 0x04, "data"), + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x18, 0x04, "dir"), +}; + +static struct platform_device ep93xx_c_gpio =3D { + .name =3D "gpio-ep93xx", + .id =3D 2, + .num_resources =3D ARRAY_SIZE(ep93xx_c_gpio_resources), + .resource =3D ep93xx_c_gpio_resources, +}; + +/* port D */ +static struct resource ep93xx_d_gpio_resources[] =3D { + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x0c, 0x04, "data"), + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x1c, 0x04, "dir"), +}; + +static struct platform_device ep93xx_d_gpio =3D { + .name =3D "gpio-ep93xx", + .id =3D 3, + .num_resources =3D ARRAY_SIZE(ep93xx_d_gpio_resources), + .resource =3D ep93xx_d_gpio_resources, +}; + +/* port E */ +static struct resource ep93xx_e_gpio_resources[] =3D { + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x20, 0x04, "data"), + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x24, 0x04, "dir"), +}; + +static struct platform_device ep93xx_e_gpio =3D { + .name =3D "gpio-ep93xx", + .id =3D 4, + .num_resources =3D ARRAY_SIZE(ep93xx_e_gpio_resources), + .resource =3D ep93xx_e_gpio_resources, +}; + +/* port F */ +static struct resource ep93xx_f_gpio_resources[] =3D { + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x30, 0x04, "data"), + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x34, 0x04, "dir"), + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x4c, 0x1c, "intr"), DEFINE_RES_IRQ(IRQ_EP93XX_GPIO0MUX), DEFINE_RES_IRQ(IRQ_EP93XX_GPIO1MUX), DEFINE_RES_IRQ(IRQ_EP93XX_GPIO2MUX), @@ -152,11 +224,34 @@ static struct resource ep93xx_gpio_resource[] =3D { DEFINE_RES_IRQ(IRQ_EP93XX_GPIO7MUX), }; =20 -static struct platform_device ep93xx_gpio_device =3D { - .name =3D "gpio-ep93xx", - .id =3D -1, - .num_resources =3D ARRAY_SIZE(ep93xx_gpio_resource), - .resource =3D ep93xx_gpio_resource, +static struct platform_device ep93xx_f_gpio =3D { + .name =3D "gpio-ep93xx", + .id =3D 5, + .num_resources =3D ARRAY_SIZE(ep93xx_f_gpio_resources), + .resource =3D ep93xx_f_gpio_resources, +}; + +/* port G */ +static struct resource ep93xx_g_gpio_resources[] =3D { + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x38, 0x04, "data"), + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x3c, 0x04, "dir"), +}; + +static struct platform_device ep93xx_g_gpio =3D { + .name =3D "gpio-ep93xx", + .id =3D 6, + .num_resources =3D ARRAY_SIZE(ep93xx_g_gpio_resources), + .resource =3D ep93xx_g_gpio_resources, +}; + +static struct platform_device *ep93xx_gpio_device[] __initdata =3D { + &ep93xx_a_gpio, + &ep93xx_b_gpio, + &ep93xx_c_gpio, + &ep93xx_d_gpio, + &ep93xx_e_gpio, + &ep93xx_f_gpio, + &ep93xx_g_gpio, }; =20 /************************************************************************* @@ -335,9 +430,9 @@ static struct gpiod_lookup_table ep93xx_i2c_gpiod_table= =3D { .dev_id =3D "i2c-gpio.0", .table =3D { /* Use local offsets on gpiochip/port "G" */ - GPIO_LOOKUP_IDX("G", 1, NULL, 0, + GPIO_LOOKUP_IDX("gpio-ep93xx.6", 1, NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - GPIO_LOOKUP_IDX("G", 0, NULL, 1, + GPIO_LOOKUP_IDX("gpio-ep93xx.6", 0, NULL, 1, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), }, }; @@ -440,8 +535,8 @@ static struct gpiod_lookup_table ep93xx_leds_gpio_table= =3D { .dev_id =3D "leds-gpio", .table =3D { /* Use local offsets on gpiochip/port "E" */ - GPIO_LOOKUP_IDX("E", 0, NULL, 0, GPIO_ACTIVE_HIGH), - GPIO_LOOKUP_IDX("E", 1, NULL, 1, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("gpio-ep93xx.4", 0, NULL, 0, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("gpio-ep93xx.4", 1, NULL, 1, GPIO_ACTIVE_HIGH), { } }, }; @@ -974,6 +1069,7 @@ static struct device __init *ep93xx_init_soc(void) struct device __init *ep93xx_init_devices(void) { struct device *parent; + int i; =20 /* Disallow access to MaverickCrunch initially */ ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA); @@ -988,7 +1084,8 @@ struct device __init *ep93xx_init_devices(void) parent =3D ep93xx_init_soc(); =20 /* Get the GPIO working early, other devices need it */ - platform_device_register(&ep93xx_gpio_device); + for (i =3D 0; i < ARRAY_SIZE(ep93xx_gpio_device); i++) + platform_device_register(ep93xx_gpio_device[i]); =20 amba_device_register(&uart1_device, &iomem_resource); amba_device_register(&uart2_device, &iomem_resource); diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c index 4b90899a66e9..c1e880946f72 100644 --- a/arch/arm/mach-ep93xx/edb93xx.c +++ b/arch/arm/mach-ep93xx/edb93xx.c @@ -105,7 +105,7 @@ static struct spi_board_info edb93xx_spi_board_info[] _= _initdata =3D { static struct gpiod_lookup_table edb93xx_spi_cs_gpio_table =3D { .dev_id =3D "spi0", .table =3D { - GPIO_LOOKUP("A", 6, "cs", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("gpio-ep93xx.0", 6, "cs", GPIO_ACTIVE_LOW), { }, }, }; diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c index d3de7283ecb3..0bbdf587c685 100644 --- a/arch/arm/mach-ep93xx/ts72xx.c +++ b/arch/arm/mach-ep93xx/ts72xx.c @@ -268,7 +268,7 @@ static struct spi_board_info bk3_spi_board_info[] __ini= tdata =3D { static struct gpiod_lookup_table bk3_spi_cs_gpio_table =3D { .dev_id =3D "spi0", .table =3D { - GPIO_LOOKUP("F", 3, "cs", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("gpio-ep93xx.5", 3, "cs", GPIO_ACTIVE_LOW), { }, }, }; @@ -318,7 +318,7 @@ static struct gpiod_lookup_table ts72xx_spi_cs_gpio_tab= le =3D { .dev_id =3D "spi0", .table =3D { /* DIO_17 */ - GPIO_LOOKUP("F", 2, "cs", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("gpio-ep93xx.5", 2, "cs", GPIO_ACTIVE_LOW), { }, }, }; diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vi= sion_ep9307.c index 30d9cf3791eb..020223b0be2b 100644 --- a/arch/arm/mach-ep93xx/vision_ep9307.c +++ b/arch/arm/mach-ep93xx/vision_ep9307.c @@ -206,9 +206,9 @@ static struct gpiod_lookup_table vision_spi_mmc_gpio_ta= ble =3D { .dev_id =3D "mmc_spi.2", /* "mmc_spi @ CS2 */ .table =3D { /* Card detect */ - GPIO_LOOKUP_IDX("B", 7, NULL, 0, GPIO_ACTIVE_LOW), + GPIO_LOOKUP_IDX("gpio-ep93xx.1", 7, NULL, 0, GPIO_ACTIVE_LOW), /* Write protect */ - GPIO_LOOKUP_IDX("F", 0, NULL, 1, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("gpio-ep93xx.5", 0, NULL, 1, GPIO_ACTIVE_HIGH), { }, }, }; @@ -244,9 +244,9 @@ static struct spi_board_info vision_spi_board_info[] __= initdata =3D { static struct gpiod_lookup_table vision_spi_cs_gpio_table =3D { .dev_id =3D "spi0", .table =3D { - GPIO_LOOKUP_IDX("A", 6, "cs", 0, GPIO_ACTIVE_LOW), - GPIO_LOOKUP_IDX("A", 7, "cs", 1, GPIO_ACTIVE_LOW), - GPIO_LOOKUP_IDX("G", 2, "cs", 2, GPIO_ACTIVE_LOW), + GPIO_LOOKUP_IDX("gpio-ep93xx.0", 6, "cs", 0, GPIO_ACTIVE_LOW), + GPIO_LOOKUP_IDX("gpio-ep93xx.0", 7, "cs", 1, GPIO_ACTIVE_LOW), + GPIO_LOOKUP_IDX("gpio-ep93xx.6", 2, "cs", 2, GPIO_ACTIVE_LOW), { }, }, }; diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 6cedf46efec6..ca508c7c4f2f 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -18,30 +18,10 @@ #include #include #include - -#define EP93XX_GPIO_F_INT_STATUS 0x5c -#define EP93XX_GPIO_A_INT_STATUS 0xa0 -#define EP93XX_GPIO_B_INT_STATUS 0xbc - -/* Maximum value for gpio line identifiers */ -#define EP93XX_GPIO_LINE_MAX 63 - -/* Number of GPIO chips in EP93XX */ -#define EP93XX_GPIO_CHIP_NUM 8 - -/* Maximum value for irq capable line identifiers */ -#define EP93XX_GPIO_LINE_MAX_IRQ 23 - -#define EP93XX_GPIO_A_IRQ_BASE 64 -#define EP93XX_GPIO_B_IRQ_BASE 72 -/* - * Static mapping of GPIO bank F IRQS: - * F0..F7 (16..24) to irq 80..87. - */ -#define EP93XX_GPIO_F_IRQ_BASE 80 +#include =20 struct ep93xx_gpio_irq_chip { - u8 irq_offset; + void __iomem *base; u8 int_unmasked; u8 int_enabled; u8 int_type1; @@ -50,15 +30,11 @@ struct ep93xx_gpio_irq_chip { }; =20 struct ep93xx_gpio_chip { + void __iomem *base; struct gpio_chip gc; struct ep93xx_gpio_irq_chip *eic; }; =20 -struct ep93xx_gpio { - void __iomem *base; - struct ep93xx_gpio_chip gc[EP93XX_GPIO_CHIP_NUM]; -}; - #define to_ep93xx_gpio_chip(x) container_of(x, struct ep93xx_gpio_chip, gc) =20 static struct ep93xx_gpio_irq_chip *to_ep93xx_gpio_irq_chip(struct gpio_ch= ip *gc) @@ -79,25 +55,23 @@ static struct ep93xx_gpio_irq_chip *to_ep93xx_gpio_irq_= chip(struct gpio_chip *gc #define EP93XX_INT_RAW_STATUS_OFFSET 0x14 #define EP93XX_INT_DEBOUNCE_OFFSET 0x18 =20 -static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg, - struct ep93xx_gpio_irq_chip *eic) +static void ep93xx_gpio_update_int_params(struct ep93xx_gpio_irq_chip *eic) { - writeb_relaxed(0, epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET); + writeb_relaxed(0, eic->base + EP93XX_INT_EN_OFFSET); =20 writeb_relaxed(eic->int_type2, - epg->base + eic->irq_offset + EP93XX_INT_TYPE2_OFFSET); + eic->base + EP93XX_INT_TYPE2_OFFSET); =20 writeb_relaxed(eic->int_type1, - epg->base + eic->irq_offset + EP93XX_INT_TYPE1_OFFSET); + eic->base + EP93XX_INT_TYPE1_OFFSET); =20 writeb_relaxed(eic->int_unmasked & eic->int_enabled, - epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET); + eic->base + EP93XX_INT_EN_OFFSET); } =20 static void ep93xx_gpio_int_debounce(struct gpio_chip *gc, unsigned int offset, bool enable) { - struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); int port_mask =3D BIT(offset); =20 @@ -107,52 +81,43 @@ static void ep93xx_gpio_int_debounce(struct gpio_chip = *gc, eic->int_debounce &=3D ~port_mask; =20 writeb(eic->int_debounce, - epg->base + eic->irq_offset + EP93XX_INT_DEBOUNCE_OFFSET); + eic->base + EP93XX_INT_DEBOUNCE_OFFSET); } =20 -static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc) +static u32 ep93xx_gpio_ab_irq_handler(struct gpio_chip *gc) { - struct gpio_chip *gc =3D irq_desc_get_handler_data(desc); - struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); - struct irq_chip *irqchip =3D irq_desc_get_chip(desc); + struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); unsigned long stat; int offset; =20 - chained_irq_enter(irqchip, desc); - - /* - * Dispatch the IRQs to the irqdomain of each A and B - * gpiochip irqdomains depending on what has fired. - * The tricky part is that the IRQ line is shared - * between bank A and B and each has their own gpiochip. - */ - stat =3D readb(epg->base + EP93XX_GPIO_A_INT_STATUS); + stat =3D readb(eic->base + EP93XX_INT_STATUS_OFFSET); for_each_set_bit(offset, &stat, 8) - generic_handle_domain_irq(epg->gc[0].gc.irq.domain, - offset); + generic_handle_domain_irq(gc->irq.domain, offset); =20 - stat =3D readb(epg->base + EP93XX_GPIO_B_INT_STATUS); - for_each_set_bit(offset, &stat, 8) - generic_handle_domain_irq(epg->gc[1].gc.irq.domain, - offset); + return stat; +} =20 - chained_irq_exit(irqchip, desc); +static irqreturn_t ep93xx_ab_irq_handler(int irq, void *dev_id) +{ + return IRQ_RETVAL(ep93xx_gpio_ab_irq_handler(dev_id)); } =20 static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc) { - /* - * map discontiguous hw irq range to continuous sw irq range: - * - * IRQ_EP93XX_GPIO{0..7}MUX -> EP93XX_GPIO_LINE_F{0..7} - */ struct irq_chip *irqchip =3D irq_desc_get_chip(desc); - unsigned int irq =3D irq_desc_get_irq(desc); - int port_f_idx =3D (irq & 7) ^ 4; /* {20..23,48..51} -> {0..7} */ - int gpio_irq =3D EP93XX_GPIO_F_IRQ_BASE + port_f_idx; + struct gpio_chip *gc =3D irq_desc_get_handler_data(desc); + struct gpio_irq_chip *gic =3D &gc->irq; + unsigned int parent =3D irq_desc_get_irq(desc); + unsigned int i; =20 chained_irq_enter(irqchip, desc); - generic_handle_irq(gpio_irq); + for (i =3D 0; i < gic->num_parents; i++) + if (gic->parents[i] =3D=3D parent) + break; + + if (i < gic->num_parents) + generic_handle_irq(irq_find_mapping(gc->irq.domain, i)); + chained_irq_exit(irqchip, desc); } =20 @@ -160,31 +125,29 @@ static void ep93xx_gpio_irq_ack(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); - struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); - int port_mask =3D BIT(d->irq & 7); + int port_mask =3D BIT(irqd_to_hwirq(d)); =20 if (irqd_get_trigger_type(d) =3D=3D IRQ_TYPE_EDGE_BOTH) { eic->int_type2 ^=3D port_mask; /* switch edge direction */ - ep93xx_gpio_update_int_params(epg, eic); + ep93xx_gpio_update_int_params(eic); } =20 - writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET); + writeb(port_mask, eic->base + EP93XX_INT_EOI_OFFSET); } =20 static void ep93xx_gpio_irq_mask_ack(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); - struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); - int port_mask =3D BIT(d->irq & 7); + int port_mask =3D BIT(irqd_to_hwirq(d)); =20 if (irqd_get_trigger_type(d) =3D=3D IRQ_TYPE_EDGE_BOTH) eic->int_type2 ^=3D port_mask; /* switch edge direction */ =20 eic->int_unmasked &=3D ~port_mask; - ep93xx_gpio_update_int_params(epg, eic); + ep93xx_gpio_update_int_params(eic); =20 - writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET); + writeb(port_mask, eic->base + EP93XX_INT_EOI_OFFSET); gpiochip_disable_irq(gc, irqd_to_hwirq(d)); } =20 @@ -192,10 +155,9 @@ static void ep93xx_gpio_irq_mask(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); - struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); =20 - eic->int_unmasked &=3D ~BIT(d->irq & 7); - ep93xx_gpio_update_int_params(epg, eic); + eic->int_unmasked &=3D ~BIT(irqd_to_hwirq(d)); + ep93xx_gpio_update_int_params(eic); gpiochip_disable_irq(gc, irqd_to_hwirq(d)); } =20 @@ -203,11 +165,10 @@ static void ep93xx_gpio_irq_unmask(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); - struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); =20 gpiochip_enable_irq(gc, irqd_to_hwirq(d)); - eic->int_unmasked |=3D BIT(d->irq & 7); - ep93xx_gpio_update_int_params(epg, eic); + eic->int_unmasked |=3D BIT(irqd_to_hwirq(d)); + ep93xx_gpio_update_int_params(eic); } =20 /* @@ -219,8 +180,7 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, uns= igned int type) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); - struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); - int offset =3D d->irq & 7; + int offset =3D irqd_to_hwirq(d); int port_mask =3D BIT(offset); irq_flow_handler_t handler; =20 @@ -264,51 +224,11 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, u= nsigned int type) =20 eic->int_enabled |=3D port_mask; =20 - ep93xx_gpio_update_int_params(epg, eic); + ep93xx_gpio_update_int_params(eic); =20 return 0; } =20 -/************************************************************************* - * gpiolib interface for EP93xx on-chip GPIOs - *************************************************************************/ -struct ep93xx_gpio_bank { - const char *label; - int data; - int dir; - int irq; - int base; - bool has_irq; - bool has_hierarchical_irq; - unsigned int irq_base; -}; - -#define EP93XX_GPIO_BANK(_label, _data, _dir, _irq, _base, _has_irq, _has_= hier, _irq_base) \ - { \ - .label =3D _label, \ - .data =3D _data, \ - .dir =3D _dir, \ - .irq =3D _irq, \ - .base =3D _base, \ - .has_irq =3D _has_irq, \ - .has_hierarchical_irq =3D _has_hier, \ - .irq_base =3D _irq_base, \ - } - -static struct ep93xx_gpio_bank ep93xx_gpio_banks[] =3D { - /* Bank A has 8 IRQs */ - EP93XX_GPIO_BANK("A", 0x00, 0x10, 0x90, 0, true, false, EP93XX_GPIO_A_IRQ= _BASE), - /* Bank B has 8 IRQs */ - EP93XX_GPIO_BANK("B", 0x04, 0x14, 0xac, 8, true, false, EP93XX_GPIO_B_IRQ= _BASE), - EP93XX_GPIO_BANK("C", 0x08, 0x18, 0x00, 40, false, false, 0), - EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 0x00, 24, false, false, 0), - EP93XX_GPIO_BANK("E", 0x20, 0x24, 0x00, 32, false, false, 0), - /* Bank F has 8 IRQs */ - EP93XX_GPIO_BANK("F", 0x30, 0x34, 0x4c, 16, false, true, EP93XX_GPIO_F_IR= Q_BASE), - EP93XX_GPIO_BANK("G", 0x38, 0x3c, 0x00, 48, false, false, 0), - EP93XX_GPIO_BANK("H", 0x40, 0x44, 0x00, 56, false, false, 0), -}; - static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset, unsigned long config) { @@ -342,110 +262,105 @@ static const struct irq_chip gpio_eic_irq_chip =3D { GPIOCHIP_IRQ_RESOURCE_HELPERS, }; =20 -static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc, - struct platform_device *pdev, - struct ep93xx_gpio *epg, - struct ep93xx_gpio_bank *bank) +static int ep93xx_setup_irqs(struct platform_device *pdev, + struct ep93xx_gpio_chip *egc) { - void __iomem *data =3D epg->base + bank->data; - void __iomem *dir =3D epg->base + bank->dir; struct gpio_chip *gc =3D &egc->gc; struct device *dev =3D &pdev->dev; - struct gpio_irq_chip *girq; - int err; - - err =3D bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0); - if (err) - return err; - - gc->label =3D bank->label; - gc->base =3D bank->base; - - girq =3D &gc->irq; - if (bank->has_irq || bank->has_hierarchical_irq) { - gc->set_config =3D ep93xx_gpio_set_config; - egc->eic =3D devm_kcalloc(dev, 1, - sizeof(*egc->eic), - GFP_KERNEL); - if (!egc->eic) - return -ENOMEM; - egc->eic->irq_offset =3D bank->irq; - gpio_irq_chip_set_chip(girq, &gpio_eic_irq_chip); - } + struct gpio_irq_chip *girq =3D &gc->irq; + int ret, irq, i =3D 0; + void __iomem *intr =3D devm_platform_ioremap_resource_byname(pdev, "intr"= ); + + if (IS_ERR(intr)) + return PTR_ERR(intr); + + gc->set_config =3D ep93xx_gpio_set_config; + egc->eic =3D devm_kcalloc(dev, 1, + sizeof(*egc->eic), + GFP_KERNEL); + if (!egc->eic) + return -ENOMEM; =20 - if (bank->has_irq) { - int ab_parent_irq =3D platform_get_irq(pdev, 0); - - girq->parent_handler =3D ep93xx_gpio_ab_irq_handler; - girq->num_parents =3D 1; - girq->parents =3D devm_kcalloc(dev, girq->num_parents, - sizeof(*girq->parents), - GFP_KERNEL); - if (!girq->parents) - return -ENOMEM; - girq->default_type =3D IRQ_TYPE_NONE; - girq->handler =3D handle_level_irq; - girq->parents[0] =3D ab_parent_irq; - girq->first =3D bank->irq_base; - } + egc->eic->base =3D intr; + gpio_irq_chip_set_chip(girq, &gpio_eic_irq_chip); + girq->num_parents =3D platform_irq_count(pdev); + if (girq->num_parents =3D=3D 0) + return -EINVAL; + + girq->parents =3D devm_kcalloc(dev, girq->num_parents, + sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; =20 - /* Only bank F has especially funky IRQ handling */ - if (bank->has_hierarchical_irq) { - int gpio_irq; - int i; + if (girq->num_parents =3D=3D 1) { /* A/B irqchips */ + irq =3D platform_get_irq(pdev, 0); + ret =3D devm_request_irq(dev, irq, + ep93xx_ab_irq_handler, + IRQF_SHARED, gc->label, gc); + if (ret) { + dev_err(dev, "error requesting IRQ : %d\n", irq); + return ret; + } =20 - /* - * FIXME: convert this to use hierarchical IRQ support! - * this requires fixing the root irqchip to be hierarchical. - */ + girq->parents[0] =3D irq; + } else { /* F irqchip */ girq->parent_handler =3D ep93xx_gpio_f_irq_handler; - girq->num_parents =3D 8; - girq->parents =3D devm_kcalloc(dev, girq->num_parents, - sizeof(*girq->parents), - GFP_KERNEL); - if (!girq->parents) - return -ENOMEM; - /* Pick resources 1..8 for these IRQs */ + for (i =3D 0; i < girq->num_parents; i++) { - girq->parents[i] =3D platform_get_irq(pdev, i + 1); - gpio_irq =3D bank->irq_base + i; - irq_set_chip_data(gpio_irq, &epg->gc[5]); - irq_set_chip_and_handler(gpio_irq, - girq->chip, - handle_level_irq); - irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST); + irq =3D platform_get_irq(pdev, i); + if (irq <=3D 0) + continue; + + girq->parents[i] =3D irq; } - girq->default_type =3D IRQ_TYPE_NONE; - girq->handler =3D handle_level_irq; - girq->first =3D bank->irq_base; + + girq->map =3D girq->parents; } =20 - return devm_gpiochip_add_data(dev, gc, epg); + girq->default_type =3D IRQ_TYPE_NONE; + /* TODO: replace with handle_bad_irq once we are fully hierarchical */ + girq->handler =3D handle_simple_irq; + + return 0; } =20 static int ep93xx_gpio_probe(struct platform_device *pdev) { - struct ep93xx_gpio *epg; - int i; - - epg =3D devm_kzalloc(&pdev->dev, sizeof(*epg), GFP_KERNEL); - if (!epg) + struct ep93xx_gpio_chip *egc; + struct gpio_chip *gc; + void __iomem *data; + void __iomem *dir; + int ret; + + egc =3D devm_kzalloc(&pdev->dev, sizeof(*egc), GFP_KERNEL); + if (!egc) return -ENOMEM; =20 - epg->base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(epg->base)) - return PTR_ERR(epg->base); + data =3D devm_platform_ioremap_resource_byname(pdev, "data"); + if (IS_ERR(data)) + return PTR_ERR(data); =20 - for (i =3D 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) { - struct ep93xx_gpio_chip *gc =3D &epg->gc[i]; - struct ep93xx_gpio_bank *bank =3D &ep93xx_gpio_banks[i]; + dir =3D devm_platform_ioremap_resource_byname(pdev, "dir"); + if (IS_ERR(dir)) + return PTR_ERR(dir); =20 - if (ep93xx_gpio_add_bank(gc, pdev, epg, bank)) - dev_warn(&pdev->dev, "Unable to add gpio bank %s\n", - bank->label); + gc =3D &egc->gc; + ret =3D bgpio_init(gc, &pdev->dev, 1, data, NULL, NULL, dir, NULL, 0); + if (ret) { + dev_err(&pdev->dev, "unable to init generic GPIO\n"); + return ret; } =20 - return 0; + gc->label =3D dev_name(&pdev->dev); + if (platform_irq_count(pdev) > 0) { + dev_dbg(&pdev->dev, "setting up irqs for %s\n", dev_name(&pdev->dev)); + ret =3D ep93xx_setup_irqs(pdev, egc); + if (ret) + dev_err(&pdev->dev, "setup irqs failed for %s\n", dev_name(&pdev->dev)); + } + + return devm_gpiochip_add_data(&pdev->dev, gc, egc); } =20 static struct platform_driver ep93xx_gpio_driver =3D { --=20 2.37.4 From nobody Thu Feb 12 10:36:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62322C77B61 for ; Mon, 24 Apr 2023 10:21:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230396AbjDXKVJ (ORCPT ); Mon, 24 Apr 2023 06:21:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44284 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231572AbjDXKUm (ORCPT ); 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dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , Linus Walleij , Hartley Sweeten , Russell King , Lukasz Majewski , Bartosz Golaszewski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [PATCH 01/43] gpio: ep93xx: split device in multiple Date: Mon, 24 Apr 2023 15:34:17 +0300 Message-Id: <20230424123522.18302-2-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This prepares ep93xx SOC gpio to convert into device tree driver: - dropped banks and legacy defines - split AB IRQ and make it shared We are relying on IRQ number information A, B ports have single shared IRQ, while F port have dedicated IRQ for each line. Also we had to split single ep93xx platform_device into multiple, one for each port, without this we can't do a full working transition from legacy platform code into device tree capable. All GPIO_LOOKUP were change to match new chip namings. Signed-off-by: Nikita Shubin Reviewed-by: Linus Walleij --- arch/arm/mach-ep93xx/core.c | 121 +++++++++- arch/arm/mach-ep93xx/edb93xx.c | 2 +- arch/arm/mach-ep93xx/ts72xx.c | 4 +- arch/arm/mach-ep93xx/vision_ep9307.c | 10 +- drivers/gpio/gpio-ep93xx.c | 323 ++++++++++----------------- 5 files changed, 236 insertions(+), 224 deletions(-) diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index 71b113976420..d61c1d2a0843 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -35,6 +35,7 @@ #include #include #include +#include =20 #include "hardware.h" #include @@ -139,9 +140,80 @@ EXPORT_SYMBOL_GPL(ep93xx_chip_revision); /************************************************************************* * EP93xx GPIO *************************************************************************/ -static struct resource ep93xx_gpio_resource[] =3D { - DEFINE_RES_MEM(EP93XX_GPIO_PHYS_BASE, 0xcc), +/* port A */ +static struct resource ep93xx_a_gpio_resources[] =3D { + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE, 0x04, "data"), + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x10, 0x04, "dir"), + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x90, 0x1c, "intr"), DEFINE_RES_IRQ(IRQ_EP93XX_GPIO_AB), +}; + +static struct platform_device ep93xx_a_gpio =3D { + .name =3D "gpio-ep93xx", + .id =3D 0, + .num_resources =3D ARRAY_SIZE(ep93xx_a_gpio_resources), + .resource =3D ep93xx_a_gpio_resources, +}; + +/* port B */ +static struct resource ep93xx_b_gpio_resources[] =3D { + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x04, 0x04, "data"), + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x14, 0x04, "dir"), + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0xac, 0x1c, "intr"), + DEFINE_RES_IRQ(IRQ_EP93XX_GPIO_AB), +}; + +static struct platform_device ep93xx_b_gpio =3D { + .name =3D "gpio-ep93xx", + .id =3D 1, + .num_resources =3D ARRAY_SIZE(ep93xx_b_gpio_resources), + .resource =3D ep93xx_b_gpio_resources, +}; + +/* port C */ +static struct resource ep93xx_c_gpio_resources[] =3D { + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x08, 0x04, "data"), + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x18, 0x04, "dir"), +}; + +static struct platform_device ep93xx_c_gpio =3D { + .name =3D "gpio-ep93xx", + .id =3D 2, + .num_resources =3D ARRAY_SIZE(ep93xx_c_gpio_resources), + .resource =3D ep93xx_c_gpio_resources, +}; + +/* port D */ +static struct resource ep93xx_d_gpio_resources[] =3D { + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x0c, 0x04, "data"), + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x1c, 0x04, "dir"), +}; + +static struct platform_device ep93xx_d_gpio =3D { + .name =3D "gpio-ep93xx", + .id =3D 3, + .num_resources =3D ARRAY_SIZE(ep93xx_d_gpio_resources), + .resource =3D ep93xx_d_gpio_resources, +}; + +/* port E */ +static struct resource ep93xx_e_gpio_resources[] =3D { + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x20, 0x04, "data"), + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x24, 0x04, "dir"), +}; + +static struct platform_device ep93xx_e_gpio =3D { + .name =3D "gpio-ep93xx", + .id =3D 4, + .num_resources =3D ARRAY_SIZE(ep93xx_e_gpio_resources), + .resource =3D ep93xx_e_gpio_resources, +}; + +/* port F */ +static struct resource ep93xx_f_gpio_resources[] =3D { + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x30, 0x04, "data"), + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x34, 0x04, "dir"), + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x4c, 0x1c, "intr"), DEFINE_RES_IRQ(IRQ_EP93XX_GPIO0MUX), DEFINE_RES_IRQ(IRQ_EP93XX_GPIO1MUX), DEFINE_RES_IRQ(IRQ_EP93XX_GPIO2MUX), @@ -152,11 +224,34 @@ static struct resource ep93xx_gpio_resource[] =3D { DEFINE_RES_IRQ(IRQ_EP93XX_GPIO7MUX), }; =20 -static struct platform_device ep93xx_gpio_device =3D { - .name =3D "gpio-ep93xx", - .id =3D -1, - .num_resources =3D ARRAY_SIZE(ep93xx_gpio_resource), - .resource =3D ep93xx_gpio_resource, +static struct platform_device ep93xx_f_gpio =3D { + .name =3D "gpio-ep93xx", + .id =3D 5, + .num_resources =3D ARRAY_SIZE(ep93xx_f_gpio_resources), + .resource =3D ep93xx_f_gpio_resources, +}; + +/* port G */ +static struct resource ep93xx_g_gpio_resources[] =3D { + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x38, 0x04, "data"), + DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x3c, 0x04, "dir"), +}; + +static struct platform_device ep93xx_g_gpio =3D { + .name =3D "gpio-ep93xx", + .id =3D 6, + .num_resources =3D ARRAY_SIZE(ep93xx_g_gpio_resources), + .resource =3D ep93xx_g_gpio_resources, +}; + +static struct platform_device *ep93xx_gpio_device[] __initdata =3D { + &ep93xx_a_gpio, + &ep93xx_b_gpio, + &ep93xx_c_gpio, + &ep93xx_d_gpio, + &ep93xx_e_gpio, + &ep93xx_f_gpio, + &ep93xx_g_gpio, }; =20 /************************************************************************* @@ -335,9 +430,9 @@ static struct gpiod_lookup_table ep93xx_i2c_gpiod_table= =3D { .dev_id =3D "i2c-gpio.0", .table =3D { /* Use local offsets on gpiochip/port "G" */ - GPIO_LOOKUP_IDX("G", 1, NULL, 0, + GPIO_LOOKUP_IDX("gpio-ep93xx.6", 1, NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - GPIO_LOOKUP_IDX("G", 0, NULL, 1, + GPIO_LOOKUP_IDX("gpio-ep93xx.6", 0, NULL, 1, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), }, }; @@ -440,8 +535,8 @@ static struct gpiod_lookup_table ep93xx_leds_gpio_table= =3D { .dev_id =3D "leds-gpio", .table =3D { /* Use local offsets on gpiochip/port "E" */ - GPIO_LOOKUP_IDX("E", 0, NULL, 0, GPIO_ACTIVE_HIGH), - GPIO_LOOKUP_IDX("E", 1, NULL, 1, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("gpio-ep93xx.4", 0, NULL, 0, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("gpio-ep93xx.4", 1, NULL, 1, GPIO_ACTIVE_HIGH), { } }, }; @@ -974,6 +1069,7 @@ static struct device __init *ep93xx_init_soc(void) struct device __init *ep93xx_init_devices(void) { struct device *parent; + int i; =20 /* Disallow access to MaverickCrunch initially */ ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA); @@ -988,7 +1084,8 @@ struct device __init *ep93xx_init_devices(void) parent =3D ep93xx_init_soc(); =20 /* Get the GPIO working early, other devices need it */ - platform_device_register(&ep93xx_gpio_device); + for (i =3D 0; i < ARRAY_SIZE(ep93xx_gpio_device); i++) + platform_device_register(ep93xx_gpio_device[i]); =20 amba_device_register(&uart1_device, &iomem_resource); amba_device_register(&uart2_device, &iomem_resource); diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c index 4b90899a66e9..c1e880946f72 100644 --- a/arch/arm/mach-ep93xx/edb93xx.c +++ b/arch/arm/mach-ep93xx/edb93xx.c @@ -105,7 +105,7 @@ static struct spi_board_info edb93xx_spi_board_info[] _= _initdata =3D { static struct gpiod_lookup_table edb93xx_spi_cs_gpio_table =3D { .dev_id =3D "spi0", .table =3D { - GPIO_LOOKUP("A", 6, "cs", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("gpio-ep93xx.0", 6, "cs", GPIO_ACTIVE_LOW), { }, }, }; diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c index d3de7283ecb3..0bbdf587c685 100644 --- a/arch/arm/mach-ep93xx/ts72xx.c +++ b/arch/arm/mach-ep93xx/ts72xx.c @@ -268,7 +268,7 @@ static struct spi_board_info bk3_spi_board_info[] __ini= tdata =3D { static struct gpiod_lookup_table bk3_spi_cs_gpio_table =3D { .dev_id =3D "spi0", .table =3D { - GPIO_LOOKUP("F", 3, "cs", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("gpio-ep93xx.5", 3, "cs", GPIO_ACTIVE_LOW), { }, }, }; @@ -318,7 +318,7 @@ static struct gpiod_lookup_table ts72xx_spi_cs_gpio_tab= le =3D { .dev_id =3D "spi0", .table =3D { /* DIO_17 */ - GPIO_LOOKUP("F", 2, "cs", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("gpio-ep93xx.5", 2, "cs", GPIO_ACTIVE_LOW), { }, }, }; diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vi= sion_ep9307.c index 30d9cf3791eb..020223b0be2b 100644 --- a/arch/arm/mach-ep93xx/vision_ep9307.c +++ b/arch/arm/mach-ep93xx/vision_ep9307.c @@ -206,9 +206,9 @@ static struct gpiod_lookup_table vision_spi_mmc_gpio_ta= ble =3D { .dev_id =3D "mmc_spi.2", /* "mmc_spi @ CS2 */ .table =3D { /* Card detect */ - GPIO_LOOKUP_IDX("B", 7, NULL, 0, GPIO_ACTIVE_LOW), + GPIO_LOOKUP_IDX("gpio-ep93xx.1", 7, NULL, 0, GPIO_ACTIVE_LOW), /* Write protect */ - GPIO_LOOKUP_IDX("F", 0, NULL, 1, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("gpio-ep93xx.5", 0, NULL, 1, GPIO_ACTIVE_HIGH), { }, }, }; @@ -244,9 +244,9 @@ static struct spi_board_info vision_spi_board_info[] __= initdata =3D { static struct gpiod_lookup_table vision_spi_cs_gpio_table =3D { .dev_id =3D "spi0", .table =3D { - GPIO_LOOKUP_IDX("A", 6, "cs", 0, GPIO_ACTIVE_LOW), - GPIO_LOOKUP_IDX("A", 7, "cs", 1, GPIO_ACTIVE_LOW), - GPIO_LOOKUP_IDX("G", 2, "cs", 2, GPIO_ACTIVE_LOW), + GPIO_LOOKUP_IDX("gpio-ep93xx.0", 6, "cs", 0, GPIO_ACTIVE_LOW), + GPIO_LOOKUP_IDX("gpio-ep93xx.0", 7, "cs", 1, GPIO_ACTIVE_LOW), + GPIO_LOOKUP_IDX("gpio-ep93xx.6", 2, "cs", 2, GPIO_ACTIVE_LOW), { }, }, }; diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index 6cedf46efec6..ca508c7c4f2f 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -18,30 +18,10 @@ #include #include #include - -#define EP93XX_GPIO_F_INT_STATUS 0x5c -#define EP93XX_GPIO_A_INT_STATUS 0xa0 -#define EP93XX_GPIO_B_INT_STATUS 0xbc - -/* Maximum value for gpio line identifiers */ -#define EP93XX_GPIO_LINE_MAX 63 - -/* Number of GPIO chips in EP93XX */ -#define EP93XX_GPIO_CHIP_NUM 8 - -/* Maximum value for irq capable line identifiers */ -#define EP93XX_GPIO_LINE_MAX_IRQ 23 - -#define EP93XX_GPIO_A_IRQ_BASE 64 -#define EP93XX_GPIO_B_IRQ_BASE 72 -/* - * Static mapping of GPIO bank F IRQS: - * F0..F7 (16..24) to irq 80..87. - */ -#define EP93XX_GPIO_F_IRQ_BASE 80 +#include =20 struct ep93xx_gpio_irq_chip { - u8 irq_offset; + void __iomem *base; u8 int_unmasked; u8 int_enabled; u8 int_type1; @@ -50,15 +30,11 @@ struct ep93xx_gpio_irq_chip { }; =20 struct ep93xx_gpio_chip { + void __iomem *base; struct gpio_chip gc; struct ep93xx_gpio_irq_chip *eic; }; =20 -struct ep93xx_gpio { - void __iomem *base; - struct ep93xx_gpio_chip gc[EP93XX_GPIO_CHIP_NUM]; -}; - #define to_ep93xx_gpio_chip(x) container_of(x, struct ep93xx_gpio_chip, gc) =20 static struct ep93xx_gpio_irq_chip *to_ep93xx_gpio_irq_chip(struct gpio_ch= ip *gc) @@ -79,25 +55,23 @@ static struct ep93xx_gpio_irq_chip *to_ep93xx_gpio_irq_= chip(struct gpio_chip *gc #define EP93XX_INT_RAW_STATUS_OFFSET 0x14 #define EP93XX_INT_DEBOUNCE_OFFSET 0x18 =20 -static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg, - struct ep93xx_gpio_irq_chip *eic) +static void ep93xx_gpio_update_int_params(struct ep93xx_gpio_irq_chip *eic) { - writeb_relaxed(0, epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET); + writeb_relaxed(0, eic->base + EP93XX_INT_EN_OFFSET); =20 writeb_relaxed(eic->int_type2, - epg->base + eic->irq_offset + EP93XX_INT_TYPE2_OFFSET); + eic->base + EP93XX_INT_TYPE2_OFFSET); =20 writeb_relaxed(eic->int_type1, - epg->base + eic->irq_offset + EP93XX_INT_TYPE1_OFFSET); + eic->base + EP93XX_INT_TYPE1_OFFSET); =20 writeb_relaxed(eic->int_unmasked & eic->int_enabled, - epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET); + eic->base + EP93XX_INT_EN_OFFSET); } =20 static void ep93xx_gpio_int_debounce(struct gpio_chip *gc, unsigned int offset, bool enable) { - struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); int port_mask =3D BIT(offset); =20 @@ -107,52 +81,43 @@ static void ep93xx_gpio_int_debounce(struct gpio_chip = *gc, eic->int_debounce &=3D ~port_mask; =20 writeb(eic->int_debounce, - epg->base + eic->irq_offset + EP93XX_INT_DEBOUNCE_OFFSET); + eic->base + EP93XX_INT_DEBOUNCE_OFFSET); } =20 -static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc) +static u32 ep93xx_gpio_ab_irq_handler(struct gpio_chip *gc) { - struct gpio_chip *gc =3D irq_desc_get_handler_data(desc); - struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); - struct irq_chip *irqchip =3D irq_desc_get_chip(desc); + struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); unsigned long stat; int offset; =20 - chained_irq_enter(irqchip, desc); - - /* - * Dispatch the IRQs to the irqdomain of each A and B - * gpiochip irqdomains depending on what has fired. - * The tricky part is that the IRQ line is shared - * between bank A and B and each has their own gpiochip. - */ - stat =3D readb(epg->base + EP93XX_GPIO_A_INT_STATUS); + stat =3D readb(eic->base + EP93XX_INT_STATUS_OFFSET); for_each_set_bit(offset, &stat, 8) - generic_handle_domain_irq(epg->gc[0].gc.irq.domain, - offset); + generic_handle_domain_irq(gc->irq.domain, offset); =20 - stat =3D readb(epg->base + EP93XX_GPIO_B_INT_STATUS); - for_each_set_bit(offset, &stat, 8) - generic_handle_domain_irq(epg->gc[1].gc.irq.domain, - offset); + return stat; +} =20 - chained_irq_exit(irqchip, desc); +static irqreturn_t ep93xx_ab_irq_handler(int irq, void *dev_id) +{ + return IRQ_RETVAL(ep93xx_gpio_ab_irq_handler(dev_id)); } =20 static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc) { - /* - * map discontiguous hw irq range to continuous sw irq range: - * - * IRQ_EP93XX_GPIO{0..7}MUX -> EP93XX_GPIO_LINE_F{0..7} - */ struct irq_chip *irqchip =3D irq_desc_get_chip(desc); - unsigned int irq =3D irq_desc_get_irq(desc); - int port_f_idx =3D (irq & 7) ^ 4; /* {20..23,48..51} -> {0..7} */ - int gpio_irq =3D EP93XX_GPIO_F_IRQ_BASE + port_f_idx; + struct gpio_chip *gc =3D irq_desc_get_handler_data(desc); + struct gpio_irq_chip *gic =3D &gc->irq; + unsigned int parent =3D irq_desc_get_irq(desc); + unsigned int i; =20 chained_irq_enter(irqchip, desc); - generic_handle_irq(gpio_irq); + for (i =3D 0; i < gic->num_parents; i++) + if (gic->parents[i] =3D=3D parent) + break; + + if (i < gic->num_parents) + generic_handle_irq(irq_find_mapping(gc->irq.domain, i)); + chained_irq_exit(irqchip, desc); } =20 @@ -160,31 +125,29 @@ static void ep93xx_gpio_irq_ack(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); - struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); - int port_mask =3D BIT(d->irq & 7); + int port_mask =3D BIT(irqd_to_hwirq(d)); =20 if (irqd_get_trigger_type(d) =3D=3D IRQ_TYPE_EDGE_BOTH) { eic->int_type2 ^=3D port_mask; /* switch edge direction */ - ep93xx_gpio_update_int_params(epg, eic); + ep93xx_gpio_update_int_params(eic); } =20 - writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET); + writeb(port_mask, eic->base + EP93XX_INT_EOI_OFFSET); } =20 static void ep93xx_gpio_irq_mask_ack(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); - struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); - int port_mask =3D BIT(d->irq & 7); + int port_mask =3D BIT(irqd_to_hwirq(d)); =20 if (irqd_get_trigger_type(d) =3D=3D IRQ_TYPE_EDGE_BOTH) eic->int_type2 ^=3D port_mask; /* switch edge direction */ =20 eic->int_unmasked &=3D ~port_mask; - ep93xx_gpio_update_int_params(epg, eic); + ep93xx_gpio_update_int_params(eic); =20 - writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET); + writeb(port_mask, eic->base + EP93XX_INT_EOI_OFFSET); gpiochip_disable_irq(gc, irqd_to_hwirq(d)); } =20 @@ -192,10 +155,9 @@ static void ep93xx_gpio_irq_mask(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); - struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); =20 - eic->int_unmasked &=3D ~BIT(d->irq & 7); - ep93xx_gpio_update_int_params(epg, eic); + eic->int_unmasked &=3D ~BIT(irqd_to_hwirq(d)); + ep93xx_gpio_update_int_params(eic); gpiochip_disable_irq(gc, irqd_to_hwirq(d)); } =20 @@ -203,11 +165,10 @@ static void ep93xx_gpio_irq_unmask(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); - struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); =20 gpiochip_enable_irq(gc, irqd_to_hwirq(d)); - eic->int_unmasked |=3D BIT(d->irq & 7); - ep93xx_gpio_update_int_params(epg, eic); + eic->int_unmasked |=3D BIT(irqd_to_hwirq(d)); + ep93xx_gpio_update_int_params(eic); } =20 /* @@ -219,8 +180,7 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, uns= igned int type) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct ep93xx_gpio_irq_chip *eic =3D to_ep93xx_gpio_irq_chip(gc); - struct ep93xx_gpio *epg =3D gpiochip_get_data(gc); - int offset =3D d->irq & 7; + int offset =3D irqd_to_hwirq(d); int port_mask =3D BIT(offset); irq_flow_handler_t handler; =20 @@ -264,51 +224,11 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, u= nsigned int type) =20 eic->int_enabled |=3D port_mask; =20 - ep93xx_gpio_update_int_params(epg, eic); + ep93xx_gpio_update_int_params(eic); =20 return 0; } =20 -/************************************************************************* - * gpiolib interface for EP93xx on-chip GPIOs - *************************************************************************/ -struct ep93xx_gpio_bank { - const char *label; - int data; - int dir; - int irq; - int base; - bool has_irq; - bool has_hierarchical_irq; - unsigned int irq_base; -}; - -#define EP93XX_GPIO_BANK(_label, _data, _dir, _irq, _base, _has_irq, _has_= hier, _irq_base) \ - { \ - .label =3D _label, \ - .data =3D _data, \ - .dir =3D _dir, \ - .irq =3D _irq, \ - .base =3D _base, \ - .has_irq =3D _has_irq, \ - .has_hierarchical_irq =3D _has_hier, \ - .irq_base =3D _irq_base, \ - } - -static struct ep93xx_gpio_bank ep93xx_gpio_banks[] =3D { - /* Bank A has 8 IRQs */ - EP93XX_GPIO_BANK("A", 0x00, 0x10, 0x90, 0, true, false, EP93XX_GPIO_A_IRQ= _BASE), - /* Bank B has 8 IRQs */ - EP93XX_GPIO_BANK("B", 0x04, 0x14, 0xac, 8, true, false, EP93XX_GPIO_B_IRQ= _BASE), - EP93XX_GPIO_BANK("C", 0x08, 0x18, 0x00, 40, false, false, 0), - EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 0x00, 24, false, false, 0), - EP93XX_GPIO_BANK("E", 0x20, 0x24, 0x00, 32, false, false, 0), - /* Bank F has 8 IRQs */ - EP93XX_GPIO_BANK("F", 0x30, 0x34, 0x4c, 16, false, true, EP93XX_GPIO_F_IR= Q_BASE), - EP93XX_GPIO_BANK("G", 0x38, 0x3c, 0x00, 48, false, false, 0), - EP93XX_GPIO_BANK("H", 0x40, 0x44, 0x00, 56, false, false, 0), -}; - static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset, unsigned long config) { @@ -342,110 +262,105 @@ static const struct irq_chip gpio_eic_irq_chip =3D { GPIOCHIP_IRQ_RESOURCE_HELPERS, }; =20 -static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc, - struct platform_device *pdev, - struct ep93xx_gpio *epg, - struct ep93xx_gpio_bank *bank) +static int ep93xx_setup_irqs(struct platform_device *pdev, + struct ep93xx_gpio_chip *egc) { - void __iomem *data =3D epg->base + bank->data; - void __iomem *dir =3D epg->base + bank->dir; struct gpio_chip *gc =3D &egc->gc; struct device *dev =3D &pdev->dev; - struct gpio_irq_chip *girq; - int err; - - err =3D bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0); - if (err) - return err; - - gc->label =3D bank->label; - gc->base =3D bank->base; - - girq =3D &gc->irq; - if (bank->has_irq || bank->has_hierarchical_irq) { - gc->set_config =3D ep93xx_gpio_set_config; - egc->eic =3D devm_kcalloc(dev, 1, - sizeof(*egc->eic), - GFP_KERNEL); - if (!egc->eic) - return -ENOMEM; - egc->eic->irq_offset =3D bank->irq; - gpio_irq_chip_set_chip(girq, &gpio_eic_irq_chip); - } + struct gpio_irq_chip *girq =3D &gc->irq; + int ret, irq, i =3D 0; + void __iomem *intr =3D devm_platform_ioremap_resource_byname(pdev, "intr"= ); + + if (IS_ERR(intr)) + return PTR_ERR(intr); + + gc->set_config =3D ep93xx_gpio_set_config; + egc->eic =3D devm_kcalloc(dev, 1, + sizeof(*egc->eic), + GFP_KERNEL); + if (!egc->eic) + return -ENOMEM; =20 - if (bank->has_irq) { - int ab_parent_irq =3D platform_get_irq(pdev, 0); - - girq->parent_handler =3D ep93xx_gpio_ab_irq_handler; - girq->num_parents =3D 1; - girq->parents =3D devm_kcalloc(dev, girq->num_parents, - sizeof(*girq->parents), - GFP_KERNEL); - if (!girq->parents) - return -ENOMEM; - girq->default_type =3D IRQ_TYPE_NONE; - girq->handler =3D handle_level_irq; - girq->parents[0] =3D ab_parent_irq; - girq->first =3D bank->irq_base; - } + egc->eic->base =3D intr; + gpio_irq_chip_set_chip(girq, &gpio_eic_irq_chip); + girq->num_parents =3D platform_irq_count(pdev); + if (girq->num_parents =3D=3D 0) + return -EINVAL; + + girq->parents =3D devm_kcalloc(dev, girq->num_parents, + sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; =20 - /* Only bank F has especially funky IRQ handling */ - if (bank->has_hierarchical_irq) { - int gpio_irq; - int i; + if (girq->num_parents =3D=3D 1) { /* A/B irqchips */ + irq =3D platform_get_irq(pdev, 0); + ret =3D devm_request_irq(dev, irq, + ep93xx_ab_irq_handler, + IRQF_SHARED, gc->label, gc); + if (ret) { + dev_err(dev, "error requesting IRQ : %d\n", irq); + return ret; + } =20 - /* - * FIXME: convert this to use hierarchical IRQ support! - * this requires fixing the root irqchip to be hierarchical. - */ + girq->parents[0] =3D irq; + } else { /* F irqchip */ girq->parent_handler =3D ep93xx_gpio_f_irq_handler; - girq->num_parents =3D 8; - girq->parents =3D devm_kcalloc(dev, girq->num_parents, - sizeof(*girq->parents), - GFP_KERNEL); - if (!girq->parents) - return -ENOMEM; - /* Pick resources 1..8 for these IRQs */ + for (i =3D 0; i < girq->num_parents; i++) { - girq->parents[i] =3D platform_get_irq(pdev, i + 1); - gpio_irq =3D bank->irq_base + i; - irq_set_chip_data(gpio_irq, &epg->gc[5]); - irq_set_chip_and_handler(gpio_irq, - girq->chip, - handle_level_irq); - irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST); + irq =3D platform_get_irq(pdev, i); + if (irq <=3D 0) + continue; + + girq->parents[i] =3D irq; } - girq->default_type =3D IRQ_TYPE_NONE; - girq->handler =3D handle_level_irq; - girq->first =3D bank->irq_base; + + girq->map =3D girq->parents; } =20 - return devm_gpiochip_add_data(dev, gc, epg); + girq->default_type =3D IRQ_TYPE_NONE; + /* TODO: replace with handle_bad_irq once we are fully hierarchical */ + girq->handler =3D handle_simple_irq; + + return 0; } =20 static int ep93xx_gpio_probe(struct platform_device *pdev) { - struct ep93xx_gpio *epg; - int i; - - epg =3D devm_kzalloc(&pdev->dev, sizeof(*epg), GFP_KERNEL); - if (!epg) + struct ep93xx_gpio_chip *egc; + struct gpio_chip *gc; + void __iomem *data; + void __iomem *dir; + int ret; + + egc =3D devm_kzalloc(&pdev->dev, sizeof(*egc), GFP_KERNEL); + if (!egc) return -ENOMEM; =20 - epg->base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(epg->base)) - return PTR_ERR(epg->base); + data =3D devm_platform_ioremap_resource_byname(pdev, "data"); + if (IS_ERR(data)) + return PTR_ERR(data); =20 - for (i =3D 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) { - struct ep93xx_gpio_chip *gc =3D &epg->gc[i]; - struct ep93xx_gpio_bank *bank =3D &ep93xx_gpio_banks[i]; + dir =3D devm_platform_ioremap_resource_byname(pdev, "dir"); + if (IS_ERR(dir)) + return PTR_ERR(dir); =20 - if (ep93xx_gpio_add_bank(gc, pdev, epg, bank)) - dev_warn(&pdev->dev, "Unable to add gpio bank %s\n", - bank->label); + gc =3D &egc->gc; + ret =3D bgpio_init(gc, &pdev->dev, 1, data, NULL, NULL, dir, NULL, 0); + if (ret) { + dev_err(&pdev->dev, "unable to init generic GPIO\n"); + return ret; } =20 - return 0; + gc->label =3D dev_name(&pdev->dev); + if (platform_irq_count(pdev) > 0) { + dev_dbg(&pdev->dev, "setting up irqs for %s\n", dev_name(&pdev->dev)); + ret =3D ep93xx_setup_irqs(pdev, egc); + if (ret) + dev_err(&pdev->dev, "setup irqs failed for %s\n", dev_name(&pdev->dev)); + } + + return devm_gpiochip_add_data(&pdev->dev, gc, egc); } =20 static struct platform_driver ep93xx_gpio_driver =3D { --=20 2.39.2 From nobody Thu Feb 12 10:36:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A76B1C77B7A for ; Thu, 1 Jun 2023 05:36:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231346AbjFAFgv (ORCPT ); Thu, 1 Jun 2023 01:36:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231278AbjFAFgn (ORCPT ); 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dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Nikita Shubin Cc: Michael Peters , Kris Bahnsen , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v1 02/43] dt-bindings: soc: Add Cirrus EP93xx Date: Thu, 1 Jun 2023 08:33:53 +0300 Message-Id: <20230601053546.9574-3-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds device tree bindings for the Cirrus Logic EP93xx. Signed-off-by: Nikita Shubin --- Notes: v0 -> v1: =20 - fixed compatible - now it specifies three boards - ts7250 - bk3 - edb9302 - fixed identation in example - dropped labels .../devicetree/bindings/arm/ep93xx.yaml | 107 ++++++++++++++++++ .../dt-bindings/clock/cirrus,ep93xx-clock.h | 53 +++++++++ 2 files changed, 160 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/ep93xx.yaml create mode 100644 include/dt-bindings/clock/cirrus,ep93xx-clock.h diff --git a/Documentation/devicetree/bindings/arm/ep93xx.yaml b/Documentat= ion/devicetree/bindings/arm/ep93xx.yaml new file mode 100644 index 000000000000..bcf9754d0763 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/ep93xx.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/ep93xx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic EP93xx device tree bindings + +description: |+ + The EP93xx SoC is a ARMv4T-based with 200 MHz ARM9 CPU. + +maintainers: + - Alexander Sverdlin + - Nikita Shubin + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: The TS-7250 is a compact, full-featured Single Board = Computer (SBC) + based upon the Cirrus EP9302 ARM9 CPU + items: + - const: technologic,ts7250 + - const: cirrus,ep9301 + + - description: The Liebherr BK3 is a derivate from ts7250 board + items: + - const: liebherr,bk3 + - const: cirrus,ep9301 + + - description: EDB302 is an evaluation board by Cirrus Logic, + based on a Cirrus Logic EP9302 CPU + items: + - const: cirrus,edb9302 + - const: cirrus,ep9301 + + soc: + type: object + patternProperties: + "^.*syscon@80930000$": + type: object + properties: + compatible: + items: + - const: cirrus,ep9301-syscon + - const: syscon + - const: simple-mfd + ep9301-reboot: + type: object + properties: + compatible: + const: cirrus,ep9301-reboot + required: + - compatible + - reg + - ep9301-reboot + + "^.*timer@80810000$": + type: object + properties: + compatible: + const: cirrus,ep9301-timer + + required: + - syscon@80930000 + - timer@80810000 + +required: + - compatible + - soc + +additionalProperties: true + +examples: + - | + / { + compatible =3D "technologic,ts7250", "cirrus,ep9301"; + model =3D "TS-7250 SBC"; + #address-cells =3D <1>; + #size-cells =3D <1>; + soc { + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + compatible =3D "simple-bus"; + + syscon@80930000 { + compatible =3D "cirrus,ep9301-syscon", + "syscon", "simple-mfd"; + reg =3D <0x80930000 0x1000>; + + ep9301-reboot { + compatible =3D "cirrus,ep9301-reboot"; + }; + }; + + timer@80810000 { + compatible =3D "cirrus,ep9301-timer"; + reg =3D <0x80810000 0x100>; + interrupt-parent =3D <&vic1>; + interrupts =3D <19>; + }; + }; + }; + +... diff --git a/include/dt-bindings/clock/cirrus,ep93xx-clock.h b/include/dt-b= indings/clock/cirrus,ep93xx-clock.h new file mode 100644 index 000000000000..6a8cf33d811b --- /dev/null +++ b/include/dt-bindings/clock/cirrus,ep93xx-clock.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef DT_BINDINGS_CIRRUS_EP93XX_CLOCK_H +#define DT_BINDINGS_CIRRUS_EP93XX_CLOCK_H + +#define EP93XX_CLK_XTALI 0 + +#define EP93XX_CLK_PLL1 1 +#define EP93XX_CLK_FCLK 2 +#define EP93XX_CLK_HCLK 3 +#define EP93XX_CLK_PCLK 4 +#define EP93XX_CLK_PLL2 5 + +#define EP93XX_CLK_UART 6 + +#define EP93XX_CLK_UART1 7 +#define EP93XX_CLK_UART2 8 +#define EP93XX_CLK_UART3 9 + +#define EP93XX_CLK_M2M0 10 +#define EP93XX_CLK_M2M1 11 + +#define EP93XX_CLK_M2P0 12 +#define EP93XX_CLK_M2P1 13 +#define EP93XX_CLK_M2P2 14 +#define EP93XX_CLK_M2P3 15 +#define EP93XX_CLK_M2P4 16 +#define EP93XX_CLK_M2P5 17 +#define EP93XX_CLK_M2P6 18 +#define EP93XX_CLK_M2P7 19 +#define EP93XX_CLK_M2P8 20 +#define EP93XX_CLK_M2P9 21 + +#define EP93XX_CLK_SPI 22 + +#define EP93XX_CLK_USB 23 + +#define EP93XX_CLK_ADC 24 +#define EP93XX_CLK_ADC_EN 25 + +#define EP93XX_CLK_KEYPAD 26 + +#define EP93XX_CLK_PWM 27 + +#define EP93XX_CLK_VIDEO 28 + +#define EP93XX_CLK_I2S_MCLK 29 +#define EP93XX_CLK_I2S_SCLK 30 +#define EP93XX_CLK_I2S_LRCLK 31 + + +#define EP93XX_NUM_CLKS (EP93XX_CLK_I2S_LRCLK + 1) + +#endif /* DT_BINDINGS_CIRRUS_EP93XX_CLOCK_H */ --=20 2.37.4 From nobody Thu Feb 12 10:36:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59A29C77B76 for ; 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a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1682328936; bh=F6ZqrcN/SPT+NEKdvisviYYJ0nz6Hh0jgcWtDLBhcrI=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=htlHupDTDM1JNR4utO/0XPqY03mws+YZwIA1NTdLFVHmBQl7SKzqAkd7CsuasTD6Q saC+o/01fGtI9LaF8YQfyWwDjRCW/SZ233vWZs/LKEe00i8hm38UlJKLn16OGdhpHx hpjO9UjvZil4KK0+OCnQwHoWCv7xH1Hr3pcvcfGE= Authentication-Results: mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , Linus Walleij , Arnd Bergmann , Joel Stanley , Conor Dooley , Lubomir Rintel , Robert Jarzmik , =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= , Hitomi Hasegawa , Walker Chen , Heiko Stuebner , Sven Peter , Brian Norris , Emil Renner Berthing , Yinbo Zhu , Vasily Gorbik , Alexander Gordeev , Sumanth Korikkar , linux-kernel@vger.kernel.org Subject: [PATCH 02/43] soc: Add SoC driver for Cirrus ep93xx Date: Mon, 24 Apr 2023 15:34:18 +0300 Message-Id: <20230424123522.18302-3-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds an SoC driver for the ep93xx. Currently there is only one thing not fitting into any other framework, and that is the swlock setting. It's used for clock settings and restart. Signed-off-by: Nikita Shubin Reviewed-by: Linus Walleij Acked-by: Alexander Sverdlin Tested-by: Alexander Sverdlin --- Notes: rfc -> v0 Alexander Sverdlin: - replace spinlock with local_irq =20 Arnd Bergmann: - wildcards changed to ep9301 =20 Linus Walleij: - added tag, i hope changes are not significant enough to drop Reviewed-by tag drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/cirrus/Kconfig | 11 +++ drivers/soc/cirrus/Makefile | 2 + drivers/soc/cirrus/soc-ep93xx.c | 134 ++++++++++++++++++++++++++++++ include/linux/soc/cirrus/ep93xx.h | 16 +++- 6 files changed, 161 insertions(+), 4 deletions(-) create mode 100644 drivers/soc/cirrus/Kconfig create mode 100644 drivers/soc/cirrus/Makefile create mode 100644 drivers/soc/cirrus/soc-ep93xx.c diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 4e176280113a..6149f0447b61 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -30,5 +30,6 @@ source "drivers/soc/ti/Kconfig" source "drivers/soc/ux500/Kconfig" source "drivers/soc/versatile/Kconfig" source "drivers/soc/xilinx/Kconfig" +source "drivers/soc/cirrus/Kconfig" =20 endmenu diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 3b0f9fb3b5c8..2ba52d7560bf 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -36,3 +36,4 @@ obj-y +=3D ti/ obj-$(CONFIG_ARCH_U8500) +=3D ux500/ obj-$(CONFIG_PLAT_VERSATILE) +=3D versatile/ obj-y +=3D xilinx/ +obj-$(CONFIG_SOC_EP93XX) +=3D cirrus/ diff --git a/drivers/soc/cirrus/Kconfig b/drivers/soc/cirrus/Kconfig new file mode 100644 index 000000000000..d7262c96a5dc --- /dev/null +++ b/drivers/soc/cirrus/Kconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0 + +if ARCH_EP93XX + +config SOC_EP93XX + bool "Cirrus EP93xx chips SoC" + default y + help + Support Soc for Cirrus EP93xx chips. + +endif diff --git a/drivers/soc/cirrus/Makefile b/drivers/soc/cirrus/Makefile new file mode 100644 index 000000000000..ed6752844c6f --- /dev/null +++ b/drivers/soc/cirrus/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-y +=3D soc-ep93xx.o diff --git a/drivers/soc/cirrus/soc-ep93xx.c b/drivers/soc/cirrus/soc-ep93x= x.c new file mode 100644 index 000000000000..64842e9e2316 --- /dev/null +++ b/drivers/soc/cirrus/soc-ep93xx.c @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Soc driver for Cirrus EP93xx chips. + * Copyright (C) 2022 Nikita Shubin + * + * Based on a rewrite of arch/arm/mach-ep93xx/core.c + * Copyright (C) 2006 Lennert Buytenhek + * Copyright (C) 2007 Herbert Valerio Riedel + * + * Thanks go to Michael Burian and Ray Lehtiniemi for their key + * role in the ep93xx linux community + */ + +#include +#include +#include +#include +#include +#include + +#define EP93XX_SYSCON_DEVCFG 0x80 + +#define EP93XX_SWLOCK_MAGICK 0xaa +#define EP93XX_SYSCON_SWLOCK 0xc0 +#define EP93XX_SYSCON_SYSCFG 0x9c +#define EP93XX_SYSCON_SYSCFG_REV_MASK (0xf0000000) +#define EP93XX_SYSCON_SYSCFG_REV_SHIFT (28) + +static struct regmap *map; + +/* EP93xx System Controller software locked register write */ +void ep93xx_syscon_swlocked_write(unsigned int val, unsigned int reg) +{ + unsigned long flags; + + local_irq_save(flags); + + regmap_write(map, EP93XX_SYSCON_SWLOCK, EP93XX_SWLOCK_MAGICK); + regmap_write(map, reg, val); + + local_irq_restore(flags); +} +EXPORT_SYMBOL_GPL(ep93xx_syscon_swlocked_write); + +void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bit= s) +{ + unsigned long flags; + unsigned int val; + + local_irq_save(flags); + + regmap_read(map, EP93XX_SYSCON_DEVCFG, &val); + val &=3D ~clear_bits; + val |=3D set_bits; + regmap_write(map, EP93XX_SYSCON_SWLOCK, EP93XX_SWLOCK_MAGICK); + regmap_write(map, EP93XX_SYSCON_DEVCFG, val); + + local_irq_restore(flags); +} +EXPORT_SYMBOL_GPL(ep93xx_devcfg_set_clear); + +void ep93xx_swlocked_update_bits(unsigned int reg, + unsigned int mask, + unsigned int val) +{ + unsigned long flags; + unsigned int tmp, orig; + + local_irq_save(flags); + + regmap_read(map, EP93XX_SYSCON_DEVCFG, &orig); + tmp =3D orig & ~mask; + tmp |=3D val & mask; + if (tmp !=3D orig) { + regmap_write(map, EP93XX_SYSCON_SWLOCK, EP93XX_SWLOCK_MAGICK); + regmap_write(map, reg, tmp); + } + + local_irq_restore(flags); +} +EXPORT_SYMBOL_GPL(ep93xx_swlocked_update_bits); + +/** + * ep93xx_chip_revision() - returns the EP93xx chip revision + * + */ +unsigned int ep93xx_chip_revision(void) +{ + unsigned int val; + + regmap_read(map, EP93XX_SYSCON_SYSCFG, &val); + val &=3D EP93XX_SYSCON_SYSCFG_REV_MASK; + val >>=3D EP93XX_SYSCON_SYSCFG_REV_SHIFT; + return val; +} +EXPORT_SYMBOL_GPL(ep93xx_chip_revision); + +static const char __init *ep93xx_get_soc_rev(void) +{ + int rev =3D ep93xx_chip_revision(); + + switch (rev) { + case EP93XX_CHIP_REV_D0: + return "D0"; + case EP93XX_CHIP_REV_D1: + return "D1"; + case EP93XX_CHIP_REV_E0: + return "E0"; + case EP93XX_CHIP_REV_E1: + return "E1"; + case EP93XX_CHIP_REV_E2: + return "E2"; + default: + return "unknown"; + } +} + +static int __init ep93xx_soc_init(void) +{ + /* Multiplatform guard, only proceed on ep93xx */ + if (!of_machine_is_compatible("cirrus,ep9301")) + return 0; + + map =3D syscon_regmap_lookup_by_compatible("cirrus,ep9301-syscon"); + if (IS_ERR(map)) + return PTR_ERR(map); + + pr_info("EP93xx SoC revision %s\n", ep93xx_get_soc_rev()); + + return 0; +} + +core_initcall(ep93xx_soc_init); + diff --git a/include/linux/soc/cirrus/ep93xx.h b/include/linux/soc/cirrus/e= p93xx.h index 56fbe2dc59b1..f0f770a103be 100644 --- a/include/linux/soc/cirrus/ep93xx.h +++ b/include/linux/soc/cirrus/ep93xx.h @@ -10,7 +10,7 @@ struct platform_device; #define EP93XX_CHIP_REV_E1 6 #define EP93XX_CHIP_REV_E2 7 =20 -#ifdef CONFIG_ARCH_EP93XX +#if defined(CONFIG_ARCH_EP93XX) && !defined(CONFIG_OF) int ep93xx_pwm_acquire_gpio(struct platform_device *pdev); void ep93xx_pwm_release_gpio(struct platform_device *pdev); int ep93xx_ide_acquire_gpio(struct platform_device *pdev); @@ -19,8 +19,6 @@ int ep93xx_keypad_acquire_gpio(struct platform_device *pd= ev); void ep93xx_keypad_release_gpio(struct platform_device *pdev); int ep93xx_i2s_acquire(void); void ep93xx_i2s_release(void); -unsigned int ep93xx_chip_revision(void); - #else static inline int ep93xx_pwm_acquire_gpio(struct platform_device *pdev) { = return 0; } static inline void ep93xx_pwm_release_gpio(struct platform_device *pdev) {} @@ -30,8 +28,18 @@ static inline int ep93xx_keypad_acquire_gpio(struct plat= form_device *pdev) { ret static inline void ep93xx_keypad_release_gpio(struct platform_device *pdev= ) {} static inline int ep93xx_i2s_acquire(void) { return 0; } static inline void ep93xx_i2s_release(void) {} -static inline unsigned int ep93xx_chip_revision(void) { return 0; } +#endif =20 +#if defined(CONFIG_ARCH_EP93XX) +unsigned int ep93xx_chip_revision(void); +#ifdef CONFIG_SOC_EP93XX +void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bit= s); +void ep93xx_syscon_swlocked_write(unsigned int val, unsigned int reg); +void ep93xx_swlocked_update_bits(unsigned int reg, + unsigned int mask, unsigned int val); +#endif +#else +static inline unsigned int ep93xx_chip_revision(void) { return 0; } #endif =20 #endif --=20 2.39.2 From nobody Thu Feb 12 10:36:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55BF6C7EE23 for ; Thu, 1 Jun 2023 05:37:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231301AbjFAFhP (ORCPT ); Thu, 1 Jun 2023 01:37:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46498 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230479AbjFAFhI (ORCPT ); Thu, 1 Jun 2023 01:37:08 -0400 Received: from forward102c.mail.yandex.net (forward102c.mail.yandex.net [178.154.239.213]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8FA291AD for ; Wed, 31 May 2023 22:36:56 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net [IPv6:2a02:6b8:c14:c83:0:640:84f9:0]) by forward102c.mail.yandex.net (Yandex) with ESMTP id 2C49560037; Thu, 1 Jun 2023 08:36:54 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id OaGNfZvWv8c0-FhxpePtS; Thu, 01 Jun 2023 08:36:52 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1685597813; bh=3PBSgKvIv+TH92lEmC7wVtKbUzpHFhwv1RWbDVvNXDg=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=Iq8YoRzj6DaGogcU+8h2b8GlqbzBJiSqgY8soyBtk9GTwgQmsZDv/xh2Seu0coWsp UeZnuFxTxMez0jXfL/BN2Cte/MiivKxKGw5n8GJSHAC/qToExHHfkidskDl8ugIX5P Oko+QUM5WgGEVq1sKcK+tN00L7nNEpzVI4ahKbDc= Authentication-Results: mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij , Joel Stanley , Conor Dooley , Heiko Stuebner , Nikita Shubin , Yinbo Zhu , Hitomi Hasegawa , =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= , Walker Chen , Paul Menzel , Emil Renner Berthing , Alexander Gordeev , Vasily Gorbik Cc: Michael Peters , Kris Bahnsen , linux-kernel@vger.kernel.org Subject: [PATCH v1 03/43] soc: Add SoC driver for Cirrus ep93xx Date: Thu, 1 Jun 2023 08:33:54 +0300 Message-Id: <20230601053546.9574-4-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds an SoC driver for the ep93xx. Currently there is only one thing not fitting into any other framework, and that is the swlock setting. It's used for clock settings and restart. Signed-off-by: Nikita Shubin Tested-by: Alexander Sverdlin Acked-by: Alexander Sverdlin Reviewed-by: Linus Walleij --- Notes: v0 -> v1 =20 Replaced defines to make this patch compile: CONFIG_ARCH_EP93XX -> CONFIG_EP93XX_SOC_COMMON =20 And made changed depend on CONFIG_EP93XX_SOC, which is selected when !EP93XX_SOC_COMMON =20 rfc -> v0 Alexander Sverdlin: - replace spinlock with local_irq =20 Arnd Bergmann: - wildcards changed to ep9301 =20 Linus Walleij: - added tag, i hope changes are not significant enough to drop Reviewed-by tag drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/cirrus/Kconfig | 11 +++ drivers/soc/cirrus/Makefile | 2 + drivers/soc/cirrus/soc-ep93xx.c | 134 ++++++++++++++++++++++++++++++ include/linux/soc/cirrus/ep93xx.h | 16 +++- 6 files changed, 161 insertions(+), 4 deletions(-) create mode 100644 drivers/soc/cirrus/Kconfig create mode 100644 drivers/soc/cirrus/Makefile create mode 100644 drivers/soc/cirrus/soc-ep93xx.c diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 4e176280113a..6149f0447b61 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -30,5 +30,6 @@ source "drivers/soc/ti/Kconfig" source "drivers/soc/ux500/Kconfig" source "drivers/soc/versatile/Kconfig" source "drivers/soc/xilinx/Kconfig" +source "drivers/soc/cirrus/Kconfig" =20 endmenu diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 3b0f9fb3b5c8..7a8a154b8d96 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -36,3 +36,4 @@ obj-y +=3D ti/ obj-$(CONFIG_ARCH_U8500) +=3D ux500/ obj-$(CONFIG_PLAT_VERSATILE) +=3D versatile/ obj-y +=3D xilinx/ +obj-$(CONFIG_EP93XX_SOC) +=3D cirrus/ diff --git a/drivers/soc/cirrus/Kconfig b/drivers/soc/cirrus/Kconfig new file mode 100644 index 000000000000..bc82c0422325 --- /dev/null +++ b/drivers/soc/cirrus/Kconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0 + +if ARCH_EP93XX + +config EP93XX_SOC + bool "Cirrus EP93xx chips SoC" + default y if !EP93XX_SOC_COMMON + help + Support Soc for Cirrus EP93xx chips. + +endif diff --git a/drivers/soc/cirrus/Makefile b/drivers/soc/cirrus/Makefile new file mode 100644 index 000000000000..ed6752844c6f --- /dev/null +++ b/drivers/soc/cirrus/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-y +=3D soc-ep93xx.o diff --git a/drivers/soc/cirrus/soc-ep93xx.c b/drivers/soc/cirrus/soc-ep93x= x.c new file mode 100644 index 000000000000..64842e9e2316 --- /dev/null +++ b/drivers/soc/cirrus/soc-ep93xx.c @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Soc driver for Cirrus EP93xx chips. + * Copyright (C) 2022 Nikita Shubin + * + * Based on a rewrite of arch/arm/mach-ep93xx/core.c + * Copyright (C) 2006 Lennert Buytenhek + * Copyright (C) 2007 Herbert Valerio Riedel + * + * Thanks go to Michael Burian and Ray Lehtiniemi for their key + * role in the ep93xx linux community + */ + +#include +#include +#include +#include +#include +#include + +#define EP93XX_SYSCON_DEVCFG 0x80 + +#define EP93XX_SWLOCK_MAGICK 0xaa +#define EP93XX_SYSCON_SWLOCK 0xc0 +#define EP93XX_SYSCON_SYSCFG 0x9c +#define EP93XX_SYSCON_SYSCFG_REV_MASK (0xf0000000) +#define EP93XX_SYSCON_SYSCFG_REV_SHIFT (28) + +static struct regmap *map; + +/* EP93xx System Controller software locked register write */ +void ep93xx_syscon_swlocked_write(unsigned int val, unsigned int reg) +{ + unsigned long flags; + + local_irq_save(flags); + + regmap_write(map, EP93XX_SYSCON_SWLOCK, EP93XX_SWLOCK_MAGICK); + regmap_write(map, reg, val); + + local_irq_restore(flags); +} +EXPORT_SYMBOL_GPL(ep93xx_syscon_swlocked_write); + +void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bit= s) +{ + unsigned long flags; + unsigned int val; + + local_irq_save(flags); + + regmap_read(map, EP93XX_SYSCON_DEVCFG, &val); + val &=3D ~clear_bits; + val |=3D set_bits; + regmap_write(map, EP93XX_SYSCON_SWLOCK, EP93XX_SWLOCK_MAGICK); + regmap_write(map, EP93XX_SYSCON_DEVCFG, val); + + local_irq_restore(flags); +} +EXPORT_SYMBOL_GPL(ep93xx_devcfg_set_clear); + +void ep93xx_swlocked_update_bits(unsigned int reg, + unsigned int mask, + unsigned int val) +{ + unsigned long flags; + unsigned int tmp, orig; + + local_irq_save(flags); + + regmap_read(map, EP93XX_SYSCON_DEVCFG, &orig); + tmp =3D orig & ~mask; + tmp |=3D val & mask; + if (tmp !=3D orig) { + regmap_write(map, EP93XX_SYSCON_SWLOCK, EP93XX_SWLOCK_MAGICK); + regmap_write(map, reg, tmp); + } + + local_irq_restore(flags); +} +EXPORT_SYMBOL_GPL(ep93xx_swlocked_update_bits); + +/** + * ep93xx_chip_revision() - returns the EP93xx chip revision + * + */ +unsigned int ep93xx_chip_revision(void) +{ + unsigned int val; + + regmap_read(map, EP93XX_SYSCON_SYSCFG, &val); + val &=3D EP93XX_SYSCON_SYSCFG_REV_MASK; + val >>=3D EP93XX_SYSCON_SYSCFG_REV_SHIFT; + return val; +} +EXPORT_SYMBOL_GPL(ep93xx_chip_revision); + +static const char __init *ep93xx_get_soc_rev(void) +{ + int rev =3D ep93xx_chip_revision(); + + switch (rev) { + case EP93XX_CHIP_REV_D0: + return "D0"; + case EP93XX_CHIP_REV_D1: + return "D1"; + case EP93XX_CHIP_REV_E0: + return "E0"; + case EP93XX_CHIP_REV_E1: + return "E1"; + case EP93XX_CHIP_REV_E2: + return "E2"; + default: + return "unknown"; + } +} + +static int __init ep93xx_soc_init(void) +{ + /* Multiplatform guard, only proceed on ep93xx */ + if (!of_machine_is_compatible("cirrus,ep9301")) + return 0; + + map =3D syscon_regmap_lookup_by_compatible("cirrus,ep9301-syscon"); + if (IS_ERR(map)) + return PTR_ERR(map); + + pr_info("EP93xx SoC revision %s\n", ep93xx_get_soc_rev()); + + return 0; +} + +core_initcall(ep93xx_soc_init); + diff --git a/include/linux/soc/cirrus/ep93xx.h b/include/linux/soc/cirrus/e= p93xx.h index 56fbe2dc59b1..37c0e17a45c0 100644 --- a/include/linux/soc/cirrus/ep93xx.h +++ b/include/linux/soc/cirrus/ep93xx.h @@ -10,7 +10,7 @@ struct platform_device; #define EP93XX_CHIP_REV_E1 6 #define EP93XX_CHIP_REV_E2 7 =20 -#ifdef CONFIG_ARCH_EP93XX +#if defined(CONFIG_EP93XX_SOC_COMMON) int ep93xx_pwm_acquire_gpio(struct platform_device *pdev); void ep93xx_pwm_release_gpio(struct platform_device *pdev); int ep93xx_ide_acquire_gpio(struct platform_device *pdev); @@ -19,8 +19,6 @@ int ep93xx_keypad_acquire_gpio(struct platform_device *pd= ev); void ep93xx_keypad_release_gpio(struct platform_device *pdev); int ep93xx_i2s_acquire(void); void ep93xx_i2s_release(void); -unsigned int ep93xx_chip_revision(void); - #else static inline int ep93xx_pwm_acquire_gpio(struct platform_device *pdev) { = return 0; } static inline void ep93xx_pwm_release_gpio(struct platform_device *pdev) {} @@ -30,8 +28,18 @@ static inline int ep93xx_keypad_acquire_gpio(struct plat= form_device *pdev) { ret static inline void ep93xx_keypad_release_gpio(struct platform_device *pdev= ) {} static inline int ep93xx_i2s_acquire(void) { return 0; } static inline void ep93xx_i2s_release(void) {} -static inline unsigned int ep93xx_chip_revision(void) { return 0; } +#endif =20 +#if defined(CONFIG_ARCH_EP93XX) +unsigned int ep93xx_chip_revision(void); +#if defined(CONFIG_EP93XX_SOC) +void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bit= s); +void ep93xx_syscon_swlocked_write(unsigned int val, unsigned int reg); +void ep93xx_swlocked_update_bits(unsigned int reg, + unsigned int mask, unsigned int val); +#endif +#else +static inline unsigned int ep93xx_chip_revision(void) { return 0; } #endif =20 #endif --=20 2.37.4 From nobody Thu Feb 12 10:36:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2159C77B61 for ; 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Mon, 24 Apr 2023 12:35:37 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1682328937; bh=LuvwFxFGRS5iNfT4J+WUehyL2rZj86DmXsjlr5Rkiuo=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=odwNcFIKvpgD7Mxs61sPi/mM0t5sONtn8X+zNZFoC++6LweyKj1K0ogUCqcp7G4DB MzgAu4cBnHr7FWS8qEq4FTsMtOG9R9JjeljUMwPy2cX/EV6XVN2P/40L1sViD/JHuX +8Ap7ni0mGO63qd1SeqIylq2dbUz3UlKA/vu1nIw= Authentication-Results: mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 03/43] dt-bindings: pinctrl: Add DT bindings ep93xx pinctrl Date: Mon, 24 Apr 2023 15:34:19 +0300 Message-Id: <20230424123522.18302-4-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add YAML bindings ep93xx SoC. Signed-off-by: Nikita Shubin Reviewed-by: Linus Walleij --- Notes: rfc->v0: - dropped separate bindings description, left only one with all groups, functions and etc... - added Alexander Sverdlin to maintainers - added Linus Reviwed-by tags, through i shoudn't =3D) too many changes - fixed warning and added seq_file header .../pinctrl/cirrus,ep93xx-pinctrl.yaml | 66 +++++++++++++++++++ 1 file changed, 66 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/cirrus,ep93xx= -pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/cirrus,ep93xx-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/cirrus,ep93xx-pinctrl.ya= ml new file mode 100644 index 000000000000..cba4be7c5994 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/cirrus,ep93xx-pinctrl.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/cirrus,ep93xx-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus ep93xx pins mux controller + +maintainers: + - Nikita Shubin + - Alexander Sverdlin + +properties: + compatible: + enum: + - cirrus,ep9301-pinctrl + - cirrus,ep9307-pinctrl + - cirrus,ep9312-pinctrl + regmap: + description: phandle to syscon + +patternProperties: + '^pinctrl-': + type: object + description: pin node + $ref: pinmux-node.yaml# + + properties: + function: + enum: [ spi, ac97, i2s, pwm, keypad, pata, lcd, gpio1, gpio2, gpio= 3, + gpio4, gpio6, gpio7 ] + groups: + minItems: 1 + maxItems: 2 + items: + enum: [ ssp, ac97, i2s_on_ssp, i2s_on_ac97, pwm1, gpio1agrp, + gpio2agrp, gpio3agrp, gpio4agrp, gpio6agrp, gpio7agrp, + rasteronsdram0grp, rasteronsdram3grp, keypadgrp, idegrp] + + required: + - function + - groups + +required: + - compatible + - regmap + +additionalProperties: false + +examples: + - | + syscon: syscon@80930000 { + compatible =3D "cirrus,ep9301-syscon", + "syscon", "simple-mfd"; + reg =3D <0x80930000 0x1000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + pinctrl: pinctrl { + compatible =3D "cirrus,ep9312-pinctrl"; + regmap =3D <&syscon>; + spi_default_pins: pinctrl-spi { + function =3D "spi"; + groups =3D "ssp"; + }; + }; + }; --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84454C77B7E for ; Mon, 24 Apr 2023 10:21:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229573AbjDXKVC (ORCPT ); Mon, 24 Apr 2023 06:21:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44282 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231515AbjDXKUl (ORCPT ); Mon, 24 Apr 2023 06:20:41 -0400 Received: from forward501c.mail.yandex.net (forward501c.mail.yandex.net [178.154.239.209]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B82AB7; Mon, 24 Apr 2023 03:20:35 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net [IPv6:2a02:6b8:c12:261e:0:640:2e3d:0]) by forward501c.mail.yandex.net (Yandex) with ESMTP id E54AE5ED86; Mon, 24 Apr 2023 12:35:38 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id JZBb1pbWwKo0-t4H74iah; Mon, 24 Apr 2023 12:35:38 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1682328938; bh=PvL00vRm5IHlg8V2yLW2pdnjxI3j0EFhxWtpI3ZMOWE=; h=Cc:Message-Id:References:Date:In-Reply-To:Subject:To:From; b=s4ONOeaLeO6lqLnoNwMzoFNiDkxUb1hz327oMBZYbtKXz0OBe1MTrU3C+CXBuGiLE 0YRJp8SVSOHmho6yctm1I7wfaA/8WwnucAcvX3rcuOIqaWJkY+oCBAauNHGIu2pvgb JiWg/JRJK6O6PCRRqZsnXTDe6/uhJjWRiec1kS+o= Authentication-Results: mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , Linus Walleij , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [PATCH 04/43] pinctrl: add a Cirrus ep93xx SoC pin controller Date: Mon, 24 Apr 2023 15:34:20 +0300 Message-Id: <20230424123522.18302-5-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This adds a pin control (only multiplexing) driver for ep93xx SoC so we can fully convert ep93xx to device tree. This driver is capable of muxing ep9301/ep9302/ep9307/ep9312/ep9315 variants, this is chosen based on "compatible" in device tree. Co-developed-by: Alexander Sverdlin Signed-off-by: Alexander Sverdlin Signed-off-by: Nikita Shubin Reviewed-by: Linus Walleij --- Notes: - added ep9307 gpio groups =20 Linus Walleij: - dropped pinconf - added tag drivers/pinctrl/Kconfig | 7 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-ep93xx.c | 1698 ++++++++++++++++++++++++++++++ 3 files changed, 1706 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-ep93xx.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index dcb53c4a9584..60c6e3ba706b 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -176,6 +176,13 @@ config PINCTRL_DIGICOLOR select PINMUX select GENERIC_PINCONF =20 +config PINCTRL_EP93XX + bool + depends on OF && (ARCH_EP93XX || COMPILE_TEST) + select PINMUX + select GENERIC_PINCONF + select MFD_SYSCON + config PINCTRL_EQUILIBRIUM tristate "Generic pinctrl and GPIO driver for Intel Lightning Mountain So= C" depends on OF && HAS_IOMEM diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index d5939840bb2a..9d70c79eadbe 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_PINCTRL_DA850_PUPD) +=3D pinctrl-da850-pupd.o obj-$(CONFIG_PINCTRL_DA9062) +=3D pinctrl-da9062.o obj-$(CONFIG_PINCTRL_DIGICOLOR) +=3D pinctrl-digicolor.o obj-$(CONFIG_PINCTRL_EQUILIBRIUM) +=3D pinctrl-equilibrium.o +obj-$(CONFIG_PINCTRL_EP93XX) +=3D pinctrl-ep93xx.o obj-$(CONFIG_PINCTRL_GEMINI) +=3D pinctrl-gemini.o obj-$(CONFIG_PINCTRL_INGENIC) +=3D pinctrl-ingenic.o obj-$(CONFIG_PINCTRL_K210) +=3D pinctrl-k210.o diff --git a/drivers/pinctrl/pinctrl-ep93xx.c b/drivers/pinctrl/pinctrl-ep9= 3xx.c new file mode 100644 index 000000000000..c16a3bc585a8 --- /dev/null +++ b/drivers/pinctrl/pinctrl-ep93xx.c @@ -0,0 +1,1698 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Driver for the EP93xx pin controller + * based on linux/drivers/pinctrl/pinmux-gemini.c + * + * Copyright (C) 2022 Nikita Shubin + * + * This is a group-only pin controller. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-utils.h" + +#define DRIVER_NAME "pinctrl-ep93xx" + +enum ep93xx_pinctrl_model { + EP93XX_9301_PINCTRL =3D 0, + EP93XX_9307_PINCTRL, + EP93XX_9312_PINCTRL +}; + +/** + * struct ep93xx_pmx - state holder for the ep93xx pin controller + * @dev: a pointer back to containing device + * @pctl: the offset to the controller in virtual memory + * @map: regmap to access registers + * @model: SoC model + */ +struct ep93xx_pmx { + struct device *dev; + struct pinctrl_dev *pctl; + struct regmap *map; + enum ep93xx_pinctrl_model model; +}; + +/** + * struct ep93xx_pin_group - describes a ep93xx pin group + * @name: the name of this specific pin group + * @pins: an array of discrete physical pins used in this group, taken + * from the driver-local pin enumeration space + * @num_pins: the number of pins in this group array, i.e. the number of + * elements in .pins so we can iterate over that array + * @mask: bits to clear to enable this when doing pin muxing + * @value: bits to set to enable this when doing pin muxing + */ +struct ep93xx_pin_group { + const char *name; + const unsigned int *pins; + const unsigned int num_pins; + u32 mask; + u32 value; +}; + +#define EP93XX_SYSCON_DEVCFG 0x80 + +/* + * There are several system configuration options selectable by the Device= Cfg and SysCfg + * registers. These registers provide the selection of several pin multipl= exing options and also + * provide software access to the system reset configuration options. Plea= se refer to the + * descriptions of the registers, =E2=80=9CDeviceCfg=E2=80=9D on page 5-25= and =E2=80=9CSysCfg=E2=80=9D on page 5-34, for a + * detailed explanation. + */ +#define EP93XX_SYSCON_DEVCFG_D1ONG BIT(30) /* not used */ +#define EP93XX_SYSCON_DEVCFG_D0ONG BIT(29) /* not used */ +#define EP93XX_SYSCON_DEVCFG_IONU2 BIT(28) /* not used */ +#define EP93XX_SYSCON_DEVCFG_GONK BIT(27) /* done */ +#define EP93XX_SYSCON_DEVCFG_TONG BIT(26) /* not used */ +#define EP93XX_SYSCON_DEVCFG_MONG BIT(25) /* not used */ +#define EP93XX_SYSCON_DEVCFG_A2ONG BIT(22) /* not used */ +#define EP93XX_SYSCON_DEVCFG_A1ONG BIT(21) /* not used */ +#define EP93XX_SYSCON_DEVCFG_HONIDE BIT(11) /* done */ +#define EP93XX_SYSCON_DEVCFG_GONIDE BIT(10) /* done */ +#define EP93XX_SYSCON_DEVCFG_PONG BIT(9) /* done */ +#define EP93XX_SYSCON_DEVCFG_EONIDE BIT(8) /* done */ +#define EP93XX_SYSCON_DEVCFG_I2SONSSP BIT(7) /* done */ +#define EP93XX_SYSCON_DEVCFG_I2SONAC97 BIT(6) /* done */ +#define EP93XX_SYSCON_DEVCFG_RASONP3 BIT(4) /* done */ + +#define PADS_MASK (GENMASK(30, 25) | BIT(22) | BIT(21) | GENMASK(11, 6) |= BIT(4)) +#define PADS_MAXBIT 30 + +/* Ordered by bit index */ +static const char * const ep93xx_padgroups[] =3D { + NULL, NULL, NULL, NULL, + "RasOnP3", + NULL, + "I2SonAC97", + "I2SonSSP", + "EonIDE", + "PonG", + "GonIDE", + "HonIDE", + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + "A1onG", + "A2onG", + NULL, NULL, + "MonG", + "TonG", + "GonK", + "IonU2", + "D0onG", + "D1onG", +}; + +/** ep9301, ep9302*/ +static const struct pinctrl_pin_desc ep9301_pins[] =3D { + PINCTRL_PIN(1, "CSn[7]"), + PINCTRL_PIN(2, "CSn[6]"), + PINCTRL_PIN(3, "CSn[3]"), + PINCTRL_PIN(4, "CSn[2]"), + PINCTRL_PIN(5, "CSn[1]"), + PINCTRL_PIN(6, "AD[25]"), + PINCTRL_PIN(7, "vdd_ring"), + PINCTRL_PIN(8, "gnd_ring"), + PINCTRL_PIN(9, "AD[24]"), + PINCTRL_PIN(10, "SDCLK"), + PINCTRL_PIN(11, "AD[23]"), + PINCTRL_PIN(12, "vdd_core"), + PINCTRL_PIN(13, "gnd_core"), + PINCTRL_PIN(14, "SDWEn"), + PINCTRL_PIN(15, "SDCSn[3]"), + PINCTRL_PIN(16, "SDCSn[2]"), + PINCTRL_PIN(17, "SDCSn[1]"), + PINCTRL_PIN(18, "SDCSn[0]"), + PINCTRL_PIN(19, "vdd_ring"), + PINCTRL_PIN(20, "gnd_ring"), + PINCTRL_PIN(21, "RASn"), + PINCTRL_PIN(22, "CASn"), + PINCTRL_PIN(23, "DQMn[1]"), + PINCTRL_PIN(24, "DQMn[0]"), + PINCTRL_PIN(25, "AD[22]"), + PINCTRL_PIN(26, "AD[21]"), + PINCTRL_PIN(27, "vdd_ring"), + PINCTRL_PIN(28, "gnd_ring"), + PINCTRL_PIN(29, "DA[15]"), + PINCTRL_PIN(30, "AD[7]"), + PINCTRL_PIN(31, "DA[14]"), + PINCTRL_PIN(32, "AD[6]"), + PINCTRL_PIN(33, "DA[13]"), + PINCTRL_PIN(34, "vdd_core"), + PINCTRL_PIN(35, "gnd_core"), + PINCTRL_PIN(36, "AD[5]"), + PINCTRL_PIN(37, "DA[12]"), + PINCTRL_PIN(38, "AD[4]"), + PINCTRL_PIN(39, "DA[11]"), + PINCTRL_PIN(40, "AD[3]"), + PINCTRL_PIN(41, "vdd_ring"), + PINCTRL_PIN(42, "gnd_ring"), + PINCTRL_PIN(43, "DA[10]"), + PINCTRL_PIN(44, "AD[2]"), + PINCTRL_PIN(45, "DA[9]"), + PINCTRL_PIN(46, "AD[1]"), + PINCTRL_PIN(47, "DA[8]"), + PINCTRL_PIN(48, "AD[0]"), + PINCTRL_PIN(49, "vdd_ring"), + PINCTRL_PIN(50, "gnd_ring"), + PINCTRL_PIN(51, "NC"), + PINCTRL_PIN(52, "NC"), + PINCTRL_PIN(53, "vdd_ring"), + PINCTRL_PIN(54, "gnd_ring"), + PINCTRL_PIN(55, "AD[15]"), + PINCTRL_PIN(56, "DA[7]"), + PINCTRL_PIN(57, "vdd_core"), + PINCTRL_PIN(58, "gnd_core"), + PINCTRL_PIN(59, "AD[14]"), + PINCTRL_PIN(60, "DA[6]"), + PINCTRL_PIN(61, "AD[13]"), + PINCTRL_PIN(62, "DA[5]"), + PINCTRL_PIN(63, "AD[12]"), + PINCTRL_PIN(64, "DA[4]"), + PINCTRL_PIN(65, "AD[11]"), + PINCTRL_PIN(66, "vdd_ring"), + PINCTRL_PIN(67, "gnd_ring"), + PINCTRL_PIN(68, "DA[3]"), + PINCTRL_PIN(69, "AD[10]"), + PINCTRL_PIN(70, "DA[2]"), + PINCTRL_PIN(71, "AD[9]"), + PINCTRL_PIN(72, "DA[1]"), + PINCTRL_PIN(73, "AD[8]"), + PINCTRL_PIN(74, "DA[0]"), + PINCTRL_PIN(75, "DSRn"), + PINCTRL_PIN(76, "DTRn"), + PINCTRL_PIN(77, "TCK"), + PINCTRL_PIN(78, "TDI"), + PINCTRL_PIN(79, "TDO"), + PINCTRL_PIN(80, "TMS"), + PINCTRL_PIN(81, "vdd_ring"), + PINCTRL_PIN(82, "gnd_ring"), + PINCTRL_PIN(83, "BOOT[1]"), + PINCTRL_PIN(84, "BOOT[0]"), + PINCTRL_PIN(85, "gnd_ring"), + PINCTRL_PIN(86, "NC"), + PINCTRL_PIN(87, "EECLK"), + PINCTRL_PIN(88, "EEDAT"), + PINCTRL_PIN(89, "ASYNC"), + PINCTRL_PIN(90, "vdd_core"), + PINCTRL_PIN(91, "gnd_core"), + PINCTRL_PIN(92, "ASDO"), + PINCTRL_PIN(93, "SCLK1"), + PINCTRL_PIN(94, "SFRM1"), + PINCTRL_PIN(95, "SSPRX1"), + PINCTRL_PIN(96, "SSPTX1"), + PINCTRL_PIN(97, "GRLED"), + PINCTRL_PIN(98, "RDLED"), + PINCTRL_PIN(99, "vdd_ring"), + PINCTRL_PIN(100, "gnd_ring"), + PINCTRL_PIN(101, "INT[3]"), + PINCTRL_PIN(102, "INT[1]"), + PINCTRL_PIN(103, "INT[0]"), + PINCTRL_PIN(104, "RTSn"), + PINCTRL_PIN(105, "USBm[0]"), + PINCTRL_PIN(106, "USBp[0]"), + PINCTRL_PIN(107, "ABITCLK"), + PINCTRL_PIN(108, "CTSn"), + PINCTRL_PIN(109, "RXD[0]"), + PINCTRL_PIN(110, "RXD[1]"), + PINCTRL_PIN(111, "vdd_ring"), + PINCTRL_PIN(112, "gnd_ring"), + PINCTRL_PIN(113, "TXD[0]"), + PINCTRL_PIN(114, "TXD[1]"), + PINCTRL_PIN(115, "CGPIO[0]"), + PINCTRL_PIN(116, "gnd_core"), + PINCTRL_PIN(117, "PLL_GND"), + PINCTRL_PIN(118, "XTALI"), + PINCTRL_PIN(119, "XTALO"), + PINCTRL_PIN(120, "PLL_VDD"), + PINCTRL_PIN(121, "vdd_core"), + PINCTRL_PIN(122, "gnd_ring"), + PINCTRL_PIN(123, "vdd_ring"), + PINCTRL_PIN(124, "RSTOn"), + PINCTRL_PIN(125, "PRSTn"), + PINCTRL_PIN(126, "CSn[0]"), + PINCTRL_PIN(127, "gnd_core"), + PINCTRL_PIN(128, "vdd_core"), + PINCTRL_PIN(129, "gnd_ring"), + PINCTRL_PIN(130, "vdd_ring"), + PINCTRL_PIN(131, "ADC[4]"), + PINCTRL_PIN(132, "ADC[3]"), + PINCTRL_PIN(133, "ADC[2]"), + PINCTRL_PIN(134, "ADC[1]"), + PINCTRL_PIN(135, "ADC[0]"), + PINCTRL_PIN(136, "ADC_VDD"), + PINCTRL_PIN(137, "RTCXTALI"), + PINCTRL_PIN(138, "RTCXTALO"), + PINCTRL_PIN(139, "ADC_GND"), + PINCTRL_PIN(140, "EGPIO[11]"), + PINCTRL_PIN(141, "EGPIO[10]"), + PINCTRL_PIN(142, "EGPIO[9]"), + PINCTRL_PIN(143, "EGPIO[8]"), + PINCTRL_PIN(144, "EGPIO[7]"), + PINCTRL_PIN(145, "EGPIO[6]"), + PINCTRL_PIN(146, "EGPIO[5]"), + PINCTRL_PIN(147, "EGPIO[4]"), + PINCTRL_PIN(148, "EGPIO[3]"), + PINCTRL_PIN(149, "gnd_ring"), + PINCTRL_PIN(150, "vdd_ring"), + PINCTRL_PIN(151, "EGPIO[2]"), + PINCTRL_PIN(152, "EGPIO[1]"), + PINCTRL_PIN(153, "EGPIO[0]"), + PINCTRL_PIN(154, "ARSTn"), + PINCTRL_PIN(155, "TRSTn"), + PINCTRL_PIN(156, "ASDI"), + PINCTRL_PIN(157, "USBm[2]"), + PINCTRL_PIN(158, "USBp[2]"), + PINCTRL_PIN(159, "WAITn"), + PINCTRL_PIN(160, "EGPIO[15]"), + PINCTRL_PIN(161, "gnd_ring"), + PINCTRL_PIN(162, "vdd_ring"), + PINCTRL_PIN(163, "EGPIO[14]"), + PINCTRL_PIN(164, "EGPIO[13]"), + PINCTRL_PIN(165, "EGPIO[12]"), + PINCTRL_PIN(166, "gnd_core"), + PINCTRL_PIN(167, "vdd_core"), + PINCTRL_PIN(168, "FGPIO[3]"), + PINCTRL_PIN(169, "FGPIO[2]"), + PINCTRL_PIN(170, "FGPIO[1]"), + PINCTRL_PIN(171, "gnd_ring"), + PINCTRL_PIN(172, "vdd_ring"), + PINCTRL_PIN(173, "CLD"), + PINCTRL_PIN(174, "CRS"), + PINCTRL_PIN(175, "TXERR"), + PINCTRL_PIN(176, "TXEN"), + PINCTRL_PIN(177, "MIITXD[0]"), + PINCTRL_PIN(178, "MIITXD[1]"), + PINCTRL_PIN(179, "MIITXD[2]"), + PINCTRL_PIN(180, "MIITXD[3]"), + PINCTRL_PIN(181, "TXCLK"), + PINCTRL_PIN(182, "RXERR"), + PINCTRL_PIN(183, "RXDVAL"), + PINCTRL_PIN(184, "MIIRXD[0]"), + PINCTRL_PIN(185, "MIIRXD[1]"), + PINCTRL_PIN(186, "MIIRXD[2]"), + PINCTRL_PIN(187, "gnd_ring"), + PINCTRL_PIN(188, "vdd_ring"), + PINCTRL_PIN(189, "MIIRXD[3]"), + PINCTRL_PIN(190, "RXCLK"), + PINCTRL_PIN(191, "MDIO"), + PINCTRL_PIN(192, "MDC"), + PINCTRL_PIN(193, "RDn"), + PINCTRL_PIN(194, "WRn"), + PINCTRL_PIN(195, "AD[16]"), + PINCTRL_PIN(196, "AD[17]"), + PINCTRL_PIN(197, "gnd_core"), + PINCTRL_PIN(198, "vdd_core"), + PINCTRL_PIN(199, "HGPIO[2]"), + PINCTRL_PIN(200, "HGPIO[3]"), + PINCTRL_PIN(201, "HGPIO[4]"), + PINCTRL_PIN(202, "HGPIO[5]"), + PINCTRL_PIN(203, "gnd_ring"), + PINCTRL_PIN(204, "vdd_ring"), + PINCTRL_PIN(205, "AD[18]"), + PINCTRL_PIN(206, "AD[19]"), + PINCTRL_PIN(207, "AD[20]"), + PINCTRL_PIN(208, "SDCLKEN"), +}; + +static const unsigned int ssp_ep9301_pins[] =3D { + 93, 94, 95, 96 +}; + +static const unsigned int ac97_ep9301_pins[] =3D { + 89, 92, 107, 154, 156 +}; + +/* + * Note: The EP9307 processor has one PWM with one output, PWMOUT. + * Note: The EP9301, EP9302, EP9312, and EP9315 processors each have two P= WMs with + * two outputs, PWMOUT and PWMO1. PWMO1 is an alternate function for EGPIO= 14. + */ +/* The GPIO14E (14) pin overlap with pwm1 */ +static const unsigned int pwm_9301_pins[] =3D { 163 }; + +static const unsigned int gpio1a_9301_pins[] =3D { 163 }; + +/* ep9301/9302 have only 4,5 pin of GPIO E Port exposed */ +static const unsigned int gpio4a_9301_pins[] =3D { 97, 98 }; + +/* ep9301/9302 have only 4,5 pin of GPIO G Port exposed */ +static const unsigned int gpio6a_9301_pins[] =3D { 87, 88 }; + +static const unsigned int gpio7a_9301_pins[] =3D { 199, 200, 201, 202 }; + +/* Groups for the ep9301/ep9302 SoC/package */ +static const struct ep93xx_pin_group ep9301_pin_groups[] =3D { + { + .name =3D "ssp", + .pins =3D ssp_ep9301_pins, + .num_pins =3D ARRAY_SIZE(ssp_ep9301_pins), + .mask =3D EP93XX_SYSCON_DEVCFG_I2SONSSP, + }, + { + .name =3D "i2s_on_ssp", + .pins =3D ssp_ep9301_pins, + .num_pins =3D ARRAY_SIZE(ssp_ep9301_pins), + .value =3D EP93XX_SYSCON_DEVCFG_I2SONSSP, + .mask =3D EP93XX_SYSCON_DEVCFG_I2SONSSP, + }, + { + .name =3D "ac97", + .pins =3D ac97_ep9301_pins, + .num_pins =3D ARRAY_SIZE(ac97_ep9301_pins), + .mask =3D EP93XX_SYSCON_DEVCFG_I2SONAC97, + }, + { + .name =3D "i2s_on_ac97", + .pins =3D ac97_ep9301_pins, + .num_pins =3D ARRAY_SIZE(ac97_ep9301_pins), + .value =3D EP93XX_SYSCON_DEVCFG_I2SONAC97, + .mask =3D EP93XX_SYSCON_DEVCFG_I2SONAC97, + }, + { + .name =3D "pwm1", + .pins =3D pwm_9301_pins, + .num_pins =3D ARRAY_SIZE(pwm_9301_pins), + .value =3D EP93XX_SYSCON_DEVCFG_PONG, + .mask =3D EP93XX_SYSCON_DEVCFG_PONG, + }, + { + .name =3D "gpio1agrp", + .pins =3D gpio1a_9301_pins, + .num_pins =3D ARRAY_SIZE(gpio1a_9301_pins), + /* Conflict with PWM1 */ + .mask =3D EP93XX_SYSCON_DEVCFG_PONG, + }, + { + .name =3D "gpio4agrp", + .pins =3D gpio4a_9301_pins, + .num_pins =3D ARRAY_SIZE(gpio4a_9301_pins), + .value =3D EP93XX_SYSCON_DEVCFG_EONIDE, + .mask =3D EP93XX_SYSCON_DEVCFG_EONIDE, + }, + { + .name =3D "gpio6agrp", + .pins =3D gpio6a_9301_pins, + .num_pins =3D ARRAY_SIZE(gpio6a_9301_pins), + .value =3D EP93XX_SYSCON_DEVCFG_GONIDE, + .mask =3D EP93XX_SYSCON_DEVCFG_GONIDE, + }, + { + .name =3D "gpio7agrp", + .pins =3D gpio7a_9301_pins, + .num_pins =3D ARRAY_SIZE(gpio7a_9301_pins), + .value =3D EP93XX_SYSCON_DEVCFG_HONIDE, + .mask =3D EP93XX_SYSCON_DEVCFG_HONIDE, + }, +}; + +static const struct pinctrl_pin_desc ep9307_pins[] =3D { + /* Row A */ + PINCTRL_PIN(0, "CSn[1]"), /* A1 */ + PINCTRL_PIN(1, "CSn[7]"), /* A2 */ + PINCTRL_PIN(2, "SDCLKEN"), /* A3 */ + PINCTRL_PIN(3, "DA[31]"), /* A4 */ + PINCTRL_PIN(4, "DA[29]"), /* A5 */ + PINCTRL_PIN(5, "DA[27]"), /* A6 */ + PINCTRL_PIN(6, "HGPIO[2]"), /* A7 */ + PINCTRL_PIN(7, "RDn"), /* A8 */ + PINCTRL_PIN(8, "MIIRXD[3]"), /* A9 */ + PINCTRL_PIN(9, "RXDVAL"), /* A10 */ + PINCTRL_PIN(10, "MIITXD[1]"), /* A11 */ + PINCTRL_PIN(11, "CRS"), /* A12 */ + PINCTRL_PIN(12, "FGPIO[7]"), /* A13 */ + PINCTRL_PIN(13, "FGPIO[0]"), /* A14 */ + PINCTRL_PIN(14, "WAITn"), /* A15 */ + PINCTRL_PIN(15, "USBm[2]"), /* A16 */ + PINCTRL_PIN(16, "ASDI"), /* A17 */ + /* Row B*/ + PINCTRL_PIN(17, "AD[25]"), /* B1 */ + PINCTRL_PIN(18, "CSn[2]"), /* B2 */ + PINCTRL_PIN(19, "CSn[6]"), /* B3 */ + PINCTRL_PIN(20, "AD[20]"), /* B4 */ + PINCTRL_PIN(21, "DA[30]"), /* B5 */ + PINCTRL_PIN(22, "AD[18]"), /* B6 */ + PINCTRL_PIN(23, "HGPIO[3]"), /* B7 */ + PINCTRL_PIN(24, "AD[17]"), /* B8 */ + PINCTRL_PIN(25, "RXCLK"), /* B9 */ + PINCTRL_PIN(26, "MIIRXD[1]"), /* B10 */ + PINCTRL_PIN(27, "MIITXD[2]"), /* B11 */ + PINCTRL_PIN(28, "TXEN"), /* B12 */ + PINCTRL_PIN(29, "FGPIO[5]"), /* B13 */ + PINCTRL_PIN(30, "EGPIO[15]"), /* B14 */ + PINCTRL_PIN(31, "USBp[2]"), /* B15 */ + PINCTRL_PIN(32, "ARSTn"), /* B16 */ + PINCTRL_PIN(33, "ADC_VDD"), /* B17 */ + /* Row C*/ + PINCTRL_PIN(34, "AD[23]"), /* C1 */ + PINCTRL_PIN(35, "DA[26]"), /* C2 */ + PINCTRL_PIN(36, "CSn[3]"), /* C3 */ + PINCTRL_PIN(37, "DA[25]"), /* C4 */ + PINCTRL_PIN(38, "AD[24]"), /* C5 */ + PINCTRL_PIN(39, "AD[19]"), /* C6 */ + PINCTRL_PIN(40, "HGPIO[5]"), /* C7 */ + PINCTRL_PIN(41, "WRn"), /* C8 */ + PINCTRL_PIN(42, "MDIO"), /* C9 */ + PINCTRL_PIN(43, "MIIRXD[2]"), /* C10 */ + PINCTRL_PIN(44, "TXCLK"), /* C11 */ + PINCTRL_PIN(45, "MIITXD[0]"), /* C12 */ + PINCTRL_PIN(46, "CLD"), /* C13 */ + PINCTRL_PIN(47, "EGPIO[13]"), /* C14 */ + PINCTRL_PIN(48, "TRSTn"), /* C15 */ + PINCTRL_PIN(49, "Xp"), /* C16 */ + PINCTRL_PIN(50, "Xm"), /* C17 */ + /* Row D*/ + PINCTRL_PIN(51, "SDCSn[3]"), /* D1 */ + PINCTRL_PIN(52, "DA[23]"), /* D2 */ + PINCTRL_PIN(53, "SDCLK"), /* D3 */ + PINCTRL_PIN(54, "DA[24]"), /* D4 */ + PINCTRL_PIN(55, "HGPIO[7]"), /* D5 */ + PINCTRL_PIN(56, "HGPIO[6]"), /* D6 */ + PINCTRL_PIN(57, "A[28]"), /* D7 */ + PINCTRL_PIN(58, "HGPIO[4]"), /* D8 */ + PINCTRL_PIN(59, "AD[16]"), /* D9 */ + PINCTRL_PIN(60, "MDC"), /* D10 */ + PINCTRL_PIN(61, "RXERR"), /* D11 */ + PINCTRL_PIN(62, "MIITXD[3]"), /* D12 */ + PINCTRL_PIN(63, "EGPIO[12]"), /* D13 */ + PINCTRL_PIN(64, "EGPIO[1]"), /* D14 */ + PINCTRL_PIN(65, "EGPIO[0]"), /* D15 */ + PINCTRL_PIN(66, "Ym"), /* D16 */ + PINCTRL_PIN(67, "Yp"), /* D17 */ + /* Row E */ + PINCTRL_PIN(68, "SDCSn[2]"), /* E1 */ + PINCTRL_PIN(69, "SDWEN"), /* E2 */ + PINCTRL_PIN(70, "DA[22]"), /* E3 */ + PINCTRL_PIN(71, "AD[3]"), /* E4 */ + PINCTRL_PIN(72, "DA[15]"), /* E5 */ + PINCTRL_PIN(73, "AD[21]"), /* E6 */ + PINCTRL_PIN(74, "DA[17]"), /* E7 */ + PINCTRL_PIN(75, "vddr"), /* E8 */ + PINCTRL_PIN(76, "vddr"), /* E9 */ + PINCTRL_PIN(77, "vddr"), /* E10 */ + PINCTRL_PIN(78, "MIIRXD[0]"), /* E11 */ + PINCTRL_PIN(79, "TXERR"), /* E12 */ + PINCTRL_PIN(80, "EGPIO[2]"), /* E13 */ + PINCTRL_PIN(81, "EGPIO[4]"), /* E14 */ + PINCTRL_PIN(82, "EGPIO[3]"), /* E15 */ + PINCTRL_PIN(83, "sXp"), /* E16 */ + PINCTRL_PIN(84, "sXm"), /* E17 */ + /* Row F*/ + PINCTRL_PIN(85, "RASn"), /* F1 */ + PINCTRL_PIN(86, "SDCSn[1]"), /* F2 */ + PINCTRL_PIN(87, "SDCSn[0]"), /* F3 */ + PINCTRL_PIN(88, "DQMn[3]"), /* F4 */ + PINCTRL_PIN(89, "AD[5]"), /* F5 */ + PINCTRL_PIN(90, "gndr"), /* F6 */ + PINCTRL_PIN(91, "gndr"), /* F7 */ + PINCTRL_PIN(92, "gndr"), /* F8 */ + PINCTRL_PIN(93, "vddc"), /* F9 */ + PINCTRL_PIN(94, "vddc"), /* F10 */ + PINCTRL_PIN(95, "gndr"), /* F11 */ + PINCTRL_PIN(96, "EGPIO[7]"), /* F12 */ + PINCTRL_PIN(97, "EGPIO[5]"), /* F13 */ + PINCTRL_PIN(98, "ADC GND"), /* F14 */ + PINCTRL_PIN(99, "EGPIO[6]"), /* F15 */ + PINCTRL_PIN(100, "sYm"), /* F16 */ + PINCTRL_PIN(101, "syp"), /* F17 */ + /* Row G */ + PINCTRL_PIN(102, "DQMn[0]"), /* G1 */ + PINCTRL_PIN(103, "CASn"), /* G2 */ + PINCTRL_PIN(104, "DA[21]"), /* G3 */ + PINCTRL_PIN(105, "AD[22]"), /* G4 */ + PINCTRL_PIN(106, "vddr"), /* G5 */ + PINCTRL_PIN(107, "gndr"), /* G6 */ + PINCTRL_PIN(108, "gndr"), /* G12 */ + PINCTRL_PIN(109, "EGPIO[9]"), /* G13 */ + PINCTRL_PIN(110, "EGPIO[10]"), /* G14 */ + PINCTRL_PIN(111, "EGPIO[11]"), /* G15 */ + PINCTRL_PIN(112, "RTCXTALO"), /* G16 */ + PINCTRL_PIN(113, "RTCXTALI"), /* G17 */ + /* Row H */ + PINCTRL_PIN(114, "DA[18]"), /* H1 */ + PINCTRL_PIN(115, "DA[20]"), /* H2 */ + PINCTRL_PIN(116, "DA[19]"), /* H3 */ + PINCTRL_PIN(117, "DA[16]"), /* H4 */ + PINCTRL_PIN(118, "vddr"), /* H5 */ + PINCTRL_PIN(119, "vddc"), /* H6 */ + PINCTRL_PIN(120, "gndc"), /* H7 */ + PINCTRL_PIN(121, "gndc"), /* H9 */ + PINCTRL_PIN(122, "gndc"), /* H10 */ + PINCTRL_PIN(123, "gndr"), /* H12 */ + PINCTRL_PIN(124, "vddr"), /* H13 */ + PINCTRL_PIN(125, "EGPIO[8]"), /* H14 */ + PINCTRL_PIN(126, "PRSTN"), /* H15 */ + PINCTRL_PIN(127, "COL[7]"), /* H16 */ + PINCTRL_PIN(128, "RSTON"), /* H17 */ + /* Row J */ + PINCTRL_PIN(129, "AD[6]"), /* J1 */ + PINCTRL_PIN(130, "DA[14]"), /* J2 */ + PINCTRL_PIN(131, "AD[7]"), /* J3 */ + PINCTRL_PIN(132, "DA[13]"), /* J4 */ + PINCTRL_PIN(133, "vddr"), /* J5 */ + PINCTRL_PIN(134, "vddc"), /* J6 */ + PINCTRL_PIN(135, "gndc"), /* J8 */ + PINCTRL_PIN(136, "gndc"), /* J10 */ + PINCTRL_PIN(137, "vddc"), /* J12 */ + PINCTRL_PIN(138, "vddr"), /* J13 */ + PINCTRL_PIN(139, "COL[5]"), /* J14 */ + PINCTRL_PIN(140, "COL[6]"), /* J15 */ + PINCTRL_PIN(141, "CSn[0]"), /* J16 */ + PINCTRL_PIN(142, "COL[3]"), /* J17 */ + /* Row K */ + PINCTRL_PIN(143, "AD[4]"), /* K1 */ + PINCTRL_PIN(144, "DA[12]"), /* K2 */ + PINCTRL_PIN(145, "DA[10]"), /* K3 */ + PINCTRL_PIN(146, "DA[11]"), /* K4 */ + PINCTRL_PIN(147, "vddr"), /* K5 */ + PINCTRL_PIN(148, "gndr"), /* K6 */ + PINCTRL_PIN(149, "gndc"), /* K8 */ + PINCTRL_PIN(150, "gndc"), /* K9 */ + PINCTRL_PIN(151, "gndc"), /* K10 */ + PINCTRL_PIN(152, "vddc"), /* K12 */ + PINCTRL_PIN(153, "COL[4]"), /* K13 */ + PINCTRL_PIN(154, "PLL_VDD"), /* K14 */ + PINCTRL_PIN(155, "COL[2]"), /* K15 */ + PINCTRL_PIN(156, "COL[1]"), /* K16 */ + PINCTRL_PIN(157, "COL[0]"), /* K17 */ + /* Row L */ + PINCTRL_PIN(158, "DA[9]"), /* L1 */ + PINCTRL_PIN(159, "AD[2]"), /* L2 */ + PINCTRL_PIN(160, "AD[1]"), /* L3 */ + PINCTRL_PIN(161, "DA[8]"), /* L4 */ + PINCTRL_PIN(162, "BLANK"), /* L5 */ + PINCTRL_PIN(163, "gndr"), /* L6 */ + PINCTRL_PIN(164, "gndr"), /* L7 */ + PINCTRL_PIN(165, "ROW[7]"), /* L8 */ + PINCTRL_PIN(166, "ROW[5]"), /* L9 */ + PINCTRL_PIN(167, "PLL GND"), /* L10 */ + PINCTRL_PIN(168, "XTALI"), /* L11 */ + PINCTRL_PIN(169, "XTALO"), /* L12 */ + /* Row M */ + PINCTRL_PIN(170, "BRIGHT"), /* M1 */ + PINCTRL_PIN(171, "AD[0]"), /* M2 */ + PINCTRL_PIN(172, "DQMn[1]"), /* M3 */ + PINCTRL_PIN(173, "DQMn[2]"), /* M4 */ + PINCTRL_PIN(174, "P[17]"), /* M5 */ + PINCTRL_PIN(175, "gndr"), /* M6 */ + PINCTRL_PIN(176, "gndr"), /* M7 */ + PINCTRL_PIN(177, "vddc"), /* M8 */ + PINCTRL_PIN(178, "vddc"), /* M9 */ + PINCTRL_PIN(179, "gndr"), /* M10 */ + PINCTRL_PIN(180, "gndr"), /* M11 */ + PINCTRL_PIN(181, "ROW[6]"), /* M12 */ + PINCTRL_PIN(182, "ROW[4]"), /* M13 */ + PINCTRL_PIN(183, "ROW[1]"), /* M14 */ + PINCTRL_PIN(184, "ROW[0]"), /* M15 */ + PINCTRL_PIN(185, "ROW[3]"), /* M16 */ + PINCTRL_PIN(186, "ROW[2]"), /* M17 */ + /* Row N */ + PINCTRL_PIN(187, "P[14]"), /* N1 */ + PINCTRL_PIN(188, "P[16]"), /* N2 */ + PINCTRL_PIN(189, "P[15]"), /* N3 */ + PINCTRL_PIN(190, "P[13]"), /* N4 */ + PINCTRL_PIN(191, "P[12]"), /* N5 */ + PINCTRL_PIN(192, "DA[5]"), /* N6 */ + PINCTRL_PIN(193, "vddr"), /* N7 */ + PINCTRL_PIN(194, "vddr"), /* N8 */ + PINCTRL_PIN(195, "vddr"), /* N9 */ + PINCTRL_PIN(196, "vddr"), /* N10 */ + PINCTRL_PIN(197, "EECLK"), /* N11 */ + PINCTRL_PIN(198, "ASDO"), /* N12 */ + PINCTRL_PIN(199, "CTSn"), /* N13 */ + PINCTRL_PIN(200, "RXD[0]"), /* N14 */ + PINCTRL_PIN(201, "TXD[0]"), /* N15 */ + PINCTRL_PIN(202, "TXD[1]"), /* N16 */ + PINCTRL_PIN(203, "TXD[2]"), /* N17 */ + /* Row P */ + PINCTRL_PIN(204, "SPCLK"), /* P1 */ + PINCTRL_PIN(205, "P[10]"), /* P2 */ + PINCTRL_PIN(206, "P[11]"), /* P3 */ + PINCTRL_PIN(207, "P[3]"), /* P4 */ + PINCTRL_PIN(208, "AD[15]"), /* P5 */ + PINCTRL_PIN(209, "AD[13]"), /* P6 */ + PINCTRL_PIN(210, "AD[12]"), /* P7 */ + PINCTRL_PIN(211, "DA[2]"), /* P8 */ + PINCTRL_PIN(212, "AD[8]"), /* P9 */ + PINCTRL_PIN(213, "TCK"), /* P10 */ + PINCTRL_PIN(214, "BOOT[1]"), /* P11 */ + PINCTRL_PIN(215, "EEDAT"), /* P12 */ + PINCTRL_PIN(216, "GRLED"), /* P13 */ + PINCTRL_PIN(217, "RDLED"), /* P14 */ + PINCTRL_PIN(218, "GGPIO[2]"), /* P15 */ + PINCTRL_PIN(219, "RXD[1]"), /* P16 */ + PINCTRL_PIN(220, "RXD[2]"), /* P17 */ + /* Row R */ + PINCTRL_PIN(221, "P[9]"), /* R1 */ + PINCTRL_PIN(222, "HSYNC"), /* R2 */ + PINCTRL_PIN(223, "P[6]"), /* R3 */ + PINCTRL_PIN(224, "P[5]"), /* R4 */ + PINCTRL_PIN(225, "P[0]"), /* R5 */ + PINCTRL_PIN(226, "AD[14]"), /* R6 */ + PINCTRL_PIN(227, "DA[4]"), /* R7 */ + PINCTRL_PIN(228, "DA[1]"), /* R8 */ + PINCTRL_PIN(229, "DTRn"), /* R9 */ + PINCTRL_PIN(230, "TDI"), /* R10 */ + PINCTRL_PIN(231, "BOOT[0]"), /* R11 */ + PINCTRL_PIN(232, "ASYNC"), /* R12 */ + PINCTRL_PIN(233, "SSPTX[1]"), /* R13 */ + PINCTRL_PIN(234, "PWMOUT"), /* R14 */ + PINCTRL_PIN(235, "USBm[0]"), /* R15 */ + PINCTRL_PIN(236, "ABITCLK"), /* R16 */ + PINCTRL_PIN(237, "USBp[0]"), /* R17 */ + /* Row T */ + PINCTRL_PIN(238, "NC"), /* T1 */ + PINCTRL_PIN(239, "NC"), /* T2 */ + PINCTRL_PIN(240, "V_CSYNC"), /* T3 */ + PINCTRL_PIN(241, "P[7]"), /* T4 */ + PINCTRL_PIN(242, "P[2]"), /* T5 */ + PINCTRL_PIN(243, "DA[7]"), /* T6 */ + PINCTRL_PIN(244, "AD[11]"), /* T7 */ + PINCTRL_PIN(245, "AD[9]"), /* T8 */ + PINCTRL_PIN(246, "DSRn"), /* T9 */ + PINCTRL_PIN(247, "TMS"), /* T10 */ + PINCTRL_PIN(248, "gndr"), /* T11 */ + PINCTRL_PIN(249, "SFRM[1]"), /* T12 */ + PINCTRL_PIN(250, "INT[2]"), /* T13 */ + PINCTRL_PIN(251, "INT[0]"), /* T14 */ + PINCTRL_PIN(252, "USBp[1]"), /* T15 */ + PINCTRL_PIN(253, "NC"), /* T16 */ + PINCTRL_PIN(254, "NC"), /* T17 */ + /* Row U */ + PINCTRL_PIN(255, "NC"), /* U1 */ + PINCTRL_PIN(256, "NC"), /* U2 */ + PINCTRL_PIN(257, "P[8]"), /* U3 */ + PINCTRL_PIN(258, "P[4]"), /* U4 */ + PINCTRL_PIN(259, "P[1]"), /* U5 */ + PINCTRL_PIN(260, "DA[6]"), /* U6 */ + PINCTRL_PIN(261, "DA[3]"), /* U7 */ + PINCTRL_PIN(262, "AD[10]"), /* U8 */ + PINCTRL_PIN(263, "DA[0]"), /* U9 */ + PINCTRL_PIN(264, "TDO"), /* U10 */ + PINCTRL_PIN(265, "NC"), /* U11 */ + PINCTRL_PIN(266, "SCLK[1]"), /* U12 */ + PINCTRL_PIN(267, "SSPRX[1]"), /* U13 */ + PINCTRL_PIN(268, "INT[1]"), /* U14 */ + PINCTRL_PIN(269, "RTSn"), /* U15 */ + PINCTRL_PIN(270, "USBm[1]"), /* U16 */ + PINCTRL_PIN(271, "NC"), /* U17 */ +}; + +static const unsigned int ssp_ep9307_pins[] =3D { + 233, 249, 266, 267 +}; + +static const unsigned int ac97_ep9307_pins[] =3D { + 16, 32, 198, 232, 236 +}; + +/* I can't find info on those - it's some internal state */ +static const unsigned int raster_on_sdram0_pins[] =3D { +}; + +static const unsigned int raster_on_sdram3_pins[] =3D { +}; + +/* ROW[N] */ +static const unsigned int gpio2a_9307_pins[] =3D { + 165, 166, 181, 182, 183, 184, 185, 186 +}; + +/* COL[N] */ +static const unsigned int gpio3a_9307_pins[] =3D { + 127, 139, 140, 142, 153, 155, 156, 157 +}; + +static const unsigned int keypad_9307_pins[] =3D { + 127, 139, 140, 142, 153, 155, 156, 157, + 165, 166, 181, 182, 183, 184, 185, 186 +}; + +/* ep9307 have only 4,5 pin of GPIO E Port exposed */ +static const unsigned int gpio4a_9307_pins[] =3D { 216, 217 }; + +/* ep9307 have only 2 pin of GPIO G Port exposed */ +static const unsigned int gpio6a_9307_pins[] =3D { 219 }; + +static const unsigned int gpio7a_9307_pins[] =3D { 7, 24, 41, 56, 57, 59 }; + +static const struct ep93xx_pin_group ep9307_pin_groups[] =3D { + { + .name =3D "ssp", + .pins =3D ssp_ep9307_pins, + .num_pins =3D ARRAY_SIZE(ssp_ep9307_pins), + .mask =3D EP93XX_SYSCON_DEVCFG_I2SONSSP, + }, + { + .name =3D "i2s_on_ssp", + .pins =3D ssp_ep9307_pins, + .num_pins =3D ARRAY_SIZE(ssp_ep9307_pins), + .value =3D EP93XX_SYSCON_DEVCFG_I2SONSSP, + .mask =3D EP93XX_SYSCON_DEVCFG_I2SONSSP, + }, + { + .name =3D "ac97", + .pins =3D ac97_ep9307_pins, + .num_pins =3D ARRAY_SIZE(ac97_ep9307_pins), + .mask =3D EP93XX_SYSCON_DEVCFG_I2SONAC97, + }, + { + .name =3D "i2s_on_ac97", + .pins =3D ac97_ep9307_pins, + .num_pins =3D ARRAY_SIZE(ac97_ep9307_pins), + .value =3D EP93XX_SYSCON_DEVCFG_I2SONAC97, + .mask =3D EP93XX_SYSCON_DEVCFG_I2SONAC97, + }, + { + .name =3D "rasteronsdram0grp", + .pins =3D raster_on_sdram0_pins, + .num_pins =3D ARRAY_SIZE(raster_on_sdram0_pins), + .mask =3D EP93XX_SYSCON_DEVCFG_RASONP3, + }, + { + .name =3D "rasteronsdram3grp", + .pins =3D raster_on_sdram3_pins, + .num_pins =3D ARRAY_SIZE(raster_on_sdram3_pins), + .value =3D EP93XX_SYSCON_DEVCFG_RASONP3, + .mask =3D EP93XX_SYSCON_DEVCFG_RASONP3, + }, + { + .name =3D "gpio2agrp", + .pins =3D gpio2a_9307_pins, + .num_pins =3D ARRAY_SIZE(gpio2a_9307_pins), + .value =3D EP93XX_SYSCON_DEVCFG_GONK, + .mask =3D EP93XX_SYSCON_DEVCFG_GONK, + }, + { + .name =3D "gpio3agrp", + .pins =3D gpio3a_9307_pins, + .num_pins =3D ARRAY_SIZE(gpio3a_9307_pins), + .value =3D EP93XX_SYSCON_DEVCFG_GONK, + .mask =3D EP93XX_SYSCON_DEVCFG_GONK, + }, + { + .name =3D "keypadgrp", + .pins =3D keypad_9307_pins, + .num_pins =3D ARRAY_SIZE(keypad_9307_pins), + .mask =3D EP93XX_SYSCON_DEVCFG_GONK, + }, + { + .name =3D "gpio4agrp", + .pins =3D gpio4a_9307_pins, + .num_pins =3D ARRAY_SIZE(gpio4a_9307_pins), + .mask =3D EP93XX_SYSCON_DEVCFG_EONIDE, + }, + { + .name =3D "gpio6agrp", + .pins =3D gpio6a_9307_pins, + .num_pins =3D ARRAY_SIZE(gpio6a_9307_pins), + .value =3D EP93XX_SYSCON_DEVCFG_GONIDE, + .mask =3D EP93XX_SYSCON_DEVCFG_GONIDE, + }, + { + .name =3D "gpio7agrp", + .pins =3D gpio7a_9307_pins, + .num_pins =3D ARRAY_SIZE(gpio7a_9307_pins), + .value =3D EP93XX_SYSCON_DEVCFG_HONIDE, + .mask =3D EP93XX_SYSCON_DEVCFG_HONIDE, + }, +}; + +/* ep9312, ep9315 */ +static const struct pinctrl_pin_desc ep9312_pins[] =3D { + /* Row A */ + PINCTRL_PIN(0, "CSN[7]"), /* A1 */ + PINCTRL_PIN(1, "DA[28]"), /* A2 */ + PINCTRL_PIN(2, "AD[18]"), /* A3 */ + PINCTRL_PIN(3, "DD[8]"), /* A4 */ + PINCTRL_PIN(4, "DD[4]"), /* A5 */ + PINCTRL_PIN(5, "AD[17]"), /* A6 */ + PINCTRL_PIN(6, "RDN"), /* A7 */ + PINCTRL_PIN(7, "RXCLK"), /* A8 */ + PINCTRL_PIN(8, "MIIRXD[0]"), /* A9 */ + PINCTRL_PIN(9, "RXDVAL"), /* A10 */ + PINCTRL_PIN(10, "MIITXD[2]"), /* A11 */ + PINCTRL_PIN(11, "TXERR"), /* A12 */ + PINCTRL_PIN(12, "CLD"), /* A13 */ + PINCTRL_PIN(13, "NC"), /* A14 */ + PINCTRL_PIN(14, "NC"), /* A15 */ + PINCTRL_PIN(15, "NC"), /* A16 */ + PINCTRL_PIN(16, "EGPIO[12]"), /* A17 */ + PINCTRL_PIN(17, "EGPIO[15]"), /* A18 */ + PINCTRL_PIN(18, "NC"), /* A19 */ + PINCTRL_PIN(19, "NC"), /* A20 */ + /* Row B */ + PINCTRL_PIN(20, "CSN[2]"), /* B1 */ + PINCTRL_PIN(21, "DA[31]"), /* B2 */ + PINCTRL_PIN(22, "DA[30]"), /* B3 */ + PINCTRL_PIN(23, "DA[27]"), /* B4 */ + PINCTRL_PIN(24, "DD[7]"), /* B5 */ + PINCTRL_PIN(25, "DD[3]"), /* B6 */ + PINCTRL_PIN(26, "WRN"), /* B7 */ + PINCTRL_PIN(27, "MDIO"), /* B8 */ + PINCTRL_PIN(28, "MIIRXD[1]"), /* B9 */ + PINCTRL_PIN(29, "RXERR"), /* B10 */ + PINCTRL_PIN(30, "MIITXD[1]"), /* B11 */ + PINCTRL_PIN(31, "CRS"), /* B12 */ + PINCTRL_PIN(32, "NC"), /* B13 */ + PINCTRL_PIN(33, "NC"), /* B14 */ + PINCTRL_PIN(34, "NC"), /* B15 */ + PINCTRL_PIN(35, "NC"), /* B16 */ + PINCTRL_PIN(36, "EGPIO[13]"), /* B17 */ + PINCTRL_PIN(37, "NC"), /* B18 */ + PINCTRL_PIN(38, "WAITN"), /* B19 */ + PINCTRL_PIN(39, "TRSTN"), /* B20 */ + /* Row C */ + PINCTRL_PIN(40, "CSN[1]"), /* C1 */ + PINCTRL_PIN(41, "CSN[3]"), /* C2 */ + PINCTRL_PIN(42, "AD[20]"), /* C3 */ + PINCTRL_PIN(43, "DA[29]"), /* C4 */ + PINCTRL_PIN(44, "DD[10]"), /* C5 */ + PINCTRL_PIN(45, "DD[6]"), /* C6 */ + PINCTRL_PIN(46, "DD[2]"), /* C7 */ + PINCTRL_PIN(47, "MDC"), /* C8 */ + PINCTRL_PIN(48, "MIIRXD[3]"), /* C9 */ + PINCTRL_PIN(49, "TXCLK"), /* C10 */ + PINCTRL_PIN(50, "MIITXD[0]"), /* C11 */ + PINCTRL_PIN(51, "NC"), /* C12 */ + PINCTRL_PIN(52, "NC"), /* C13 */ + PINCTRL_PIN(53, "NC"), /* C14 */ + PINCTRL_PIN(54, "NC"), /* C15 */ + PINCTRL_PIN(55, "NC"), /* C16 */ + PINCTRL_PIN(56, "NC"), /* C17 */ + PINCTRL_PIN(57, "USBP[2]"), /* C18 */ + PINCTRL_PIN(58, "IORDY"), /* C19 */ + PINCTRL_PIN(59, "DMACKN"), /* C20 */ + /* Row D */ + PINCTRL_PIN(60, "AD[24]"), /* D1 */ + PINCTRL_PIN(61, "DA[25]"), /* D2 */ + PINCTRL_PIN(62, "DD[11]"), /* D3 */ + PINCTRL_PIN(63, "SDCLKEN"), /* D4 */ + PINCTRL_PIN(64, "AD[19]"), /* D5 */ + PINCTRL_PIN(65, "DD[9]"), /* D6 */ + PINCTRL_PIN(66, "DD[5]"), /* D7 */ + PINCTRL_PIN(67, "AD[16]"), /* D8 */ + PINCTRL_PIN(68, "MIIRXD[2]"), /* D9 */ + PINCTRL_PIN(69, "MIITXD[3]"), /* D10 */ + PINCTRL_PIN(70, "TXEN"), /* D11 */ + PINCTRL_PIN(71, "NC"), /* D12 */ + PINCTRL_PIN(72, "NC"), /* D13 */ + PINCTRL_PIN(73, "NC"), /* D14 */ + PINCTRL_PIN(74, "EGPIO[14]"), /* D15 */ + PINCTRL_PIN(75, "NC"), /* D16 */ + PINCTRL_PIN(76, "USBM[2]"), /* D17 */ + PINCTRL_PIN(77, "ARSTN"), /* D18 */ + PINCTRL_PIN(78, "DIORN"), /* D19 */ + PINCTRL_PIN(79, "EGPIO[1]"), /* D20 */ + /* Row E */ + PINCTRL_PIN(80, "AD[23]"), /* E1 */ + PINCTRL_PIN(81, "DA[23]"), /* E2 */ + PINCTRL_PIN(82, "DA[26]"), /* E3 */ + PINCTRL_PIN(83, "CSN[6]"), /* E4 */ + PINCTRL_PIN(84, "GND"), /* E5 */ + PINCTRL_PIN(85, "GND"), /* E6 */ + PINCTRL_PIN(86, "CVDD"), /* E7 */ + PINCTRL_PIN(87, "CVDD"), /* E8 */ + PINCTRL_PIN(88, "RVDD"), /* E9 */ + PINCTRL_PIN(89, "GND"), /* E10 */ + PINCTRL_PIN(90, "GND"), /* E11 */ + PINCTRL_PIN(91, "RVDD"), /* E12 */ + PINCTRL_PIN(92, "CVDD"), /* E13 */ + PINCTRL_PIN(93, "CVDD"), /* E14 */ + PINCTRL_PIN(94, "GND"), /* E15 */ + PINCTRL_PIN(95, "ASDI"), /* E16 */ + PINCTRL_PIN(96, "DIOWN"), /* E17 */ + PINCTRL_PIN(97, "EGPIO[0]"), /* E18 */ + PINCTRL_PIN(98, "EGPIO[3]"), /* E19 */ + PINCTRL_PIN(99, "EGPIO[5]"), /* E20 */ + /* Row F */ + PINCTRL_PIN(100, "SDCSN[3]"), /* F1 */ + PINCTRL_PIN(101, "DA[22]"), /* F2 */ + PINCTRL_PIN(102, "DA[24]"), /* F3 */ + PINCTRL_PIN(103, "AD[25]"), /* F4 */ + PINCTRL_PIN(104, "RVDD"), /* F5 */ + PINCTRL_PIN(105, "GND"), /* F6 */ + PINCTRL_PIN(106, "CVDD"), /* F7 */ + PINCTRL_PIN(107, "CVDD"), /* F14 */ + PINCTRL_PIN(108, "GND"), /* F15 */ + PINCTRL_PIN(109, "GND"), /* F16 */ + PINCTRL_PIN(110, "EGPIO[2]"), /* F17 */ + PINCTRL_PIN(111, "EGPIO[4]"), /* F18 */ + PINCTRL_PIN(112, "EGPIO[6]"), /* F19 */ + PINCTRL_PIN(113, "EGPIO[8]"), /* F20 */ + /* Row G */ + PINCTRL_PIN(114, "SDCSN[0]"), /* G1 */ + PINCTRL_PIN(115, "SDCSN[1]"), /* G2 */ + PINCTRL_PIN(116, "SDWEN"), /* G3 */ + PINCTRL_PIN(117, "SDCLK"), /* G4 */ + PINCTRL_PIN(118, "RVDD"), /* G5 */ + PINCTRL_PIN(119, "RVDD"), /* G6 */ + PINCTRL_PIN(120, "RVDD"), /* G15 */ + PINCTRL_PIN(121, "RVDD"), /* G16 */ + PINCTRL_PIN(122, "EGPIO[7]"), /* G17 */ + PINCTRL_PIN(123, "EGPIO[9]"), /* G18 */ + PINCTRL_PIN(124, "EGPIO[10]"), /* G19 */ + PINCTRL_PIN(125, "EGPIO[11]"), /* G20 */ + /* Row H */ + PINCTRL_PIN(126, "DQMN[3]"), /* H1 */ + PINCTRL_PIN(127, "CASN"), /* H2 */ + PINCTRL_PIN(128, "RASN"), /* H3 */ + PINCTRL_PIN(129, "SDCSN[2]"), /* H4 */ + PINCTRL_PIN(130, "CVDD"), /* H5 */ + PINCTRL_PIN(131, "GND"), /* H8 */ + PINCTRL_PIN(132, "GND"), /* H9 */ + PINCTRL_PIN(133, "GND"), /* H10 */ + PINCTRL_PIN(134, "GND"), /* H11 */ + PINCTRL_PIN(135, "GND"), /* H12 */ + PINCTRL_PIN(136, "GND"), /* H13 */ + PINCTRL_PIN(137, "RVDD"), /* H16 */ + PINCTRL_PIN(138, "RTCXTALO"), /* H17 */ + PINCTRL_PIN(139, "ADC_VDD"), /* H18 */ + PINCTRL_PIN(140, "ADC_GND"), /* H19 */ + PINCTRL_PIN(141, "XP"), /* H20 */ + /* Row J */ + PINCTRL_PIN(142, "DA[21]"), /* J1 */ + PINCTRL_PIN(143, "DQMN[0]"), /* J2 */ + PINCTRL_PIN(144, "DQMN[1]"), /* J3 */ + PINCTRL_PIN(145, "DQMN[2]"), /* J4 */ + PINCTRL_PIN(146, "GND"), /* J5 */ + PINCTRL_PIN(147, "GND"), /* J8 */ + PINCTRL_PIN(148, "GND"), /* J9 */ + PINCTRL_PIN(149, "GND"), /* J10 */ + PINCTRL_PIN(150, "GND"), /* J11 */ + PINCTRL_PIN(151, "GND"), /* J12 */ + PINCTRL_PIN(152, "GND"), /* J13 */ + PINCTRL_PIN(153, "CVDD"), /* J16 */ + PINCTRL_PIN(154, "RTCXTALI"), /* J17 */ + PINCTRL_PIN(155, "XM"), /* J18 */ + PINCTRL_PIN(156, "YP"), /* J19 */ + PINCTRL_PIN(157, "YM"), /* J20 */ + /* Row K */ + PINCTRL_PIN(158, "AD[22]"), /* K1 */ + PINCTRL_PIN(159, "DA[20]"), /* K2 */ + PINCTRL_PIN(160, "AD[21]"), /* K3 */ + PINCTRL_PIN(161, "DA[19]"), /* K4 */ + PINCTRL_PIN(162, "RVDD"), /* K5 */ + PINCTRL_PIN(163, "GND"), /* K8 */ + PINCTRL_PIN(164, "GND"), /* K9 */ + PINCTRL_PIN(165, "GND"), /* K10 */ + PINCTRL_PIN(166, "GND"), /* K11 */ + PINCTRL_PIN(167, "GND"), /* K12 */ + PINCTRL_PIN(168, "GND"), /* K13 */ + PINCTRL_PIN(169, "CVDD"), /* K16 */ + PINCTRL_PIN(170, "SYM"), /* K17 */ + PINCTRL_PIN(171, "SYP"), /* K18 */ + PINCTRL_PIN(172, "SXM"), /* K19 */ + PINCTRL_PIN(173, "SXP"), /* K20 */ + /* Row L */ + PINCTRL_PIN(174, "DA[18]"), /* L1 */ + PINCTRL_PIN(175, "DA[17]"), /* L2 */ + PINCTRL_PIN(176, "DA[16]"), /* L3 */ + PINCTRL_PIN(177, "DA[15]"), /* L4 */ + PINCTRL_PIN(178, "GND"), /* L5 */ + PINCTRL_PIN(179, "GND"), /* L8 */ + PINCTRL_PIN(180, "GND"), /* L9 */ + PINCTRL_PIN(181, "GND"), /* L10 */ + PINCTRL_PIN(182, "GND"), /* L11 */ + PINCTRL_PIN(183, "GND"), /* L12 */ + PINCTRL_PIN(184, "GND"), /* L13 */ + PINCTRL_PIN(185, "CVDD"), /* L16 */ + PINCTRL_PIN(186, "COL[5]"), /* L17 */ + PINCTRL_PIN(187, "COL[7]"), /* L18 */ + PINCTRL_PIN(188, "RSTON"), /* L19 */ + PINCTRL_PIN(189, "PRSTN"), /* L20 */ + /* Row M */ + PINCTRL_PIN(190, "AD[7]"), /* M1 */ + PINCTRL_PIN(191, "DA[14]"), /* M2 */ + PINCTRL_PIN(192, "AD[6]"), /* M3 */ + PINCTRL_PIN(193, "AD[5]"), /* M4 */ + PINCTRL_PIN(194, "CVDD"), /* M5 */ + PINCTRL_PIN(195, "GND"), /* M8 */ + PINCTRL_PIN(196, "GND"), /* M9 */ + PINCTRL_PIN(197, "GND"), /* M10 */ + PINCTRL_PIN(198, "GND"), /* M11 */ + PINCTRL_PIN(199, "GND"), /* M12 */ + PINCTRL_PIN(200, "GND"), /* M13 */ + PINCTRL_PIN(201, "GND"), /* M16 */ + PINCTRL_PIN(202, "COL[4]"), /* M17 */ + PINCTRL_PIN(203, "COL[3]"), /* M18 */ + PINCTRL_PIN(204, "COL[6]"), /* M19 */ + PINCTRL_PIN(205, "CSN[0]"), /* M20 */ + /* Row N */ + PINCTRL_PIN(206, "DA[13]"), /* N1 */ + PINCTRL_PIN(207, "DA[12]"), /* N2 */ + PINCTRL_PIN(208, "DA[11]"), /* N3 */ + PINCTRL_PIN(209, "AD[3]"), /* N4 */ + PINCTRL_PIN(210, "CVDD"), /* N5 */ + PINCTRL_PIN(211, "CVDD"), /* N6 */ + PINCTRL_PIN(212, "GND"), /* N8 */ + PINCTRL_PIN(213, "GND"), /* N9 */ + PINCTRL_PIN(214, "GND"), /* N10 */ + PINCTRL_PIN(215, "GND"), /* N11 */ + PINCTRL_PIN(216, "GND"), /* N12 */ + PINCTRL_PIN(217, "GND"), /* N13 */ + PINCTRL_PIN(218, "GND"), /* N15 */ + PINCTRL_PIN(219, "GND"), /* N16 */ + PINCTRL_PIN(220, "XTALO"), /* N17 */ + PINCTRL_PIN(221, "COL[0]"), /* N18 */ + PINCTRL_PIN(222, "COL[1]"), /* N19 */ + PINCTRL_PIN(223, "COL[2]"), /* N20 */ + /* Row P */ + PINCTRL_PIN(224, "AD[4]"), /* P1 */ + PINCTRL_PIN(225, "DA[10]"), /* P2 */ + PINCTRL_PIN(226, "DA[9]"), /* P3 */ + PINCTRL_PIN(227, "BRIGHT"), /* P4 */ + PINCTRL_PIN(228, "RVDD"), /* P5 */ + PINCTRL_PIN(229, "RVDD"), /* P6 */ + PINCTRL_PIN(230, "RVDD"), /* P15 */ + PINCTRL_PIN(231, "RVDD"), /* P16 */ + PINCTRL_PIN(232, "XTALI"), /* P17 */ + PINCTRL_PIN(233, "PLL_VDD"), /* P18 */ + PINCTRL_PIN(234, "ROW[6]"), /* P19 */ + PINCTRL_PIN(235, "ROW[7]"), /* P20 */ + /* Row R */ + PINCTRL_PIN(236, "AD[2]"), /* R1 */ + PINCTRL_PIN(237, "AD[1]"), /* R2 */ + PINCTRL_PIN(238, "P[17]"), /* R3 */ + PINCTRL_PIN(239, "P[14]"), /* R4 */ + PINCTRL_PIN(240, "RVDD"), /* R5 */ + PINCTRL_PIN(241, "RVDD"), /* R6 */ + PINCTRL_PIN(242, "GND"), /* R7 */ + PINCTRL_PIN(243, "CVDD"), /* R8 */ + PINCTRL_PIN(244, "CVDD"), /* R13 */ + PINCTRL_PIN(245, "GND"), /* R14 */ + PINCTRL_PIN(246, "RVDD"), /* R15 */ + PINCTRL_PIN(247, "RVDD"), /* R16 */ + PINCTRL_PIN(248, "ROW[0]"), /* R17 */ + PINCTRL_PIN(249, "ROW[3]"), /* R18 */ + PINCTRL_PIN(250, "PLL_GND"), /* R19 */ + PINCTRL_PIN(251, "ROW[5]"), /* R20 */ + /* Row T */ + PINCTRL_PIN(252, "DA[8]"), /* T1 */ + PINCTRL_PIN(253, "BLANK"), /* T2 */ + PINCTRL_PIN(254, "P[13]"), /* T3 */ + PINCTRL_PIN(255, "SPCLK"), /* T4 */ + PINCTRL_PIN(256, "V_CSYNC"), /* T5 */ + PINCTRL_PIN(257, "DD[14]"), /* T6 */ + PINCTRL_PIN(258, "GND"), /* T7 */ + PINCTRL_PIN(259, "CVDD"), /* T8 */ + PINCTRL_PIN(260, "RVDD"), /* T9 */ + PINCTRL_PIN(261, "GND"), /* T10 */ + PINCTRL_PIN(262, "GND"), /* T11 */ + PINCTRL_PIN(263, "RVDD"), /* T12 */ + PINCTRL_PIN(264, "CVDD"), /* T13 */ + PINCTRL_PIN(265, "GND"), /* T14 */ + PINCTRL_PIN(266, "INT[0]"), /* T15 */ + PINCTRL_PIN(267, "USBM[1]"), /* T16 */ + PINCTRL_PIN(268, "RXD[0]"), /* T17 */ + PINCTRL_PIN(269, "TXD[2]"), /* T18 */ + PINCTRL_PIN(270, "ROW[2]"), /* T19 */ + PINCTRL_PIN(271, "ROW[4]"), /* T20 */ + /* Row U */ + PINCTRL_PIN(272, "AD[0]"), /* U1 */ + PINCTRL_PIN(273, "P[15]"), /* U2 */ + PINCTRL_PIN(274, "P[10]"), /* U3 */ + PINCTRL_PIN(275, "P[7]"), /* U4 */ + PINCTRL_PIN(276, "P[6]"), /* U5 */ + PINCTRL_PIN(277, "P[4]"), /* U6 */ + PINCTRL_PIN(278, "P[0]"), /* U7 */ + PINCTRL_PIN(279, "AD[13]"), /* U8 */ + PINCTRL_PIN(280, "DA[3]"), /* U9 */ + PINCTRL_PIN(281, "DA[0]"), /* U10 */ + PINCTRL_PIN(282, "DSRN"), /* U11 */ + PINCTRL_PIN(283, "BOOT[1]"), /* U12 */ + PINCTRL_PIN(284, "NC"), /* U13 */ + PINCTRL_PIN(285, "SSPRX1"), /* U14 */ + PINCTRL_PIN(286, "INT[1]"), /* U15 */ + PINCTRL_PIN(287, "PWMOUT"), /* U16 */ + PINCTRL_PIN(288, "USBM[0]"), /* U17 */ + PINCTRL_PIN(289, "RXD[1]"), /* U18 */ + PINCTRL_PIN(290, "TXD[1]"), /* U19 */ + PINCTRL_PIN(291, "ROW[1]"), /* U20 */ + /* Row V */ + PINCTRL_PIN(292, "P[16]"), /* V1 */ + PINCTRL_PIN(293, "P[11]"), /* V2 */ + PINCTRL_PIN(294, "P[8]"), /* V3 */ + PINCTRL_PIN(295, "DD[15]"), /* V4 */ + PINCTRL_PIN(296, "DD[13]"), /* V5 */ + PINCTRL_PIN(297, "P[1]"), /* V6 */ + PINCTRL_PIN(298, "AD[14]"), /* V7 */ + PINCTRL_PIN(299, "AD[12]"), /* V8 */ + PINCTRL_PIN(300, "DA[2]"), /* V9 */ + PINCTRL_PIN(301, "IDECS0N"), /* V10 */ + PINCTRL_PIN(302, "IDEDA[2]"), /* V11 */ + PINCTRL_PIN(303, "TDI"), /* V12 */ + PINCTRL_PIN(304, "GND"), /* V13 */ + PINCTRL_PIN(305, "ASYNC"), /* V14 */ + PINCTRL_PIN(306, "SSPTX1"), /* V15 */ + PINCTRL_PIN(307, "INT[2]"), /* V16 */ + PINCTRL_PIN(308, "RTSN"), /* V17 */ + PINCTRL_PIN(309, "USBP[0]"), /* V18 */ + PINCTRL_PIN(310, "CTSN"), /* V19 */ + PINCTRL_PIN(311, "TXD[0]"), /* V20 */ + /* Row W */ + PINCTRL_PIN(312, "P[12]"), /* W1 */ + PINCTRL_PIN(313, "P[9]"), /* W2 */ + PINCTRL_PIN(314, "DD[0]"), /* W3 */ + PINCTRL_PIN(315, "P[5]"), /* W4 */ + PINCTRL_PIN(316, "P[3]"), /* W5 */ + PINCTRL_PIN(317, "DA[7]"), /* W6 */ + PINCTRL_PIN(318, "DA[5]"), /* W7 */ + PINCTRL_PIN(319, "AD[11]"), /* W8 */ + PINCTRL_PIN(320, "AD[9]"), /* W9 */ + PINCTRL_PIN(321, "IDECS1N"), /* W10 */ + PINCTRL_PIN(322, "IDEDA[1]"), /* W11 */ + PINCTRL_PIN(323, "TCK"), /* W12 */ + PINCTRL_PIN(324, "TMS"), /* W13 */ + PINCTRL_PIN(325, "EECLK"), /* W14 */ + PINCTRL_PIN(326, "SCLK1"), /* W15 */ + PINCTRL_PIN(327, "GRLED"), /* W16 */ + PINCTRL_PIN(328, "INT[3]"), /* W17 */ + PINCTRL_PIN(329, "SLA[1]"), /* W18 */ + PINCTRL_PIN(330, "SLA[0]"), /* W19 */ + PINCTRL_PIN(331, "RXD[2]"), /* W20 */ + /* Row Y */ + PINCTRL_PIN(332, "HSYNC"), /* Y1 */ + PINCTRL_PIN(333, "DD[1]"), /* Y2 */ + PINCTRL_PIN(334, "DD[12]"), /* Y3 */ + PINCTRL_PIN(335, "P[2]"), /* Y4 */ + PINCTRL_PIN(336, "AD[15]"), /* Y5 */ + PINCTRL_PIN(337, "DA[6]"), /* Y6 */ + PINCTRL_PIN(338, "DA[4]"), /* Y7 */ + PINCTRL_PIN(339, "AD[10]"), /* Y8 */ + PINCTRL_PIN(340, "DA[1]"), /* Y9 */ + PINCTRL_PIN(341, "AD[8]"), /* Y10 */ + PINCTRL_PIN(342, "IDEDA[0]"), /* Y11 */ + PINCTRL_PIN(343, "DTRN"), /* Y12 */ + PINCTRL_PIN(344, "TDO"), /* Y13 */ + PINCTRL_PIN(345, "BOOT[0]"), /* Y14 */ + PINCTRL_PIN(346, "EEDAT"), /* Y15 */ + PINCTRL_PIN(347, "ASDO"), /* Y16 */ + PINCTRL_PIN(348, "SFRM1"), /* Y17 */ + PINCTRL_PIN(349, "RDLED"), /* Y18 */ + PINCTRL_PIN(350, "USBP[1]"), /* Y19 */ + PINCTRL_PIN(351, "ABITCLK"), /* Y20 */ +}; + +static const unsigned int ssp_ep9312_pins[] =3D { + 285, 306, 326, 348 +}; + +static const unsigned int ac97_ep9312_pins[] =3D { + 77, 95, 305, 347, 351 +}; + +static const unsigned int pwm_ep9312_pins[] =3D { 74 }; + +static const unsigned int gpio1a_ep9312_pins[] =3D { 74 }; + +static const unsigned int gpio2a_9312_pins[] =3D { + 234, 235, 248, 249, 251, 270, 271, 291 +}; + +static const unsigned int gpio3a_9312_pins[] =3D { + 186, 187, 202, 203, 204, 221, 222, 223 +}; + +static const unsigned int keypad_9312_pins[] =3D { + 186, 187, 202, 203, 204, 221, 222, 223, + 234, 235, 248, 249, 251, 270, 271, 291 +}; + +static const unsigned int gpio4a_9312_pins[] =3D { + 78, 301, 302, 321, 322, 342 +}; + +static const unsigned int gpio6a_9312_pins[] =3D { + 257, 295, 296, 334 +}; + +static const unsigned int gpio7a_9312_pins[] =3D { + 4, 24, 25, 45, 46, 66, 314, 333 +}; + +static const unsigned int ide_9312_pins[] =3D { + 78, 301, 302, 321, 322, 342, + 257, 295, 296, 334, + 4, 24, 25, 45, 46, 66, 314, 333 +}; + +static const struct ep93xx_pin_group ep9312_pin_groups[] =3D { + { + .name =3D "ssp", + .pins =3D ssp_ep9312_pins, + .num_pins =3D ARRAY_SIZE(ssp_ep9312_pins), + .mask =3D EP93XX_SYSCON_DEVCFG_I2SONSSP, + }, + { + .name =3D "i2s_on_ssp", + .pins =3D ssp_ep9312_pins, + .num_pins =3D ARRAY_SIZE(ssp_ep9312_pins), + .value =3D EP93XX_SYSCON_DEVCFG_I2SONSSP, + .mask =3D EP93XX_SYSCON_DEVCFG_I2SONSSP, + }, + { + .name =3D "pwm1", + .pins =3D pwm_ep9312_pins, + .num_pins =3D ARRAY_SIZE(pwm_ep9312_pins), + .value =3D EP93XX_SYSCON_DEVCFG_PONG, + .mask =3D EP93XX_SYSCON_DEVCFG_PONG, + }, + { + .name =3D "gpio1agrp", + .pins =3D gpio1a_ep9312_pins, + .num_pins =3D ARRAY_SIZE(gpio1a_ep9312_pins), + /* Conflict with PWM1 */ + .mask =3D EP93XX_SYSCON_DEVCFG_PONG, + }, + { + .name =3D "ac97", + .pins =3D ac97_ep9312_pins, + .num_pins =3D ARRAY_SIZE(ac97_ep9312_pins), + .mask =3D EP93XX_SYSCON_DEVCFG_I2SONAC97, + }, + { + .name =3D "i2s_on_ac97", + .pins =3D ac97_ep9312_pins, + .num_pins =3D ARRAY_SIZE(ac97_ep9312_pins), + .value =3D EP93XX_SYSCON_DEVCFG_I2SONAC97, + .mask =3D EP93XX_SYSCON_DEVCFG_I2SONAC97, + }, + { + .name =3D "rasteronsdram0grp", + .pins =3D raster_on_sdram0_pins, + .num_pins =3D ARRAY_SIZE(raster_on_sdram0_pins), + .mask =3D EP93XX_SYSCON_DEVCFG_RASONP3, + }, + { + .name =3D "rasteronsdram3grp", + .pins =3D raster_on_sdram3_pins, + .num_pins =3D ARRAY_SIZE(raster_on_sdram3_pins), + .value =3D EP93XX_SYSCON_DEVCFG_RASONP3, + .mask =3D EP93XX_SYSCON_DEVCFG_RASONP3, + }, + { + .name =3D "gpio2agrp", + .pins =3D gpio2a_9312_pins, + .num_pins =3D ARRAY_SIZE(gpio2a_9312_pins), + .value =3D EP93XX_SYSCON_DEVCFG_GONK, + .mask =3D EP93XX_SYSCON_DEVCFG_GONK, + }, + { + .name =3D "gpio3agrp", + .pins =3D gpio3a_9312_pins, + .num_pins =3D ARRAY_SIZE(gpio3a_9312_pins), + .value =3D EP93XX_SYSCON_DEVCFG_GONK, + .mask =3D EP93XX_SYSCON_DEVCFG_GONK, + }, + { + .name =3D "keypadgrp", + .pins =3D keypad_9307_pins, + .num_pins =3D ARRAY_SIZE(keypad_9307_pins), + .mask =3D EP93XX_SYSCON_DEVCFG_GONK, + }, + { + .name =3D "gpio4agrp", + .pins =3D gpio4a_9312_pins, + .num_pins =3D ARRAY_SIZE(gpio4a_9312_pins), + .value =3D EP93XX_SYSCON_DEVCFG_EONIDE, + .mask =3D EP93XX_SYSCON_DEVCFG_EONIDE, + }, + { + .name =3D "gpio6agrp", + .pins =3D gpio6a_9312_pins, + .num_pins =3D ARRAY_SIZE(gpio6a_9312_pins), + .value =3D EP93XX_SYSCON_DEVCFG_GONIDE, + .mask =3D EP93XX_SYSCON_DEVCFG_GONIDE, + }, + { + .name =3D "gpio7agrp", + .pins =3D gpio7a_9312_pins, + .num_pins =3D ARRAY_SIZE(gpio7a_9312_pins), + .value =3D EP93XX_SYSCON_DEVCFG_HONIDE, + .mask =3D EP93XX_SYSCON_DEVCFG_HONIDE, + }, + { + .name =3D "idegrp", + .pins =3D ide_9312_pins, + .num_pins =3D ARRAY_SIZE(ide_9312_pins), + .mask =3D EP93XX_SYSCON_DEVCFG_EONIDE | EP93XX_SYSCON_DEVCFG_GONIDE | + EP93XX_SYSCON_DEVCFG_HONIDE, + }, +}; + +static int ep93xx_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct ep93xx_pmx *pmx =3D pinctrl_dev_get_drvdata(pctldev); + + switch (pmx->model) { + case EP93XX_9301_PINCTRL: + return ARRAY_SIZE(ep9301_pin_groups); + case EP93XX_9307_PINCTRL: + return ARRAY_SIZE(ep9307_pin_groups); + case EP93XX_9312_PINCTRL: + return ARRAY_SIZE(ep9312_pin_groups); + } + + return 0; +} + +static const char *ep93xx_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct ep93xx_pmx *pmx =3D pinctrl_dev_get_drvdata(pctldev); + + switch (pmx->model) { + case EP93XX_9301_PINCTRL: + return ep9301_pin_groups[selector].name; + case EP93XX_9307_PINCTRL: + return ep9307_pin_groups[selector].name; + case EP93XX_9312_PINCTRL: + return ep9312_pin_groups[selector].name; + } + + return NULL; +} + +static int ep93xx_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, + const unsigned int **pins, + unsigned int *num_pins) +{ + struct ep93xx_pmx *pmx =3D pinctrl_dev_get_drvdata(pctldev); + + switch (pmx->model) { + case EP93XX_9301_PINCTRL: + *pins =3D ep9301_pin_groups[selector].pins; + *num_pins =3D ep9301_pin_groups[selector].num_pins; + break; + case EP93XX_9307_PINCTRL: + *pins =3D ep9307_pin_groups[selector].pins; + *num_pins =3D ep9307_pin_groups[selector].num_pins; + break; + case EP93XX_9312_PINCTRL: + *pins =3D ep9312_pin_groups[selector].pins; + *num_pins =3D ep9312_pin_groups[selector].num_pins; + break; + } + + return 0; +} + +static void ep93xx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_fi= le *s, + unsigned int offset) +{ + seq_printf(s, " " DRIVER_NAME); +} + +static const struct pinctrl_ops ep93xx_pctrl_ops =3D { + .get_groups_count =3D ep93xx_get_groups_count, + .get_group_name =3D ep93xx_get_group_name, + .get_group_pins =3D ep93xx_get_group_pins, + .pin_dbg_show =3D ep93xx_pin_dbg_show, + .dt_node_to_map =3D pinconf_generic_dt_node_to_map_all, + .dt_free_map =3D pinconf_generic_dt_free_map, +}; + +/** + * struct ep93xx_pmx_func - describes ep93xx pinmux functions + * @name: the name of this specific function + * @groups: corresponding pin groups + */ +struct ep93xx_pmx_func { + const char *name; + const char * const *groups; + const unsigned int num_groups; +}; + +static const char * const spigrps[] =3D { "ssp" }; +static const char * const ac97grps[] =3D { "ac97" }; +static const char * const i2sgrps[] =3D { "i2s_on_ssp", "i2s_on_ac97" }; +static const char * const pwm1grps[] =3D { "pwm1" }; +static const char * const gpio1grps[] =3D { "gpio1agrp" }; +static const char * const gpio2grps[] =3D { "gpio2agrp" }; +static const char * const gpio3grps[] =3D { "gpio3agrp" }; +static const char * const gpio4grps[] =3D { "gpio4agrp" }; +static const char * const gpio6grps[] =3D { "gpio6agrp" }; +static const char * const gpio7grps[] =3D { "gpio7agrp" }; +static const char * const rastergrps[] =3D { "rasteronsdram0grp", "rastero= nsdram3grp"}; +static const char * const keypadgrps[] =3D { "keypadgrp"}; +static const char * const idegrps[] =3D { "idegrp"}; + + +static const struct ep93xx_pmx_func ep93xx_pmx_functions[] =3D { + { + .name =3D "spi", + .groups =3D spigrps, + .num_groups =3D ARRAY_SIZE(spigrps), + }, + { + .name =3D "ac97", + .groups =3D ac97grps, + .num_groups =3D ARRAY_SIZE(ac97grps), + }, + { + .name =3D "i2s", + .groups =3D i2sgrps, + .num_groups =3D ARRAY_SIZE(i2sgrps), + }, + { + .name =3D "pwm", + .groups =3D pwm1grps, + .num_groups =3D ARRAY_SIZE(pwm1grps), + }, + { + .name =3D "keypad", + .groups =3D keypadgrps, + .num_groups =3D ARRAY_SIZE(keypadgrps), + }, + { + .name =3D "pata", + .groups =3D idegrps, + .num_groups =3D ARRAY_SIZE(idegrps), + }, + { + .name =3D "lcd", + .groups =3D rastergrps, + .num_groups =3D ARRAY_SIZE(rastergrps), + }, + { + .name =3D "gpio1", + .groups =3D gpio1grps, + .num_groups =3D ARRAY_SIZE(gpio1grps), + }, + { + .name =3D "gpio2", + .groups =3D gpio2grps, + .num_groups =3D ARRAY_SIZE(gpio2grps), + }, + { + .name =3D "gpio3", + .groups =3D gpio3grps, + .num_groups =3D ARRAY_SIZE(gpio3grps), + }, + { + .name =3D "gpio4", + .groups =3D gpio4grps, + .num_groups =3D ARRAY_SIZE(gpio4grps), + }, + { + .name =3D "gpio6", + .groups =3D gpio6grps, + .num_groups =3D ARRAY_SIZE(gpio6grps), + }, + { + .name =3D "gpio7", + .groups =3D gpio7grps, + .num_groups =3D ARRAY_SIZE(gpio7grps), + }, +}; + +static int ep93xx_pmx_set_mux(struct pinctrl_dev *pctldev, + unsigned int selector, + unsigned int group) +{ + struct ep93xx_pmx *pmx; + const struct ep93xx_pmx_func *func; + const struct ep93xx_pin_group *grp; + u32 before, after, expected; + unsigned long tmp; + int i; + + pmx =3D pinctrl_dev_get_drvdata(pctldev); + + func =3D &ep93xx_pmx_functions[selector]; + + switch (pmx->model) { + case EP93XX_9301_PINCTRL: + grp =3D &ep9301_pin_groups[group]; + break; + case EP93XX_9307_PINCTRL: + grp =3D &ep9307_pin_groups[group]; + break; + case EP93XX_9312_PINCTRL: + grp =3D &ep9312_pin_groups[group]; + break; + } + + dev_dbg(pmx->dev, + "ACTIVATE function \"%s\" with group \"%s\" (mask=3D0x%x, value=3D0x%x)\= n", + func->name, grp->name, grp->mask, grp->value); + + regmap_read(pmx->map, EP93XX_SYSCON_DEVCFG, &before); + ep93xx_swlocked_update_bits(EP93XX_SYSCON_DEVCFG, + grp->mask, grp->value); + regmap_read(pmx->map, EP93XX_SYSCON_DEVCFG, &after); + + dev_dbg(pmx->dev, + "before=3D0x%x, after=3D0x%x, mask=3D0x%lx\n", + before, after, PADS_MASK); + + /* Which bits changed */ + before &=3D PADS_MASK; + after &=3D PADS_MASK; + expected =3D before & ~grp->mask; + expected |=3D grp->value; + expected &=3D PADS_MASK; + + /* Print changed states */ + tmp =3D expected ^ after; + for_each_set_bit(i, &tmp, PADS_MAXBIT) { + bool enabled =3D expected & BIT(i); + + dev_err(pmx->dev, + "pin group %s could not be %s: probably a hardware limitation\n", + ep93xx_padgroups[i], enabled ? "enabled" : "disabled"); + dev_err(pmx->dev, + "DeviceCfg before: %08x, after %08x, expected %08x\n", + before, after, expected); + } + + return tmp ? -EINVAL : 0; +}; + +static int ep93xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(ep93xx_pmx_functions); +} + +static const char *ep93xx_pmx_get_func_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return ep93xx_pmx_functions[selector].name; +} + +static int ep93xx_pmx_get_groups(struct pinctrl_dev *pctldev, + unsigned int selector, + const char * const **groups, + unsigned int * const num_groups) +{ + *groups =3D ep93xx_pmx_functions[selector].groups; + *num_groups =3D ep93xx_pmx_functions[selector].num_groups; + return 0; +} + +static const struct pinmux_ops ep93xx_pmx_ops =3D { + .get_functions_count =3D ep93xx_pmx_get_funcs_count, + .get_function_name =3D ep93xx_pmx_get_func_name, + .get_function_groups =3D ep93xx_pmx_get_groups, + .set_mux =3D ep93xx_pmx_set_mux, +}; + +static struct pinctrl_desc ep93xx_pmx_desc =3D { + .name =3D DRIVER_NAME, + .pctlops =3D &ep93xx_pctrl_ops, + .pmxops =3D &ep93xx_pmx_ops, + .owner =3D THIS_MODULE, +}; + +static const struct of_device_id ep93xx_pinctrl_of_ids[] =3D { + { .compatible =3D "cirrus,ep9301-pinctrl", .data =3D (void *)EP93XX_9301_= PINCTRL}, + { .compatible =3D "cirrus,ep9307-pinctrl", .data =3D (void *)EP93XX_9307_= PINCTRL}, + { .compatible =3D "cirrus,ep9312-pinctrl", .data =3D (void *)EP93XX_9312_= PINCTRL}, + {}, +}; + +static int ep93xx_pmx_probe(struct platform_device *pdev) +{ + const struct of_device_id *match =3D of_match_node(ep93xx_pinctrl_of_ids,= pdev->dev.of_node); + struct ep93xx_pmx *pmx; + struct regmap *map; + struct device *dev =3D &pdev->dev; + struct device *parent; + + /* Create state holders etc for this driver */ + pmx =3D devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); + if (!pmx) + return -ENOMEM; + + pmx->dev =3D &pdev->dev; + parent =3D dev->parent; + if (!parent) { + dev_err(dev, "no parent to pin controller\n"); + return -ENODEV; + } + + map =3D syscon_node_to_regmap(parent->of_node); + if (IS_ERR(map)) { + dev_err(dev, "no syscon regmap\n"); + return PTR_ERR(map); + } + pmx->map =3D map; + + pmx->model =3D (int) match->data; + switch (pmx->model) { + case EP93XX_9301_PINCTRL: + ep93xx_pmx_desc.pins =3D ep9301_pins; + ep93xx_pmx_desc.npins =3D ARRAY_SIZE(ep9301_pins); + dev_info(dev, "detected 9301/9302 chip variant\n"); + break; + case EP93XX_9307_PINCTRL: + ep93xx_pmx_desc.pins =3D ep9307_pins; + ep93xx_pmx_desc.npins =3D ARRAY_SIZE(ep9307_pins); + dev_info(dev, "detected 9307 chip variant\n"); + break; + case EP93XX_9312_PINCTRL: + ep93xx_pmx_desc.pins =3D ep9312_pins; + ep93xx_pmx_desc.npins =3D ARRAY_SIZE(ep9312_pins); + dev_info(dev, "detected 9312/9315 chip variant\n"); + break; + } + + pmx->pctl =3D devm_pinctrl_register(dev, &ep93xx_pmx_desc, pmx); + if (IS_ERR(pmx->pctl)) { + dev_err(dev, "could not register pinmux driver\n"); + return PTR_ERR(pmx->pctl); + } + + dev_info(dev, "initialized ep93xx pin control driver\n"); + + return 0; +}; + +static struct platform_driver ep93xx_pmx_driver =3D { + .driver =3D { + .name =3D DRIVER_NAME, + .of_match_table =3D ep93xx_pinctrl_of_ids, + }, + .probe =3D ep93xx_pmx_probe, +}; + +static int __init ep93xx_pmx_init(void) +{ + return platform_driver_register(&ep93xx_pmx_driver); +} +arch_initcall(ep93xx_pmx_init); --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2058DC7EE2E for ; Thu, 1 Jun 2023 05:37:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230110AbjFAFh0 (ORCPT ); Thu, 1 Jun 2023 01:37:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46908 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231221AbjFAFhR (ORCPT ); Thu, 1 Jun 2023 01:37:17 -0400 Received: from forward101c.mail.yandex.net (forward101c.mail.yandex.net [178.154.239.212]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 284561BE; Wed, 31 May 2023 22:36:58 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net [IPv6:2a02:6b8:c14:c83:0:640:84f9:0]) by forward101c.mail.yandex.net (Yandex) with ESMTP id CA60F600FB; Thu, 1 Jun 2023 08:36:55 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id OaGNfZvWv8c0-ljXORRHt; Thu, 01 Jun 2023 08:36:55 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1685597815; bh=zIJEhcZ91Oaqa6Xmm24KHPdM/EoDuW4yx6hKsFtUgXw=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=idlakvnNspTx/hhaf1scWcevr+yryNuzxvfQEdwBri6tBVlLw8q+i9LEJ1rFbfXvP VWI3pcacmkyMJkSqi/yJkfrLllDi5wFiXPRLIMULIdz65wwmZs9VcAPSI4UFrQwtci G1/yTh1J1qbmJd19/0fmpteYQn9kNbb3rkCQXuq8= Authentication-Results: mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Nikita Shubin Cc: Michael Peters , Kris Bahnsen , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 04/43] dt-bindings: clock: Add Cirrus EP93xx Date: Thu, 1 Jun 2023 08:33:55 +0300 Message-Id: <20230601053546.9574-5-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds device tree bindings for the Cirrus Logic EP93xx clock block used in these SoCs. Signed-off-by: Nikita Shubin --- Notes: v0 -> v1: =20 - it's now a clock controller .../bindings/clock/cirrus,ep9301.yaml | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/cirrus,ep9301.y= aml diff --git a/Documentation/devicetree/bindings/clock/cirrus,ep9301.yaml b/D= ocumentation/devicetree/bindings/clock/cirrus,ep9301.yaml new file mode 100644 index 000000000000..4f9e0d483698 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/cirrus,ep9301.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/cirrus,ep9301.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic ep93xx SoC's clock controller + +maintainers: + - Nikita Shubin + - Alexander Sverdlin + +description: | + Cirrus Logic EP93XX SoC clocks driver bindings. The clock + controller node must be defined as a child node of the ep93xx + system controller node. + + See also: + - dt-bindings/clock/cirrus,ep93xx-clock.h + +properties: + compatible: + oneOf: + - const: cirrus,ep9301-clk + - items: + - enum: + - cirrus,ep9302-clk + - cirrus,ep9307-clk + - cirrus,ep9312-clk + - cirrus,ep9315-clk + - const: cirrus,ep9301-clk + + "#clock-cells": + const: 1 + + clocks: + description: List of clock specifiers which are external input + clocks to the given clock controller. + items: + - description: reference clock + +required: + - compatible + - "#clock-cells" + - clocks + +additionalProperties: false + +examples: + - | + clocks { + xtali: oscillator { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <14745600>; + }; + }; + + clock-controller { + #clock-cells =3D <1>; + compatible =3D "cirrus,ep9301-clk"; + clocks =3D <&xtali>; + }; +... --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49706C77B7E for ; Mon, 24 Apr 2023 09:43:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231166AbjDXJnZ (ORCPT ); Mon, 24 Apr 2023 05:43:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39716 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229522AbjDXJnX (ORCPT ); Mon, 24 Apr 2023 05:43:23 -0400 Received: from forward500b.mail.yandex.net (forward500b.mail.yandex.net [178.154.239.144]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7BF6E1BE6; Mon, 24 Apr 2023 02:43:22 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net [IPv6:2a02:6b8:c12:261e:0:640:2e3d:0]) by forward500b.mail.yandex.net (Yandex) with ESMTP id F26065EB6B; Mon, 24 Apr 2023 12:35:39 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id JZBb1pbWwKo0-Qivh3H9j; Mon, 24 Apr 2023 12:35:39 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1682328939; bh=hEtxBdyI2HO9wKRIi0w86SPEAP4jiwD5d234QJI8KJM=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=Pg41pce8J2/HqfIkzznYYKb27LAhjQIPZtMdsv3D+qt7YuC0/8oxQoFXvEn0EqM3W UN8oZZhVzsrAJzCSlh+T+xFIHBcbrZa3nxmvcjspMYDf5nBw9oqWdbsBsCPgbaFX80 6qTLA2T8nbT1YDP1JQXfH+GC6cneDlP2iMEdrdq8= Authentication-Results: mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Hartley Sweeten , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 05/43] dt-bindings: timers: add DT bindings for Cirrus EP93xx Date: Mon, 24 Apr 2023 15:34:21 +0300 Message-Id: <20230424123522.18302-6-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds device tree bindings for the Cirrus Logic EP93xx timer block used in these SoCs. Signed-off-by: Nikita Shubin Reviewed-by: Krzysztof Kozlowski --- Notes: Arnd Bergmann: - replaced ep93xx wildcard with ep9301 .../bindings/timer/cirrus,ep93xx-timer.yaml | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/cirrus,ep93xx-t= imer.yaml diff --git a/Documentation/devicetree/bindings/timer/cirrus,ep93xx-timer.ya= ml b/Documentation/devicetree/bindings/timer/cirrus,ep93xx-timer.yaml new file mode 100644 index 000000000000..ce8b8a5cb90a --- /dev/null +++ b/Documentation/devicetree/bindings/timer/cirrus,ep93xx-timer.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/cirrus,ep93xx-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic EP93xx timers bindings + +maintainers: + - Hartley Sweeten + - Alexander Sverdlin + +properties: + compatible: + const: cirrus,ep9301-timer + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + timer@80810000 { + compatible =3D "cirrus,ep9301-timer"; + reg =3D <0x80810000 0x100>; + interrupt-parent =3D <&vic1>; + interrupts =3D <19>; + }; +... --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB5CCC7EE23 for ; Thu, 1 Jun 2023 05:37:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231363AbjFAFhm (ORCPT ); Thu, 1 Jun 2023 01:37:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46908 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231219AbjFAFh1 (ORCPT ); Thu, 1 Jun 2023 01:37:27 -0400 Received: from forward101c.mail.yandex.net (forward101c.mail.yandex.net [IPv6:2a02:6b8:c03:500:1:45:d181:d101]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 04FFEE4C for ; Wed, 31 May 2023 22:37:00 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net [IPv6:2a02:6b8:c14:c83:0:640:84f9:0]) by forward101c.mail.yandex.net (Yandex) with ESMTP id 1344D60035; Thu, 1 Jun 2023 08:36:58 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id OaGNfZvWv8c0-1Ei1IgtB; Thu, 01 Jun 2023 08:36:57 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1685597817; bh=QQ3F5MayytDWeiENHmf+SnmETDC1ZfItgSNEnRIRE1U=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=CAs37a6domuEeR1/cdZc5lqxJC2YeiG2e374NZjPy2DH2UbsKlpOubiT3gdywgJ46 +ZJ3RpM+FHo50Xj9PVBkySqae2KxxpDuqmRwpuRf7rc89wSLqhUBYaaW5zWhkkVz7f FlUpU2QlqlvRSEY6tHnT2qagInS1MieunNhRmc5I= Authentication-Results: mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij , Michael Turquette , Stephen Boyd Cc: Nikita Shubin , Michael Peters , Kris Bahnsen , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v1 05/43] clk: ep93xx: add DT support for Cirrus EP93xx Date: Thu, 1 Jun 2023 08:33:56 +0300 Message-Id: <20230601053546.9574-6-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This is a rewrite of EP93xx timer driver in arch/arm/mach-ep93xx/clock.c trying to do everything the device tree way: - convert to syscon driver - provide clock acces via of Co-developed-by: Alexander Sverdlin Signed-off-by: Alexander Sverdlin Signed-off-by: Nikita Shubin --- Notes: v0 -> v1: =20 Stephen Boyd: - dropped clkdev - Kconfig sorted - make lock name uniq - make divisors const - u64 rate and drop cast for calc_pll_rate - use parent_data - locking all the time - reworked parents in muxes - using clk_hw_register everywhere - inlined defines =20 rfc -> v0: =20 Linus Walleij: - renamed all __underscore =20 Alexander Sverdlin: - "Logick" -> "Logic" =20 Changes by Alexander Sverdlin: - remove pr_info - DIV_ROUND_UP_ULL -> DIV_ROUND_CLOSEST - fix zeroing bitfield in ep93xx_div_set_rate - add sanity check for EP93XX_SYSCON_CHIPID_ID - use bit index for DMA clock's - ep93xx_clk_register_gate() takes bit index, not mask - remove redundant define - use DIV_ROUND_CLOSEST() everywhere to achieve frequencies closer to t= hose requested - Add the forgotten configuration from the deleted arch/arm/mach-ep93xx/core.c drivers/clk/Kconfig | 8 + drivers/clk/Makefile | 1 + drivers/clk/clk-ep93xx.c | 850 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 859 insertions(+) create mode 100644 drivers/clk/clk-ep93xx.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 1eef05bb1f99..acd28167b46c 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -218,6 +218,14 @@ config COMMON_CLK_EN7523 This driver provides the fixed clocks and gates present on Airoha ARM silicon. =20 +config COMMON_CLK_EP93XX + bool "Clock driver for Cirrus Logic ep93xx SoC" + depends on ARCH_EP93XX || COMPILE_TEST + select MFD_SYSCON + select REGMAP + help + This driver supports the SoC clocks on the Cirrus Logic ep93xx. + config COMMON_CLK_FSL_FLEXSPI tristate "Clock driver for FlexSPI on Layerscape SoCs" depends on ARCH_LAYERSCAPE || COMPILE_TEST diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index e3ca0d058a25..deec25ffd004 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE706) +=3D clk-cdce706.o obj-$(CONFIG_COMMON_CLK_CDCE925) +=3D clk-cdce925.o obj-$(CONFIG_ARCH_CLPS711X) +=3D clk-clps711x.o obj-$(CONFIG_COMMON_CLK_CS2000_CP) +=3D clk-cs2000-cp.o +obj-$(CONFIG_COMMON_CLK_EP93XX) +=3D clk-ep93xx.o obj-$(CONFIG_ARCH_SPARX5) +=3D clk-sparx5.o obj-$(CONFIG_COMMON_CLK_EN7523) +=3D clk-en7523.o obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) +=3D clk-fixed-mmio.o diff --git a/drivers/clk/clk-ep93xx.c b/drivers/clk/clk-ep93xx.c new file mode 100644 index 000000000000..e83571f83b5a --- /dev/null +++ b/drivers/clk/clk-ep93xx.c @@ -0,0 +1,850 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Clock control for Cirrus EP93xx chips. + * Copyright (C) 2021 Nikita Shubin + * + * Based on a rewrite of arch/arm/mach-ep93xx/clock.c: + * Copyright (C) 2006 Lennert Buytenhek + */ +#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define EP93XX_EXT_CLK_RATE 14745600 +#define EP93XX_EXT_RTC_RATE 32768 + +#define EP93XX_SYSCON_POWER_STATE 0x00 +#define EP93XX_SYSCON_PWRCNT 0x04 +#define EP93XX_SYSCON_PWRCNT_UARTBAUD BIT(29) +#define EP93XX_SYSCON_PWRCNT_USH_EN 28 +#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 27 +#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 26 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 25 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 24 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 23 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 22 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 21 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 20 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 19 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 18 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 17 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 16 +#define EP93XX_SYSCON_CLKSET1 0x20 +#define EP93XX_SYSCON_CLKSET1_NBYP1 BIT(23) +#define EP93XX_SYSCON_CLKSET2 0x24 +#define EP93XX_SYSCON_CLKSET2_NBYP2 BIT(19) +#define EP93XX_SYSCON_CLKSET2_PLL2_EN BIT(18) +#define EP93XX_SYSCON_DEVCFG 0x80 +#define EP93XX_SYSCON_DEVCFG_U3EN 24 +#define EP93XX_SYSCON_DEVCFG_U2EN 20 +#define EP93XX_SYSCON_DEVCFG_U1EN 18 +#define EP93XX_SYSCON_VIDCLKDIV 0x84 +#define EP93XX_SYSCON_CLKDIV_ENABLE 15 +#define EP93XX_SYSCON_CLKDIV_ESEL BIT(14) +#define EP93XX_SYSCON_CLKDIV_PSEL BIT(13) +#define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8 +#define EP93XX_SYSCON_I2SCLKDIV 0x8c +#define EP93XX_SYSCON_I2SCLKDIV_SENA 31 +#define EP93XX_SYSCON_I2SCLKDIV_ORIDE BIT(29) +#define EP93XX_SYSCON_I2SCLKDIV_SPOL BIT(19) +#define EP93XX_I2SCLKDIV_SDIV (1 << 16) +#define EP93XX_I2SCLKDIV_LRDIV32 (0 << 17) +#define EP93XX_I2SCLKDIV_LRDIV64 (1 << 17) +#define EP93XX_I2SCLKDIV_LRDIV128 (2 << 17) +#define EP93XX_I2SCLKDIV_LRDIV_MASK (3 << 17) +#define EP93XX_SYSCON_KEYTCHCLKDIV 0x90 +#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN 31 +#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV 16 +#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN 15 +#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV 0 +#define EP93XX_SYSCON_CHIPID 0x94 +#define EP93XX_SYSCON_CHIPID_ID 0x9213 + +static DEFINE_SPINLOCK(ep93xx_clk_lock); +static struct regmap *ep93xx_map; +#define ep93xx_regmap_read(reg, val) regmap_read(ep93xx_map, reg, val) +#define ep93xx_regmap_write(reg, val) regmap_write(ep93xx_map, reg, val) + +/* Keeps track of all clocks */ +static struct clk_hw_onecell_data *ep93xx_clk_data; + +static const char fclk_divisors[] =3D { 1, 2, 4, 8, 16, 1, 1, 1 }; +static const char hclk_divisors[] =3D { 1, 2, 4, 5, 6, 8, 16, 32 }; +static const char pclk_divisors[] =3D { 1, 2, 4, 8 }; + +static const char adc_divisors[] =3D { 16, 4 }; +static const char sclk_divisors[] =3D { 2, 4 }; +static const char lrclk_divisors[] =3D { 32, 64, 128 }; + +#define EP_PARENT(NAME) { .name =3D NAME, .fw_name =3D NAME } + +static const struct clk_parent_data ep93xx_clk_parents[] =3D { + EP_PARENT("xtali"), + EP_PARENT("pll1"), + EP_PARENT("pll2") +}; + +/* + * PLL rate =3D 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^= PS + */ +static unsigned long calc_pll_rate(u64 rate, u32 config_word) +{ + int i; + + rate *=3D ((config_word >> 11) & 0x1f) + 1; /* X1FBD */ + rate *=3D ((config_word >> 5) & 0x3f) + 1; /* X2FBD */ + do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */ + for (i =3D 0; i < ((config_word >> 16) & 3); i++) /* PS */ + rate >>=3D 1; + + return rate; +} + +struct clk_psc { + struct clk_hw hw; + unsigned int reg; + u8 bit_idx; + u32 mask; + u8 shift; + u8 width; + const char *div; + u8 num_div; + spinlock_t *lock; + bool nolock; +}; + +#define to_clk_psc(_hw) container_of(_hw, struct clk_psc, hw) + +static int ep93xx_clk_is_enabled(struct clk_hw *hw) +{ + struct clk_psc *psc =3D to_clk_psc(hw); + u32 val; + + ep93xx_regmap_read(psc->reg, &val); + + return (val & BIT(psc->bit_idx)) ? 1 : 0; +} + +static int ep93xx_clk_enable(struct clk_hw *hw) +{ + struct clk_psc *psc =3D to_clk_psc(hw); + unsigned long flags =3D 0; + u32 val; + + spin_lock_irqsave(psc->lock, flags); + + ep93xx_regmap_read(psc->reg, &val); + val |=3D BIT(psc->bit_idx); + + if (psc->nolock) + ep93xx_regmap_write(psc->reg, val); + else + ep93xx_syscon_swlocked_write(val, psc->reg); + + spin_unlock_irqrestore(psc->lock, flags); + + return 0; +} + +static void ep93xx_clk_disable(struct clk_hw *hw) +{ + struct clk_psc *psc =3D to_clk_psc(hw); + unsigned long flags =3D 0; + u32 val; + + spin_lock_irqsave(psc->lock, flags); + + ep93xx_regmap_read(psc->reg, &val); + val &=3D ~BIT(psc->bit_idx); + + if (psc->nolock) + ep93xx_regmap_write(psc->reg, val); + else + ep93xx_syscon_swlocked_write(val, psc->reg); + + spin_unlock_irqrestore(psc->lock, flags); +} + +static const struct clk_ops clk_ep93xx_gate_ops =3D { + .enable =3D ep93xx_clk_enable, + .disable =3D ep93xx_clk_disable, + .is_enabled =3D ep93xx_clk_is_enabled, +}; + +static struct clk_hw *ep93xx_clk_register_gate(const char *name, + const char *parent_name, + unsigned long flags, + unsigned int reg, + u8 bit_idx, + bool nolock) +{ + struct clk_parent_data parent_data =3D { }; + struct clk_init_data init =3D { }; + struct clk_psc *psc; + int ret; + + psc =3D kzalloc(sizeof(*psc), GFP_KERNEL); + if (!psc) + return ERR_PTR(-ENOMEM); + + init.name =3D name; + init.ops =3D &clk_ep93xx_gate_ops; + init.flags =3D flags; + + parent_data.fw_name =3D parent_name; + parent_data.name =3D parent_name; + init.parent_data =3D &parent_data; + init.num_parents =3D 1; + + psc->reg =3D reg; + psc->bit_idx =3D bit_idx; + psc->hw.init =3D &init; + psc->lock =3D &ep93xx_clk_lock; + psc->nolock =3D nolock; + + ret =3D clk_hw_register(NULL, &psc->hw); + if (ret) { + kfree(psc); + return ERR_PTR(ret); + } + + return &psc->hw; +} + +static u8 ep93xx_mux_get_parent(struct clk_hw *hw) +{ + struct clk_psc *psc =3D to_clk_psc(hw); + u32 val; + + ep93xx_regmap_read(psc->reg, &val); + if (!(val & EP93XX_SYSCON_CLKDIV_ESEL)) + return 0; + + if (!(val & EP93XX_SYSCON_CLKDIV_PSEL)) + return 1; + + return 2; +} + +static int ep93xx_mux_set_parent_lock(struct clk_hw *hw, u8 index) +{ + struct clk_psc *psc =3D to_clk_psc(hw); + unsigned long flags =3D 0; + u32 val; + + if (index >=3D ARRAY_SIZE(ep93xx_clk_parents)) + return -EINVAL; + + if (psc->lock) + spin_lock_irqsave(psc->lock, flags); + + ep93xx_regmap_read(psc->reg, &val); + val &=3D ~(EP93XX_SYSCON_CLKDIV_ESEL | EP93XX_SYSCON_CLKDIV_PSEL); + + if (index !=3D 0) { + val |=3D EP93XX_SYSCON_CLKDIV_ESEL; + val |=3D (index - 1) ? EP93XX_SYSCON_CLKDIV_PSEL : 0; + } + + ep93xx_syscon_swlocked_write(val, psc->reg); + + if (psc->lock) + spin_unlock_irqrestore(psc->lock, flags); + + return 0; +} + +static bool is_best(unsigned long rate, unsigned long now, + unsigned long best) +{ + return abs(rate - now) < abs(rate - best); +} + +static int ep93xx_mux_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + unsigned long rate =3D req->rate; + struct clk_hw *parent_best =3D NULL; + unsigned long parent_rate; + unsigned long best_rate =3D 0, actual_rate, mclk_rate; + unsigned long parent_rate_best; + int div, pdiv; + int i; + + /* + * Try the two pll's and the external clock + * Because the valid predividers are 2, 2.5 and 3, we multiply + * all the clocks by 2 to avoid floating point math. + * + * This is based on the algorithm in the ep93xx raster guide: + * http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf + * + */ + for (i =3D 0; i < clk_hw_get_num_parents(hw); i++) { + struct clk_hw *parent =3D clk_hw_get_parent_by_index(hw, i); + + parent_rate =3D clk_hw_get_rate(parent); + mclk_rate =3D parent_rate * 2; + + /* Try each predivider value */ + for (pdiv =3D 4; pdiv <=3D 6; pdiv++) { + div =3D DIV_ROUND_CLOSEST(mclk_rate, rate * pdiv); + if (div < 1 || div > 127) + continue; + + actual_rate =3D DIV_ROUND_CLOSEST(mclk_rate, pdiv * div); + + if (is_best(rate, actual_rate, best_rate)) { + best_rate =3D actual_rate; + parent_rate_best =3D parent_rate; + parent_best =3D parent; + } + } + } + + if (!parent_best) + return -EINVAL; + + req->best_parent_rate =3D parent_rate_best; + req->best_parent_hw =3D parent_best; + req->rate =3D best_rate; + + return 0; +} + +static unsigned long ep93xx_ddiv_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_psc *psc =3D to_clk_psc(hw); + unsigned long rate =3D 0; + u32 val; + int pdiv, div; + + ep93xx_regmap_read(psc->reg, &val); + pdiv =3D ((val >> EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) & 0x03); + div =3D val & 0x7f; + if (div > 0) + rate =3D DIV_ROUND_CLOSEST(parent_rate * 2, (pdiv + 3) * div); + + return rate; +} + +static int ep93xx_ddiv_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_psc *psc =3D to_clk_psc(hw); + int pdiv, div, npdiv, ndiv; + unsigned long actual_rate, mclk_rate, rate_err =3D -1; + int found =3D 0; + u32 val; + + ep93xx_regmap_read(psc->reg, &val); + mclk_rate =3D parent_rate * 2; + + for (pdiv =3D 4; pdiv <=3D 6; pdiv++) { + div =3D DIV_ROUND_CLOSEST(mclk_rate, rate * pdiv); + if (div < 1 || div > 127) + continue; + + actual_rate =3D DIV_ROUND_CLOSEST(mclk_rate, pdiv * div); + + if (!found || abs(actual_rate - rate) < rate_err) { + npdiv =3D pdiv - 3; + ndiv =3D div; + rate_err =3D abs(actual_rate - rate); + found =3D 1; + } + } + + if (!found) + return -EINVAL; + + /* Clear old dividers */ + val &=3D ~0x37f; + + /* Set the new pdiv and div bits for the new clock rate */ + val |=3D (npdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | ndiv; + + ep93xx_syscon_swlocked_write(val, psc->reg); + + return 0; +} + +static const struct clk_ops clk_ddiv_ops =3D { + .enable =3D ep93xx_clk_enable, + .disable =3D ep93xx_clk_disable, + .is_enabled =3D ep93xx_clk_is_enabled, + .get_parent =3D ep93xx_mux_get_parent, + .set_parent =3D ep93xx_mux_set_parent_lock, + .determine_rate =3D ep93xx_mux_determine_rate, + .recalc_rate =3D ep93xx_ddiv_recalc_rate, + .set_rate =3D ep93xx_ddiv_set_rate, +}; + +static struct clk_hw *clk_hw_register_ddiv(const char *name, + unsigned int reg, + u8 bit_idx) +{ + struct clk_init_data init =3D { }; + struct clk_psc *psc; + int ret; + + psc =3D kzalloc(sizeof(*psc), GFP_KERNEL); + if (!psc) + return ERR_PTR(-ENOMEM); + + init.name =3D name; + init.ops =3D &clk_ddiv_ops; + init.flags =3D 0; + init.parent_data =3D ep93xx_clk_parents; + init.num_parents =3D ARRAY_SIZE(ep93xx_clk_parents); + + psc->reg =3D reg; + psc->bit_idx =3D bit_idx; + psc->lock =3D &ep93xx_clk_lock; + psc->hw.init =3D &init; + + ret =3D clk_hw_register(NULL, &psc->hw); + if (ret) { + kfree(psc); + return ERR_PTR(ret); + } + + return &psc->hw; +} + +static unsigned long ep93xx_div_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_psc *psc =3D to_clk_psc(hw); + u32 val; + u8 index; + + ep93xx_regmap_read(psc->reg, &val); + index =3D (val & psc->mask) >> psc->shift; + if (index > psc->num_div) + return 0; + + return DIV_ROUND_CLOSEST(parent_rate, psc->div[index]); +} + +static long ep93xx_div_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct clk_psc *psc =3D to_clk_psc(hw); + unsigned long best =3D 0, now; + bool assigned =3D false; + int i; + + for (i =3D 0; i < psc->num_div; i++) { + if ((rate * psc->div[i]) =3D=3D *parent_rate) + return rate; + + now =3D DIV_ROUND_CLOSEST(*parent_rate, psc->div[i]); + + if (!assigned || is_best(rate, now, best)) + best =3D now; + assigned =3D true; + } + + return best; +} + +static int ep93xx_div_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_psc *psc =3D to_clk_psc(hw); + u32 val; + int i; + + ep93xx_regmap_read(psc->reg, &val); + val &=3D ~psc->mask; + for (i =3D 0; i < psc->num_div; i++) + if (rate =3D=3D DIV_ROUND_CLOSEST(parent_rate, psc->div[i])) { + val |=3D i << psc->shift; + break; + } + + if (i =3D=3D psc->num_div) + return -EINVAL; + + ep93xx_syscon_swlocked_write(val, psc->reg); + + return 0; +} + +static const struct clk_ops ep93xx_div_ops =3D { + .enable =3D ep93xx_clk_enable, + .disable =3D ep93xx_clk_disable, + .is_enabled =3D ep93xx_clk_is_enabled, + .recalc_rate =3D ep93xx_div_recalc_rate, + .round_rate =3D ep93xx_div_round_rate, + .set_rate =3D ep93xx_div_set_rate, +}; + +static struct clk_hw *clk_hw_register_div(const char *name, + const char *parent_name, + unsigned int reg, + u8 enable_bit, + u8 shift, + u8 width, + const char *clk_divisors, + u8 num_div) +{ + struct clk_parent_data parent_data =3D { }; + struct clk_init_data init =3D { }; + struct clk_psc *psc; + int ret; + + psc =3D kzalloc(sizeof(*psc), GFP_KERNEL); + if (!psc) + return ERR_PTR(-ENOMEM); + + init.name =3D name; + init.ops =3D &ep93xx_div_ops; + init.flags =3D 0; + parent_data.fw_name =3D parent_name; + parent_data.name =3D parent_name; + init.parent_data =3D &parent_data; + init.num_parents =3D 1; + + psc->reg =3D reg; + psc->bit_idx =3D enable_bit; + psc->mask =3D GENMASK(shift + width - 1, shift); + psc->shift =3D shift; + psc->div =3D clk_divisors; + psc->num_div =3D num_div; + psc->lock =3D &ep93xx_clk_lock; + psc->hw.init =3D &init; + + ret =3D clk_hw_register(NULL, &psc->hw); + if (ret) { + kfree(psc); + return ERR_PTR(ret); + } + + return &psc->hw; +} + +struct ep93xx_gate { + unsigned int idx; + unsigned int bit; + const char *name; +}; + +static const struct ep93xx_gate ep93xx_uarts[] =3D { + { EP93XX_CLK_UART1, EP93XX_SYSCON_DEVCFG_U1EN, "uart1" }, + { EP93XX_CLK_UART2, EP93XX_SYSCON_DEVCFG_U2EN, "uart2" }, + { EP93XX_CLK_UART3, EP93XX_SYSCON_DEVCFG_U3EN, "uart3" }, +}; + +static void ep93xx_uart_clock_init(void) +{ + unsigned int i; + struct clk_hw *hw; + u32 val; + unsigned int clk_uart_div; + + ep93xx_regmap_read(EP93XX_SYSCON_PWRCNT, &val); + if (val & EP93XX_SYSCON_PWRCNT_UARTBAUD) + clk_uart_div =3D 1; + else + clk_uart_div =3D 2; + + hw =3D clk_hw_register_fixed_factor(NULL, "uart", "xtali", 0, 1, clk_uart= _div); + ep93xx_clk_data->hws[EP93XX_CLK_UART] =3D hw; + + /* parenting uart gate clocks to uart clock */ + for (i =3D 0; i < ARRAY_SIZE(ep93xx_uarts); i++) { + hw =3D ep93xx_clk_register_gate(ep93xx_uarts[i].name, + "uart", + CLK_SET_RATE_PARENT, + EP93XX_SYSCON_DEVCFG, + ep93xx_uarts[i].bit, + false); + + ep93xx_clk_data->hws[ep93xx_uarts[i].idx] =3D hw; + } +} + +static const struct ep93xx_gate ep93xx_dmas[] =3D { + { EP93XX_CLK_M2P0, EP93XX_SYSCON_PWRCNT_DMA_M2P0, "m2p0" }, + { EP93XX_CLK_M2P1, EP93XX_SYSCON_PWRCNT_DMA_M2P1, "m2p1" }, + { EP93XX_CLK_M2P2, EP93XX_SYSCON_PWRCNT_DMA_M2P2, "m2p2" }, + { EP93XX_CLK_M2P3, EP93XX_SYSCON_PWRCNT_DMA_M2P3, "m2p3" }, + { EP93XX_CLK_M2P4, EP93XX_SYSCON_PWRCNT_DMA_M2P4, "m2p4" }, + { EP93XX_CLK_M2P5, EP93XX_SYSCON_PWRCNT_DMA_M2P5, "m2p5" }, + { EP93XX_CLK_M2P6, EP93XX_SYSCON_PWRCNT_DMA_M2P6, "m2p6" }, + { EP93XX_CLK_M2P7, EP93XX_SYSCON_PWRCNT_DMA_M2P7, "m2p7" }, + { EP93XX_CLK_M2P8, EP93XX_SYSCON_PWRCNT_DMA_M2P8, "m2p8" }, + { EP93XX_CLK_M2P9, EP93XX_SYSCON_PWRCNT_DMA_M2P9, "m2p9" }, + { EP93XX_CLK_M2M0, EP93XX_SYSCON_PWRCNT_DMA_M2M0, "m2m0" }, + { EP93XX_CLK_M2M1, EP93XX_SYSCON_PWRCNT_DMA_M2M1, "m2m1" }, +}; + +static void ep93xx_dma_clock_init(void) +{ + int i; + struct clk_hw *hw; + + for (i =3D 0; i < ARRAY_SIZE(ep93xx_dmas); i++) { + hw =3D ep93xx_clk_register_gate(ep93xx_dmas[i].name, + "hclk", 0, + EP93XX_SYSCON_PWRCNT, + ep93xx_dmas[i].bit, + true); + + ep93xx_clk_data->hws[ep93xx_dmas[i].idx] =3D hw; + } +} + +static int ep93xx_clk_probe(struct platform_device *pdev) +{ + unsigned int clk_usb_div; + unsigned long clk_spi_div; + struct clk_hw *hw; + u32 value; + + ep93xx_regmap_read(EP93XX_SYSCON_CLKSET2, &value); + clk_usb_div =3D (((value >> 28) & 0xf) + 1); + hw =3D clk_hw_register_fixed_factor(NULL, "usb_clk", "pll2", 0, 1, clk_us= b_div); + hw =3D ep93xx_clk_register_gate("ohci-platform", + "usb_clk", 0, + EP93XX_SYSCON_PWRCNT, + EP93XX_SYSCON_PWRCNT_USH_EN, + true); + ep93xx_clk_data->hws[EP93XX_CLK_USB] =3D hw; + + /* + * EP93xx SSP clock rate was doubled in version E2. For more information + * see: + * http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf + */ + clk_spi_div =3D 1; + if (ep93xx_chip_revision() < EP93XX_CHIP_REV_E2) + clk_spi_div =3D 2; + hw =3D clk_hw_register_fixed_factor(NULL, "ep93xx-spi.0", "xtali", 0, 1, = clk_spi_div); + ep93xx_clk_data->hws[EP93XX_CLK_SPI] =3D hw; + + /* pwm clock */ + hw =3D clk_hw_register_fixed_factor(NULL, "pwm_clk", "xtali", 0, 1, 1); + ep93xx_clk_data->hws[EP93XX_CLK_PWM] =3D hw; + + ep93xx_uart_clock_init(); + + /* touchscreen/adc clock */ + hw =3D clk_hw_register_div("ep93xx-adc", + "xtali", + EP93XX_SYSCON_KEYTCHCLKDIV, + EP93XX_SYSCON_KEYTCHCLKDIV_TSEN, + EP93XX_SYSCON_KEYTCHCLKDIV_ADIV, + 1, + adc_divisors, + ARRAY_SIZE(adc_divisors)); + + ep93xx_clk_data->hws[EP93XX_CLK_ADC] =3D hw; + + /* keypad clock */ + hw =3D clk_hw_register_div("ep93xx-keypad", + "xtali", + EP93XX_SYSCON_KEYTCHCLKDIV, + EP93XX_SYSCON_KEYTCHCLKDIV_KEN, + EP93XX_SYSCON_KEYTCHCLKDIV_KDIV, + 1, + adc_divisors, + ARRAY_SIZE(adc_divisors)); + + ep93xx_clk_data->hws[EP93XX_CLK_KEYPAD] =3D hw; + + /* + * On reset PDIV and VDIV is set to zero, while PDIV zero + * means clock disable, VDIV shouldn't be zero. + * So i set both dividers to minimum. + */ + /* ENA - Enable CLK divider. */ + /* PDIV - 00 - Disable clock */ + /* VDIV - at least 2 */ + /* Check and enable video clk registers */ + ep93xx_regmap_read(EP93XX_SYSCON_VIDCLKDIV, &value); + value |=3D (1 << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | 2; + ep93xx_syscon_swlocked_write(value, EP93XX_SYSCON_VIDCLKDIV); + + /* check and enable i2s clk registers */ + ep93xx_regmap_read(EP93XX_SYSCON_I2SCLKDIV, &value); + value |=3D (1 << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | 2; + /* + * Override the SAI_MSTR_CLK_CFG from the I2S block and use the + * I2SClkDiv Register settings. LRCLK transitions on the falling SCLK + * edge. + */ + value |=3D EP93XX_SYSCON_I2SCLKDIV_ORIDE | EP93XX_SYSCON_I2SCLKDIV_SPOL; + ep93xx_syscon_swlocked_write(value, EP93XX_SYSCON_I2SCLKDIV); + + /* video clk */ + hw =3D clk_hw_register_ddiv("ep93xx-fb", + EP93XX_SYSCON_VIDCLKDIV, + EP93XX_SYSCON_CLKDIV_ENABLE); + + ep93xx_clk_data->hws[EP93XX_CLK_VIDEO] =3D hw; + + /* i2s clk */ + hw =3D clk_hw_register_ddiv("mclk", + EP93XX_SYSCON_I2SCLKDIV, + EP93XX_SYSCON_CLKDIV_ENABLE); + + ep93xx_clk_data->hws[EP93XX_CLK_I2S_MCLK] =3D hw; + + /* i2s sclk */ + hw =3D clk_hw_register_div("sclk", + "mclk", + EP93XX_SYSCON_I2SCLKDIV, + EP93XX_SYSCON_I2SCLKDIV_SENA, + 16, /* EP93XX_I2SCLKDIV_SDIV_SHIFT */ + 1, /* EP93XX_I2SCLKDIV_SDIV_WIDTH */ + sclk_divisors, + ARRAY_SIZE(sclk_divisors)); + + ep93xx_clk_data->hws[EP93XX_CLK_I2S_SCLK] =3D hw; + + /* i2s lrclk */ + hw =3D clk_hw_register_div("lrclk", + "sclk", + EP93XX_SYSCON_I2SCLKDIV, + EP93XX_SYSCON_I2SCLKDIV_SENA, + 17, /* EP93XX_I2SCLKDIV_LRDIV32_SHIFT */ + 2, /* EP93XX_I2SCLKDIV_LRDIV32_WIDTH */ + lrclk_divisors, + ARRAY_SIZE(lrclk_divisors)); + + ep93xx_clk_data->hws[EP93XX_CLK_I2S_LRCLK] =3D hw; + + /* IrDa clk uses same pattern but no init code presents in original clock= driver */ + return 0; +} + +static const struct of_device_id ep93xx_clk_dt_ids[] =3D { + { .compatible =3D "cirrus,ep9301-clk", }, + { /* sentinel */ } +}; + +static struct platform_driver ep93xx_clk_driver =3D { + .probe =3D ep93xx_clk_probe, + .driver =3D { + .name =3D "ep93xx-clk", + .of_match_table =3D ep93xx_clk_dt_ids, + .suppress_bind_attrs =3D true, + }, +}; +builtin_platform_driver(ep93xx_clk_driver); + +static void __init ep93xx_clock_init(struct device_node *np) +{ + int i; + int ret; + u32 value; + struct clk_hw *hw; + struct device_node *parent; + unsigned long clk_pll1_rate; + unsigned long clk_pll2_rate; + unsigned int clk_f_div; + unsigned int clk_h_div; + unsigned int clk_p_div; + + ep93xx_clk_data =3D kzalloc(struct_size(ep93xx_clk_data, hws, + EP93XX_NUM_CLKS), + GFP_KERNEL); + + if (!ep93xx_clk_data) + return; + + /* + * This way all clock fetched before the platform device probes, + * except those we assign here for early use, will be deferred. + */ + for (i =3D 0; i < EP93XX_NUM_CLKS; i++) + ep93xx_clk_data->hws[i] =3D ERR_PTR(-EPROBE_DEFER); + + parent =3D of_get_parent(np); + if (!parent) { + pr_err("no syscon parent for clk node\n"); + return; + } + + ep93xx_map =3D syscon_node_to_regmap(parent); + of_node_put(parent); + if (IS_ERR(ep93xx_map)) { + pr_err("no syscon regmap\n"); + return; + } + + /* + * We check that the regmap works on this very first access, + * but as this is an MMIO-backed regmap, subsequent regmap + * access is not going to fail and we skip error checks from + * this point. + */ + ret =3D ep93xx_regmap_read(EP93XX_SYSCON_CHIPID, &value); + if (ret || (value & 0xffff) !=3D EP93XX_SYSCON_CHIPID_ID) { + pr_err("failed to read global status register\n"); + return; + } + + /* Determine the bootloader configured pll1 rate */ + ep93xx_regmap_read(EP93XX_SYSCON_CLKSET1, &value); + if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1)) + clk_pll1_rate =3D EP93XX_EXT_CLK_RATE; + else + clk_pll1_rate =3D calc_pll_rate(EP93XX_EXT_CLK_RATE, value); + + hw =3D clk_hw_register_fixed_rate(NULL, "pll1", "xtali", 0, clk_pll1_rate= ); + ep93xx_clk_data->hws[EP93XX_CLK_PLL1] =3D hw; + + /* Initialize the pll1 derived clocks */ + clk_f_div =3D fclk_divisors[(value >> 25) & 0x7]; + clk_h_div =3D hclk_divisors[(value >> 20) & 0x7]; + clk_p_div =3D pclk_divisors[(value >> 18) & 0x3]; + + hw =3D clk_hw_register_fixed_factor(NULL, "fclk", "pll1", 0, 1, clk_f_div= ); + ep93xx_clk_data->hws[EP93XX_CLK_FCLK] =3D hw; + hw =3D clk_hw_register_fixed_factor(NULL, "hclk", "pll1", 0, 1, clk_h_div= ); + ep93xx_clk_data->hws[EP93XX_CLK_HCLK] =3D hw; + hw =3D clk_hw_register_fixed_factor(NULL, "pclk", "hclk", 0, 1, clk_p_div= ); + ep93xx_clk_data->hws[EP93XX_CLK_PCLK] =3D hw; + + /* Dma probing uses subsys_initcall, so we require to init them early */ + ep93xx_dma_clock_init(); + + /* Determine the bootloader configured pll2 rate */ + ep93xx_regmap_read(EP93XX_SYSCON_CLKSET2, &value); + if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2)) + clk_pll2_rate =3D EP93XX_EXT_CLK_RATE; + else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN) + clk_pll2_rate =3D calc_pll_rate(EP93XX_EXT_CLK_RATE, value); + else + clk_pll2_rate =3D 0; + + hw =3D clk_hw_register_fixed_rate(NULL, "pll2", "xtali", 0, clk_pll2_rate= ); + ep93xx_clk_data->hws[EP93XX_CLK_PLL2] =3D hw; + + ep93xx_clk_data->num =3D EP93XX_NUM_CLKS; + of_clk_add_hw_provider(np, of_clk_hw_onecell_get, ep93xx_clk_data); +} + +CLK_OF_DECLARE_DRIVER(ep93xx, "cirrus,ep9301-clk", ep93xx_clock_init); --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C403C77B76 for ; Mon, 24 Apr 2023 09:55:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230228AbjDXJzt (ORCPT ); Mon, 24 Apr 2023 05:55:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54976 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231133AbjDXJzq (ORCPT ); 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dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , Daniel Lezcano , Thomas Gleixner , linux-kernel@vger.kernel.org Subject: [PATCH 06/43] clocksource: ep93xx: Add driver for Cirrus Logic EP93xx Date: Mon, 24 Apr 2023 15:34:22 +0300 Message-Id: <20230424123522.18302-7-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This us a rewrite of EP93xx timer driver in arch/arm/mach-ep93xx/timer-ep93xx.c trying to do everything the device tree way: - Make every IO-access relative to a base address and dynamic so we can do a dynamic ioremap and get going. - Find register range and interrupt from the device tree. Signed-off-by: Nikita Shubin Acked-by: Alexander Sverdlin Reviewed-by: Linus Walleij Tested-by: Alexander Sverdlin --- drivers/clocksource/Kconfig | 11 ++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-ep93xx.c | 191 +++++++++++++++++++++++++++++ 3 files changed, 203 insertions(+) create mode 100644 drivers/clocksource/timer-ep93xx.c diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 5fc8f0e7fb38..40bfc7c86756 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -721,4 +721,15 @@ config GOLDFISH_TIMER help Support for the timer/counter of goldfish-rtc =20 +config EP93XX_TIMER + bool "Cirrus Logic ep93xx timer driver" if COMPILE_TEST + depends on ARCH_EP93XX + depends on GENERIC_CLOCKEVENTS + depends on HAS_IOMEM + select CLKSRC_MMIO + select TIMER_OF + help + Enables support for the Cirrus Logic timer block + EP93XX. + endmenu diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 64ab547de97b..09c2d4e5d809 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -88,3 +88,4 @@ obj-$(CONFIG_MICROCHIP_PIT64B) +=3D timer-microchip-pit6= 4b.o obj-$(CONFIG_MSC313E_TIMER) +=3D timer-msc313e.o obj-$(CONFIG_GOLDFISH_TIMER) +=3D timer-goldfish.o obj-$(CONFIG_GXP_TIMER) +=3D timer-gxp.o +obj-$(CONFIG_EP93XX_TIMER) +=3D timer-ep93xx.o diff --git a/drivers/clocksource/timer-ep93xx.c b/drivers/clocksource/timer= -ep93xx.c new file mode 100644 index 000000000000..58dc15a21318 --- /dev/null +++ b/drivers/clocksource/timer-ep93xx.c @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Cirrus Logic EP93xx timer driver. + * Copyright (C) 2021 Nikita Shubin + * + * Based on a rewrite of arch/arm/mach-ep93xx/timer.c: + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/************************************************************************* + * Timer handling for EP93xx + ************************************************************************* + * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and + * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate + * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz, + * is free-running, and can't generate interrupts. + * + * The 508 kHz timers are ideal for use for the timer interrupt, as the + * most common values of HZ divide 508 kHz nicely. We pick the 32 bit + * timer (timer 3) to get as long sleep intervals as possible when using + * CONFIG_NO_HZ. + * + * The higher clock rate of timer 4 makes it a better choice than the + * other timers for use as clock source and for sched_clock(), providing + * a stable 40 bit time base. + ************************************************************************* + */ + +#define EP93XX_TIMER1_LOAD 0x00 +#define EP93XX_TIMER1_VALUE 0x04 +#define EP93XX_TIMER1_CONTROL 0x08 +#define EP93XX_TIMER123_CONTROL_ENABLE BIT(7) +#define EP93XX_TIMER123_CONTROL_MODE BIT(6) +#define EP93XX_TIMER123_CONTROL_CLKSEL BIT(3) +#define EP93XX_TIMER1_CLEAR 0x0c +#define EP93XX_TIMER2_LOAD 0x20 +#define EP93XX_TIMER2_VALUE 0x24 +#define EP93XX_TIMER2_CONTROL 0x28 +#define EP93XX_TIMER2_CLEAR 0x2c +/* This read-only register contains the low word of the time stamp debug t= imer + * ( Timer4). When this register is read, the high byte of the Timer4 coun= ter is + * saved in the Timer4ValueHigh register. + */ +#define EP93XX_TIMER4_VALUE_LOW 0x60 +#define EP93XX_TIMER4_VALUE_HIGH 0x64 +#define EP93XX_TIMER4_VALUE_HIGH_ENABLE BIT(8) +#define EP93XX_TIMER3_LOAD 0x80 +#define EP93XX_TIMER3_VALUE 0x84 +#define EP93XX_TIMER3_CONTROL 0x88 +#define EP93XX_TIMER3_CLEAR 0x8c + +#define EP93XX_TIMER123_RATE 508469 +#define EP93XX_TIMER4_RATE 983040 + +struct ep93xx_tcu { + void __iomem *base; +}; + +static struct ep93xx_tcu *ep93xx_tcu; + +static u64 ep93xx_clocksource_read(struct clocksource *c) +{ + struct ep93xx_tcu *tcu =3D ep93xx_tcu; + u64 ret; + + ret =3D readl(tcu->base + EP93XX_TIMER4_VALUE_LOW); + ret |=3D ((u64) (readl(tcu->base + EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 3= 2); + return (u64) ret; +} + +static u64 notrace ep93xx_read_sched_clock(void) +{ + return ep93xx_clocksource_read(NULL); +} + +static int ep93xx_clkevt_set_next_event(unsigned long next, + struct clock_event_device *evt) +{ + struct ep93xx_tcu *tcu =3D ep93xx_tcu; + /* Default mode: periodic, off, 508 kHz */ + u32 tmode =3D EP93XX_TIMER123_CONTROL_MODE | + EP93XX_TIMER123_CONTROL_CLKSEL; + + /* Clear timer */ + writel(tmode, tcu->base + EP93XX_TIMER3_CONTROL); + + /* Set next event */ + writel(next, tcu->base + EP93XX_TIMER3_LOAD); + writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE, + tcu->base + EP93XX_TIMER3_CONTROL); + return 0; +} + +static int ep93xx_clkevt_shutdown(struct clock_event_device *evt) +{ + struct ep93xx_tcu *tcu =3D ep93xx_tcu; + /* Disable timer */ + writel(0, tcu->base + EP93XX_TIMER3_CONTROL); + + return 0; +} + +static struct clock_event_device ep93xx_clockevent =3D { + .name =3D "timer1", + .features =3D CLOCK_EVT_FEAT_ONESHOT, + .set_state_shutdown =3D ep93xx_clkevt_shutdown, + .set_state_oneshot =3D ep93xx_clkevt_shutdown, + .tick_resume =3D ep93xx_clkevt_shutdown, + .set_next_event =3D ep93xx_clkevt_set_next_event, + .rating =3D 300, +}; + +static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id) +{ + struct ep93xx_tcu *tcu =3D ep93xx_tcu; + struct clock_event_device *evt =3D dev_id; + + /* Writing any value clears the timer interrupt */ + writel(1, tcu->base + EP93XX_TIMER3_CLEAR); + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static int __init ep93xx_timer_of_init(struct device_node *np) +{ + int irq; + unsigned long flags =3D IRQF_TIMER | IRQF_IRQPOLL; + struct ep93xx_tcu *tcu; + int ret; + + tcu =3D kzalloc(sizeof(*tcu), GFP_KERNEL); + if (!tcu) + return -ENOMEM; + + tcu->base =3D of_iomap(np, 0); + if (!tcu->base) { + pr_err("Can't remap registers\n"); + ret =3D -ENXIO; + goto out_free; + } + + ep93xx_tcu =3D tcu; + + irq =3D irq_of_parse_and_map(np, 0); + if (irq <=3D 0) { + pr_err("ERROR: invalid interrupt number\n"); + ret =3D -EINVAL; + goto out_free; + } + + /* Enable and register clocksource and sched_clock on timer 4 */ + writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE, + tcu->base + EP93XX_TIMER4_VALUE_HIGH); + clocksource_mmio_init(NULL, "timer4", + EP93XX_TIMER4_RATE, 200, 40, + ep93xx_clocksource_read); + sched_clock_register(ep93xx_read_sched_clock, 40, + EP93XX_TIMER4_RATE); + + /* Set up clockevent on timer 3 */ + if (request_irq(irq, ep93xx_timer_interrupt, flags, "ep93xx timer", + &ep93xx_clockevent)) + pr_err("Failed to request irq %d (ep93xx timer)\n", irq); + clockevents_config_and_register(&ep93xx_clockevent, + EP93XX_TIMER123_RATE, + 1, + 0xffffffffU); + + return 0; + +out_free: + kfree(tcu); + return ret; +} + +TIMER_OF_DECLARE(ep93xx_timer, "cirrus,ep9301-timer", ep93xx_timer_of_init= ); --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82394C77B7A for ; Thu, 1 Jun 2023 05:37:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231325AbjFAFhf (ORCPT ); Thu, 1 Jun 2023 01:37:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47022 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231221AbjFAFh0 (ORCPT ); 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dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Nikita Shubin Cc: Michael Peters , Kris Bahnsen , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 06/43] dt-bindings: pinctrl: Add Cirrus EP93xx Date: Thu, 1 Jun 2023 08:33:57 +0300 Message-Id: <20230601053546.9574-7-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add YAML bindings for ep93xx SoC pinctrl. Signed-off-by: Nikita Shubin Reviewed-by: Linus Walleij --- Notes: v0 -> v1: =20 Krzysztof Kozlowski: - removed wildcards - use fallback compatible and list all possible compatibles - fix ident - dropped bindings in title .../pinctrl/cirrus,ep9301-pinctrl.yaml | 66 +++++++++++++++++++ 1 file changed, 66 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/cirrus,ep9301= -pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/cirrus,ep9301-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/cirrus,ep9301-pinctrl.ya= ml new file mode 100644 index 000000000000..ff7b30a11bab --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/cirrus,ep9301-pinctrl.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/cirrus,ep9301-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus ep93xx pins mux controller + +maintainers: + - Nikita Shubin + - Alexander Sverdlin + +properties: + compatible: + oneOf: + - const: cirrus,ep9301-pinctrl + - items: + - enum: + - cirrus,ep9302-pinctrl + - cirrus,ep9307-pinctrl + - cirrus,ep9312-pinctrl + - cirrus,ep9315-pinctrl + - const: cirrus,ep9301-pinctrl + +patternProperties: + '^pins-': + type: object + description: pin node + $ref: pinmux-node.yaml# + + properties: + function: + enum: [ spi, ac97, i2s, pwm, keypad, pata, lcd, gpio ] + groups: + minItems: 1 + maxItems: 2 + items: + enum: [ ssp, ac97, i2s_on_ssp, i2s_on_ac97, pwm1, gpio1agrp, + gpio2agrp, gpio3agrp, gpio4agrp, gpio6agrp, gpio7agrp, + rasteronsdram0grp, rasteronsdram3grp, keypadgrp, idegrp] + + required: + - function + - groups + +required: + - compatible + +additionalProperties: false + +examples: + - | + syscon@80930000 { + compatible =3D "cirrus,ep9301-syscon", + "syscon", "simple-mfd"; + reg =3D <0x80930000 0x1000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + pinctrl { + compatible =3D "cirrus,ep9312-pinctrl", "cirrus,ep9301-pinctrl"; + spi_default_pins: pins-spi { + function =3D "spi"; + groups =3D "ssp"; + }; + }; + }; --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD984C77B7A for ; Thu, 1 Jun 2023 05:38:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231401AbjFAFh7 (ORCPT ); Thu, 1 Jun 2023 01:37:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231349AbjFAFhi (ORCPT ); Thu, 1 Jun 2023 01:37:38 -0400 Received: from forward101b.mail.yandex.net (forward101b.mail.yandex.net [IPv6:2a02:6b8:c02:900:1:45:d181:d101]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0AF8DE5B; Wed, 31 May 2023 22:37:03 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net [IPv6:2a02:6b8:c14:c83:0:640:84f9:0]) by forward101b.mail.yandex.net (Yandex) with ESMTP id 6F3D260064; Thu, 1 Jun 2023 08:37:02 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id OaGNfZvWv8c0-4sBSIUzb; Thu, 01 Jun 2023 08:37:01 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1685597821; bh=cccFuk36PzIBTCy63SNepP4Fq6f83dZZmcDbCbBSN/w=; h=Cc:Message-Id:References:Date:In-Reply-To:Subject:To:From; b=c8a7+l3AH2IWwlTl5T1fz7+EtiMdwE5ztl+YRWLUqhWhhE3DjLRcEA6ns3grEgHcZ 4R837FRpTk7MaXX9mVaS8gOlqPhOlzp5+G+/wrkKwtQApZwXynvmfNfOmbU11f7TlW gWWk0qVRiA5rprJizHPdCh3gTk4uVR6t+mbM9eAk= Authentication-Results: mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij Cc: Nikita Shubin , Michael Peters , Kris Bahnsen , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [PATCH v1 07/43] pinctrl: add a Cirrus ep93xx SoC pin controller Date: Thu, 1 Jun 2023 08:33:58 +0300 Message-Id: <20230601053546.9574-8-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This adds a pin control (only multiplexing) driver for ep93xx SoC so we can fully convert ep93xx to device tree. This driver is capable of muxing ep9301/ep9302/ep9307/ep9312/ep9315 variants, this is chosen based on "compatible" in device tree. Co-developed-by: Alexander Sverdlin Signed-off-by: Alexander Sverdlin Signed-off-by: Nikita Shubin Reviewed-by: Linus Walleij --- Notes: v0 -> v1: =20 - dropped redundant gpio groups - headers sorted drivers/pinctrl/Kconfig | 7 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-ep93xx.c | 1672 ++++++++++++++++++++++++++++++ 3 files changed, 1680 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-ep93xx.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index dcb53c4a9584..60c6e3ba706b 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -176,6 +176,13 @@ config PINCTRL_DIGICOLOR select PINMUX select GENERIC_PINCONF =20 +config PINCTRL_EP93XX + bool + depends on OF && (ARCH_EP93XX || COMPILE_TEST) + select PINMUX + select GENERIC_PINCONF + select MFD_SYSCON + config PINCTRL_EQUILIBRIUM tristate "Generic pinctrl and GPIO driver for Intel Lightning Mountain So= C" depends on OF && HAS_IOMEM diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index d5939840bb2a..9d70c79eadbe 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_PINCTRL_DA850_PUPD) +=3D pinctrl-da850-pupd.o obj-$(CONFIG_PINCTRL_DA9062) +=3D pinctrl-da9062.o obj-$(CONFIG_PINCTRL_DIGICOLOR) +=3D pinctrl-digicolor.o obj-$(CONFIG_PINCTRL_EQUILIBRIUM) +=3D pinctrl-equilibrium.o +obj-$(CONFIG_PINCTRL_EP93XX) +=3D pinctrl-ep93xx.o obj-$(CONFIG_PINCTRL_GEMINI) +=3D pinctrl-gemini.o obj-$(CONFIG_PINCTRL_INGENIC) +=3D pinctrl-ingenic.o obj-$(CONFIG_PINCTRL_K210) +=3D pinctrl-k210.o diff --git a/drivers/pinctrl/pinctrl-ep93xx.c b/drivers/pinctrl/pinctrl-ep9= 3xx.c new file mode 100644 index 000000000000..0e1bcbf32e6d --- /dev/null +++ b/drivers/pinctrl/pinctrl-ep93xx.c @@ -0,0 +1,1672 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Driver for the EP93xx pin controller + * based on linux/drivers/pinctrl/pinmux-gemini.c + * + * Copyright (C) 2022 Nikita Shubin + * + * This is a group-only pin controller. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "pinctrl-utils.h" + +#define DRIVER_NAME "pinctrl-ep93xx" + +enum ep93xx_pinctrl_model { + EP93XX_9301_PINCTRL =3D 0, + EP93XX_9307_PINCTRL, + EP93XX_9312_PINCTRL +}; + +/** + * struct ep93xx_pmx - state holder for the ep93xx pin controller + * @dev: a pointer back to containing device + * @pctl: the offset to the controller in virtual memory + * @map: regmap to access registers + * @model: SoC model + */ +struct ep93xx_pmx { + struct device *dev; + struct pinctrl_dev *pctl; + struct regmap *map; + enum ep93xx_pinctrl_model model; +}; + +/** + * struct ep93xx_pin_group - describes a ep93xx pin group + * @name: the name of this specific pin group + * @pins: an array of discrete physical pins used in this group, taken + * from the driver-local pin enumeration space + * @num_pins: the number of pins in this group array, i.e. the number of + * elements in .pins so we can iterate over that array + * @mask: bits to clear to enable this when doing pin muxing + * @value: bits to set to enable this when doing pin muxing + */ +struct ep93xx_pin_group { + const char *name; + const unsigned int *pins; + const unsigned int num_pins; + u32 mask; + u32 value; +}; + +#define EP93XX_SYSCON_DEVCFG 0x80 + +/* + * There are several system configuration options selectable by the Device= Cfg and SysCfg + * registers. These registers provide the selection of several pin multipl= exing options and also + * provide software access to the system reset configuration options. Plea= se refer to the + * descriptions of the registers, =E2=80=9CDeviceCfg=E2=80=9D on page 5-25= and =E2=80=9CSysCfg=E2=80=9D on page 5-34, for a + * detailed explanation. + */ +#define EP93XX_SYSCON_DEVCFG_D1ONG BIT(30) /* not used */ +#define EP93XX_SYSCON_DEVCFG_D0ONG BIT(29) /* not used */ +#define EP93XX_SYSCON_DEVCFG_IONU2 BIT(28) /* not used */ +#define EP93XX_SYSCON_DEVCFG_GONK BIT(27) /* done */ +#define EP93XX_SYSCON_DEVCFG_TONG BIT(26) /* not used */ +#define EP93XX_SYSCON_DEVCFG_MONG BIT(25) /* not used */ +#define EP93XX_SYSCON_DEVCFG_A2ONG BIT(22) /* not used */ +#define EP93XX_SYSCON_DEVCFG_A1ONG BIT(21) /* not used */ +#define EP93XX_SYSCON_DEVCFG_HONIDE BIT(11) /* done */ +#define EP93XX_SYSCON_DEVCFG_GONIDE BIT(10) /* done */ +#define EP93XX_SYSCON_DEVCFG_PONG BIT(9) /* done */ +#define EP93XX_SYSCON_DEVCFG_EONIDE BIT(8) /* done */ +#define EP93XX_SYSCON_DEVCFG_I2SONSSP BIT(7) /* done */ +#define EP93XX_SYSCON_DEVCFG_I2SONAC97 BIT(6) /* done */ +#define EP93XX_SYSCON_DEVCFG_RASONP3 BIT(4) /* done */ + +#define PADS_MASK (GENMASK(30, 25) | BIT(22) | BIT(21) | GENMASK(11, 6) |= BIT(4)) +#define PADS_MAXBIT 30 + +/* Ordered by bit index */ +static const char * const ep93xx_padgroups[] =3D { + NULL, NULL, NULL, NULL, + "RasOnP3", + NULL, + "I2SonAC97", + "I2SonSSP", + "EonIDE", + "PonG", + "GonIDE", + "HonIDE", + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + "A1onG", + "A2onG", + NULL, NULL, + "MonG", + "TonG", + "GonK", + "IonU2", + "D0onG", + "D1onG", +}; + +/** ep9301, ep9302*/ +static const struct pinctrl_pin_desc ep9301_pins[] =3D { + PINCTRL_PIN(1, "CSn[7]"), + PINCTRL_PIN(2, "CSn[6]"), + PINCTRL_PIN(3, "CSn[3]"), + PINCTRL_PIN(4, "CSn[2]"), + PINCTRL_PIN(5, "CSn[1]"), + PINCTRL_PIN(6, "AD[25]"), + PINCTRL_PIN(7, "vdd_ring"), + PINCTRL_PIN(8, "gnd_ring"), + PINCTRL_PIN(9, "AD[24]"), + PINCTRL_PIN(10, "SDCLK"), + PINCTRL_PIN(11, "AD[23]"), + PINCTRL_PIN(12, "vdd_core"), + PINCTRL_PIN(13, "gnd_core"), + PINCTRL_PIN(14, "SDWEn"), + PINCTRL_PIN(15, "SDCSn[3]"), + PINCTRL_PIN(16, "SDCSn[2]"), + PINCTRL_PIN(17, "SDCSn[1]"), + PINCTRL_PIN(18, "SDCSn[0]"), + PINCTRL_PIN(19, "vdd_ring"), + PINCTRL_PIN(20, "gnd_ring"), + PINCTRL_PIN(21, "RASn"), + PINCTRL_PIN(22, "CASn"), + PINCTRL_PIN(23, "DQMn[1]"), + PINCTRL_PIN(24, "DQMn[0]"), + PINCTRL_PIN(25, "AD[22]"), + PINCTRL_PIN(26, "AD[21]"), + PINCTRL_PIN(27, "vdd_ring"), + PINCTRL_PIN(28, "gnd_ring"), + PINCTRL_PIN(29, "DA[15]"), + PINCTRL_PIN(30, "AD[7]"), + PINCTRL_PIN(31, "DA[14]"), + PINCTRL_PIN(32, "AD[6]"), + PINCTRL_PIN(33, "DA[13]"), + PINCTRL_PIN(34, "vdd_core"), + PINCTRL_PIN(35, "gnd_core"), + PINCTRL_PIN(36, "AD[5]"), + PINCTRL_PIN(37, "DA[12]"), + PINCTRL_PIN(38, "AD[4]"), + PINCTRL_PIN(39, "DA[11]"), + PINCTRL_PIN(40, "AD[3]"), + PINCTRL_PIN(41, "vdd_ring"), + PINCTRL_PIN(42, "gnd_ring"), + PINCTRL_PIN(43, "DA[10]"), + PINCTRL_PIN(44, "AD[2]"), + PINCTRL_PIN(45, "DA[9]"), + PINCTRL_PIN(46, "AD[1]"), + PINCTRL_PIN(47, "DA[8]"), + PINCTRL_PIN(48, "AD[0]"), + PINCTRL_PIN(49, "vdd_ring"), + PINCTRL_PIN(50, "gnd_ring"), + PINCTRL_PIN(51, "NC"), + PINCTRL_PIN(52, "NC"), + PINCTRL_PIN(53, "vdd_ring"), + PINCTRL_PIN(54, "gnd_ring"), + PINCTRL_PIN(55, "AD[15]"), + PINCTRL_PIN(56, "DA[7]"), + PINCTRL_PIN(57, "vdd_core"), + PINCTRL_PIN(58, "gnd_core"), + PINCTRL_PIN(59, "AD[14]"), + PINCTRL_PIN(60, "DA[6]"), + PINCTRL_PIN(61, "AD[13]"), + PINCTRL_PIN(62, "DA[5]"), + PINCTRL_PIN(63, "AD[12]"), + PINCTRL_PIN(64, "DA[4]"), + PINCTRL_PIN(65, "AD[11]"), + PINCTRL_PIN(66, "vdd_ring"), + PINCTRL_PIN(67, "gnd_ring"), + PINCTRL_PIN(68, "DA[3]"), + PINCTRL_PIN(69, "AD[10]"), + PINCTRL_PIN(70, "DA[2]"), + PINCTRL_PIN(71, "AD[9]"), + PINCTRL_PIN(72, "DA[1]"), + PINCTRL_PIN(73, "AD[8]"), + PINCTRL_PIN(74, "DA[0]"), + PINCTRL_PIN(75, "DSRn"), + PINCTRL_PIN(76, "DTRn"), + PINCTRL_PIN(77, "TCK"), + PINCTRL_PIN(78, "TDI"), + PINCTRL_PIN(79, "TDO"), + PINCTRL_PIN(80, "TMS"), + PINCTRL_PIN(81, "vdd_ring"), + PINCTRL_PIN(82, "gnd_ring"), + PINCTRL_PIN(83, "BOOT[1]"), + PINCTRL_PIN(84, "BOOT[0]"), + PINCTRL_PIN(85, "gnd_ring"), + PINCTRL_PIN(86, "NC"), + PINCTRL_PIN(87, "EECLK"), + PINCTRL_PIN(88, "EEDAT"), + PINCTRL_PIN(89, "ASYNC"), + PINCTRL_PIN(90, "vdd_core"), + PINCTRL_PIN(91, "gnd_core"), + PINCTRL_PIN(92, "ASDO"), + PINCTRL_PIN(93, "SCLK1"), + PINCTRL_PIN(94, "SFRM1"), + PINCTRL_PIN(95, "SSPRX1"), + PINCTRL_PIN(96, "SSPTX1"), + PINCTRL_PIN(97, "GRLED"), + PINCTRL_PIN(98, "RDLED"), + PINCTRL_PIN(99, "vdd_ring"), + PINCTRL_PIN(100, "gnd_ring"), + PINCTRL_PIN(101, "INT[3]"), + PINCTRL_PIN(102, "INT[1]"), + PINCTRL_PIN(103, "INT[0]"), + PINCTRL_PIN(104, "RTSn"), + PINCTRL_PIN(105, "USBm[0]"), + PINCTRL_PIN(106, "USBp[0]"), + PINCTRL_PIN(107, "ABITCLK"), + PINCTRL_PIN(108, "CTSn"), + PINCTRL_PIN(109, "RXD[0]"), + PINCTRL_PIN(110, "RXD[1]"), + PINCTRL_PIN(111, "vdd_ring"), + PINCTRL_PIN(112, "gnd_ring"), + PINCTRL_PIN(113, "TXD[0]"), + PINCTRL_PIN(114, "TXD[1]"), + PINCTRL_PIN(115, "CGPIO[0]"), + PINCTRL_PIN(116, "gnd_core"), + PINCTRL_PIN(117, "PLL_GND"), + PINCTRL_PIN(118, "XTALI"), + PINCTRL_PIN(119, "XTALO"), + PINCTRL_PIN(120, "PLL_VDD"), + PINCTRL_PIN(121, "vdd_core"), + PINCTRL_PIN(122, "gnd_ring"), + PINCTRL_PIN(123, "vdd_ring"), + PINCTRL_PIN(124, "RSTOn"), + PINCTRL_PIN(125, "PRSTn"), + PINCTRL_PIN(126, "CSn[0]"), + PINCTRL_PIN(127, "gnd_core"), + PINCTRL_PIN(128, "vdd_core"), + PINCTRL_PIN(129, "gnd_ring"), + PINCTRL_PIN(130, "vdd_ring"), + PINCTRL_PIN(131, "ADC[4]"), + PINCTRL_PIN(132, "ADC[3]"), + PINCTRL_PIN(133, "ADC[2]"), + PINCTRL_PIN(134, "ADC[1]"), + PINCTRL_PIN(135, "ADC[0]"), + PINCTRL_PIN(136, "ADC_VDD"), + PINCTRL_PIN(137, "RTCXTALI"), + PINCTRL_PIN(138, "RTCXTALO"), + PINCTRL_PIN(139, "ADC_GND"), + PINCTRL_PIN(140, "EGPIO[11]"), + PINCTRL_PIN(141, "EGPIO[10]"), + PINCTRL_PIN(142, "EGPIO[9]"), + PINCTRL_PIN(143, "EGPIO[8]"), + PINCTRL_PIN(144, "EGPIO[7]"), + PINCTRL_PIN(145, "EGPIO[6]"), + PINCTRL_PIN(146, "EGPIO[5]"), + PINCTRL_PIN(147, "EGPIO[4]"), + PINCTRL_PIN(148, "EGPIO[3]"), + PINCTRL_PIN(149, "gnd_ring"), + PINCTRL_PIN(150, "vdd_ring"), + PINCTRL_PIN(151, "EGPIO[2]"), + PINCTRL_PIN(152, "EGPIO[1]"), + PINCTRL_PIN(153, "EGPIO[0]"), + PINCTRL_PIN(154, "ARSTn"), + PINCTRL_PIN(155, "TRSTn"), + PINCTRL_PIN(156, "ASDI"), + PINCTRL_PIN(157, "USBm[2]"), + PINCTRL_PIN(158, "USBp[2]"), + PINCTRL_PIN(159, "WAITn"), + PINCTRL_PIN(160, "EGPIO[15]"), + PINCTRL_PIN(161, "gnd_ring"), + PINCTRL_PIN(162, "vdd_ring"), + PINCTRL_PIN(163, "EGPIO[14]"), + PINCTRL_PIN(164, "EGPIO[13]"), + PINCTRL_PIN(165, "EGPIO[12]"), + PINCTRL_PIN(166, "gnd_core"), + PINCTRL_PIN(167, "vdd_core"), + PINCTRL_PIN(168, "FGPIO[3]"), + PINCTRL_PIN(169, "FGPIO[2]"), + PINCTRL_PIN(170, "FGPIO[1]"), + PINCTRL_PIN(171, "gnd_ring"), + PINCTRL_PIN(172, "vdd_ring"), + PINCTRL_PIN(173, "CLD"), + PINCTRL_PIN(174, "CRS"), + PINCTRL_PIN(175, "TXERR"), + PINCTRL_PIN(176, "TXEN"), + PINCTRL_PIN(177, "MIITXD[0]"), + PINCTRL_PIN(178, "MIITXD[1]"), + PINCTRL_PIN(179, "MIITXD[2]"), + PINCTRL_PIN(180, "MIITXD[3]"), + PINCTRL_PIN(181, "TXCLK"), + PINCTRL_PIN(182, "RXERR"), + PINCTRL_PIN(183, "RXDVAL"), + PINCTRL_PIN(184, "MIIRXD[0]"), + PINCTRL_PIN(185, "MIIRXD[1]"), + PINCTRL_PIN(186, "MIIRXD[2]"), + PINCTRL_PIN(187, "gnd_ring"), + PINCTRL_PIN(188, "vdd_ring"), + PINCTRL_PIN(189, "MIIRXD[3]"), + PINCTRL_PIN(190, "RXCLK"), + PINCTRL_PIN(191, "MDIO"), + PINCTRL_PIN(192, "MDC"), + PINCTRL_PIN(193, "RDn"), + PINCTRL_PIN(194, "WRn"), + PINCTRL_PIN(195, "AD[16]"), + PINCTRL_PIN(196, "AD[17]"), + PINCTRL_PIN(197, "gnd_core"), + PINCTRL_PIN(198, "vdd_core"), + PINCTRL_PIN(199, "HGPIO[2]"), + PINCTRL_PIN(200, "HGPIO[3]"), + PINCTRL_PIN(201, "HGPIO[4]"), + PINCTRL_PIN(202, "HGPIO[5]"), + PINCTRL_PIN(203, "gnd_ring"), + PINCTRL_PIN(204, "vdd_ring"), + PINCTRL_PIN(205, "AD[18]"), + PINCTRL_PIN(206, "AD[19]"), + PINCTRL_PIN(207, "AD[20]"), + PINCTRL_PIN(208, "SDCLKEN"), +}; + +static const unsigned int ssp_ep9301_pins[] =3D { + 93, 94, 95, 96 +}; + +static const unsigned int ac97_ep9301_pins[] =3D { + 89, 92, 107, 154, 156 +}; + +/* + * Note: The EP9307 processor has one PWM with one output, PWMOUT. + * Note: The EP9301, EP9302, EP9312, and EP9315 processors each have two P= WMs with + * two outputs, PWMOUT and PWMO1. PWMO1 is an alternate function for EGPIO= 14. + */ +/* The GPIO14E (14) pin overlap with pwm1 */ +static const unsigned int pwm_9301_pins[] =3D { 163 }; + +static const unsigned int gpio1a_9301_pins[] =3D { 163 }; + +/* ep9301/9302 have only 4,5 pin of GPIO E Port exposed */ +static const unsigned int gpio4a_9301_pins[] =3D { 97, 98 }; + +/* ep9301/9302 have only 4,5 pin of GPIO G Port exposed */ +static const unsigned int gpio6a_9301_pins[] =3D { 87, 88 }; + +static const unsigned int gpio7a_9301_pins[] =3D { 199, 200, 201, 202 }; + +/* Groups for the ep9301/ep9302 SoC/package */ +static const struct ep93xx_pin_group ep9301_pin_groups[] =3D { + { + .name =3D "ssp", + .pins =3D ssp_ep9301_pins, + .num_pins =3D ARRAY_SIZE(ssp_ep9301_pins), + .mask =3D EP93XX_SYSCON_DEVCFG_I2SONSSP, + }, + { + .name =3D "i2s_on_ssp", + .pins =3D ssp_ep9301_pins, + .num_pins =3D ARRAY_SIZE(ssp_ep9301_pins), + .value =3D EP93XX_SYSCON_DEVCFG_I2SONSSP, + .mask =3D EP93XX_SYSCON_DEVCFG_I2SONSSP, + }, + { + .name =3D "ac97", + .pins =3D ac97_ep9301_pins, + .num_pins =3D ARRAY_SIZE(ac97_ep9301_pins), + .mask =3D EP93XX_SYSCON_DEVCFG_I2SONAC97, + }, + { + .name =3D "i2s_on_ac97", + .pins =3D ac97_ep9301_pins, + .num_pins =3D ARRAY_SIZE(ac97_ep9301_pins), + .value =3D EP93XX_SYSCON_DEVCFG_I2SONAC97, + .mask =3D EP93XX_SYSCON_DEVCFG_I2SONAC97, + }, + { + .name =3D "pwm1", + .pins =3D pwm_9301_pins, + .num_pins =3D ARRAY_SIZE(pwm_9301_pins), + .value =3D EP93XX_SYSCON_DEVCFG_PONG, + .mask =3D EP93XX_SYSCON_DEVCFG_PONG, + }, + { + .name =3D "gpio1agrp", + .pins =3D gpio1a_9301_pins, + .num_pins =3D ARRAY_SIZE(gpio1a_9301_pins), + /* Conflict with PWM1 */ + .mask =3D EP93XX_SYSCON_DEVCFG_PONG, + }, + { + .name =3D "gpio4agrp", + .pins =3D gpio4a_9301_pins, + .num_pins =3D ARRAY_SIZE(gpio4a_9301_pins), + .value =3D EP93XX_SYSCON_DEVCFG_EONIDE, + .mask =3D EP93XX_SYSCON_DEVCFG_EONIDE, + }, + { + .name =3D "gpio6agrp", + .pins =3D gpio6a_9301_pins, + .num_pins =3D ARRAY_SIZE(gpio6a_9301_pins), + .value =3D EP93XX_SYSCON_DEVCFG_GONIDE, + .mask =3D EP93XX_SYSCON_DEVCFG_GONIDE, + }, + { + .name =3D "gpio7agrp", + .pins =3D gpio7a_9301_pins, + .num_pins =3D ARRAY_SIZE(gpio7a_9301_pins), + .value =3D EP93XX_SYSCON_DEVCFG_HONIDE, + .mask =3D EP93XX_SYSCON_DEVCFG_HONIDE, + }, +}; + +static const struct pinctrl_pin_desc ep9307_pins[] =3D { + /* Row A */ + PINCTRL_PIN(0, "CSn[1]"), /* A1 */ + PINCTRL_PIN(1, "CSn[7]"), /* A2 */ + PINCTRL_PIN(2, "SDCLKEN"), /* A3 */ + PINCTRL_PIN(3, "DA[31]"), /* A4 */ + PINCTRL_PIN(4, "DA[29]"), /* A5 */ + PINCTRL_PIN(5, "DA[27]"), /* A6 */ + PINCTRL_PIN(6, "HGPIO[2]"), /* A7 */ + PINCTRL_PIN(7, "RDn"), /* A8 */ + PINCTRL_PIN(8, "MIIRXD[3]"), /* A9 */ + PINCTRL_PIN(9, "RXDVAL"), /* A10 */ + PINCTRL_PIN(10, "MIITXD[1]"), /* A11 */ + PINCTRL_PIN(11, "CRS"), /* A12 */ + PINCTRL_PIN(12, "FGPIO[7]"), /* A13 */ + PINCTRL_PIN(13, "FGPIO[0]"), /* A14 */ + PINCTRL_PIN(14, "WAITn"), /* A15 */ + PINCTRL_PIN(15, "USBm[2]"), /* A16 */ + PINCTRL_PIN(16, "ASDI"), /* A17 */ + /* Row B*/ + PINCTRL_PIN(17, "AD[25]"), /* B1 */ + PINCTRL_PIN(18, "CSn[2]"), /* B2 */ + PINCTRL_PIN(19, "CSn[6]"), /* B3 */ + PINCTRL_PIN(20, "AD[20]"), /* B4 */ + PINCTRL_PIN(21, "DA[30]"), /* B5 */ + PINCTRL_PIN(22, "AD[18]"), /* B6 */ + PINCTRL_PIN(23, "HGPIO[3]"), /* B7 */ + PINCTRL_PIN(24, "AD[17]"), /* B8 */ + PINCTRL_PIN(25, "RXCLK"), /* B9 */ + PINCTRL_PIN(26, "MIIRXD[1]"), /* B10 */ + PINCTRL_PIN(27, "MIITXD[2]"), /* B11 */ + PINCTRL_PIN(28, "TXEN"), /* B12 */ + PINCTRL_PIN(29, "FGPIO[5]"), /* B13 */ + PINCTRL_PIN(30, "EGPIO[15]"), /* B14 */ + PINCTRL_PIN(31, "USBp[2]"), /* B15 */ + PINCTRL_PIN(32, "ARSTn"), /* B16 */ + PINCTRL_PIN(33, "ADC_VDD"), /* B17 */ + /* Row C*/ + PINCTRL_PIN(34, "AD[23]"), /* C1 */ + PINCTRL_PIN(35, "DA[26]"), /* C2 */ + PINCTRL_PIN(36, "CSn[3]"), /* C3 */ + PINCTRL_PIN(37, "DA[25]"), /* C4 */ + PINCTRL_PIN(38, "AD[24]"), /* C5 */ + PINCTRL_PIN(39, "AD[19]"), /* C6 */ + PINCTRL_PIN(40, "HGPIO[5]"), /* C7 */ + PINCTRL_PIN(41, "WRn"), /* C8 */ + PINCTRL_PIN(42, "MDIO"), /* C9 */ + PINCTRL_PIN(43, "MIIRXD[2]"), /* C10 */ + PINCTRL_PIN(44, "TXCLK"), /* C11 */ + PINCTRL_PIN(45, "MIITXD[0]"), /* C12 */ + PINCTRL_PIN(46, "CLD"), /* C13 */ + PINCTRL_PIN(47, "EGPIO[13]"), /* C14 */ + PINCTRL_PIN(48, "TRSTn"), /* C15 */ + PINCTRL_PIN(49, "Xp"), /* C16 */ + PINCTRL_PIN(50, "Xm"), /* C17 */ + /* Row D*/ + PINCTRL_PIN(51, "SDCSn[3]"), /* D1 */ + PINCTRL_PIN(52, "DA[23]"), /* D2 */ + PINCTRL_PIN(53, "SDCLK"), /* D3 */ + PINCTRL_PIN(54, "DA[24]"), /* D4 */ + PINCTRL_PIN(55, "HGPIO[7]"), /* D5 */ + PINCTRL_PIN(56, "HGPIO[6]"), /* D6 */ + PINCTRL_PIN(57, "A[28]"), /* D7 */ + PINCTRL_PIN(58, "HGPIO[4]"), /* D8 */ + PINCTRL_PIN(59, "AD[16]"), /* D9 */ + PINCTRL_PIN(60, "MDC"), /* D10 */ + PINCTRL_PIN(61, "RXERR"), /* D11 */ + PINCTRL_PIN(62, "MIITXD[3]"), /* D12 */ + PINCTRL_PIN(63, "EGPIO[12]"), /* D13 */ + PINCTRL_PIN(64, "EGPIO[1]"), /* D14 */ + PINCTRL_PIN(65, "EGPIO[0]"), /* D15 */ + PINCTRL_PIN(66, "Ym"), /* D16 */ + PINCTRL_PIN(67, "Yp"), /* D17 */ + /* Row E */ + PINCTRL_PIN(68, "SDCSn[2]"), /* E1 */ + PINCTRL_PIN(69, "SDWEN"), /* E2 */ + PINCTRL_PIN(70, "DA[22]"), /* E3 */ + PINCTRL_PIN(71, "AD[3]"), /* E4 */ + PINCTRL_PIN(72, "DA[15]"), /* E5 */ + PINCTRL_PIN(73, "AD[21]"), /* E6 */ + PINCTRL_PIN(74, "DA[17]"), /* E7 */ + PINCTRL_PIN(75, "vddr"), /* E8 */ + PINCTRL_PIN(76, "vddr"), /* E9 */ + PINCTRL_PIN(77, "vddr"), /* E10 */ + PINCTRL_PIN(78, "MIIRXD[0]"), /* E11 */ + PINCTRL_PIN(79, "TXERR"), /* E12 */ + PINCTRL_PIN(80, "EGPIO[2]"), /* E13 */ + PINCTRL_PIN(81, "EGPIO[4]"), /* E14 */ + PINCTRL_PIN(82, "EGPIO[3]"), /* E15 */ + PINCTRL_PIN(83, "sXp"), /* E16 */ + PINCTRL_PIN(84, "sXm"), /* E17 */ + /* Row F*/ + PINCTRL_PIN(85, "RASn"), /* F1 */ + PINCTRL_PIN(86, "SDCSn[1]"), /* F2 */ + PINCTRL_PIN(87, "SDCSn[0]"), /* F3 */ + PINCTRL_PIN(88, "DQMn[3]"), /* F4 */ + PINCTRL_PIN(89, "AD[5]"), /* F5 */ + PINCTRL_PIN(90, "gndr"), /* F6 */ + PINCTRL_PIN(91, "gndr"), /* F7 */ + PINCTRL_PIN(92, "gndr"), /* F8 */ + PINCTRL_PIN(93, "vddc"), /* F9 */ + PINCTRL_PIN(94, "vddc"), /* F10 */ + PINCTRL_PIN(95, "gndr"), /* F11 */ + PINCTRL_PIN(96, "EGPIO[7]"), /* F12 */ + PINCTRL_PIN(97, "EGPIO[5]"), /* F13 */ + PINCTRL_PIN(98, "ADC GND"), /* F14 */ + PINCTRL_PIN(99, "EGPIO[6]"), /* F15 */ + PINCTRL_PIN(100, "sYm"), /* F16 */ + PINCTRL_PIN(101, "syp"), /* F17 */ + /* Row G */ + PINCTRL_PIN(102, "DQMn[0]"), /* G1 */ + PINCTRL_PIN(103, "CASn"), /* G2 */ + PINCTRL_PIN(104, "DA[21]"), /* G3 */ + PINCTRL_PIN(105, "AD[22]"), /* G4 */ + PINCTRL_PIN(106, "vddr"), /* G5 */ + PINCTRL_PIN(107, "gndr"), /* G6 */ + PINCTRL_PIN(108, "gndr"), /* G12 */ + PINCTRL_PIN(109, "EGPIO[9]"), /* G13 */ + PINCTRL_PIN(110, "EGPIO[10]"), /* G14 */ + PINCTRL_PIN(111, "EGPIO[11]"), /* G15 */ + PINCTRL_PIN(112, "RTCXTALO"), /* G16 */ + PINCTRL_PIN(113, "RTCXTALI"), /* G17 */ + /* Row H */ + PINCTRL_PIN(114, "DA[18]"), /* H1 */ + PINCTRL_PIN(115, "DA[20]"), /* H2 */ + PINCTRL_PIN(116, "DA[19]"), /* H3 */ + PINCTRL_PIN(117, "DA[16]"), /* H4 */ + PINCTRL_PIN(118, "vddr"), /* H5 */ + PINCTRL_PIN(119, "vddc"), /* H6 */ + PINCTRL_PIN(120, "gndc"), /* H7 */ + PINCTRL_PIN(121, "gndc"), /* H9 */ + PINCTRL_PIN(122, "gndc"), /* H10 */ + PINCTRL_PIN(123, "gndr"), /* H12 */ + PINCTRL_PIN(124, "vddr"), /* H13 */ + PINCTRL_PIN(125, "EGPIO[8]"), /* H14 */ + PINCTRL_PIN(126, "PRSTN"), /* H15 */ + PINCTRL_PIN(127, "COL[7]"), /* H16 */ + PINCTRL_PIN(128, "RSTON"), /* H17 */ + /* Row J */ + PINCTRL_PIN(129, "AD[6]"), /* J1 */ + PINCTRL_PIN(130, "DA[14]"), /* J2 */ + PINCTRL_PIN(131, "AD[7]"), /* J3 */ + PINCTRL_PIN(132, "DA[13]"), /* J4 */ + PINCTRL_PIN(133, "vddr"), /* J5 */ + PINCTRL_PIN(134, "vddc"), /* J6 */ + PINCTRL_PIN(135, "gndc"), /* J8 */ + PINCTRL_PIN(136, "gndc"), /* J10 */ + PINCTRL_PIN(137, "vddc"), /* J12 */ + PINCTRL_PIN(138, "vddr"), /* J13 */ + PINCTRL_PIN(139, "COL[5]"), /* J14 */ + PINCTRL_PIN(140, "COL[6]"), /* J15 */ + PINCTRL_PIN(141, "CSn[0]"), /* J16 */ + PINCTRL_PIN(142, "COL[3]"), /* J17 */ + /* Row K */ + PINCTRL_PIN(143, "AD[4]"), /* K1 */ + PINCTRL_PIN(144, "DA[12]"), /* K2 */ + PINCTRL_PIN(145, "DA[10]"), /* K3 */ + PINCTRL_PIN(146, "DA[11]"), /* K4 */ + PINCTRL_PIN(147, "vddr"), /* K5 */ + PINCTRL_PIN(148, "gndr"), /* K6 */ + PINCTRL_PIN(149, "gndc"), /* K8 */ + PINCTRL_PIN(150, "gndc"), /* K9 */ + PINCTRL_PIN(151, "gndc"), /* K10 */ + PINCTRL_PIN(152, "vddc"), /* K12 */ + PINCTRL_PIN(153, "COL[4]"), /* K13 */ + PINCTRL_PIN(154, "PLL_VDD"), /* K14 */ + PINCTRL_PIN(155, "COL[2]"), /* K15 */ + PINCTRL_PIN(156, "COL[1]"), /* K16 */ + PINCTRL_PIN(157, "COL[0]"), /* K17 */ + /* Row L */ + PINCTRL_PIN(158, "DA[9]"), /* L1 */ + PINCTRL_PIN(159, "AD[2]"), /* L2 */ + PINCTRL_PIN(160, "AD[1]"), /* L3 */ + PINCTRL_PIN(161, "DA[8]"), /* L4 */ + PINCTRL_PIN(162, "BLANK"), /* L5 */ + PINCTRL_PIN(163, "gndr"), /* L6 */ + PINCTRL_PIN(164, "gndr"), /* L7 */ + PINCTRL_PIN(165, "ROW[7]"), /* L8 */ + PINCTRL_PIN(166, "ROW[5]"), /* L9 */ + PINCTRL_PIN(167, "PLL GND"), /* L10 */ + PINCTRL_PIN(168, "XTALI"), /* L11 */ + PINCTRL_PIN(169, "XTALO"), /* L12 */ + /* Row M */ + PINCTRL_PIN(170, "BRIGHT"), /* M1 */ + PINCTRL_PIN(171, "AD[0]"), /* M2 */ + PINCTRL_PIN(172, "DQMn[1]"), /* M3 */ + PINCTRL_PIN(173, "DQMn[2]"), /* M4 */ + PINCTRL_PIN(174, "P[17]"), /* M5 */ + PINCTRL_PIN(175, "gndr"), /* M6 */ + PINCTRL_PIN(176, "gndr"), /* M7 */ + PINCTRL_PIN(177, "vddc"), /* M8 */ + PINCTRL_PIN(178, "vddc"), /* M9 */ + PINCTRL_PIN(179, "gndr"), /* M10 */ + PINCTRL_PIN(180, "gndr"), /* M11 */ + PINCTRL_PIN(181, "ROW[6]"), /* M12 */ + PINCTRL_PIN(182, "ROW[4]"), /* M13 */ + PINCTRL_PIN(183, "ROW[1]"), /* M14 */ + PINCTRL_PIN(184, "ROW[0]"), /* M15 */ + PINCTRL_PIN(185, "ROW[3]"), /* M16 */ + PINCTRL_PIN(186, "ROW[2]"), /* M17 */ + /* Row N */ + PINCTRL_PIN(187, "P[14]"), /* N1 */ + PINCTRL_PIN(188, "P[16]"), /* N2 */ + PINCTRL_PIN(189, "P[15]"), /* N3 */ + PINCTRL_PIN(190, "P[13]"), /* N4 */ + PINCTRL_PIN(191, "P[12]"), /* N5 */ + PINCTRL_PIN(192, "DA[5]"), /* N6 */ + PINCTRL_PIN(193, "vddr"), /* N7 */ + PINCTRL_PIN(194, "vddr"), /* N8 */ + PINCTRL_PIN(195, "vddr"), /* N9 */ + PINCTRL_PIN(196, "vddr"), /* N10 */ + PINCTRL_PIN(197, "EECLK"), /* N11 */ + PINCTRL_PIN(198, "ASDO"), /* N12 */ + PINCTRL_PIN(199, "CTSn"), /* N13 */ + PINCTRL_PIN(200, "RXD[0]"), /* N14 */ + PINCTRL_PIN(201, "TXD[0]"), /* N15 */ + PINCTRL_PIN(202, "TXD[1]"), /* N16 */ + PINCTRL_PIN(203, "TXD[2]"), /* N17 */ + /* Row P */ + PINCTRL_PIN(204, "SPCLK"), /* P1 */ + PINCTRL_PIN(205, "P[10]"), /* P2 */ + PINCTRL_PIN(206, "P[11]"), /* P3 */ + PINCTRL_PIN(207, "P[3]"), /* P4 */ + PINCTRL_PIN(208, "AD[15]"), /* P5 */ + PINCTRL_PIN(209, "AD[13]"), /* P6 */ + PINCTRL_PIN(210, "AD[12]"), /* P7 */ + PINCTRL_PIN(211, "DA[2]"), /* P8 */ + PINCTRL_PIN(212, "AD[8]"), /* P9 */ + PINCTRL_PIN(213, "TCK"), /* P10 */ + PINCTRL_PIN(214, "BOOT[1]"), /* P11 */ + PINCTRL_PIN(215, "EEDAT"), /* P12 */ + PINCTRL_PIN(216, "GRLED"), /* P13 */ + PINCTRL_PIN(217, "RDLED"), /* P14 */ + PINCTRL_PIN(218, "GGPIO[2]"), /* P15 */ + PINCTRL_PIN(219, "RXD[1]"), /* P16 */ + PINCTRL_PIN(220, "RXD[2]"), /* P17 */ + /* Row R */ + PINCTRL_PIN(221, "P[9]"), /* R1 */ + PINCTRL_PIN(222, "HSYNC"), /* R2 */ + PINCTRL_PIN(223, "P[6]"), /* R3 */ + PINCTRL_PIN(224, "P[5]"), /* R4 */ + PINCTRL_PIN(225, "P[0]"), /* R5 */ + PINCTRL_PIN(226, "AD[14]"), /* R6 */ + PINCTRL_PIN(227, "DA[4]"), /* R7 */ + PINCTRL_PIN(228, "DA[1]"), /* R8 */ + PINCTRL_PIN(229, "DTRn"), /* R9 */ + PINCTRL_PIN(230, "TDI"), /* R10 */ + PINCTRL_PIN(231, "BOOT[0]"), /* R11 */ + PINCTRL_PIN(232, "ASYNC"), /* R12 */ + PINCTRL_PIN(233, "SSPTX[1]"), /* R13 */ + PINCTRL_PIN(234, "PWMOUT"), /* R14 */ + PINCTRL_PIN(235, "USBm[0]"), /* R15 */ + PINCTRL_PIN(236, "ABITCLK"), /* R16 */ + PINCTRL_PIN(237, "USBp[0]"), /* R17 */ + /* Row T */ + PINCTRL_PIN(238, "NC"), /* T1 */ + PINCTRL_PIN(239, "NC"), /* T2 */ + PINCTRL_PIN(240, "V_CSYNC"), /* T3 */ + PINCTRL_PIN(241, "P[7]"), /* T4 */ + PINCTRL_PIN(242, "P[2]"), /* T5 */ + PINCTRL_PIN(243, "DA[7]"), /* T6 */ + PINCTRL_PIN(244, "AD[11]"), /* T7 */ + PINCTRL_PIN(245, "AD[9]"), /* T8 */ + PINCTRL_PIN(246, "DSRn"), /* T9 */ + PINCTRL_PIN(247, "TMS"), /* T10 */ + PINCTRL_PIN(248, "gndr"), /* T11 */ + PINCTRL_PIN(249, "SFRM[1]"), /* T12 */ + PINCTRL_PIN(250, "INT[2]"), /* T13 */ + PINCTRL_PIN(251, "INT[0]"), /* T14 */ + PINCTRL_PIN(252, "USBp[1]"), /* T15 */ + PINCTRL_PIN(253, "NC"), /* T16 */ + PINCTRL_PIN(254, "NC"), /* T17 */ + /* Row U */ + PINCTRL_PIN(255, "NC"), /* U1 */ + PINCTRL_PIN(256, "NC"), /* U2 */ + PINCTRL_PIN(257, "P[8]"), /* U3 */ + PINCTRL_PIN(258, "P[4]"), /* U4 */ + PINCTRL_PIN(259, "P[1]"), /* U5 */ + PINCTRL_PIN(260, "DA[6]"), /* U6 */ + PINCTRL_PIN(261, "DA[3]"), /* U7 */ + PINCTRL_PIN(262, "AD[10]"), /* U8 */ + PINCTRL_PIN(263, "DA[0]"), /* U9 */ + PINCTRL_PIN(264, "TDO"), /* U10 */ + PINCTRL_PIN(265, "NC"), /* U11 */ + PINCTRL_PIN(266, "SCLK[1]"), /* U12 */ + PINCTRL_PIN(267, "SSPRX[1]"), /* U13 */ + PINCTRL_PIN(268, "INT[1]"), /* U14 */ + PINCTRL_PIN(269, "RTSn"), /* U15 */ + PINCTRL_PIN(270, "USBm[1]"), /* U16 */ + PINCTRL_PIN(271, "NC"), /* U17 */ +}; + +static const unsigned int ssp_ep9307_pins[] =3D { + 233, 249, 266, 267 +}; + +static const unsigned int ac97_ep9307_pins[] =3D { + 16, 32, 198, 232, 236 +}; + +/* I can't find info on those - it's some internal state */ +static const unsigned int raster_on_sdram0_pins[] =3D { +}; + +static const unsigned int raster_on_sdram3_pins[] =3D { +}; + +/* ROW[N] */ +static const unsigned int gpio2a_9307_pins[] =3D { + 165, 166, 181, 182, 183, 184, 185, 186 +}; + +/* COL[N] */ +static const unsigned int gpio3a_9307_pins[] =3D { + 127, 139, 140, 142, 153, 155, 156, 157 +}; + +static const unsigned int keypad_9307_pins[] =3D { + 127, 139, 140, 142, 153, 155, 156, 157, + 165, 166, 181, 182, 183, 184, 185, 186 +}; + +/* ep9307 have only 4,5 pin of GPIO E Port exposed */ +static const unsigned int gpio4a_9307_pins[] =3D { 216, 217 }; + +/* ep9307 have only 2 pin of GPIO G Port exposed */ +static const unsigned int gpio6a_9307_pins[] =3D { 219 }; + +static const unsigned int gpio7a_9307_pins[] =3D { 7, 24, 41, 56, 57, 59 }; + +static const struct ep93xx_pin_group ep9307_pin_groups[] =3D { + { + .name =3D "ssp", + .pins =3D ssp_ep9307_pins, + .num_pins =3D ARRAY_SIZE(ssp_ep9307_pins), + .mask =3D EP93XX_SYSCON_DEVCFG_I2SONSSP, + }, + { + .name =3D "i2s_on_ssp", + .pins =3D ssp_ep9307_pins, + .num_pins =3D ARRAY_SIZE(ssp_ep9307_pins), + .value =3D EP93XX_SYSCON_DEVCFG_I2SONSSP, + .mask =3D EP93XX_SYSCON_DEVCFG_I2SONSSP, + }, + { + .name =3D "ac97", + .pins =3D ac97_ep9307_pins, + .num_pins =3D ARRAY_SIZE(ac97_ep9307_pins), + .mask =3D EP93XX_SYSCON_DEVCFG_I2SONAC97, + }, + { + .name =3D "i2s_on_ac97", + .pins =3D ac97_ep9307_pins, + .num_pins =3D ARRAY_SIZE(ac97_ep9307_pins), + .value =3D EP93XX_SYSCON_DEVCFG_I2SONAC97, + .mask =3D EP93XX_SYSCON_DEVCFG_I2SONAC97, + }, + { + .name =3D "rasteronsdram0grp", + .pins =3D raster_on_sdram0_pins, + .num_pins =3D ARRAY_SIZE(raster_on_sdram0_pins), + .mask =3D EP93XX_SYSCON_DEVCFG_RASONP3, + }, + { + .name =3D "rasteronsdram3grp", + .pins =3D raster_on_sdram3_pins, + .num_pins =3D ARRAY_SIZE(raster_on_sdram3_pins), + .value =3D EP93XX_SYSCON_DEVCFG_RASONP3, + .mask =3D EP93XX_SYSCON_DEVCFG_RASONP3, + }, + { + .name =3D "gpio2agrp", + .pins =3D gpio2a_9307_pins, + .num_pins =3D ARRAY_SIZE(gpio2a_9307_pins), + .value =3D EP93XX_SYSCON_DEVCFG_GONK, + .mask =3D EP93XX_SYSCON_DEVCFG_GONK, + }, + { + .name =3D "gpio3agrp", + .pins =3D gpio3a_9307_pins, + .num_pins =3D ARRAY_SIZE(gpio3a_9307_pins), + .value =3D EP93XX_SYSCON_DEVCFG_GONK, + .mask =3D EP93XX_SYSCON_DEVCFG_GONK, + }, + { + .name =3D "keypadgrp", + .pins =3D keypad_9307_pins, + .num_pins =3D ARRAY_SIZE(keypad_9307_pins), + .mask =3D EP93XX_SYSCON_DEVCFG_GONK, + }, + { + .name =3D "gpio4agrp", + .pins =3D gpio4a_9307_pins, + .num_pins =3D ARRAY_SIZE(gpio4a_9307_pins), + .mask =3D EP93XX_SYSCON_DEVCFG_EONIDE, + }, + { + .name =3D "gpio6agrp", + .pins =3D gpio6a_9307_pins, + .num_pins =3D ARRAY_SIZE(gpio6a_9307_pins), + .value =3D EP93XX_SYSCON_DEVCFG_GONIDE, + .mask =3D EP93XX_SYSCON_DEVCFG_GONIDE, + }, + { + .name =3D "gpio7agrp", + .pins =3D gpio7a_9307_pins, + .num_pins =3D ARRAY_SIZE(gpio7a_9307_pins), + .value =3D EP93XX_SYSCON_DEVCFG_HONIDE, + .mask =3D EP93XX_SYSCON_DEVCFG_HONIDE, + }, +}; + +/* ep9312, ep9315 */ +static const struct pinctrl_pin_desc ep9312_pins[] =3D { + /* Row A */ + PINCTRL_PIN(0, "CSN[7]"), /* A1 */ + PINCTRL_PIN(1, "DA[28]"), /* A2 */ + PINCTRL_PIN(2, "AD[18]"), /* A3 */ + PINCTRL_PIN(3, "DD[8]"), /* A4 */ + PINCTRL_PIN(4, "DD[4]"), /* A5 */ + PINCTRL_PIN(5, "AD[17]"), /* A6 */ + PINCTRL_PIN(6, "RDN"), /* A7 */ + PINCTRL_PIN(7, "RXCLK"), /* A8 */ + PINCTRL_PIN(8, "MIIRXD[0]"), /* A9 */ + PINCTRL_PIN(9, "RXDVAL"), /* A10 */ + PINCTRL_PIN(10, "MIITXD[2]"), /* A11 */ + PINCTRL_PIN(11, "TXERR"), /* A12 */ + PINCTRL_PIN(12, "CLD"), /* A13 */ + PINCTRL_PIN(13, "NC"), /* A14 */ + PINCTRL_PIN(14, "NC"), /* A15 */ + PINCTRL_PIN(15, "NC"), /* A16 */ + PINCTRL_PIN(16, "EGPIO[12]"), /* A17 */ + PINCTRL_PIN(17, "EGPIO[15]"), /* A18 */ + PINCTRL_PIN(18, "NC"), /* A19 */ + PINCTRL_PIN(19, "NC"), /* A20 */ + /* Row B */ + PINCTRL_PIN(20, "CSN[2]"), /* B1 */ + PINCTRL_PIN(21, "DA[31]"), /* B2 */ + PINCTRL_PIN(22, "DA[30]"), /* B3 */ + PINCTRL_PIN(23, "DA[27]"), /* B4 */ + PINCTRL_PIN(24, "DD[7]"), /* B5 */ + PINCTRL_PIN(25, "DD[3]"), /* B6 */ + PINCTRL_PIN(26, "WRN"), /* B7 */ + PINCTRL_PIN(27, "MDIO"), /* B8 */ + PINCTRL_PIN(28, "MIIRXD[1]"), /* B9 */ + PINCTRL_PIN(29, "RXERR"), /* B10 */ + PINCTRL_PIN(30, "MIITXD[1]"), /* B11 */ + PINCTRL_PIN(31, "CRS"), /* B12 */ + PINCTRL_PIN(32, "NC"), /* B13 */ + PINCTRL_PIN(33, "NC"), /* B14 */ + PINCTRL_PIN(34, "NC"), /* B15 */ + PINCTRL_PIN(35, "NC"), /* B16 */ + PINCTRL_PIN(36, "EGPIO[13]"), /* B17 */ + PINCTRL_PIN(37, "NC"), /* B18 */ + PINCTRL_PIN(38, "WAITN"), /* B19 */ + PINCTRL_PIN(39, "TRSTN"), /* B20 */ + /* Row C */ + PINCTRL_PIN(40, "CSN[1]"), /* C1 */ + PINCTRL_PIN(41, "CSN[3]"), /* C2 */ + PINCTRL_PIN(42, "AD[20]"), /* C3 */ + PINCTRL_PIN(43, "DA[29]"), /* C4 */ + PINCTRL_PIN(44, "DD[10]"), /* C5 */ + PINCTRL_PIN(45, "DD[6]"), /* C6 */ + PINCTRL_PIN(46, "DD[2]"), /* C7 */ + PINCTRL_PIN(47, "MDC"), /* C8 */ + PINCTRL_PIN(48, "MIIRXD[3]"), /* C9 */ + PINCTRL_PIN(49, "TXCLK"), /* C10 */ + PINCTRL_PIN(50, "MIITXD[0]"), /* C11 */ + PINCTRL_PIN(51, "NC"), /* C12 */ + PINCTRL_PIN(52, "NC"), /* C13 */ + PINCTRL_PIN(53, "NC"), /* C14 */ + PINCTRL_PIN(54, "NC"), /* C15 */ + PINCTRL_PIN(55, "NC"), /* C16 */ + PINCTRL_PIN(56, "NC"), /* C17 */ + PINCTRL_PIN(57, "USBP[2]"), /* C18 */ + PINCTRL_PIN(58, "IORDY"), /* C19 */ + PINCTRL_PIN(59, "DMACKN"), /* C20 */ + /* Row D */ + PINCTRL_PIN(60, "AD[24]"), /* D1 */ + PINCTRL_PIN(61, "DA[25]"), /* D2 */ + PINCTRL_PIN(62, "DD[11]"), /* D3 */ + PINCTRL_PIN(63, "SDCLKEN"), /* D4 */ + PINCTRL_PIN(64, "AD[19]"), /* D5 */ + PINCTRL_PIN(65, "DD[9]"), /* D6 */ + PINCTRL_PIN(66, "DD[5]"), /* D7 */ + PINCTRL_PIN(67, "AD[16]"), /* D8 */ + PINCTRL_PIN(68, "MIIRXD[2]"), /* D9 */ + PINCTRL_PIN(69, "MIITXD[3]"), /* D10 */ + PINCTRL_PIN(70, "TXEN"), /* D11 */ + PINCTRL_PIN(71, "NC"), /* D12 */ + PINCTRL_PIN(72, "NC"), /* D13 */ + PINCTRL_PIN(73, "NC"), /* D14 */ + PINCTRL_PIN(74, "EGPIO[14]"), /* D15 */ + PINCTRL_PIN(75, "NC"), /* D16 */ + PINCTRL_PIN(76, "USBM[2]"), /* D17 */ + PINCTRL_PIN(77, "ARSTN"), /* D18 */ + PINCTRL_PIN(78, "DIORN"), /* D19 */ + PINCTRL_PIN(79, "EGPIO[1]"), /* D20 */ + /* Row E */ + PINCTRL_PIN(80, "AD[23]"), /* E1 */ + PINCTRL_PIN(81, "DA[23]"), /* E2 */ + PINCTRL_PIN(82, "DA[26]"), /* E3 */ + PINCTRL_PIN(83, "CSN[6]"), /* E4 */ + PINCTRL_PIN(84, "GND"), /* E5 */ + PINCTRL_PIN(85, "GND"), /* E6 */ + PINCTRL_PIN(86, "CVDD"), /* E7 */ + PINCTRL_PIN(87, "CVDD"), /* E8 */ + PINCTRL_PIN(88, "RVDD"), /* E9 */ + PINCTRL_PIN(89, "GND"), /* E10 */ + PINCTRL_PIN(90, "GND"), /* E11 */ + PINCTRL_PIN(91, "RVDD"), /* E12 */ + PINCTRL_PIN(92, "CVDD"), /* E13 */ + PINCTRL_PIN(93, "CVDD"), /* E14 */ + PINCTRL_PIN(94, "GND"), /* E15 */ + PINCTRL_PIN(95, "ASDI"), /* E16 */ + PINCTRL_PIN(96, "DIOWN"), /* E17 */ + PINCTRL_PIN(97, "EGPIO[0]"), /* E18 */ + PINCTRL_PIN(98, "EGPIO[3]"), /* E19 */ + PINCTRL_PIN(99, "EGPIO[5]"), /* E20 */ + /* Row F */ + PINCTRL_PIN(100, "SDCSN[3]"), /* F1 */ + PINCTRL_PIN(101, "DA[22]"), /* F2 */ + PINCTRL_PIN(102, "DA[24]"), /* F3 */ + PINCTRL_PIN(103, "AD[25]"), /* F4 */ + PINCTRL_PIN(104, "RVDD"), /* F5 */ + PINCTRL_PIN(105, "GND"), /* F6 */ + PINCTRL_PIN(106, "CVDD"), /* F7 */ + PINCTRL_PIN(107, "CVDD"), /* F14 */ + PINCTRL_PIN(108, "GND"), /* F15 */ + PINCTRL_PIN(109, "GND"), /* F16 */ + PINCTRL_PIN(110, "EGPIO[2]"), /* F17 */ + PINCTRL_PIN(111, "EGPIO[4]"), /* F18 */ + PINCTRL_PIN(112, "EGPIO[6]"), /* F19 */ + PINCTRL_PIN(113, "EGPIO[8]"), /* F20 */ + /* Row G */ + PINCTRL_PIN(114, "SDCSN[0]"), /* G1 */ + PINCTRL_PIN(115, "SDCSN[1]"), /* G2 */ + PINCTRL_PIN(116, "SDWEN"), /* G3 */ + PINCTRL_PIN(117, "SDCLK"), /* G4 */ + PINCTRL_PIN(118, "RVDD"), /* G5 */ + PINCTRL_PIN(119, "RVDD"), /* G6 */ + PINCTRL_PIN(120, "RVDD"), /* G15 */ + PINCTRL_PIN(121, "RVDD"), /* G16 */ + PINCTRL_PIN(122, "EGPIO[7]"), /* G17 */ + PINCTRL_PIN(123, "EGPIO[9]"), /* G18 */ + PINCTRL_PIN(124, "EGPIO[10]"), /* G19 */ + PINCTRL_PIN(125, "EGPIO[11]"), /* G20 */ + /* Row H */ + PINCTRL_PIN(126, "DQMN[3]"), /* H1 */ + PINCTRL_PIN(127, "CASN"), /* H2 */ + PINCTRL_PIN(128, "RASN"), /* H3 */ + PINCTRL_PIN(129, "SDCSN[2]"), /* H4 */ + PINCTRL_PIN(130, "CVDD"), /* H5 */ + PINCTRL_PIN(131, "GND"), /* H8 */ + PINCTRL_PIN(132, "GND"), /* H9 */ + PINCTRL_PIN(133, "GND"), /* H10 */ + PINCTRL_PIN(134, "GND"), /* H11 */ + PINCTRL_PIN(135, "GND"), /* H12 */ + PINCTRL_PIN(136, "GND"), /* H13 */ + PINCTRL_PIN(137, "RVDD"), /* H16 */ + PINCTRL_PIN(138, "RTCXTALO"), /* H17 */ + PINCTRL_PIN(139, "ADC_VDD"), /* H18 */ + PINCTRL_PIN(140, "ADC_GND"), /* H19 */ + PINCTRL_PIN(141, "XP"), /* H20 */ + /* Row J */ + PINCTRL_PIN(142, "DA[21]"), /* J1 */ + PINCTRL_PIN(143, "DQMN[0]"), /* J2 */ + PINCTRL_PIN(144, "DQMN[1]"), /* J3 */ + PINCTRL_PIN(145, "DQMN[2]"), /* J4 */ + PINCTRL_PIN(146, "GND"), /* J5 */ + PINCTRL_PIN(147, "GND"), /* J8 */ + PINCTRL_PIN(148, "GND"), /* J9 */ + PINCTRL_PIN(149, "GND"), /* J10 */ + PINCTRL_PIN(150, "GND"), /* J11 */ + PINCTRL_PIN(151, "GND"), /* J12 */ + PINCTRL_PIN(152, "GND"), /* J13 */ + PINCTRL_PIN(153, "CVDD"), /* J16 */ + PINCTRL_PIN(154, "RTCXTALI"), /* J17 */ + PINCTRL_PIN(155, "XM"), /* J18 */ + PINCTRL_PIN(156, "YP"), /* J19 */ + PINCTRL_PIN(157, "YM"), /* J20 */ + /* Row K */ + PINCTRL_PIN(158, "AD[22]"), /* K1 */ + PINCTRL_PIN(159, "DA[20]"), /* K2 */ + PINCTRL_PIN(160, "AD[21]"), /* K3 */ + PINCTRL_PIN(161, "DA[19]"), /* K4 */ + PINCTRL_PIN(162, "RVDD"), /* K5 */ + PINCTRL_PIN(163, "GND"), /* K8 */ + PINCTRL_PIN(164, "GND"), /* K9 */ + PINCTRL_PIN(165, "GND"), /* K10 */ + PINCTRL_PIN(166, "GND"), /* K11 */ + PINCTRL_PIN(167, "GND"), /* K12 */ + PINCTRL_PIN(168, "GND"), /* K13 */ + PINCTRL_PIN(169, "CVDD"), /* K16 */ + PINCTRL_PIN(170, "SYM"), /* K17 */ + PINCTRL_PIN(171, "SYP"), /* K18 */ + PINCTRL_PIN(172, "SXM"), /* K19 */ + PINCTRL_PIN(173, "SXP"), /* K20 */ + /* Row L */ + PINCTRL_PIN(174, "DA[18]"), /* L1 */ + PINCTRL_PIN(175, "DA[17]"), /* L2 */ + PINCTRL_PIN(176, "DA[16]"), /* L3 */ + PINCTRL_PIN(177, "DA[15]"), /* L4 */ + PINCTRL_PIN(178, "GND"), /* L5 */ + PINCTRL_PIN(179, "GND"), /* L8 */ + PINCTRL_PIN(180, "GND"), /* L9 */ + PINCTRL_PIN(181, "GND"), /* L10 */ + PINCTRL_PIN(182, "GND"), /* L11 */ + PINCTRL_PIN(183, "GND"), /* L12 */ + PINCTRL_PIN(184, "GND"), /* L13 */ + PINCTRL_PIN(185, "CVDD"), /* L16 */ + PINCTRL_PIN(186, "COL[5]"), /* L17 */ + PINCTRL_PIN(187, "COL[7]"), /* L18 */ + PINCTRL_PIN(188, "RSTON"), /* L19 */ + PINCTRL_PIN(189, "PRSTN"), /* L20 */ + /* Row M */ + PINCTRL_PIN(190, "AD[7]"), /* M1 */ + PINCTRL_PIN(191, "DA[14]"), /* M2 */ + PINCTRL_PIN(192, "AD[6]"), /* M3 */ + PINCTRL_PIN(193, "AD[5]"), /* M4 */ + PINCTRL_PIN(194, "CVDD"), /* M5 */ + PINCTRL_PIN(195, "GND"), /* M8 */ + PINCTRL_PIN(196, "GND"), /* M9 */ + PINCTRL_PIN(197, "GND"), /* M10 */ + PINCTRL_PIN(198, "GND"), /* M11 */ + PINCTRL_PIN(199, "GND"), /* M12 */ + PINCTRL_PIN(200, "GND"), /* M13 */ + PINCTRL_PIN(201, "GND"), /* M16 */ + PINCTRL_PIN(202, "COL[4]"), /* M17 */ + PINCTRL_PIN(203, "COL[3]"), /* M18 */ + PINCTRL_PIN(204, "COL[6]"), /* M19 */ + PINCTRL_PIN(205, "CSN[0]"), /* M20 */ + /* Row N */ + PINCTRL_PIN(206, "DA[13]"), /* N1 */ + PINCTRL_PIN(207, "DA[12]"), /* N2 */ + PINCTRL_PIN(208, "DA[11]"), /* N3 */ + PINCTRL_PIN(209, "AD[3]"), /* N4 */ + PINCTRL_PIN(210, "CVDD"), /* N5 */ + PINCTRL_PIN(211, "CVDD"), /* N6 */ + PINCTRL_PIN(212, "GND"), /* N8 */ + PINCTRL_PIN(213, "GND"), /* N9 */ + PINCTRL_PIN(214, "GND"), /* N10 */ + PINCTRL_PIN(215, "GND"), /* N11 */ + PINCTRL_PIN(216, "GND"), /* N12 */ + PINCTRL_PIN(217, "GND"), /* N13 */ + PINCTRL_PIN(218, "GND"), /* N15 */ + PINCTRL_PIN(219, "GND"), /* N16 */ + PINCTRL_PIN(220, "XTALO"), /* N17 */ + PINCTRL_PIN(221, "COL[0]"), /* N18 */ + PINCTRL_PIN(222, "COL[1]"), /* N19 */ + PINCTRL_PIN(223, "COL[2]"), /* N20 */ + /* Row P */ + PINCTRL_PIN(224, "AD[4]"), /* P1 */ + PINCTRL_PIN(225, "DA[10]"), /* P2 */ + PINCTRL_PIN(226, "DA[9]"), /* P3 */ + PINCTRL_PIN(227, "BRIGHT"), /* P4 */ + PINCTRL_PIN(228, "RVDD"), /* P5 */ + PINCTRL_PIN(229, "RVDD"), /* P6 */ + PINCTRL_PIN(230, "RVDD"), /* P15 */ + PINCTRL_PIN(231, "RVDD"), /* P16 */ + PINCTRL_PIN(232, "XTALI"), /* P17 */ + PINCTRL_PIN(233, "PLL_VDD"), /* P18 */ + PINCTRL_PIN(234, "ROW[6]"), /* P19 */ + PINCTRL_PIN(235, "ROW[7]"), /* P20 */ + /* Row R */ + PINCTRL_PIN(236, "AD[2]"), /* R1 */ + PINCTRL_PIN(237, "AD[1]"), /* R2 */ + PINCTRL_PIN(238, "P[17]"), /* R3 */ + PINCTRL_PIN(239, "P[14]"), /* R4 */ + PINCTRL_PIN(240, "RVDD"), /* R5 */ + PINCTRL_PIN(241, "RVDD"), /* R6 */ + PINCTRL_PIN(242, "GND"), /* R7 */ + PINCTRL_PIN(243, "CVDD"), /* R8 */ + PINCTRL_PIN(244, "CVDD"), /* R13 */ + PINCTRL_PIN(245, "GND"), /* R14 */ + PINCTRL_PIN(246, "RVDD"), /* R15 */ + PINCTRL_PIN(247, "RVDD"), /* R16 */ + PINCTRL_PIN(248, "ROW[0]"), /* R17 */ + PINCTRL_PIN(249, "ROW[3]"), /* R18 */ + PINCTRL_PIN(250, "PLL_GND"), /* R19 */ + PINCTRL_PIN(251, "ROW[5]"), /* R20 */ + /* Row T */ + PINCTRL_PIN(252, "DA[8]"), /* T1 */ + PINCTRL_PIN(253, "BLANK"), /* T2 */ + PINCTRL_PIN(254, "P[13]"), /* T3 */ + PINCTRL_PIN(255, "SPCLK"), /* T4 */ + PINCTRL_PIN(256, "V_CSYNC"), /* T5 */ + PINCTRL_PIN(257, "DD[14]"), /* T6 */ + PINCTRL_PIN(258, "GND"), /* T7 */ + PINCTRL_PIN(259, "CVDD"), /* T8 */ + PINCTRL_PIN(260, "RVDD"), /* T9 */ + PINCTRL_PIN(261, "GND"), /* T10 */ + PINCTRL_PIN(262, "GND"), /* T11 */ + PINCTRL_PIN(263, "RVDD"), /* T12 */ + PINCTRL_PIN(264, "CVDD"), /* T13 */ + PINCTRL_PIN(265, "GND"), /* T14 */ + PINCTRL_PIN(266, "INT[0]"), /* T15 */ + PINCTRL_PIN(267, "USBM[1]"), /* T16 */ + PINCTRL_PIN(268, "RXD[0]"), /* T17 */ + PINCTRL_PIN(269, "TXD[2]"), /* T18 */ + PINCTRL_PIN(270, "ROW[2]"), /* T19 */ + PINCTRL_PIN(271, "ROW[4]"), /* T20 */ + /* Row U */ + PINCTRL_PIN(272, "AD[0]"), /* U1 */ + PINCTRL_PIN(273, "P[15]"), /* U2 */ + PINCTRL_PIN(274, "P[10]"), /* U3 */ + PINCTRL_PIN(275, "P[7]"), /* U4 */ + PINCTRL_PIN(276, "P[6]"), /* U5 */ + PINCTRL_PIN(277, "P[4]"), /* U6 */ + PINCTRL_PIN(278, "P[0]"), /* U7 */ + PINCTRL_PIN(279, "AD[13]"), /* U8 */ + PINCTRL_PIN(280, "DA[3]"), /* U9 */ + PINCTRL_PIN(281, "DA[0]"), /* U10 */ + PINCTRL_PIN(282, "DSRN"), /* U11 */ + PINCTRL_PIN(283, "BOOT[1]"), /* U12 */ + PINCTRL_PIN(284, "NC"), /* U13 */ + PINCTRL_PIN(285, "SSPRX1"), /* U14 */ + PINCTRL_PIN(286, "INT[1]"), /* U15 */ + PINCTRL_PIN(287, "PWMOUT"), /* U16 */ + PINCTRL_PIN(288, "USBM[0]"), /* U17 */ + PINCTRL_PIN(289, "RXD[1]"), /* U18 */ + PINCTRL_PIN(290, "TXD[1]"), /* U19 */ + PINCTRL_PIN(291, "ROW[1]"), /* U20 */ + /* Row V */ + PINCTRL_PIN(292, "P[16]"), /* V1 */ + PINCTRL_PIN(293, "P[11]"), /* V2 */ + PINCTRL_PIN(294, "P[8]"), /* V3 */ + PINCTRL_PIN(295, "DD[15]"), /* V4 */ + PINCTRL_PIN(296, "DD[13]"), /* V5 */ + PINCTRL_PIN(297, "P[1]"), /* V6 */ + PINCTRL_PIN(298, "AD[14]"), /* V7 */ + PINCTRL_PIN(299, "AD[12]"), /* V8 */ + PINCTRL_PIN(300, "DA[2]"), /* V9 */ + PINCTRL_PIN(301, "IDECS0N"), /* V10 */ + PINCTRL_PIN(302, "IDEDA[2]"), /* V11 */ + PINCTRL_PIN(303, "TDI"), /* V12 */ + PINCTRL_PIN(304, "GND"), /* V13 */ + PINCTRL_PIN(305, "ASYNC"), /* V14 */ + PINCTRL_PIN(306, "SSPTX1"), /* V15 */ + PINCTRL_PIN(307, "INT[2]"), /* V16 */ + PINCTRL_PIN(308, "RTSN"), /* V17 */ + PINCTRL_PIN(309, "USBP[0]"), /* V18 */ + PINCTRL_PIN(310, "CTSN"), /* V19 */ + PINCTRL_PIN(311, "TXD[0]"), /* V20 */ + /* Row W */ + PINCTRL_PIN(312, "P[12]"), /* W1 */ + PINCTRL_PIN(313, "P[9]"), /* W2 */ + PINCTRL_PIN(314, "DD[0]"), /* W3 */ + PINCTRL_PIN(315, "P[5]"), /* W4 */ + PINCTRL_PIN(316, "P[3]"), /* W5 */ + PINCTRL_PIN(317, "DA[7]"), /* W6 */ + PINCTRL_PIN(318, "DA[5]"), /* W7 */ + PINCTRL_PIN(319, "AD[11]"), /* W8 */ + PINCTRL_PIN(320, "AD[9]"), /* W9 */ + PINCTRL_PIN(321, "IDECS1N"), /* W10 */ + PINCTRL_PIN(322, "IDEDA[1]"), /* W11 */ + PINCTRL_PIN(323, "TCK"), /* W12 */ + PINCTRL_PIN(324, "TMS"), /* W13 */ + PINCTRL_PIN(325, "EECLK"), /* W14 */ + PINCTRL_PIN(326, "SCLK1"), /* W15 */ + PINCTRL_PIN(327, "GRLED"), /* W16 */ + PINCTRL_PIN(328, "INT[3]"), /* W17 */ + PINCTRL_PIN(329, "SLA[1]"), /* W18 */ + PINCTRL_PIN(330, "SLA[0]"), /* W19 */ + PINCTRL_PIN(331, "RXD[2]"), /* W20 */ + /* Row Y */ + PINCTRL_PIN(332, "HSYNC"), /* Y1 */ + PINCTRL_PIN(333, "DD[1]"), /* Y2 */ + PINCTRL_PIN(334, "DD[12]"), /* Y3 */ + PINCTRL_PIN(335, "P[2]"), /* Y4 */ + PINCTRL_PIN(336, "AD[15]"), /* Y5 */ + PINCTRL_PIN(337, "DA[6]"), /* Y6 */ + PINCTRL_PIN(338, "DA[4]"), /* Y7 */ + PINCTRL_PIN(339, "AD[10]"), /* Y8 */ + PINCTRL_PIN(340, "DA[1]"), /* Y9 */ + PINCTRL_PIN(341, "AD[8]"), /* Y10 */ + PINCTRL_PIN(342, "IDEDA[0]"), /* Y11 */ + PINCTRL_PIN(343, "DTRN"), /* Y12 */ + PINCTRL_PIN(344, "TDO"), /* Y13 */ + PINCTRL_PIN(345, "BOOT[0]"), /* Y14 */ + PINCTRL_PIN(346, "EEDAT"), /* Y15 */ + PINCTRL_PIN(347, "ASDO"), /* Y16 */ + PINCTRL_PIN(348, "SFRM1"), /* Y17 */ + PINCTRL_PIN(349, "RDLED"), /* Y18 */ + PINCTRL_PIN(350, "USBP[1]"), /* Y19 */ + PINCTRL_PIN(351, "ABITCLK"), /* Y20 */ +}; + +static const unsigned int ssp_ep9312_pins[] =3D { + 285, 306, 326, 348 +}; + +static const unsigned int ac97_ep9312_pins[] =3D { + 77, 95, 305, 347, 351 +}; + +static const unsigned int pwm_ep9312_pins[] =3D { 74 }; + +static const unsigned int gpio1a_ep9312_pins[] =3D { 74 }; + +static const unsigned int gpio2a_9312_pins[] =3D { + 234, 235, 248, 249, 251, 270, 271, 291 +}; + +static const unsigned int gpio3a_9312_pins[] =3D { + 186, 187, 202, 203, 204, 221, 222, 223 +}; + +static const unsigned int keypad_9312_pins[] =3D { + 186, 187, 202, 203, 204, 221, 222, 223, + 234, 235, 248, 249, 251, 270, 271, 291 +}; + +static const unsigned int gpio4a_9312_pins[] =3D { + 78, 301, 302, 321, 322, 342 +}; + +static const unsigned int gpio6a_9312_pins[] =3D { + 257, 295, 296, 334 +}; + +static const unsigned int gpio7a_9312_pins[] =3D { + 4, 24, 25, 45, 46, 66, 314, 333 +}; + +static const unsigned int ide_9312_pins[] =3D { + 78, 301, 302, 321, 322, 342, + 257, 295, 296, 334, + 4, 24, 25, 45, 46, 66, 314, 333 +}; + +static const struct ep93xx_pin_group ep9312_pin_groups[] =3D { + { + .name =3D "ssp", + .pins =3D ssp_ep9312_pins, + .num_pins =3D ARRAY_SIZE(ssp_ep9312_pins), + .mask =3D EP93XX_SYSCON_DEVCFG_I2SONSSP, + }, + { + .name =3D "i2s_on_ssp", + .pins =3D ssp_ep9312_pins, + .num_pins =3D ARRAY_SIZE(ssp_ep9312_pins), + .value =3D EP93XX_SYSCON_DEVCFG_I2SONSSP, + .mask =3D EP93XX_SYSCON_DEVCFG_I2SONSSP, + }, + { + .name =3D "pwm1", + .pins =3D pwm_ep9312_pins, + .num_pins =3D ARRAY_SIZE(pwm_ep9312_pins), + .value =3D EP93XX_SYSCON_DEVCFG_PONG, + .mask =3D EP93XX_SYSCON_DEVCFG_PONG, + }, + { + .name =3D "gpio1agrp", + .pins =3D gpio1a_ep9312_pins, + .num_pins =3D ARRAY_SIZE(gpio1a_ep9312_pins), + /* Conflict with PWM1 */ + .mask =3D EP93XX_SYSCON_DEVCFG_PONG, + }, + { + .name =3D "ac97", + .pins =3D ac97_ep9312_pins, + .num_pins =3D ARRAY_SIZE(ac97_ep9312_pins), + .mask =3D EP93XX_SYSCON_DEVCFG_I2SONAC97, + }, + { + .name =3D "i2s_on_ac97", + .pins =3D ac97_ep9312_pins, + .num_pins =3D ARRAY_SIZE(ac97_ep9312_pins), + .value =3D EP93XX_SYSCON_DEVCFG_I2SONAC97, + .mask =3D EP93XX_SYSCON_DEVCFG_I2SONAC97, + }, + { + .name =3D "rasteronsdram0grp", + .pins =3D raster_on_sdram0_pins, + .num_pins =3D ARRAY_SIZE(raster_on_sdram0_pins), + .mask =3D EP93XX_SYSCON_DEVCFG_RASONP3, + }, + { + .name =3D "rasteronsdram3grp", + .pins =3D raster_on_sdram3_pins, + .num_pins =3D ARRAY_SIZE(raster_on_sdram3_pins), + .value =3D EP93XX_SYSCON_DEVCFG_RASONP3, + .mask =3D EP93XX_SYSCON_DEVCFG_RASONP3, + }, + { + .name =3D "gpio2agrp", + .pins =3D gpio2a_9312_pins, + .num_pins =3D ARRAY_SIZE(gpio2a_9312_pins), + .value =3D EP93XX_SYSCON_DEVCFG_GONK, + .mask =3D EP93XX_SYSCON_DEVCFG_GONK, + }, + { + .name =3D "gpio3agrp", + .pins =3D gpio3a_9312_pins, + .num_pins =3D ARRAY_SIZE(gpio3a_9312_pins), + .value =3D EP93XX_SYSCON_DEVCFG_GONK, + .mask =3D EP93XX_SYSCON_DEVCFG_GONK, + }, + { + .name =3D "keypadgrp", + .pins =3D keypad_9307_pins, + .num_pins =3D ARRAY_SIZE(keypad_9307_pins), + .mask =3D EP93XX_SYSCON_DEVCFG_GONK, + }, + { + .name =3D "gpio4agrp", + .pins =3D gpio4a_9312_pins, + .num_pins =3D ARRAY_SIZE(gpio4a_9312_pins), + .value =3D EP93XX_SYSCON_DEVCFG_EONIDE, + .mask =3D EP93XX_SYSCON_DEVCFG_EONIDE, + }, + { + .name =3D "gpio6agrp", + .pins =3D gpio6a_9312_pins, + .num_pins =3D ARRAY_SIZE(gpio6a_9312_pins), + .value =3D EP93XX_SYSCON_DEVCFG_GONIDE, + .mask =3D EP93XX_SYSCON_DEVCFG_GONIDE, + }, + { + .name =3D "gpio7agrp", + .pins =3D gpio7a_9312_pins, + .num_pins =3D ARRAY_SIZE(gpio7a_9312_pins), + .value =3D EP93XX_SYSCON_DEVCFG_HONIDE, + .mask =3D EP93XX_SYSCON_DEVCFG_HONIDE, + }, + { + .name =3D "idegrp", + .pins =3D ide_9312_pins, + .num_pins =3D ARRAY_SIZE(ide_9312_pins), + .mask =3D EP93XX_SYSCON_DEVCFG_EONIDE | EP93XX_SYSCON_DEVCFG_GONIDE | + EP93XX_SYSCON_DEVCFG_HONIDE, + }, +}; + +static int ep93xx_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct ep93xx_pmx *pmx =3D pinctrl_dev_get_drvdata(pctldev); + + switch (pmx->model) { + case EP93XX_9301_PINCTRL: + return ARRAY_SIZE(ep9301_pin_groups); + case EP93XX_9307_PINCTRL: + return ARRAY_SIZE(ep9307_pin_groups); + case EP93XX_9312_PINCTRL: + return ARRAY_SIZE(ep9312_pin_groups); + } + + return 0; +} + +static const char *ep93xx_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct ep93xx_pmx *pmx =3D pinctrl_dev_get_drvdata(pctldev); + + switch (pmx->model) { + case EP93XX_9301_PINCTRL: + return ep9301_pin_groups[selector].name; + case EP93XX_9307_PINCTRL: + return ep9307_pin_groups[selector].name; + case EP93XX_9312_PINCTRL: + return ep9312_pin_groups[selector].name; + } + + return NULL; +} + +static int ep93xx_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, + const unsigned int **pins, + unsigned int *num_pins) +{ + struct ep93xx_pmx *pmx =3D pinctrl_dev_get_drvdata(pctldev); + + switch (pmx->model) { + case EP93XX_9301_PINCTRL: + *pins =3D ep9301_pin_groups[selector].pins; + *num_pins =3D ep9301_pin_groups[selector].num_pins; + break; + case EP93XX_9307_PINCTRL: + *pins =3D ep9307_pin_groups[selector].pins; + *num_pins =3D ep9307_pin_groups[selector].num_pins; + break; + case EP93XX_9312_PINCTRL: + *pins =3D ep9312_pin_groups[selector].pins; + *num_pins =3D ep9312_pin_groups[selector].num_pins; + break; + } + + return 0; +} + +static void ep93xx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_fi= le *s, + unsigned int offset) +{ + seq_printf(s, " " DRIVER_NAME); +} + +static const struct pinctrl_ops ep93xx_pctrl_ops =3D { + .get_groups_count =3D ep93xx_get_groups_count, + .get_group_name =3D ep93xx_get_group_name, + .get_group_pins =3D ep93xx_get_group_pins, + .pin_dbg_show =3D ep93xx_pin_dbg_show, + .dt_node_to_map =3D pinconf_generic_dt_node_to_map_all, + .dt_free_map =3D pinconf_generic_dt_free_map, +}; + +/** + * struct ep93xx_pmx_func - describes ep93xx pinmux functions + * @name: the name of this specific function + * @groups: corresponding pin groups + */ +struct ep93xx_pmx_func { + const char *name; + const char * const *groups; + const unsigned int num_groups; +}; + +static const char * const spigrps[] =3D { "ssp" }; +static const char * const ac97grps[] =3D { "ac97" }; +static const char * const i2sgrps[] =3D { "i2s_on_ssp", "i2s_on_ac97" }; +static const char * const pwm1grps[] =3D { "pwm1" }; +static const char * const gpiogrps[] =3D { "gpio1agrp", "gpio2agrp", "gpio= 3agrp", + "gpio4agrp", "gpio6agrp", "gpio7agrp" }; +static const char * const rastergrps[] =3D { "rasteronsdram0grp", "rastero= nsdram3grp"}; +static const char * const keypadgrps[] =3D { "keypadgrp"}; +static const char * const idegrps[] =3D { "idegrp"}; + + +static const struct ep93xx_pmx_func ep93xx_pmx_functions[] =3D { + { + .name =3D "spi", + .groups =3D spigrps, + .num_groups =3D ARRAY_SIZE(spigrps), + }, + { + .name =3D "ac97", + .groups =3D ac97grps, + .num_groups =3D ARRAY_SIZE(ac97grps), + }, + { + .name =3D "i2s", + .groups =3D i2sgrps, + .num_groups =3D ARRAY_SIZE(i2sgrps), + }, + { + .name =3D "pwm", + .groups =3D pwm1grps, + .num_groups =3D ARRAY_SIZE(pwm1grps), + }, + { + .name =3D "keypad", + .groups =3D keypadgrps, + .num_groups =3D ARRAY_SIZE(keypadgrps), + }, + { + .name =3D "pata", + .groups =3D idegrps, + .num_groups =3D ARRAY_SIZE(idegrps), + }, + { + .name =3D "lcd", + .groups =3D rastergrps, + .num_groups =3D ARRAY_SIZE(rastergrps), + }, + { + .name =3D "gpio", + .groups =3D gpiogrps, + .num_groups =3D ARRAY_SIZE(gpiogrps), + }, +}; + +static int ep93xx_pmx_set_mux(struct pinctrl_dev *pctldev, + unsigned int selector, + unsigned int group) +{ + struct ep93xx_pmx *pmx; + const struct ep93xx_pmx_func *func; + const struct ep93xx_pin_group *grp; + u32 before, after, expected; + unsigned long tmp; + int i; + + pmx =3D pinctrl_dev_get_drvdata(pctldev); + + func =3D &ep93xx_pmx_functions[selector]; + + switch (pmx->model) { + case EP93XX_9301_PINCTRL: + grp =3D &ep9301_pin_groups[group]; + break; + case EP93XX_9307_PINCTRL: + grp =3D &ep9307_pin_groups[group]; + break; + case EP93XX_9312_PINCTRL: + grp =3D &ep9312_pin_groups[group]; + break; + } + + dev_dbg(pmx->dev, + "ACTIVATE function \"%s\" with group \"%s\" (mask=3D0x%x, value=3D0x%x)\= n", + func->name, grp->name, grp->mask, grp->value); + + regmap_read(pmx->map, EP93XX_SYSCON_DEVCFG, &before); + ep93xx_swlocked_update_bits(EP93XX_SYSCON_DEVCFG, + grp->mask, grp->value); + regmap_read(pmx->map, EP93XX_SYSCON_DEVCFG, &after); + + dev_dbg(pmx->dev, + "before=3D0x%x, after=3D0x%x, mask=3D0x%lx\n", + before, after, PADS_MASK); + + /* Which bits changed */ + before &=3D PADS_MASK; + after &=3D PADS_MASK; + expected =3D before & ~grp->mask; + expected |=3D grp->value; + expected &=3D PADS_MASK; + + /* Print changed states */ + tmp =3D expected ^ after; + for_each_set_bit(i, &tmp, PADS_MAXBIT) { + bool enabled =3D expected & BIT(i); + + dev_err(pmx->dev, + "pin group %s could not be %s: probably a hardware limitation\n", + ep93xx_padgroups[i], enabled ? "enabled" : "disabled"); + dev_err(pmx->dev, + "DeviceCfg before: %08x, after %08x, expected %08x\n", + before, after, expected); + } + + return tmp ? -EINVAL : 0; +}; + +static int ep93xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(ep93xx_pmx_functions); +} + +static const char *ep93xx_pmx_get_func_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return ep93xx_pmx_functions[selector].name; +} + +static int ep93xx_pmx_get_groups(struct pinctrl_dev *pctldev, + unsigned int selector, + const char * const **groups, + unsigned int * const num_groups) +{ + *groups =3D ep93xx_pmx_functions[selector].groups; + *num_groups =3D ep93xx_pmx_functions[selector].num_groups; + return 0; +} + +static const struct pinmux_ops ep93xx_pmx_ops =3D { + .get_functions_count =3D ep93xx_pmx_get_funcs_count, + .get_function_name =3D ep93xx_pmx_get_func_name, + .get_function_groups =3D ep93xx_pmx_get_groups, + .set_mux =3D ep93xx_pmx_set_mux, +}; + +static struct pinctrl_desc ep93xx_pmx_desc =3D { + .name =3D DRIVER_NAME, + .pctlops =3D &ep93xx_pctrl_ops, + .pmxops =3D &ep93xx_pmx_ops, + .owner =3D THIS_MODULE, +}; + +static const struct of_device_id ep93xx_pinctrl_of_ids[] =3D { + { .compatible =3D "cirrus,ep9301-pinctrl", .data =3D (void *)EP93XX_9301_= PINCTRL}, + { .compatible =3D "cirrus,ep9302-pinctrl", .data =3D (void *)EP93XX_9301_= PINCTRL}, + { .compatible =3D "cirrus,ep9307-pinctrl", .data =3D (void *)EP93XX_9307_= PINCTRL}, + { .compatible =3D "cirrus,ep9312-pinctrl", .data =3D (void *)EP93XX_9312_= PINCTRL}, + { .compatible =3D "cirrus,ep9315-pinctrl", .data =3D (void *)EP93XX_9312_= PINCTRL}, + {}, +}; + +static int ep93xx_pmx_probe(struct platform_device *pdev) +{ + const struct of_device_id *match =3D of_match_node(ep93xx_pinctrl_of_ids,= pdev->dev.of_node); + struct ep93xx_pmx *pmx; + struct regmap *map; + struct device *dev =3D &pdev->dev; + struct device *parent; + + /* Create state holders etc for this driver */ + pmx =3D devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); + if (!pmx) + return -ENOMEM; + + pmx->dev =3D &pdev->dev; + parent =3D dev->parent; + if (!parent) { + dev_err(dev, "no parent to pin controller\n"); + return -ENODEV; + } + + map =3D syscon_node_to_regmap(parent->of_node); + if (IS_ERR(map)) { + dev_err(dev, "no syscon regmap\n"); + return PTR_ERR(map); + } + pmx->map =3D map; + + pmx->model =3D (int) match->data; + switch (pmx->model) { + case EP93XX_9301_PINCTRL: + ep93xx_pmx_desc.pins =3D ep9301_pins; + ep93xx_pmx_desc.npins =3D ARRAY_SIZE(ep9301_pins); + dev_info(dev, "detected 9301/9302 chip variant\n"); + break; + case EP93XX_9307_PINCTRL: + ep93xx_pmx_desc.pins =3D ep9307_pins; + ep93xx_pmx_desc.npins =3D ARRAY_SIZE(ep9307_pins); + dev_info(dev, "detected 9307 chip variant\n"); + break; + case EP93XX_9312_PINCTRL: + ep93xx_pmx_desc.pins =3D ep9312_pins; + ep93xx_pmx_desc.npins =3D ARRAY_SIZE(ep9312_pins); + dev_info(dev, "detected 9312/9315 chip variant\n"); + break; + } + + pmx->pctl =3D devm_pinctrl_register(dev, &ep93xx_pmx_desc, pmx); + if (IS_ERR(pmx->pctl)) { + dev_err(dev, "could not register pinmux driver\n"); + return PTR_ERR(pmx->pctl); + } + + dev_info(dev, "initialized ep93xx pin control driver\n"); + + return 0; +}; + +static struct platform_driver ep93xx_pmx_driver =3D { + .driver =3D { + .name =3D DRIVER_NAME, + .of_match_table =3D ep93xx_pinctrl_of_ids, + }, + .probe =3D ep93xx_pmx_probe, +}; + +static int __init ep93xx_pmx_init(void) +{ + return platform_driver_register(&ep93xx_pmx_driver); +} +arch_initcall(ep93xx_pmx_init); --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81791C7618E for ; Mon, 24 Apr 2023 09:55:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231649AbjDXJzw (ORCPT ); Mon, 24 Apr 2023 05:55:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54974 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230499AbjDXJzq (ORCPT ); Mon, 24 Apr 2023 05:55:46 -0400 X-Greylist: delayed 453 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; 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dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , Alessandro Zummo , Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Hartley Sweeten , linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 07/43] dt-bindings: rtc: add DT bindings for Cirrus EP93xx Date: Mon, 24 Apr 2023 15:34:23 +0300 Message-Id: <20230424123522.18302-8-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds device tree bindings for the Cirrus Logic EP93xx RTC block used in these SoCs. Signed-off-by: Nikita Shubin --- .../bindings/rtc/cirrus,ep93xx-rtc.yaml | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/cirrus,ep93xx-rtc= .yaml diff --git a/Documentation/devicetree/bindings/rtc/cirrus,ep93xx-rtc.yaml b= /Documentation/devicetree/bindings/rtc/cirrus,ep93xx-rtc.yaml new file mode 100644 index 000000000000..d4774e984e7b --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/cirrus,ep93xx-rtc.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/cirrus,ep93xx-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus EP93xx Real Time Clock controller + +maintainers: + - Hartley Sweeten + - Alexander Sverdlin + +properties: + compatible: + const: cirrus,ep9301-rtc + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + rtc0: rtc@80920000 { + compatible =3D "cirrus,ep9301-rtc"; + reg =3D <0x80920000 0x100>; + }; + --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2C4FC77B7A for ; Thu, 1 Jun 2023 05:37:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231364AbjFAFhw (ORCPT ); Thu, 1 Jun 2023 01:37:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47146 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230467AbjFAFhh (ORCPT ); Thu, 1 Jun 2023 01:37:37 -0400 Received: from forward103c.mail.yandex.net (forward103c.mail.yandex.net [IPv6:2a02:6b8:c03:500:1:45:d181:d103]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CAF0218C; Wed, 31 May 2023 22:37:05 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net [IPv6:2a02:6b8:c14:c83:0:640:84f9:0]) by forward103c.mail.yandex.net (Yandex) with ESMTP id 2B2C2600DA; Thu, 1 Jun 2023 08:37:04 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id OaGNfZvWv8c0-OHBZTyTv; Thu, 01 Jun 2023 08:37:03 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1685597823; bh=VatStSR66GucNc5hVUrQNwqWDpGGl1rlhns6r178kkM=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=eeu24hSjn422AAJ0Cd8fpSKtfTaL5kQtg5tDkOnJnog5dw4SUWPAXLzdqT2YPlcPC JOMo3bM7xF8tkMWxSaL1bHksCU6Zz+rlWxii+gE600bYmjpoG/kDCuxv71FrlHmExa RPuYkXUIcYE3u5YbMMt4kaBfHoxoSCdvSd/ObszU= Authentication-Results: mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij , Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Nikita Shubin Cc: Michael Peters , Kris Bahnsen , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v1 08/43] dt-bindings: timers: Add Cirrus EP93xx Date: Thu, 1 Jun 2023 08:33:59 +0300 Message-Id: <20230601053546.9574-9-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds device tree bindings for the Cirrus Logic EP93xx timer block used in these SoCs. Signed-off-by: Nikita Shubin Reviewed-by: Krzysztof Kozlowski --- Notes: v0 -> v1: - as Hartley (unfortunately) looks like not interested in dt rework, added myself instead =20 Krzysztof Kozlowski: - removed wildcards - use fallback compatible and list all possible compatibles - fix ident - dropped bindings in title .../bindings/timer/cirrus,ep9301-timer.yaml | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/cirrus,ep9301-t= imer.yaml diff --git a/Documentation/devicetree/bindings/timer/cirrus,ep9301-timer.ya= ml b/Documentation/devicetree/bindings/timer/cirrus,ep9301-timer.yaml new file mode 100644 index 000000000000..e463e11e259d --- /dev/null +++ b/Documentation/devicetree/bindings/timer/cirrus,ep9301-timer.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/cirrus,ep9301-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic EP93xx timer + +maintainers: + - Alexander Sverdlin + - Nikita Shubin + +properties: + compatible: + oneOf: + - const: cirrus,ep9301-timer + - items: + - enum: + - cirrus,ep9302-timer + - cirrus,ep9307-timer + - cirrus,ep9312-timer + - cirrus,ep9315-timer + - const: cirrus,ep9301-timer + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + timer@80810000 { + compatible =3D "cirrus,ep9301-timer"; + reg =3D <0x80810000 0x100>; + interrupt-parent =3D <&vic1>; + interrupts =3D <19>; + }; +... --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43751C77B61 for ; Mon, 24 Apr 2023 10:21:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231760AbjDXKVe (ORCPT ); Mon, 24 Apr 2023 06:21:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231675AbjDXKUr (ORCPT ); Mon, 24 Apr 2023 06:20:47 -0400 Received: from forward501c.mail.yandex.net (forward501c.mail.yandex.net [IPv6:2a02:6b8:c03:500:1:45:d181:d501]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BCA1A3A90 for ; Mon, 24 Apr 2023 03:20:45 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net [IPv6:2a02:6b8:c12:261e:0:640:2e3d:0]) by forward501c.mail.yandex.net (Yandex) with ESMTP id 8404E5EE57; Mon, 24 Apr 2023 12:35:42 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id JZBb1pbWwKo0-z9Flm1CE; Mon, 24 Apr 2023 12:35:42 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1682328942; bh=K1BrJFARres8quvGFHRVDGGD0XFqhKg6JqfWlOl6IWw=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=ZgzB4YwjgAjrXUb5wN89rYvQobvH0KISWKTeScRVSVTn29bGMW+oBR8/DNYxTVYCY DNnGeToeHxUtNeLITjsni9W4ljpNVZ65qJQZybU/QY/v0tdnGXVJcIJvysB6xWV/Z8 yf9K1JDB4dwhtTJPEoT8ecqwsKjMjIZNZ0z6Wzh4= Authentication-Results: mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , Alessandro Zummo , Alexandre Belloni , linux-rtc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 08/43] rtc: ep93xx: add DT support for Cirrus EP93xx Date: Mon, 24 Apr 2023 15:34:24 +0300 Message-Id: <20230424123522.18302-9-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" - Find register range from the device tree. Signed-off-by: Nikita Shubin --- Notes: Arnd Bergmann: - wildcards ep93xx to something meaningful, i.e. ep9301 - drop wrappers drivers/rtc/rtc-ep93xx.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/rtc/rtc-ep93xx.c b/drivers/rtc/rtc-ep93xx.c index acae7f16808f..8bda20a4940a 100644 --- a/drivers/rtc/rtc-ep93xx.c +++ b/drivers/rtc/rtc-ep93xx.c @@ -8,6 +8,7 @@ =20 #include #include +#include #include #include #include @@ -148,9 +149,16 @@ static int ep93xx_rtc_probe(struct platform_device *pd= ev) return devm_rtc_register_device(ep93xx_rtc->rtc); } =20 +static const struct of_device_id ep93xx_rtc_of_ids[] =3D { + { .compatible =3D "cirrus,ep9301-rtc" }, + {}, +}; +MODULE_DEVICE_TABLE(of, ep93xx_rtc_of_ids); + static struct platform_driver ep93xx_rtc_driver =3D { .driver =3D { .name =3D "ep93xx-rtc", + .of_match_table =3D ep93xx_rtc_of_ids, }, .probe =3D ep93xx_rtc_probe, }; --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 364F0C77B7A for ; Thu, 1 Jun 2023 05:38:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231454AbjFAFiS (ORCPT ); Thu, 1 Jun 2023 01:38:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47258 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231386AbjFAFhr (ORCPT ); Thu, 1 Jun 2023 01:37:47 -0400 Received: from forward103b.mail.yandex.net (forward103b.mail.yandex.net [IPv6:2a02:6b8:c02:900:1:45:d181:d103]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ABAF019A for ; Wed, 31 May 2023 22:37:07 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net [IPv6:2a02:6b8:c14:c83:0:640:84f9:0]) by forward103b.mail.yandex.net (Yandex) with ESMTP id 12E8A6003A; Thu, 1 Jun 2023 08:37:06 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id OaGNfZvWv8c0-yW1VRVnU; Thu, 01 Jun 2023 08:37:05 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1685597825; bh=g8/iXOMoo563uPEc6cSJSl/YThiDFqPeIO/2uKpNO4s=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=CvtkRTViJJ0y+T6fxIL/UEdAr8TIJSHj/h5pH22UHlo13ZapUCS0ikbEeSnjXF8XT H9GKmqaCSgH3KAzXZHCihKBwPQ9vSyej5T7Wuhb5Gasjohb+UrHm3Vqb4o/h3PUh43 ECqWMqDfK7TXSA7JEdApevB+cpAR6YWMZfMCczzY= Authentication-Results: mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij , Daniel Lezcano , Thomas Gleixner Cc: Nikita Shubin , Michael Peters , Kris Bahnsen , linux-kernel@vger.kernel.org Subject: [PATCH v1 09/43] clocksource: ep93xx: Add driver for Cirrus Logic EP93xx Date: Thu, 1 Jun 2023 08:34:00 +0300 Message-Id: <20230601053546.9574-10-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This us a rewrite of EP93xx timer driver in arch/arm/mach-ep93xx/timer-ep93xx.c trying to do everything the device tree way: - Make every IO-access relative to a base address and dynamic so we can do a dynamic ioremap and get going. - Find register range and interrupt from the device tree. Reviewed-by: Linus Walleij Signed-off-by: Nikita Shubin Tested-by: Alexander Sverdlin --- Notes: v0 -> v1: =20 - fixed headers drivers/clocksource/Kconfig | 11 ++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-ep93xx.c | 189 +++++++++++++++++++++++++++++ 3 files changed, 201 insertions(+) create mode 100644 drivers/clocksource/timer-ep93xx.c diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 5fc8f0e7fb38..40bfc7c86756 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -721,4 +721,15 @@ config GOLDFISH_TIMER help Support for the timer/counter of goldfish-rtc =20 +config EP93XX_TIMER + bool "Cirrus Logic ep93xx timer driver" if COMPILE_TEST + depends on ARCH_EP93XX + depends on GENERIC_CLOCKEVENTS + depends on HAS_IOMEM + select CLKSRC_MMIO + select TIMER_OF + help + Enables support for the Cirrus Logic timer block + EP93XX. + endmenu diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 64ab547de97b..09c2d4e5d809 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -88,3 +88,4 @@ obj-$(CONFIG_MICROCHIP_PIT64B) +=3D timer-microchip-pit6= 4b.o obj-$(CONFIG_MSC313E_TIMER) +=3D timer-msc313e.o obj-$(CONFIG_GOLDFISH_TIMER) +=3D timer-goldfish.o obj-$(CONFIG_GXP_TIMER) +=3D timer-gxp.o +obj-$(CONFIG_EP93XX_TIMER) +=3D timer-ep93xx.o diff --git a/drivers/clocksource/timer-ep93xx.c b/drivers/clocksource/timer= -ep93xx.c new file mode 100644 index 000000000000..966502169aa0 --- /dev/null +++ b/drivers/clocksource/timer-ep93xx.c @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Cirrus Logic EP93xx timer driver. + * Copyright (C) 2021 Nikita Shubin + * + * Based on a rewrite of arch/arm/mach-ep93xx/timer.c: + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/************************************************************************* + * Timer handling for EP93xx + ************************************************************************* + * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and + * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate + * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz, + * is free-running, and can't generate interrupts. + * + * The 508 kHz timers are ideal for use for the timer interrupt, as the + * most common values of HZ divide 508 kHz nicely. We pick the 32 bit + * timer (timer 3) to get as long sleep intervals as possible when using + * CONFIG_NO_HZ. + * + * The higher clock rate of timer 4 makes it a better choice than the + * other timers for use as clock source and for sched_clock(), providing + * a stable 40 bit time base. + ************************************************************************* + */ + +#define EP93XX_TIMER1_LOAD 0x00 +#define EP93XX_TIMER1_VALUE 0x04 +#define EP93XX_TIMER1_CONTROL 0x08 +#define EP93XX_TIMER123_CONTROL_ENABLE BIT(7) +#define EP93XX_TIMER123_CONTROL_MODE BIT(6) +#define EP93XX_TIMER123_CONTROL_CLKSEL BIT(3) +#define EP93XX_TIMER1_CLEAR 0x0c +#define EP93XX_TIMER2_LOAD 0x20 +#define EP93XX_TIMER2_VALUE 0x24 +#define EP93XX_TIMER2_CONTROL 0x28 +#define EP93XX_TIMER2_CLEAR 0x2c +/* This read-only register contains the low word of the time stamp debug t= imer + * ( Timer4). When this register is read, the high byte of the Timer4 coun= ter is + * saved in the Timer4ValueHigh register. + */ +#define EP93XX_TIMER4_VALUE_LOW 0x60 +#define EP93XX_TIMER4_VALUE_HIGH 0x64 +#define EP93XX_TIMER4_VALUE_HIGH_ENABLE BIT(8) +#define EP93XX_TIMER3_LOAD 0x80 +#define EP93XX_TIMER3_VALUE 0x84 +#define EP93XX_TIMER3_CONTROL 0x88 +#define EP93XX_TIMER3_CLEAR 0x8c + +#define EP93XX_TIMER123_RATE 508469 +#define EP93XX_TIMER4_RATE 983040 + +struct ep93xx_tcu { + void __iomem *base; +}; + +static struct ep93xx_tcu *ep93xx_tcu; + +static u64 ep93xx_clocksource_read(struct clocksource *c) +{ + struct ep93xx_tcu *tcu =3D ep93xx_tcu; + u64 ret; + + ret =3D readl(tcu->base + EP93XX_TIMER4_VALUE_LOW); + ret |=3D ((u64) (readl(tcu->base + EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 3= 2); + return (u64) ret; +} + +static u64 notrace ep93xx_read_sched_clock(void) +{ + return ep93xx_clocksource_read(NULL); +} + +static int ep93xx_clkevt_set_next_event(unsigned long next, + struct clock_event_device *evt) +{ + struct ep93xx_tcu *tcu =3D ep93xx_tcu; + /* Default mode: periodic, off, 508 kHz */ + u32 tmode =3D EP93XX_TIMER123_CONTROL_MODE | + EP93XX_TIMER123_CONTROL_CLKSEL; + + /* Clear timer */ + writel(tmode, tcu->base + EP93XX_TIMER3_CONTROL); + + /* Set next event */ + writel(next, tcu->base + EP93XX_TIMER3_LOAD); + writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE, + tcu->base + EP93XX_TIMER3_CONTROL); + return 0; +} + +static int ep93xx_clkevt_shutdown(struct clock_event_device *evt) +{ + struct ep93xx_tcu *tcu =3D ep93xx_tcu; + /* Disable timer */ + writel(0, tcu->base + EP93XX_TIMER3_CONTROL); + + return 0; +} + +static struct clock_event_device ep93xx_clockevent =3D { + .name =3D "timer1", + .features =3D CLOCK_EVT_FEAT_ONESHOT, + .set_state_shutdown =3D ep93xx_clkevt_shutdown, + .set_state_oneshot =3D ep93xx_clkevt_shutdown, + .tick_resume =3D ep93xx_clkevt_shutdown, + .set_next_event =3D ep93xx_clkevt_set_next_event, + .rating =3D 300, +}; + +static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id) +{ + struct ep93xx_tcu *tcu =3D ep93xx_tcu; + struct clock_event_device *evt =3D dev_id; + + /* Writing any value clears the timer interrupt */ + writel(1, tcu->base + EP93XX_TIMER3_CLEAR); + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static int __init ep93xx_timer_of_init(struct device_node *np) +{ + int irq; + unsigned long flags =3D IRQF_TIMER | IRQF_IRQPOLL; + struct ep93xx_tcu *tcu; + int ret; + + tcu =3D kzalloc(sizeof(*tcu), GFP_KERNEL); + if (!tcu) + return -ENOMEM; + + tcu->base =3D of_iomap(np, 0); + if (!tcu->base) { + pr_err("Can't remap registers\n"); + ret =3D -ENXIO; + goto out_free; + } + + ep93xx_tcu =3D tcu; + + irq =3D irq_of_parse_and_map(np, 0); + if (irq <=3D 0) { + pr_err("ERROR: invalid interrupt number\n"); + ret =3D -EINVAL; + goto out_free; + } + + /* Enable and register clocksource and sched_clock on timer 4 */ + writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE, + tcu->base + EP93XX_TIMER4_VALUE_HIGH); + clocksource_mmio_init(NULL, "timer4", + EP93XX_TIMER4_RATE, 200, 40, + ep93xx_clocksource_read); + sched_clock_register(ep93xx_read_sched_clock, 40, + EP93XX_TIMER4_RATE); + + /* Set up clockevent on timer 3 */ + if (request_irq(irq, ep93xx_timer_interrupt, flags, "ep93xx timer", + &ep93xx_clockevent)) + pr_err("Failed to request irq %d (ep93xx timer)\n", irq); + clockevents_config_and_register(&ep93xx_clockevent, + EP93XX_TIMER123_RATE, + 1, + 0xffffffffU); + + return 0; + +out_free: + kfree(tcu); + return ret; +} + +TIMER_OF_DECLARE(ep93xx_timer, "cirrus,ep9301-timer", ep93xx_timer_of_init= ); --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47E29C7618E for ; Mon, 24 Apr 2023 10:35:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231274AbjDXKfO (ORCPT ); Mon, 24 Apr 2023 06:35:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57588 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231139AbjDXKeq (ORCPT ); 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dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 09/43] dt-bindings: watchdog: add DT bindings for Cirrus EP93x Date: Mon, 24 Apr 2023 15:34:25 +0300 Message-Id: <20230424123522.18302-10-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds device tree bindings for the Cirrus Logic EP93xx watchdog block used in these SoCs. Signed-off-by: Nikita Shubin --- .../bindings/watchdog/cirrus,ep93xx-wdt.yaml | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/cirrus,ep93x= x-wdt.yaml diff --git a/Documentation/devicetree/bindings/watchdog/cirrus,ep93xx-wdt.y= aml b/Documentation/devicetree/bindings/watchdog/cirrus,ep93xx-wdt.yaml new file mode 100644 index 000000000000..f39d6b14062d --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/cirrus,ep93xx-wdt.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/cirrus,ep93xx-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic EP93xx Watchdog Timer + +maintainers: + - Wim Van Sebroeck + +description: + Watchdog driver for Cirrus Logic EP93xx family of devices. + +allOf: + - $ref: "watchdog.yaml#" + +properties: + compatible: + enum: + - cirrus,ep9301-wdt + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + wdt0: watchdog@80940000 { + compatible =3D "cirrus,ep9301-wdt"; + reg =3D <0x80940000 0x08>; + }; + --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F548C77B7E for ; Mon, 24 Apr 2023 10:21:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231777AbjDXKVp (ORCPT ); Mon, 24 Apr 2023 06:21:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44284 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231415AbjDXKU6 (ORCPT ); Mon, 24 Apr 2023 06:20:58 -0400 Received: from forward502b.mail.yandex.net (forward502b.mail.yandex.net [178.154.239.146]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7BBD519B3; Mon, 24 Apr 2023 03:20:46 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net [IPv6:2a02:6b8:c12:261e:0:640:2e3d:0]) by forward502b.mail.yandex.net (Yandex) with ESMTP id EE11B5ED42; Mon, 24 Apr 2023 12:35:43 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id JZBb1pbWwKo0-AZ7pI60e; Mon, 24 Apr 2023 12:35:43 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1682328943; bh=Ykq/wbEgP3PIeiGBN7Mik/1VdEeec2rPLqi1x7QHMOk=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=X0ySFbm28PrBbp8i8IjzZMwqHRpl49jkfcAEIRgxnS+737rkjp2GoRoeqEDegkfKb lrqNd+8jzB6vzQ/Qo3r7giKJ8ZtUln/AH6KzpnI27dcqEY4NVuPMgj3bs4e79nBGDt ikwiuzdY7+dh942zHzbIw6qHgA0jmeK9vTgusp9M= Authentication-Results: mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , Wim Van Sebroeck , Guenter Roeck , linux-watchdog@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/43] watchdog: ep93xx: add DT support for Cirrus EP93xx Date: Mon, 24 Apr 2023 15:34:26 +0300 Message-Id: <20230424123522.18302-11-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" - Find register range from the device tree. Signed-off-by: Nikita Shubin --- Notes: Arnd Bergmann: - wildcards ep93xx to something meaningful, i.e. ep9301 - drop wrappers drivers/watchdog/ep93xx_wdt.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/watchdog/ep93xx_wdt.c b/drivers/watchdog/ep93xx_wdt.c index 38e26f160b9a..0f9b1b3b4307 100644 --- a/drivers/watchdog/ep93xx_wdt.c +++ b/drivers/watchdog/ep93xx_wdt.c @@ -21,6 +21,7 @@ * daemon dies. */ =20 +#include #include #include #include @@ -130,9 +131,16 @@ static int ep93xx_wdt_probe(struct platform_device *pd= ev) return 0; } =20 +static const struct of_device_id ep93xx_wdt_of_ids[] =3D { + { .compatible =3D "cirrus,ep9301-wdt" }, + {}, +}; +MODULE_DEVICE_TABLE(of, ep93xx_wdt_of_ids); + static struct platform_driver ep93xx_wdt_driver =3D { .driver =3D { .name =3D "ep93xx-wdt", + .of_match_table =3D ep93xx_wdt_of_ids, }, .probe =3D ep93xx_wdt_probe, }; --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D19EAC77B7E for ; Thu, 1 Jun 2023 05:38:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231501AbjFAFiZ (ORCPT ); Thu, 1 Jun 2023 01:38:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47248 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231359AbjFAFhs (ORCPT ); Thu, 1 Jun 2023 01:37:48 -0400 Received: from forward100c.mail.yandex.net (forward100c.mail.yandex.net [178.154.239.211]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 97922136; Wed, 31 May 2023 22:37:09 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net [IPv6:2a02:6b8:c14:c83:0:640:84f9:0]) by forward100c.mail.yandex.net (Yandex) with ESMTP id B6FEA600D3; Thu, 1 Jun 2023 08:37:07 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id OaGNfZvWv8c0-FpBrcpQV; Thu, 01 Jun 2023 08:37:07 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1685597827; bh=qOkogIySk519S7an/UqDAaBb8UQhyT0kSjiOdERaRIs=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=n7ypch4LzDr5/chZbGWNTasJLTDMY4ucB9n/AFwmXFxTXkX2xllvO13F5luUfMhOX AcStIUv7Fj5ICxW65Op3AxicHU2ZipbJJvXPaIEaH4X2ww9IJSxdzyrwxBzA7KYBiG GnguUE4pYzC97+prPDEbgTGejxKjRCsWd19pcl4s= Authentication-Results: mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij , Alessandro Zummo , Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Hartley Sweeten Cc: Nikita Shubin , Michael Peters , Kris Bahnsen , linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 10/43] dt-bindings: rtc: Add Cirrus EP93xx Date: Thu, 1 Jun 2023 08:34:01 +0300 Message-Id: <20230601053546.9574-11-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds device tree bindings for the Cirrus Logic EP93xx RTC block used in these SoCs. Signed-off-by: Nikita Shubin --- Notes: v0 -> v1: Krzysztof Kozlowski: - removed wildcards - use fallback compatible and list all possible compatibles - dropped label - fix ident .../bindings/rtc/cirrus,ep9301-rtc.yaml | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/cirrus,ep9301-rtc= .yaml diff --git a/Documentation/devicetree/bindings/rtc/cirrus,ep9301-rtc.yaml b= /Documentation/devicetree/bindings/rtc/cirrus,ep9301-rtc.yaml new file mode 100644 index 000000000000..63572c197e92 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/cirrus,ep9301-rtc.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/cirrus,ep9301-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus EP93xx Real Time Clock controller + +maintainers: + - Hartley Sweeten + - Alexander Sverdlin + +properties: + compatible: + oneOf: + - const: cirrus,ep9301-rtc + - items: + - enum: + - cirrus,ep9302-rtc + - cirrus,ep9307-rtc + - cirrus,ep9312-rtc + - cirrus,ep9315-rtc + - const: cirrus,ep9301-rtc + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + rtc@80920000 { + compatible =3D "cirrus,ep9301-rtc"; + reg =3D <0x80920000 0x100>; + }; + --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94C78C77B7E for ; Thu, 1 Jun 2023 05:38:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231514AbjFAFib (ORCPT ); Thu, 1 Jun 2023 01:38:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47282 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231373AbjFAFhs (ORCPT ); Thu, 1 Jun 2023 01:37:48 -0400 Received: from forward100b.mail.yandex.net (forward100b.mail.yandex.net [178.154.239.147]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 492C5134; Wed, 31 May 2023 22:37:10 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net [IPv6:2a02:6b8:c14:c83:0:640:84f9:0]) by forward100b.mail.yandex.net (Yandex) with ESMTP id CAC3C600D4; Thu, 1 Jun 2023 08:37:08 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id OaGNfZvWv8c0-6hcLzyhA; Thu, 01 Jun 2023 08:37:08 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1685597828; bh=R+Pz7YByYt2SATeGDLe/ccdxjieXmmvUqEMemvxyK3o=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=GE4qmciVDxM7OEXSzFXGcIiE537k0frwF7ZjWFt55Hd1bYs/DGl/p7zSrwRQoqtWT MlRuagrWKA6v6096m9Rwnx1B2UCEMyAVAQeCVhtuWL1ddPtb3rBLww2tWW34yZ/t/K lMwcGIeqid4xvnxfCKa3NxUbmxKYBzfp1Frhn6O4= Authentication-Results: mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij , Alessandro Zummo , Alexandre Belloni Cc: Nikita Shubin , Michael Peters , Kris Bahnsen , linux-rtc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 11/43] rtc: ep93xx: add DT support for Cirrus EP93xx Date: Thu, 1 Jun 2023 08:34:02 +0300 Message-Id: <20230601053546.9574-12-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" - Find register range from the device tree. Signed-off-by: Nikita Shubin Reviewed-by: Andy Shevchenko --- Notes: v0 -> v1: =20 - fixed headers drivers/rtc/rtc-ep93xx.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/rtc/rtc-ep93xx.c b/drivers/rtc/rtc-ep93xx.c index acae7f16808f..1fdd20d01560 100644 --- a/drivers/rtc/rtc-ep93xx.c +++ b/drivers/rtc/rtc-ep93xx.c @@ -7,6 +7,7 @@ */ =20 #include +#include #include #include #include @@ -148,9 +149,16 @@ static int ep93xx_rtc_probe(struct platform_device *pd= ev) return devm_rtc_register_device(ep93xx_rtc->rtc); } =20 +static const struct of_device_id ep93xx_rtc_of_ids[] =3D { + { .compatible =3D "cirrus,ep9301-rtc" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ep93xx_rtc_of_ids); + static struct platform_driver ep93xx_rtc_driver =3D { .driver =3D { .name =3D "ep93xx-rtc", + .of_match_table =3D ep93xx_rtc_of_ids, }, .probe =3D ep93xx_rtc_probe, }; --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D650C7618E for ; Mon, 24 Apr 2023 09:51:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231562AbjDXJvz (ORCPT ); Mon, 24 Apr 2023 05:51:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49716 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231344AbjDXJvj (ORCPT ); Mon, 24 Apr 2023 05:51:39 -0400 Received: from forward501b.mail.yandex.net (forward501b.mail.yandex.net [IPv6:2a02:6b8:c02:900:1:45:d181:d501]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 82444E2; Mon, 24 Apr 2023 02:51:32 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net [IPv6:2a02:6b8:c12:261e:0:640:2e3d:0]) by forward501b.mail.yandex.net (Yandex) with ESMTP id 2C9835EB09; Mon, 24 Apr 2023 12:35:46 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id JZBb1pbWwKo0-PugXVV2y; Mon, 24 Apr 2023 12:35:45 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1682328945; bh=zEohvvi5jcGAdvJYuQgDDbgSuHmAwruvCaRdhaNqILY=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=lT+bS88MebwD7/X8CoNTFe4dw8aR+hv5EJXM/+buz/nbg4M7wWjfTCO77HWO5Paym I8UGTcsfTyXK6H6y3xLjkxjsGLQuZ5voQfsnj7ZW2Sh8HChCK0QVIos1P4fuMP+dyQ lwQGxwxVswX1S2MkQ8CvA59JOZmcuUT9+6nN+dc8= Authentication-Results: mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , Rob Herring , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Hartley Sweeten , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 11/43] dt-bindings: clock: add DT bindings for Cirrus EP93xx Date: Mon, 24 Apr 2023 15:34:27 +0300 Message-Id: <20230424123522.18302-12-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds device tree bindings for the Cirrus Logic EP93xx clock block used in these SoCs. Signed-off-by: Nikita Shubin --- .../devicetree/bindings/arm/ep93xx.yaml | 102 ++++++++++++++++++ .../dt-bindings/clock/cirrus,ep93xx-clock.h | 53 +++++++++ 2 files changed, 155 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/ep93xx.yaml create mode 100644 include/dt-bindings/clock/cirrus,ep93xx-clock.h diff --git a/Documentation/devicetree/bindings/arm/ep93xx.yaml b/Documentat= ion/devicetree/bindings/arm/ep93xx.yaml new file mode 100644 index 000000000000..de7020f4f356 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/ep93xx.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/ep93xx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logick EP93xx device tree bindings + +description: |+ + The EP93xx SoC is a ARMv4T-based with 200 MHz ARM9 CPU. + +maintainers: + - Hartley Sweeten + - Alexander Sverdlin + - Nikita Shubin + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: The TS-7250 is a compact, full-featured Single Board = Computer (SBC) + based upon the Cirrus EP9302 ARM9 CPU. + items: + - const: technologic,ts7250 + - const: liebherr,bk3 + - const: cirrus,ep9301 + - const: cirrus,edb9302 + + soc: + type: object + patternProperties: + "^.*syscon@80930000$": + type: object + properties: + compatible: + items: + - const: cirrus,ep9301-syscon + - const: syscon + - const: simple-mfd + ep9301-reboot: + type: object + properties: + compatible: + const: cirrus,ep9301-reboot + required: + - compatible + - reg + - '#clock-cells' + - ep9301-reboot + + "^.*timer@80810000$": + type: object + properties: + compatible: + const: cirrus,ep9301-timer + + required: + - syscon@80930000 + - timer@80810000 + +required: + - compatible + - soc + +additionalProperties: true + +examples: + - | + / { + compatible =3D "technologic,ts7250", "cirrus,ep9301"; + model =3D "TS-7250 SBC"; + #address-cells =3D <1>; + #size-cells =3D <1>; + soc { + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + compatible =3D "simple-bus"; + + syscon: syscon@80930000 { + compatible =3D "cirrus,ep9301-syscon", + "syscon", "simple-mfd"; + reg =3D <0x80930000 0x1000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + + ep9301-reboot { + compatible =3D "cirrus,ep9301-reboot"; + }; + }; + + timer: timer@80810000 { + compatible =3D "cirrus,ep9301-timer"; + reg =3D <0x80810000 0x100>; + interrupt-parent =3D <&vic1>; + interrupts =3D <19>; + }; + }; + }; + +... diff --git a/include/dt-bindings/clock/cirrus,ep93xx-clock.h b/include/dt-b= indings/clock/cirrus,ep93xx-clock.h new file mode 100644 index 000000000000..ad796314fb11 --- /dev/null +++ b/include/dt-bindings/clock/cirrus,ep93xx-clock.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef DT_BINDINGS_CIRRUS_EP93XX_CLOCK_H +#define DT_BINDINGS_CIRRUS_EP93XX_CLOCK_H + +#define EP93XX_CLK_XTALI 0 + +#define EP93XX_CLK_PLL1 1 +#define EP93XX_CLK_FCLK 2 +#define EP93XX_CLK_HCLK 3 +#define EP93XX_CLK_PCLK 4 +#define EP93XX_CLK_PLL2 5 + +#define EP93XX_CLK_UART 6 + +#define EP93XX_CLK_UART1 7 +#define EP93XX_CLK_UART2 8 +#define EP93XX_CLK_UART3 9 + +#define EP93XX_CLK_M2M0 10 +#define EP93XX_CLK_M2M1 11 + +#define EP93XX_CLK_M2P0 12 +#define EP93XX_CLK_M2P1 13 +#define EP93XX_CLK_M2P2 14 +#define EP93XX_CLK_M2P3 15 +#define EP93XX_CLK_M2P4 16 +#define EP93XX_CLK_M2P5 17 +#define EP93XX_CLK_M2P6 18 +#define EP93XX_CLK_M2P7 19 +#define EP93XX_CLK_M2P8 20 +#define EP93XX_CLK_M2P9 21 + +#define EP93XX_CLK_SPI 22 + +#define EP93XX_CLK_USB 23 + +#define EP93XX_CLK_ADC 24 +#define EP93XX_CLK_ADC_EN 25 + +#define EP93XX_CLK_KEYPAD 26 + +#define EP93XX_CLK_PWM 27 + +#define EP93XX_CLK_VIDEO 28 + +#define EP93XX_CLK_I2S_MCLK 29 +#define EP93XX_CLK_I2S_SCLK 30 +#define EP93XX_CLK_I2S_LRCLK 31 + + +#define EP93XX_NUM_CLKS (EP93XX_CLK_I2S_LRCLK + 1) + +#endif /* DT_BINDINGS_CIRRUS_EP93XX_CLOCK_H */ --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E9ACC77B7E for ; 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a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1685597830; bh=tbntiGejzUX9Xa7D02DcVIzLdCU/SNV9zJmM1dCdOAM=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=su6Vrc1ACopG+w/X8BL0atMVhqY2XhPeLhyc17GBJEqlMO7CCYGu2U/8ePY0+euHJ Pco3/BZ2HM/CJ2EqJwJ6clPTr9s8oVX3zO4MbSZbd/n/V4+RKehElzUJnNyIwRrnqz vT0C44DCNiFozHpsLUr4JtmxBuLZBwTmBe10U7uI= Authentication-Results: mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij , Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Nikita Shubin Cc: Michael Peters , Kris Bahnsen , linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 12/43] dt-bindings: watchdog: Add Cirrus EP93x Date: Thu, 1 Jun 2023 08:34:03 +0300 Message-Id: <20230601053546.9574-13-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds device tree bindings for the Cirrus Logic EP93xx watchdog block used in these SoCs. Signed-off-by: Nikita Shubin --- Notes: v0 -> v1: Krzysztof Kozlowski: - replaced maintainers to me and Alexander - removed wildcards - use fallback compatible and list all possible compatibles - dropped label - dropped quotes in ref - fix ident - fixed description .../bindings/watchdog/cirrus,ep9301-wdt.yaml | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/cirrus,ep930= 1-wdt.yaml diff --git a/Documentation/devicetree/bindings/watchdog/cirrus,ep9301-wdt.y= aml b/Documentation/devicetree/bindings/watchdog/cirrus,ep9301-wdt.yaml new file mode 100644 index 000000000000..d54595174a12 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/cirrus,ep9301-wdt.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/cirrus,ep9301-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic EP93xx Watchdog Timer + +maintainers: + - Nikita Shubin + - Alexander Sverdlin + +description: + Cirrus Logic EP93xx SoC family has it's own watchdog implementation + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + oneOf: + - const: cirrus,ep9301-wdt + - items: + - enum: + - cirrus,ep9302-wdt + - cirrus,ep9307-wdt + - cirrus,ep9312-wdt + - cirrus,ep9315-wdt + - const: cirrus,ep9301-wdt + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + watchdog@80940000 { + compatible =3D "cirrus,ep9301-wdt"; + reg =3D <0x80940000 0x08>; + }; + --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0F90C77B61 for ; Mon, 24 Apr 2023 09:51:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via 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t=1682328946; bh=w0ppteDq/qqsUSxCdi4TNLRnjUB//w+l0T7HBBB8MOU=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=kfLH3T6B6v9N6JTM7y95P4f1tFoKY3f9qezcNR9NVhW89fITPv8LUNQv03AugOuJu kLsFe0NTdOLh2WZtVxb41gDba2RvdZU6YR8NOY/mh6pRx5zQCQJzwRg8ch69Ppb2YZ 9FSwX7ItRLMbC3IkWKWO0SLA3zE1U1Cid61DtJw0= Authentication-Results: mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 12/43] clk: ep93xx: add DT support for Cirrus EP93xx Date: Mon, 24 Apr 2023 15:34:28 +0300 Message-Id: <20230424123522.18302-13-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This is a rewrite of EP93xx timer driver in arch/arm/mach-ep93xx/clock.c trying to do everything the device tree way: - convert to syscon driver - provide clock acces via of Co-developed-by: Alexander Sverdlin Signed-off-by: Alexander Sverdlin Signed-off-by: Nikita Shubin --- Notes: rfc->v0 Linus Walleij: - renamed all __underscore =20 Alexander Sverdlin: - "Logick" -> "Logic" =20 Changes by Alexander Sverdlin: - remove pr_info - DIV_ROUND_UP_ULL -> DIV_ROUND_CLOSEST - fix zeroing bitfield in ep93xx_div_set_rate - add sanity check for EP93XX_SYSCON_CHIPID_ID - use bit index for DMA clock's - ep93xx_clk_register_gate() takes bit index, not mask - remove redundant define - use DIV_ROUND_CLOSEST() everywhere to achieve frequencies closer to t= hose requested - Add the forgotten configuration from the deleted arch/arm/mach-ep93xx/core.c drivers/clk/Kconfig | 8 + drivers/clk/Makefile | 1 + drivers/clk/clk-ep93xx.c | 880 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 889 insertions(+) create mode 100644 drivers/clk/clk-ep93xx.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 1eef05bb1f99..d3ad975b688e 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -436,6 +436,14 @@ config COMMON_CLK_K210 help Support for the Canaan Kendryte K210 RISC-V SoC clocks. =20 +config COMMON_CLK_EP93XX + bool "Clock driver for Cirrus Logic ep93xx SoC" + depends on ARCH_EP93XX || COMPILE_TEST + select MFD_SYSCON + select REGMAP + help + This driver supports the SoC clocks on the Cirrus Logic ep93xx. + source "drivers/clk/actions/Kconfig" source "drivers/clk/analogbits/Kconfig" source "drivers/clk/baikal-t1/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index e3ca0d058a25..deec25ffd004 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE706) +=3D clk-cdce706.o obj-$(CONFIG_COMMON_CLK_CDCE925) +=3D clk-cdce925.o obj-$(CONFIG_ARCH_CLPS711X) +=3D clk-clps711x.o obj-$(CONFIG_COMMON_CLK_CS2000_CP) +=3D clk-cs2000-cp.o +obj-$(CONFIG_COMMON_CLK_EP93XX) +=3D clk-ep93xx.o obj-$(CONFIG_ARCH_SPARX5) +=3D clk-sparx5.o obj-$(CONFIG_COMMON_CLK_EN7523) +=3D clk-en7523.o obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) +=3D clk-fixed-mmio.o diff --git a/drivers/clk/clk-ep93xx.c b/drivers/clk/clk-ep93xx.c new file mode 100644 index 000000000000..e5913fc4c39b --- /dev/null +++ b/drivers/clk/clk-ep93xx.c @@ -0,0 +1,880 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Clock control for Cirrus EP93xx chips. + * Copyright (C) 2021 Nikita Shubin + * + * Based on a rewrite of arch/arm/mach-ep93xx/clock.c: + * Copyright (C) 2006 Lennert Buytenhek + */ +#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define EP93XX_EXT_CLK_RATE 14745600 +#define EP93XX_EXT_RTC_RATE 32768 + +#define EP93XX_SYSCON_POWER_STATE 0x00 +#define EP93XX_SYSCON_PWRCNT 0x04 +#define EP93XX_SYSCON_PWRCNT_UARTBAUD BIT(29) +#define EP93XX_SYSCON_PWRCNT_USH_EN 28 +#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 27 +#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 26 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 25 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 24 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 23 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 22 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 21 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 20 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 19 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 18 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 17 +#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 16 +#define EP93XX_SYSCON_CLKSET1 0x20 +#define EP93XX_SYSCON_CLKSET1_NBYP1 BIT(23) +#define EP93XX_SYSCON_CLKSET2 0x24 +#define EP93XX_SYSCON_CLKSET2_NBYP2 BIT(19) +#define EP93XX_SYSCON_CLKSET2_PLL2_EN BIT(18) +#define EP93XX_SYSCON_DEVCFG 0x80 +#define EP93XX_SYSCON_DEVCFG_U3EN 24 +#define EP93XX_SYSCON_DEVCFG_U2EN 20 +#define EP93XX_SYSCON_DEVCFG_U1EN 18 +#define EP93XX_SYSCON_VIDCLKDIV 0x84 +#define EP93XX_SYSCON_CLKDIV_ENABLE 15 +#define EP93XX_SYSCON_CLKDIV_ESEL BIT(14) +#define EP93XX_SYSCON_CLKDIV_PSEL BIT(13) +#define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8 +#define EP93XX_SYSCON_I2SCLKDIV 0x8c +#define EP93XX_SYSCON_I2SCLKDIV_SENA 31 +#define EP93XX_SYSCON_I2SCLKDIV_ORIDE BIT(29) +#define EP93XX_SYSCON_I2SCLKDIV_SPOL BIT(19) +#define EP93XX_I2SCLKDIV_SDIV (1 << 16) +#define EP93XX_I2SCLKDIV_LRDIV32 (0 << 17) +#define EP93XX_I2SCLKDIV_LRDIV64 (1 << 17) +#define EP93XX_I2SCLKDIV_LRDIV128 (2 << 17) +#define EP93XX_I2SCLKDIV_LRDIV_MASK (3 << 17) +#define EP93XX_SYSCON_KEYTCHCLKDIV 0x90 +#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN 31 +#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV 16 +#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN 15 +#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV 0 +#define EP93XX_SYSCON_CHIPID 0x94 +#define EP93XX_SYSCON_CHIPID_ID 0x9213 + +static DEFINE_SPINLOCK(clk_lock); +static struct regmap *ep93xx_map; +#define ep93xx_regmap_read(reg, val) regmap_read(ep93xx_map, reg, val) + +/* Keeps track of all clocks */ +static struct clk_hw_onecell_data *ep93xx_clk_data; + +static char fclk_divisors[] =3D { 1, 2, 4, 8, 16, 1, 1, 1 }; +static char hclk_divisors[] =3D { 1, 2, 4, 5, 6, 8, 16, 32 }; +static char pclk_divisors[] =3D { 1, 2, 4, 8 }; + +static char adc_divisors[] =3D { 16, 4 }; +static char sclk_divisors[] =3D { 2, 4 }; +static char lrclk_divisors[] =3D { 32, 64, 128 }; + +static const char * const mux_parents[] =3D { + "xtali", + "pll1", + "pll2" +}; + +/* + * PLL rate =3D 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^= PS + */ +static unsigned long calc_pll_rate(unsigned long long rate, u32 config_wor= d) +{ + int i; + + rate *=3D ((config_word >> 11) & 0x1f) + 1; /* X1FBD */ + rate *=3D ((config_word >> 5) & 0x3f) + 1; /* X2FBD */ + do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */ + for (i =3D 0; i < ((config_word >> 16) & 3); i++) /* PS */ + rate >>=3D 1; + + return (unsigned long)rate; +} + +struct clk_psc { + struct clk_hw hw; + unsigned int reg; + u8 bit_idx; + u32 mask; + u8 shift; + u8 width; + char *div; + u8 num_div; + spinlock_t *lock; +}; + +#define to_clk_psc(_hw) container_of(_hw, struct clk_psc, hw) + +static int ep93xx_clk_is_enabled(struct clk_hw *hw) +{ + struct clk_psc *psc =3D to_clk_psc(hw); + u32 val; + + ep93xx_regmap_read(psc->reg, &val); + + return (val & BIT(psc->bit_idx)) ? 1 : 0; +} + +static int ep93xx_clk_enable(struct clk_hw *hw) +{ + struct clk_psc *psc =3D to_clk_psc(hw); + unsigned long flags =3D 0; + u32 val; + + if (psc->lock) + spin_lock_irqsave(psc->lock, flags); + + ep93xx_regmap_read(psc->reg, &val); + val |=3D BIT(psc->bit_idx); + + ep93xx_syscon_swlocked_write(val, psc->reg); + + if (psc->lock) + spin_unlock_irqrestore(psc->lock, flags); + + return 0; +} + +static void ep93xx_clk_disable(struct clk_hw *hw) +{ + struct clk_psc *psc =3D to_clk_psc(hw); + unsigned long flags =3D 0; + u32 val; + + if (psc->lock) + spin_lock_irqsave(psc->lock, flags); + + ep93xx_regmap_read(psc->reg, &val); + val &=3D ~BIT(psc->bit_idx); + + ep93xx_syscon_swlocked_write(val, psc->reg); + + if (psc->lock) + spin_unlock_irqrestore(psc->lock, flags); +} + +static const struct clk_ops clk_ep93xx_gate_ops =3D { + .enable =3D ep93xx_clk_enable, + .disable =3D ep93xx_clk_disable, + .is_enabled =3D ep93xx_clk_is_enabled, +}; + +static struct clk_hw *ep93xx_clk_register_gate(const char *name, + const char *parent_name, + unsigned int reg, + u8 bit_idx) +{ + struct clk_init_data init; + struct clk_psc *psc; + struct clk *clk; + + psc =3D kzalloc(sizeof(*psc), GFP_KERNEL); + if (!psc) + return ERR_PTR(-ENOMEM); + + init.name =3D name; + init.ops =3D &clk_ep93xx_gate_ops; + init.flags =3D CLK_SET_RATE_PARENT; + init.parent_names =3D (parent_name ? &parent_name : NULL); + init.num_parents =3D (parent_name ? 1 : 0); + + psc->reg =3D reg; + psc->bit_idx =3D bit_idx; + psc->hw.init =3D &init; + psc->lock =3D &clk_lock; + + clk =3D clk_register(NULL, &psc->hw); + if (IS_ERR(clk)) { + kfree(psc); + return ERR_CAST(clk); + } + + return &psc->hw; +} + +static u8 ep93xx_mux_get_parent(struct clk_hw *hw) +{ + struct clk_psc *psc =3D to_clk_psc(hw); + u32 val; + + ep93xx_regmap_read(psc->reg, &val); + if (!(val & EP93XX_SYSCON_CLKDIV_ESEL)) + return 0; + + if (!(val & EP93XX_SYSCON_CLKDIV_PSEL)) + return 1; + + return 2; +} + +static int ep93xx_mux_set_parent_lock(struct clk_hw *hw, u8 index) +{ + struct clk_psc *psc =3D to_clk_psc(hw); + unsigned long flags =3D 0; + u32 val; + + if (index >=3D ARRAY_SIZE(mux_parents)) + return -EINVAL; + + if (psc->lock) + spin_lock_irqsave(psc->lock, flags); + + ep93xx_regmap_read(psc->reg, &val); + val &=3D ~(EP93XX_SYSCON_CLKDIV_ESEL | EP93XX_SYSCON_CLKDIV_PSEL); + + if (index !=3D 0) { + val |=3D EP93XX_SYSCON_CLKDIV_ESEL; + val |=3D (index - 1) ? EP93XX_SYSCON_CLKDIV_PSEL : 0; + } + + ep93xx_syscon_swlocked_write(val, psc->reg); + + if (psc->lock) + spin_unlock_irqrestore(psc->lock, flags); + + return 0; +} + +static bool is_best(unsigned long rate, unsigned long now, + unsigned long best) +{ + return abs(rate - now) < abs(rate - best); +} + +static int ep93xx_mux_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + unsigned long rate =3D req->rate; + struct clk *parent_best =3D NULL; + unsigned long parent_rate; + unsigned long best_rate =3D 0, actual_rate, mclk_rate; + unsigned long parent_rate_best; + int div, pdiv; + int i; + + /* + * Try the two pll's and the external clock + * Because the valid predividers are 2, 2.5 and 3, we multiply + * all the clocks by 2 to avoid floating point math. + * + * This is based on the algorithm in the ep93xx raster guide: + * http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf + * + */ + for (i =3D 0; i < ARRAY_SIZE(mux_parents); i++) { + struct clk *parent =3D clk_get_sys(mux_parents[i], NULL); + + parent_rate =3D clk_get_rate(parent); + mclk_rate =3D parent_rate * 2; + + /* Try each predivider value */ + for (pdiv =3D 4; pdiv <=3D 6; pdiv++) { + div =3D DIV_ROUND_CLOSEST(mclk_rate, rate * pdiv); + if (div < 1 || div > 127) + continue; + + actual_rate =3D DIV_ROUND_CLOSEST(mclk_rate, pdiv * div); + + if (is_best(rate, actual_rate, best_rate)) { + best_rate =3D actual_rate; + parent_rate_best =3D parent_rate; + parent_best =3D parent; + } + } + } + + if (!parent_best) + return -EINVAL; + + req->best_parent_rate =3D parent_rate_best; + req->best_parent_hw =3D __clk_get_hw(parent_best); + req->rate =3D best_rate; + + return 0; +} + +static unsigned long ep93xx_ddiv_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_psc *psc =3D to_clk_psc(hw); + unsigned long rate =3D 0; + u32 val; + int pdiv, div; + + ep93xx_regmap_read(psc->reg, &val); + pdiv =3D ((val >> EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) & 0x03); + div =3D val & 0x7f; + if (div > 0) + rate =3D DIV_ROUND_CLOSEST(parent_rate * 2, (pdiv + 3) * div); + + return rate; +} + +static int ep93xx_ddiv_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_psc *psc =3D to_clk_psc(hw); + int pdiv, div, npdiv, ndiv; + unsigned long actual_rate, mclk_rate, rate_err =3D -1; + int found =3D 0; + u32 val; + + ep93xx_regmap_read(psc->reg, &val); + mclk_rate =3D parent_rate * 2; + + for (pdiv =3D 4; pdiv <=3D 6; pdiv++) { + div =3D DIV_ROUND_CLOSEST(mclk_rate, rate * pdiv); + if (div < 1 || div > 127) + continue; + + actual_rate =3D DIV_ROUND_CLOSEST(mclk_rate, pdiv * div); + + if (!found || abs(actual_rate - rate) < rate_err) { + npdiv =3D pdiv - 3; + ndiv =3D div; + rate_err =3D abs(actual_rate - rate); + found =3D 1; + } + } + + if (!found) + return -EINVAL; + + /* Clear old dividers */ + val &=3D ~0x37f; + + /* Set the new pdiv and div bits for the new clock rate */ + val |=3D (npdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | ndiv; + + ep93xx_syscon_swlocked_write(val, psc->reg); + + return 0; +} + +static const struct clk_ops clk_ddiv_ops =3D { + .enable =3D ep93xx_clk_enable, + .disable =3D ep93xx_clk_disable, + .is_enabled =3D ep93xx_clk_is_enabled, + .get_parent =3D ep93xx_mux_get_parent, + .set_parent =3D ep93xx_mux_set_parent_lock, + .determine_rate =3D ep93xx_mux_determine_rate, + .recalc_rate =3D ep93xx_ddiv_recalc_rate, + .set_rate =3D ep93xx_ddiv_set_rate, +}; + +static struct clk_hw *clk_hw_register_ddiv(const char *name, + unsigned int reg, + u8 bit_idx) +{ + struct clk_init_data init; + struct clk_psc *psc; + struct clk *clk; + + psc =3D kzalloc(sizeof(*psc), GFP_KERNEL); + if (!psc) + return ERR_PTR(-ENOMEM); + + init.name =3D name; + init.ops =3D &clk_ddiv_ops; + init.flags =3D 0; + init.parent_names =3D mux_parents; + init.num_parents =3D ARRAY_SIZE(mux_parents); + + psc->reg =3D reg; + psc->bit_idx =3D bit_idx; + psc->lock =3D &clk_lock; + psc->hw.init =3D &init; + + clk =3D clk_register(NULL, &psc->hw); + if (IS_ERR(clk)) { + kfree(psc); + return ERR_CAST(clk); + } + + return &psc->hw; +} + +static unsigned long ep93xx_div_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_psc *psc =3D to_clk_psc(hw); + u32 val; + u8 index; + + ep93xx_regmap_read(psc->reg, &val); + index =3D (val & psc->mask) >> psc->shift; + if (index > psc->num_div) + return 0; + + return DIV_ROUND_CLOSEST(parent_rate, psc->div[index]); +} + +static long ep93xx_div_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct clk_psc *psc =3D to_clk_psc(hw); + unsigned long best =3D 0, now; + bool assigned =3D false; + int i; + + for (i =3D 0; i < psc->num_div; i++) { + if ((rate * psc->div[i]) =3D=3D *parent_rate) + return rate; + + now =3D DIV_ROUND_CLOSEST(*parent_rate, psc->div[i]); + + if (!assigned || is_best(rate, now, best)) + best =3D now; + assigned =3D true; + } + + return best; +} + +static int ep93xx_div_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_psc *psc =3D to_clk_psc(hw); + u32 val; + int i; + + ep93xx_regmap_read(psc->reg, &val); + val &=3D ~psc->mask; + for (i =3D 0; i < psc->num_div; i++) + if (rate =3D=3D DIV_ROUND_CLOSEST(parent_rate, psc->div[i])) { + val |=3D i << psc->shift; + break; + } + + if (i =3D=3D psc->num_div) + return -EINVAL; + + ep93xx_syscon_swlocked_write(val, psc->reg); + + return 0; +} + +static const struct clk_ops ep93xx_div_ops =3D { + .enable =3D ep93xx_clk_enable, + .disable =3D ep93xx_clk_disable, + .is_enabled =3D ep93xx_clk_is_enabled, + .recalc_rate =3D ep93xx_div_recalc_rate, + .round_rate =3D ep93xx_div_round_rate, + .set_rate =3D ep93xx_div_set_rate, +}; + +static struct clk_hw *clk_hw_register_div(const char *name, + const char *parent_name, + unsigned int reg, + u8 enable_bit, + u8 shift, + u8 width, + char *clk_divisors, + u8 num_div) +{ + struct clk_init_data init; + struct clk_psc *psc; + struct clk *clk; + + psc =3D kzalloc(sizeof(*psc), GFP_KERNEL); + if (!psc) + return ERR_PTR(-ENOMEM); + + init.name =3D name; + init.ops =3D &ep93xx_div_ops; + init.flags =3D 0; + init.parent_names =3D (parent_name ? &parent_name : NULL); + init.num_parents =3D 1; + + psc->reg =3D reg; + psc->bit_idx =3D enable_bit; + psc->mask =3D GENMASK(shift + width - 1, shift); + psc->shift =3D shift; + psc->div =3D clk_divisors; + psc->num_div =3D num_div; + psc->lock =3D &clk_lock; + psc->hw.init =3D &init; + + clk =3D clk_register(NULL, &psc->hw); + if (IS_ERR(clk)) { + kfree(psc); + return ERR_CAST(clk); + } + + return &psc->hw; +} + +struct ep93xx_gate { + unsigned int idx; + unsigned int bit; + const char *dev_id; + const char *con_id; +}; + +static struct ep93xx_gate ep93xx_uarts[] =3D { + {EP93XX_CLK_UART1, EP93XX_SYSCON_DEVCFG_U1EN, "apb:uart1", NULL}, + {EP93XX_CLK_UART2, EP93XX_SYSCON_DEVCFG_U2EN, "apb:uart2", NULL}, + {EP93XX_CLK_UART3, EP93XX_SYSCON_DEVCFG_U3EN, "apb:uart3", NULL}, +}; + +static void ep93xx_uart_clock_init(void) +{ + unsigned int i; + struct clk_hw *hw; + u32 val; + unsigned int clk_uart_div; + + ep93xx_regmap_read(EP93XX_SYSCON_PWRCNT, &val); + if (val & EP93XX_SYSCON_PWRCNT_UARTBAUD) + clk_uart_div =3D 1; + else + clk_uart_div =3D 2; + + hw =3D clk_hw_register_fixed_factor(NULL, "uart", "xtali", 0, 1, clk_uart= _div); + ep93xx_clk_data->hws[EP93XX_CLK_UART] =3D hw; + + /* parenting uart gate clocks to uart clock */ + for (i =3D 0; i < ARRAY_SIZE(ep93xx_uarts); i++) { + hw =3D ep93xx_clk_register_gate(ep93xx_uarts[i].dev_id, + "uart", + EP93XX_SYSCON_DEVCFG, + ep93xx_uarts[i].bit); + + ep93xx_clk_data->hws[ep93xx_uarts[i].idx] =3D hw; + } +} + +static struct ep93xx_gate ep93xx_dmas[] =3D { + {EP93XX_CLK_M2P0, EP93XX_SYSCON_PWRCNT_DMA_M2P0, NULL, "m2p0"}, + {EP93XX_CLK_M2P1, EP93XX_SYSCON_PWRCNT_DMA_M2P1, NULL, "m2p1"}, + {EP93XX_CLK_M2P2, EP93XX_SYSCON_PWRCNT_DMA_M2P2, NULL, "m2p2"}, + {EP93XX_CLK_M2P3, EP93XX_SYSCON_PWRCNT_DMA_M2P3, NULL, "m2p3"}, + {EP93XX_CLK_M2P4, EP93XX_SYSCON_PWRCNT_DMA_M2P4, NULL, "m2p4"}, + {EP93XX_CLK_M2P5, EP93XX_SYSCON_PWRCNT_DMA_M2P5, NULL, "m2p5"}, + {EP93XX_CLK_M2P6, EP93XX_SYSCON_PWRCNT_DMA_M2P6, NULL, "m2p6"}, + {EP93XX_CLK_M2P7, EP93XX_SYSCON_PWRCNT_DMA_M2P7, NULL, "m2p7"}, + {EP93XX_CLK_M2P8, EP93XX_SYSCON_PWRCNT_DMA_M2P8, NULL, "m2p8"}, + {EP93XX_CLK_M2P9, EP93XX_SYSCON_PWRCNT_DMA_M2P9, NULL, "m2p9"}, + {EP93XX_CLK_M2M0, EP93XX_SYSCON_PWRCNT_DMA_M2M0, NULL, "m2m0"}, + {EP93XX_CLK_M2M1, EP93XX_SYSCON_PWRCNT_DMA_M2M1, NULL, "m2m1"}, +}; + +static void ep93xx_dma_clock_init(void __iomem *base) +{ + int i; + struct clk_hw *hw; + int ret; + + for (i =3D 0; i < ARRAY_SIZE(ep93xx_dmas); i++) { + hw =3D clk_hw_register_gate(NULL, ep93xx_dmas[i].con_id, + "hclk", 0, + base + EP93XX_SYSCON_PWRCNT, + ep93xx_dmas[i].bit, + 0, + &clk_lock); + + ret =3D clk_hw_register_clkdev(hw, ep93xx_dmas[i].con_id, NULL); + if (ret) { + pr_err("%s: failed to register lookup %s\n", + __func__, ep93xx_dmas[i].con_id); + continue; + } + + ep93xx_clk_data->hws[ep93xx_dmas[i].idx] =3D hw; + } +} + +static int ep93xx_clk_probe(struct platform_device *pdev) +{ + void __iomem *base; + unsigned int clk_usb_div; + unsigned long clk_spi_div; + struct clk_hw *hw; + struct device *dev =3D &pdev->dev; + u32 value; + struct resource *res; + + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + base =3D devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + ep93xx_regmap_read(EP93XX_SYSCON_CLKSET2, &value); + clk_usb_div =3D (((value >> 28) & 0xf) + 1); + hw =3D clk_hw_register_fixed_factor(NULL, "usb_clk", "pll2", 0, 1, clk_us= b_div); + hw =3D clk_hw_register_gate(NULL, "ohci-platform", + "usb_clk", 0, + base + EP93XX_SYSCON_PWRCNT, + EP93XX_SYSCON_PWRCNT_USH_EN, + 0, + &clk_lock); + clk_hw_register_clkdev(hw, NULL, "ohci-platform"); + ep93xx_clk_data->hws[EP93XX_CLK_USB] =3D hw; + + /* + * EP93xx SSP clock rate was doubled in version E2. For more information + * see: + * http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf + */ + clk_spi_div =3D 1; + if (ep93xx_chip_revision() < EP93XX_CHIP_REV_E2) + clk_spi_div =3D 2; + hw =3D clk_hw_register_fixed_factor(NULL, "ep93xx-spi.0", "xtali", 0, 1, = clk_spi_div); + clk_hw_register_clkdev(hw, NULL, "ep93xx-spi.0"); + ep93xx_clk_data->hws[EP93XX_CLK_SPI] =3D hw; + + /* pwm clock */ + hw =3D clk_hw_register_fixed_factor(NULL, "pwm_clk", "xtali", 0, 1, 1); + clk_hw_register_clkdev(hw, "pwm_clk", NULL); + ep93xx_clk_data->hws[EP93XX_CLK_PWM] =3D hw; + + ep93xx_uart_clock_init(); + + /* touchscreen/adc clock */ + hw =3D clk_hw_register_div("ep93xx-adc", + "xtali", + EP93XX_SYSCON_KEYTCHCLKDIV, + EP93XX_SYSCON_KEYTCHCLKDIV_TSEN, + EP93XX_SYSCON_KEYTCHCLKDIV_ADIV, + 1, + adc_divisors, + ARRAY_SIZE(adc_divisors)); + + clk_hw_register_clkdev(hw, NULL, "ep93xx-adc"); + ep93xx_clk_data->hws[EP93XX_CLK_ADC] =3D hw; + + /* keypad clock */ + hw =3D clk_hw_register_div("ep93xx-keypad", + "xtali", + EP93XX_SYSCON_KEYTCHCLKDIV, + EP93XX_SYSCON_KEYTCHCLKDIV_KEN, + EP93XX_SYSCON_KEYTCHCLKDIV_KDIV, + 1, + adc_divisors, + ARRAY_SIZE(adc_divisors)); + + clk_hw_register_clkdev(hw, NULL, "ep93xx-keypad"); + ep93xx_clk_data->hws[EP93XX_CLK_KEYPAD] =3D hw; + + /* On reset PDIV and VDIV is set to zero, while PDIV zero + * means clock disable, VDIV shouldn't be zero. + * So i set both dividers to minimum. + */ + /* ENA - Enable CLK divider. */ + /* PDIV - 00 - Disable clock */ + /* VDIV - at least 2 */ + /* Check and enable video clk registers */ + ep93xx_regmap_read(EP93XX_SYSCON_VIDCLKDIV, &value); + value |=3D (1 << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | 2; + ep93xx_syscon_swlocked_write(value, EP93XX_SYSCON_VIDCLKDIV); + + /* check and enable i2s clk registers */ + ep93xx_regmap_read(EP93XX_SYSCON_I2SCLKDIV, &value); + value |=3D (1 << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | 2; + /* + * Override the SAI_MSTR_CLK_CFG from the I2S block and use the + * I2SClkDiv Register settings. LRCLK transitions on the falling SCLK + * edge. + */ + value |=3D EP93XX_SYSCON_I2SCLKDIV_ORIDE | EP93XX_SYSCON_I2SCLKDIV_SPOL; + ep93xx_syscon_swlocked_write(value, EP93XX_SYSCON_I2SCLKDIV); + + /* video clk */ + hw =3D clk_hw_register_ddiv("ep93xx-fb", + EP93XX_SYSCON_VIDCLKDIV, + EP93XX_SYSCON_CLKDIV_ENABLE); + + clk_hw_register_clkdev(hw, NULL, "ep93xx-fb"); + ep93xx_clk_data->hws[EP93XX_CLK_VIDEO] =3D hw; + + /* i2s clk */ + hw =3D clk_hw_register_ddiv("mclk", + EP93XX_SYSCON_I2SCLKDIV, + EP93XX_SYSCON_CLKDIV_ENABLE); + + clk_hw_register_clkdev(hw, "mclk", "ep93xx-i2s"); + ep93xx_clk_data->hws[EP93XX_CLK_I2S_MCLK] =3D hw; + + /* i2s sclk */ +#define EP93XX_I2SCLKDIV_SDIV_SHIFT 16 +#define EP93XX_I2SCLKDIV_SDIV_WIDTH 1 + hw =3D clk_hw_register_div("sclk", + "mclk", + EP93XX_SYSCON_I2SCLKDIV, + EP93XX_SYSCON_I2SCLKDIV_SENA, + EP93XX_I2SCLKDIV_SDIV_SHIFT, + EP93XX_I2SCLKDIV_SDIV_WIDTH, + sclk_divisors, + ARRAY_SIZE(sclk_divisors)); + + clk_hw_register_clkdev(hw, "sclk", "ep93xx-i2s"); + ep93xx_clk_data->hws[EP93XX_CLK_I2S_SCLK] =3D hw; + + /* i2s lrclk */ +#define EP93XX_I2SCLKDIV_LRDIV32_SHIFT 17 +#define EP93XX_I2SCLKDIV_LRDIV32_WIDTH 2 + hw =3D clk_hw_register_div("lrclk", + "sclk", + EP93XX_SYSCON_I2SCLKDIV, + EP93XX_SYSCON_I2SCLKDIV_SENA, + EP93XX_I2SCLKDIV_LRDIV32_SHIFT, + EP93XX_I2SCLKDIV_LRDIV32_WIDTH, + lrclk_divisors, + ARRAY_SIZE(lrclk_divisors)); + + clk_hw_register_clkdev(hw, "lrclk", "ep93xx-i2s"); + ep93xx_clk_data->hws[EP93XX_CLK_I2S_LRCLK] =3D hw; + + /* IrDa clk uses same pattern but no init code presents in original clock= driver */ + return 0; +} + +static const struct of_device_id ep93xx_clk_dt_ids[] =3D { + { .compatible =3D "cirrus,ep9301-syscon", }, + { /* sentinel */ }, +}; + +static struct platform_driver ep93xx_clk_driver =3D { + .probe =3D ep93xx_clk_probe, + .driver =3D { + .name =3D "ep93xx-clk", + .of_match_table =3D ep93xx_clk_dt_ids, + .suppress_bind_attrs =3D true, + }, +}; +builtin_platform_driver(ep93xx_clk_driver); + +static void __init ep93xx_clock_init(struct device_node *np) +{ + void __iomem *base; + int i; + int ret; + u32 value; + struct clk_hw *hw; + unsigned long clk_pll1_rate; + unsigned long clk_f_rate; + unsigned long clk_h_rate; + unsigned long clk_p_rate; + unsigned long clk_pll2_rate; + unsigned int clk_f_div; + unsigned int clk_h_div; + unsigned int clk_p_div; + + ep93xx_clk_data =3D kzalloc(struct_size(ep93xx_clk_data, hws, + EP93XX_NUM_CLKS), + GFP_KERNEL); + + if (!ep93xx_clk_data) + return; + + /* + * This way all clock fetched before the platform device probes, + * except those we assign here for early use, will be deferred. + */ + for (i =3D 0; i < EP93XX_NUM_CLKS; i++) + ep93xx_clk_data->hws[i] =3D ERR_PTR(-EPROBE_DEFER); + + base =3D of_iomap(np, 0); + /* Remap the system controller for the exclusive register */ + if (IS_ERR(base)) { + pr_err("failed to map base\n"); + return; + } + + ep93xx_map =3D syscon_node_to_regmap(np); + if (IS_ERR(ep93xx_map)) { + pr_err("no syscon regmap\n"); + return; + } + + /* + * We check that the regmap works on this very first access, + * but as this is an MMIO-backed regmap, subsequent regmap + * access is not going to fail and we skip error checks from + * this point. + */ + ret =3D ep93xx_regmap_read(EP93XX_SYSCON_CHIPID, &value); + if (ret || (value & 0xffff) !=3D EP93XX_SYSCON_CHIPID_ID) { + pr_err("failed to read global status register\n"); + return; + } + + hw =3D clk_hw_register_fixed_rate(NULL, "xtali", NULL, 0, EP93XX_EXT_CLK_= RATE); + clk_hw_register_clkdev(hw, NULL, "xtali"); + + /* Determine the bootloader configured pll1 rate */ + ep93xx_regmap_read(EP93XX_SYSCON_CLKSET1, &value); + if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1)) + clk_pll1_rate =3D EP93XX_EXT_CLK_RATE; + else + clk_pll1_rate =3D calc_pll_rate(EP93XX_EXT_CLK_RATE, value); + + hw =3D clk_hw_register_fixed_rate(NULL, "pll1", "xtali", 0, clk_pll1_rate= ); + clk_hw_register_clkdev(hw, NULL, "pll1"); + ep93xx_clk_data->hws[EP93XX_CLK_PLL1] =3D hw; + + /* Initialize the pll1 derived clocks */ + clk_f_div =3D fclk_divisors[(value >> 25) & 0x7]; + clk_h_div =3D hclk_divisors[(value >> 20) & 0x7]; + clk_p_div =3D pclk_divisors[(value >> 18) & 0x3]; + + hw =3D clk_hw_register_fixed_factor(NULL, "fclk", "pll1", 0, 1, clk_f_div= ); + clk_f_rate =3D clk_get_rate(hw->clk); + ep93xx_clk_data->hws[EP93XX_CLK_FCLK] =3D hw; + hw =3D clk_hw_register_fixed_factor(NULL, "hclk", "pll1", 0, 1, clk_h_div= ); + clk_h_rate =3D clk_get_rate(hw->clk); + ep93xx_clk_data->hws[EP93XX_CLK_HCLK] =3D hw; + hw =3D clk_hw_register_fixed_factor(NULL, "pclk", "hclk", 0, 1, clk_p_div= ); + clk_p_rate =3D clk_get_rate(hw->clk); + ep93xx_clk_data->hws[EP93XX_CLK_PCLK] =3D hw; + + clk_hw_register_clkdev(hw, "apb_pclk", NULL); + + ep93xx_dma_clock_init(base); + + /* Determine the bootloader configured pll2 rate */ + ep93xx_regmap_read(EP93XX_SYSCON_CLKSET2, &value); + if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2)) + clk_pll2_rate =3D EP93XX_EXT_CLK_RATE; + else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN) + clk_pll2_rate =3D calc_pll_rate(EP93XX_EXT_CLK_RATE, value); + else + clk_pll2_rate =3D 0; + + hw =3D clk_hw_register_fixed_rate(NULL, "pll2", "xtali", 0, clk_pll2_rate= ); + ep93xx_clk_data->hws[EP93XX_CLK_PLL2] =3D hw; + clk_hw_register_clkdev(hw, NULL, "pll2"); + + ep93xx_clk_data->num =3D EP93XX_NUM_CLKS; + of_clk_add_hw_provider(np, of_clk_hw_onecell_get, ep93xx_clk_data); + + pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n", + clk_pll1_rate / 1000000, clk_pll2_rate / 1000000); + pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n", + clk_f_rate / 1000000, clk_h_rate / 1000000, + clk_p_rate / 1000000); +} +CLK_OF_DECLARE_DRIVER(ep93xx_cc, "cirrus,ep9301-syscon", ep93xx_clock_init= ); --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D732C77B61 for ; Mon, 24 Apr 2023 09:56:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231641AbjDXJz7 (ORCPT ); Mon, 24 Apr 2023 05:55:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54992 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231523AbjDXJzr (ORCPT ); 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dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , Sebastian Reichel , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH 13/43] power: reset: Add a driver for the ep93xx reset Date: Mon, 24 Apr 2023 15:34:29 +0300 Message-Id: <20230424123522.18302-14-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Implement the reset behaviour of the various EP93xx SoCS in drivers/power/r= eset. It used to be located in arch/arm/mach-ep93xx. Signed-off-by: Nikita Shubin Acked-by: Sebastian Reichel --- drivers/power/reset/Kconfig | 10 +++++ drivers/power/reset/Makefile | 1 + drivers/power/reset/ep93xx-restart.c | 65 ++++++++++++++++++++++++++++ 3 files changed, 76 insertions(+) create mode 100644 drivers/power/reset/ep93xx-restart.c diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig index 8c87eeda0fec..2a61afbb047b 100644 --- a/drivers/power/reset/Kconfig +++ b/drivers/power/reset/Kconfig @@ -75,6 +75,16 @@ config POWER_RESET_BRCMSTB Say Y here if you have a Broadcom STB board and you wish to have restart support. =20 +config POWER_RESET_EP93XX + bool "Cirrus EP93XX reset driver" if COMPILE_TEST + depends on MFD_SYSCON + default ARCH_EP93XX + help + This driver provides restart support for Cirrus EP93XX SoC. + + Say Y here if you have a Cirrus EP93XX SoC and you wish + to have restart support. + config POWER_RESET_GEMINI_POWEROFF bool "Cortina Gemini power-off driver" depends on ARCH_GEMINI || COMPILE_TEST diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile index d763e6735ee3..61f4e11619b2 100644 --- a/drivers/power/reset/Makefile +++ b/drivers/power/reset/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_POWER_RESET_ATC260X) +=3D atc260x-poweroff.o obj-$(CONFIG_POWER_RESET_AXXIA) +=3D axxia-reset.o obj-$(CONFIG_POWER_RESET_BRCMKONA) +=3D brcm-kona-reset.o obj-$(CONFIG_POWER_RESET_BRCMSTB) +=3D brcmstb-reboot.o +obj-$(CONFIG_POWER_RESET_EP93XX) +=3D ep93xx-restart.o obj-$(CONFIG_POWER_RESET_GEMINI_POWEROFF) +=3D gemini-poweroff.o obj-$(CONFIG_POWER_RESET_GPIO) +=3D gpio-poweroff.o obj-$(CONFIG_POWER_RESET_GPIO_RESTART) +=3D gpio-restart.o diff --git a/drivers/power/reset/ep93xx-restart.c b/drivers/power/reset/ep9= 3xx-restart.c new file mode 100644 index 000000000000..0dab09d4fd3c --- /dev/null +++ b/drivers/power/reset/ep93xx-restart.c @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * Cirrus EP93xx SoC reset driver + * + * Copyright (C) 2021 Nikita Shubin + */ + +#include +#include +#include +#include +#include + +#include + +#define EP93XX_SYSCON_DEVCFG_SWRST BIT(31) + +static int ep93xx_restart_handle(struct notifier_block *this, + unsigned long mode, void *cmd) +{ + /* Issue the reboot */ + ep93xx_devcfg_set_clear(EP93XX_SYSCON_DEVCFG_SWRST, 0x00); + ep93xx_devcfg_set_clear(0x00, EP93XX_SYSCON_DEVCFG_SWRST); + + mdelay(1000); + + pr_emerg("Unable to restart system\n"); + return NOTIFY_DONE; +} + +static int ep93xx_reboot_probe(struct platform_device *pdev) +{ + struct notifier_block *res_han; + struct device *dev =3D &pdev->dev; + int err; + + res_han =3D devm_kzalloc(&pdev->dev, sizeof(*res_han), GFP_KERNEL); + if (!res_han) + return -ENOMEM; + + res_han->notifier_call =3D ep93xx_restart_handle; + res_han->priority =3D 128; + + err =3D register_restart_handler(res_han); + if (err) + dev_err(dev, "can't register restart notifier (err=3D%d)\n", err); + + return err; +} + +static const struct of_device_id ep93xx_reboot_of_match[] =3D { + { + .compatible =3D "cirrus,ep9301-reboot", + }, + {} +}; + +static struct platform_driver ep93xx_reboot_driver =3D { + .probe =3D ep93xx_reboot_probe, + .driver =3D { + .name =3D "ep9301-reboot", + .of_match_table =3D ep93xx_reboot_of_match, + }, +}; +builtin_platform_driver(ep93xx_reboot_driver); --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C70FBC77B7A for ; Thu, 1 Jun 2023 05:38:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231550AbjFAFii (ORCPT ); Thu, 1 Jun 2023 01:38:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47266 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231379AbjFAFiO (ORCPT ); Thu, 1 Jun 2023 01:38:14 -0400 Received: from forward101c.mail.yandex.net (forward101c.mail.yandex.net [178.154.239.212]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C9F211A7; Wed, 31 May 2023 22:37:18 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net [IPv6:2a02:6b8:c14:c83:0:640:84f9:0]) by forward101c.mail.yandex.net (Yandex) with ESMTP id B0F66600D1; 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charset="utf-8" - Find register range from the device tree. Signed-off-by: Nikita Shubin --- drivers/watchdog/ep93xx_wdt.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/watchdog/ep93xx_wdt.c b/drivers/watchdog/ep93xx_wdt.c index 38e26f160b9a..088b88aad94f 100644 --- a/drivers/watchdog/ep93xx_wdt.c +++ b/drivers/watchdog/ep93xx_wdt.c @@ -21,6 +21,7 @@ * daemon dies. */ =20 +#include #include #include #include @@ -130,9 +131,16 @@ static int ep93xx_wdt_probe(struct platform_device *pd= ev) return 0; } =20 +static const struct of_device_id ep93xx_wdt_of_ids[] =3D { + { .compatible =3D "cirrus,ep9301-wdt" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ep93xx_wdt_of_ids); + static struct platform_driver ep93xx_wdt_driver =3D { .driver =3D { .name =3D "ep93xx-wdt", + .of_match_table =3D ep93xx_wdt_of_ids, }, .probe =3D ep93xx_wdt_probe, }; --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA8DCC77B7E for ; Thu, 1 Jun 2023 05:38:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231544AbjFAFig (ORCPT ); Thu, 1 Jun 2023 01:38:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231408AbjFAFiN (ORCPT ); Thu, 1 Jun 2023 01:38:13 -0400 Received: from forward103b.mail.yandex.net (forward103b.mail.yandex.net [178.154.239.150]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A72A19D; Wed, 31 May 2023 22:37:17 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net [IPv6:2a02:6b8:c14:c83:0:640:84f9:0]) by forward103b.mail.yandex.net (Yandex) with ESMTP id 7B13660064; Thu, 1 Jun 2023 08:37:13 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id OaGNfZvWv8c0-bTdTQYrz; Thu, 01 Jun 2023 08:37:13 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1685597833; bh=RJv1enniNURToHuLUERjxyUqTf6LjwxVg1LD+JWPLmA=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=MVDnefRDt1lyXlfumLMMFOHp2cWmDIMGCBXR3hDxQlR6guXnuyb7pMZ6HqAVlsH8F AWZDG6eYzf0T1M2YTVtYoyXGYFPpWbKttRKXkr9pQwhtJT2nzlHHu1ZoqyaOi7tdPn bI6w0fP3B45FnW6riDtFHfA/qreqG3ZCfplp/xWc= Authentication-Results: mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij , Sebastian Reichel Cc: Nikita Shubin , Michael Peters , Kris Bahnsen , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v1 14/43] power: reset: Add a driver for the ep93xx reset Date: Thu, 1 Jun 2023 08:34:05 +0300 Message-Id: <20230601053546.9574-15-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Implement the reset behaviour of the various EP93xx SoCS in drivers/power/r= eset. It used to be located in arch/arm/mach-ep93xx. Signed-off-by: Nikita Shubin Acked-by: Sebastian Reichel --- drivers/power/reset/Kconfig | 10 +++++ drivers/power/reset/Makefile | 1 + drivers/power/reset/ep93xx-restart.c | 65 ++++++++++++++++++++++++++++ 3 files changed, 76 insertions(+) create mode 100644 drivers/power/reset/ep93xx-restart.c diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig index 8c87eeda0fec..2a61afbb047b 100644 --- a/drivers/power/reset/Kconfig +++ b/drivers/power/reset/Kconfig @@ -75,6 +75,16 @@ config POWER_RESET_BRCMSTB Say Y here if you have a Broadcom STB board and you wish to have restart support. =20 +config POWER_RESET_EP93XX + bool "Cirrus EP93XX reset driver" if COMPILE_TEST + depends on MFD_SYSCON + default ARCH_EP93XX + help + This driver provides restart support for Cirrus EP93XX SoC. + + Say Y here if you have a Cirrus EP93XX SoC and you wish + to have restart support. + config POWER_RESET_GEMINI_POWEROFF bool "Cortina Gemini power-off driver" depends on ARCH_GEMINI || COMPILE_TEST diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile index d763e6735ee3..61f4e11619b2 100644 --- a/drivers/power/reset/Makefile +++ b/drivers/power/reset/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_POWER_RESET_ATC260X) +=3D atc260x-poweroff.o obj-$(CONFIG_POWER_RESET_AXXIA) +=3D axxia-reset.o obj-$(CONFIG_POWER_RESET_BRCMKONA) +=3D brcm-kona-reset.o obj-$(CONFIG_POWER_RESET_BRCMSTB) +=3D brcmstb-reboot.o +obj-$(CONFIG_POWER_RESET_EP93XX) +=3D ep93xx-restart.o obj-$(CONFIG_POWER_RESET_GEMINI_POWEROFF) +=3D gemini-poweroff.o obj-$(CONFIG_POWER_RESET_GPIO) +=3D gpio-poweroff.o obj-$(CONFIG_POWER_RESET_GPIO_RESTART) +=3D gpio-restart.o diff --git a/drivers/power/reset/ep93xx-restart.c b/drivers/power/reset/ep9= 3xx-restart.c new file mode 100644 index 000000000000..0dab09d4fd3c --- /dev/null +++ b/drivers/power/reset/ep93xx-restart.c @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * Cirrus EP93xx SoC reset driver + * + * Copyright (C) 2021 Nikita Shubin + */ + +#include +#include +#include +#include +#include + +#include + +#define EP93XX_SYSCON_DEVCFG_SWRST BIT(31) + +static int ep93xx_restart_handle(struct notifier_block *this, + unsigned long mode, void *cmd) +{ + /* Issue the reboot */ + ep93xx_devcfg_set_clear(EP93XX_SYSCON_DEVCFG_SWRST, 0x00); + ep93xx_devcfg_set_clear(0x00, EP93XX_SYSCON_DEVCFG_SWRST); + + mdelay(1000); + + pr_emerg("Unable to restart system\n"); + return NOTIFY_DONE; +} + +static int ep93xx_reboot_probe(struct platform_device *pdev) +{ + struct notifier_block *res_han; + struct device *dev =3D &pdev->dev; + int err; + + res_han =3D devm_kzalloc(&pdev->dev, sizeof(*res_han), GFP_KERNEL); + if (!res_han) + return -ENOMEM; + + res_han->notifier_call =3D ep93xx_restart_handle; + res_han->priority =3D 128; + + err =3D register_restart_handler(res_han); + if (err) + dev_err(dev, "can't register restart notifier (err=3D%d)\n", err); + + return err; +} + +static const struct of_device_id ep93xx_reboot_of_match[] =3D { + { + .compatible =3D "cirrus,ep9301-reboot", + }, + {} +}; + +static struct platform_driver ep93xx_reboot_driver =3D { + .probe =3D ep93xx_reboot_probe, + .driver =3D { + .name =3D "ep9301-reboot", + .of_match_table =3D ep93xx_reboot_of_match, + }, +}; +builtin_platform_driver(ep93xx_reboot_driver); --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D77EC77B76 for ; Mon, 24 Apr 2023 10:21:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231474AbjDXKV1 (ORCPT ); Mon, 24 Apr 2023 06:21:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44286 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231660AbjDXKUp (ORCPT ); Mon, 24 Apr 2023 06:20:45 -0400 Received: from forward501c.mail.yandex.net (forward501c.mail.yandex.net [178.154.239.209]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4D7EB7; Mon, 24 Apr 2023 03:20:44 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net [IPv6:2a02:6b8:c12:261e:0:640:2e3d:0]) by forward501c.mail.yandex.net (Yandex) with ESMTP id D30BD5EEAB; Mon, 24 Apr 2023 12:35:48 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id JZBb1pbWwKo0-PtXC2aiQ; Mon, 24 Apr 2023 12:35:48 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1682328948; bh=55tZgmJXA8qbnRPP2qpobAYIKju7ySH3raZBDLq41Vw=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=JKotEwuQesXgy6k7oJ/OF1r0lrxaWeEWpyRRRPhv7r1r5udgnHnY7a1EN6op9r8ch 7y/BMGZuhb/mWsTdGU6W/jNRVBUcRzJLRC2wQ9+cdwGOlQ8UBgNBtWK0zo1OlXc7fw T7fvloDW0v7zzerjKB2uywWJYgEJit5A87Yv7kMg= Authentication-Results: mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 14/43] dt-bindings: pwm: Add DT bindings ep93xx PWM Date: Mon, 24 Apr 2023 15:34:30 +0300 Message-Id: <20230424123522.18302-15-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add YAML bindings for ep93xx SoC. Signed-off-by: Nikita Shubin --- .../bindings/pwm/cirrus,ep93xx-pwm.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/cirrus,ep93xx-pwm= .yaml diff --git a/Documentation/devicetree/bindings/pwm/cirrus,ep93xx-pwm.yaml b= /Documentation/devicetree/bindings/pwm/cirrus,ep93xx-pwm.yaml new file mode 100644 index 000000000000..8f67eb152f8b --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/cirrus,ep93xx-pwm.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/cirrus,ep93xx-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logick ep93xx PWM controller + +maintainers: + - Thierry Reding + +properties: + compatible: + enum: + - cirrus,ep9301-pwm + reg: + maxItems: 1 + + clocks: + items: + - description: SoC PWM clock + + clock-names: + items: + - const: pwm_clk + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + pwm0: pwm@80910000 { + compatible =3D "cirrus,ep9301-pwm"; + reg =3D <0x80910000 0x10>; + clocks =3D <&syscon EP93XX_CLK_PWM>; + clock-names =3D "pwm_clk"; + }; + +... --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 721A5C77B7A for ; Thu, 1 Jun 2023 05:39:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231416AbjFAFjL (ORCPT ); Thu, 1 Jun 2023 01:39:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231523AbjFAFib (ORCPT ); Thu, 1 Jun 2023 01:38:31 -0400 Received: from forward102c.mail.yandex.net (forward102c.mail.yandex.net [IPv6:2a02:6b8:c03:500:1:45:d181:d102]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF9E7E5C; Wed, 31 May 2023 22:37:48 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net [IPv6:2a02:6b8:c14:c83:0:640:84f9:0]) by forward102c.mail.yandex.net (Yandex) with ESMTP id 1A34260029; Thu, 1 Jun 2023 08:37:15 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id OaGNfZvWv8c0-f03XGDan; Thu, 01 Jun 2023 08:37:14 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1685597834; bh=9x0sbFQMwOV8xWUuOaTI2MOW2vx9aWzbCEMNaf6KDSI=; h=Cc:Message-Id:References:Date:In-Reply-To:Subject:To:From; b=qcg1M1DR3YgW20BtroUceN5m2HYVKM2WoDzai59NDIX00oMkdWmHGHhMh2FcuRzFS e/Z87wDY/E6cYrIOVbIVqf7YTY4ulo7sfuasa/iriFa9CnnZW4mUeaHENccpEKuumX ybGNYw87bzKLrADOAZ+ZLkNobXf6/LqQy9UeueeA= Authentication-Results: mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij , Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Nikita Shubin Cc: Michael Peters , Kris Bahnsen , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 15/43] dt-bindings: pwm: Add Cirrus EP93xx Date: Thu, 1 Jun 2023 08:34:06 +0300 Message-Id: <20230601053546.9574-16-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add YAML bindings for ep93xx SoC PWM. Signed-off-by: Nikita Shubin Acked-by: Uwe Kleine-K=C3=B6nig --- Notes: v0 -> v1: Krzysztof Kozlowski: - replaced maintainers with Alexander and me - removed wildcards - use fallback compatible and list all possible compatibles - dropped label - dopped "clock-names" - fix ident .../bindings/pwm/cirrus,ep9301-pwm.yaml | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/cirrus,ep9301-pwm= .yaml diff --git a/Documentation/devicetree/bindings/pwm/cirrus,ep9301-pwm.yaml b= /Documentation/devicetree/bindings/pwm/cirrus,ep9301-pwm.yaml new file mode 100644 index 000000000000..825c321073ff --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/cirrus,ep9301-pwm.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/cirrus,ep9301-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logick ep93xx PWM controller + +maintainers: + - Alexander Sverdlin + - Nikita Shubin + +properties: + compatible: + oneOf: + - const: cirrus,ep9301-pwm + - items: + - enum: + - cirrus,ep9302-pwm + - cirrus,ep9307-pwm + - cirrus,ep9312-pwm + - cirrus,ep9315-pwm + - const: cirrus,ep9301-pwm + + reg: + maxItems: 1 + + clocks: + items: + - description: SoC PWM clock + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + #include + pwm@80910000 { + compatible =3D "cirrus,ep9301-pwm"; + reg =3D <0x80910000 0x10>; + clocks =3D <&syscon EP93XX_CLK_PWM>; + }; + +... --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94EE8C77B61 for ; Mon, 24 Apr 2023 10:35:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231572AbjDXKfR (ORCPT ); Mon, 24 Apr 2023 06:35:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231137AbjDXKeq (ORCPT ); Mon, 24 Apr 2023 06:34:46 -0400 Received: from forward502c.mail.yandex.net (forward502c.mail.yandex.net [178.154.239.210]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E444030ED; Mon, 24 Apr 2023 03:34:22 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net [IPv6:2a02:6b8:c12:261e:0:640:2e3d:0]) by forward502c.mail.yandex.net (Yandex) with ESMTP id 5EAB55EC51; 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(no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" - find register range from the device tree - provide clock access via of Signed-off-by: Nikita Shubin --- Notes: Arnd Bergmann: - wildcards ep93xx to something meaningful, i.e. ep9301 - drop wrappers drivers/pwm/pwm-ep93xx.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pwm/pwm-ep93xx.c b/drivers/pwm/pwm-ep93xx.c index c45a75e65c86..8bfe6cfbb3db 100644 --- a/drivers/pwm/pwm-ep93xx.c +++ b/drivers/pwm/pwm-ep93xx.c @@ -17,6 +17,7 @@ */ =20 #include +#include #include #include #include @@ -190,9 +191,16 @@ static int ep93xx_pwm_probe(struct platform_device *pd= ev) return 0; } =20 +static const struct of_device_id ep93xx_pwm_of_ids[] =3D { + { .compatible =3D "cirrus,ep9301-pwm" }, + {}, +}; +MODULE_DEVICE_TABLE(of, ep93xx_pwm_of_ids); + static struct platform_driver ep93xx_pwm_driver =3D { .driver =3D { .name =3D "ep93xx-pwm", + .of_match_table =3D ep93xx_pwm_of_ids, }, .probe =3D ep93xx_pwm_probe, }; --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44E05C77B7A for ; Thu, 1 Jun 2023 05:38:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231336AbjFAFim (ORCPT ); Thu, 1 Jun 2023 01:38:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47614 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231415AbjFAFiO (ORCPT ); Thu, 1 Jun 2023 01:38:14 -0400 Received: from forward101c.mail.yandex.net (forward101c.mail.yandex.net [178.154.239.212]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7E98D1A8; Wed, 31 May 2023 22:37:19 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net [IPv6:2a02:6b8:c14:c83:0:640:84f9:0]) by forward101c.mail.yandex.net (Yandex) with ESMTP id F0B7C60054; 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charset="utf-8" - find register range from the device tree - provide clock access via of Signed-off-by: Nikita Shubin Acked-by: Uwe Kleine-K=C3=B6nig Reviewed-by: Andy Shevchenko --- Notes: v0 -> v1: =20 - fixed headers - fixed id table drivers/pwm/pwm-ep93xx.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pwm/pwm-ep93xx.c b/drivers/pwm/pwm-ep93xx.c index c45a75e65c86..361984ef4c0b 100644 --- a/drivers/pwm/pwm-ep93xx.c +++ b/drivers/pwm/pwm-ep93xx.c @@ -17,6 +17,7 @@ */ =20 #include +#include #include #include #include @@ -190,9 +191,16 @@ static int ep93xx_pwm_probe(struct platform_device *pd= ev) return 0; } =20 +static const struct of_device_id ep93xx_pwm_of_ids[] =3D { + { .compatible =3D "cirrus,ep9301-pwm" }, + { /* sentinel */} +}; +MODULE_DEVICE_TABLE(of, ep93xx_pwm_of_ids); + static struct platform_driver ep93xx_pwm_driver =3D { .driver =3D { .name =3D "ep93xx-pwm", + .of_match_table =3D ep93xx_pwm_of_ids, }, .probe =3D ep93xx_pwm_probe, }; --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7696EC7EE20 for ; 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a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1682328949; bh=vU9bRggzAhYOEIOo6hHktg3BN7ZN9WtqIzyEyFF0Ons=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=ZqzxMTukQJ9ZInTO2NfwuEnV628LAWgWX5APJIe8emmO12TIBiSRn5d+fLGZ+nRek m9W59ISxM6G4zSkaAcHhI5fmqZnk5iO/EGrQm2iYJOIybQUCdPkaG0xRQqsDpFtXCl 3BRfon+kQs4Vm8brpmEk7h97HFPBx6I7sWhyU+is= Authentication-Results: mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , Mark Brown , Rob Herring , Krzysztof Kozlowski , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 16/43] dt-bindings: spi: Add DT bindings ep93xx spi Date: Mon, 24 Apr 2023 15:34:32 +0300 Message-Id: <20230424123522.18302-17-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add YAML bindings for ep93xx SoC. Signed-off-by: Nikita Shubin --- .../devicetree/bindings/spi/spi-ep93xx.yaml | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-ep93xx.yaml diff --git a/Documentation/devicetree/bindings/spi/spi-ep93xx.yaml b/Docume= ntation/devicetree/bindings/spi/spi-ep93xx.yaml new file mode 100644 index 000000000000..e09ab50629fb --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-ep93xx.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/spi-ep93xx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EP93xx SoC SPI controller + +maintainers: + - Mark Brown + +allOf: + - $ref: "spi-controller.yaml#" + +properties: + "#address-cells": true + "#size-cells": true + + compatible: + items: + - const: cirrus,ep9301-spi + + reg: + items: + - description: SPI registers region + + interrupts: + maxItems: 1 + + clocks: + items: + - description: SPI Controller reference clock source + + clock-names: + items: + - const: ep93xx-spi.0 + + cs-gpios: true + + use_dma: + type: boolean + items: + - description: Flag indicating that the SPI should use dma + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + spi0: spi@808a0000 { + compatible =3D "cirrus,ep9301-spi"; + reg =3D <0x808a0000 0x18>; + interrupt-parent =3D <&vic1>; + interrupts =3D <21>; + clocks =3D <&syscon EP93XX_CLK_SPI>; + clock-names =3D "ep93xx-spi.0"; + cs-gpios =3D <&gpio5 2 0>; + use_dma; + }; + +... --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F370BC77B61 for ; Mon, 24 Apr 2023 10:21:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231757AbjDXKVa (ORCPT ); Mon, 24 Apr 2023 06:21:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44428 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231674AbjDXKUr (ORCPT ); Mon, 24 Apr 2023 06:20:47 -0400 X-Greylist: delayed 1524 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Mon, 24 Apr 2023 03:20:45 PDT Received: from forward501c.mail.yandex.net (forward501c.mail.yandex.net [IPv6:2a02:6b8:c03:500:1:45:d181:d501]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BB5531BE6; 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(no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" - find register range from the device tree - provide clock access via of - use_dma as a DT node Signed-off-by: Nikita Shubin Acked-by: Alexander Sverdlin Reviewed-by: Linus Walleij Tested-by: Alexander Sverdlin --- Notes: Arnd Bergmann: - wildcards ep93xx to something meaningful, i.e. ep9301 - drop wrappers drivers/spi/spi-ep93xx.c | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-ep93xx.c b/drivers/spi/spi-ep93xx.c index 5896a7b2fade..b37be7109161 100644 --- a/drivers/spi/spi-ep93xx.c +++ b/drivers/spi/spi-ep93xx.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -644,6 +645,25 @@ static void ep93xx_spi_release_dma(struct ep93xx_spi *= espi) free_page((unsigned long)espi->zeropage); } =20 +#ifdef CONFIG_OF +static struct ep93xx_spi_info dt_spi_info; + +static struct ep93xx_spi_info *ep93xx_spi_get_platdata(struct platform_dev= ice *pdev) +{ + struct device_node *np =3D pdev->dev.of_node; + + if (np && of_property_read_bool(np, "use_dma")) + dt_spi_info.use_dma =3D 1; + + return &dt_spi_info; +} +#else +static struct ep93xx_spi_info *ep93xx_spi_get_platdata(struct platform_dev= ice *pdev) +{ + return dev_get_platdata(&pdev->dev); +} +#endif + static int ep93xx_spi_probe(struct platform_device *pdev) { struct spi_master *master; @@ -653,7 +673,7 @@ static int ep93xx_spi_probe(struct platform_device *pde= v) int irq; int error; =20 - info =3D dev_get_platdata(&pdev->dev); + info =3D ep93xx_spi_get_platdata(pdev); if (!info) { dev_err(&pdev->dev, "missing platform data\n"); return -EINVAL; @@ -726,6 +746,8 @@ static int ep93xx_spi_probe(struct platform_device *pde= v) /* make sure that the hardware is disabled */ writel(0, espi->mmio + SSPCR1); =20 + master->dev.of_node =3D pdev->dev.of_node; + error =3D devm_spi_register_master(&pdev->dev, master); if (error) { dev_err(&pdev->dev, "failed to register SPI master\n"); @@ -755,9 +777,16 @@ static int ep93xx_spi_remove(struct platform_device *p= dev) return 0; } =20 +static const struct of_device_id ep93xx_spi_of_ids[] =3D { + { .compatible =3D "cirrus,ep9301-spi" }, + {}, +}; +MODULE_DEVICE_TABLE(of, ep93xx_spi_of_ids); + static struct platform_driver ep93xx_spi_driver =3D { .driver =3D { .name =3D "ep93xx-spi", + .of_match_table =3D ep93xx_spi_of_ids, }, .probe =3D ep93xx_spi_probe, .remove =3D ep93xx_spi_remove, --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25486C77B7E for ; Thu, 1 Jun 2023 05:39:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231420AbjFAFjz (ORCPT ); Thu, 1 Jun 2023 01:39:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47626 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231493AbjFAFj0 (ORCPT ); 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dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij , Mark Brown , Rob Herring , Krzysztof Kozlowski , Nikita Shubin Cc: Michael Peters , Kris Bahnsen , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 17/43] dt-bindings: spi: Add Cirrus EP93xx Date: Thu, 1 Jun 2023 08:34:08 +0300 Message-Id: <20230601053546.9574-18-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add YAML bindings for ep93xx SoC SPI. Signed-off-by: Nikita Shubin --- Notes: v0 -> v1: Krzysztof Kozlowski: - replaced maintainers - removed wildcards - use fallback compatible and list all possible compatibles - drop quotes in ref - dropped "clock-names" - dropped label - fix ident .../devicetree/bindings/spi/spi-ep9301.yaml | 69 +++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-ep9301.yaml diff --git a/Documentation/devicetree/bindings/spi/spi-ep9301.yaml b/Docume= ntation/devicetree/bindings/spi/spi-ep9301.yaml new file mode 100644 index 000000000000..c363b25a3074 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-ep9301.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/spi-ep9301.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EP93xx SoC SPI controller + +maintainers: + - Alexander Sverdlin + - Nikita Shubin + +allOf: + - $ref: spi-controller.yaml# + +properties: + "#address-cells": true + "#size-cells": true + + compatible: + oneOf: + - const: cirrus,ep9301-spi + - items: + - enum: + - cirrus,ep9302-spi + - cirrus,ep9307-spi + - cirrus,ep9312-spi + - cirrus,ep9315-spi + - const: cirrus,ep9301-spi + + reg: + items: + - description: SPI registers region + + interrupts: + maxItems: 1 + + clocks: + items: + - description: SPI Controller reference clock source + + cs-gpios: true + + cirrus,ep9301-use-dma: + description: Flag indicating that the SPI should use dma + type: boolean + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + spi@808a0000 { + compatible =3D "cirrus,ep9301-spi"; + reg =3D <0x808a0000 0x18>; + interrupt-parent =3D <&vic1>; + interrupts =3D <21>; + clocks =3D <&syscon EP93XX_CLK_SPI>; + cs-gpios =3D <&gpio5 2 0>; + cirrus,ep9301-use-dma; + }; + +... --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5FC22C7618E for ; Mon, 24 Apr 2023 10:20:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231686AbjDXKUw (ORCPT ); Mon, 24 Apr 2023 06:20:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44266 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231278AbjDXKUk (ORCPT ); Mon, 24 Apr 2023 06:20:40 -0400 X-Greylist: delayed 1516 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Mon, 24 Apr 2023 03:20:37 PDT Received: from forward501c.mail.yandex.net (forward501c.mail.yandex.net [IPv6:2a02:6b8:c03:500:1:45:d181:d501]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4722010DF; Mon, 24 Apr 2023 03:20:37 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net [IPv6:2a02:6b8:c12:261e:0:640:2e3d:0]) by forward501c.mail.yandex.net (Yandex) with ESMTP id 7DE0C5EE97; Mon, 24 Apr 2023 12:35:51 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id JZBb1pbWwKo0-71ti2XdL; Mon, 24 Apr 2023 12:35:51 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1682328951; bh=9OWyaTijH8WZgd/u9wb0Try8woOOARXYqCsnpX6d1qM=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=nBWGWBMiM9Od+YnfT7BAtTGa5YQ2BdqzrkqVqtMVbSvilPeSrljQzo0e40adGGbAt VZ/hKmw+vqOkRC0+6yP4k5wVL5MvARibL+ByuJg+cR3DG3Pb6B7vT7wlu5OtzXYVJZ ZKVDu9N7Z/18CSukw+SRwoBx1iquZpX99c0PACbk= Authentication-Results: mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Hartley Sweeten , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 18/43] dt-bindings: net: Add DT bindings ep93xx eth Date: Mon, 24 Apr 2023 15:34:34 +0300 Message-Id: <20230424123522.18302-19-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add YAML bindings for ep93xx SoC. Signed-off-by: Nikita Shubin --- .../bindings/net/cirrus,ep93xx_eth.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/cirrus,ep93xx_eth= .yaml diff --git a/Documentation/devicetree/bindings/net/cirrus,ep93xx_eth.yaml b= /Documentation/devicetree/bindings/net/cirrus,ep93xx_eth.yaml new file mode 100644 index 000000000000..7e73cf0ddde9 --- /dev/null +++ b/Documentation/devicetree/bindings/net/cirrus,ep93xx_eth.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/cirrus,ep93xx_eth.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: The ethernet hardware included in EP93xx CPUs module Device Tree Bi= ndings + +maintainers: + - Hartley Sweeten + +properties: + compatible: + const: cirrus,ep9301-eth + + reg: + items: + - description: The physical base address and size of IO range + + interrupts: + items: + - description: Combined signal for various interrupt events + + copy_addr: + type: boolean + description: + Flag indicating that the MAC address should be copied + from the IndAd registers (as programmed by the bootloader) + + phy_id: + description: MII phy_id to use + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + eth0: eth@80010000 { + compatible =3D "cirrus,ep9301-eth"; + reg =3D <0x80010000 0x10000>; + interrupt-parent =3D <&vic1>; + interrupts =3D <7>; + copy_addr; + phy_id =3D < 1 >; + }; + +... --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5317DC77B7E for ; Thu, 1 Jun 2023 05:38:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231447AbjFAFir (ORCPT ); Thu, 1 Jun 2023 01:38:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47624 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231424AbjFAFiP (ORCPT ); Thu, 1 Jun 2023 01:38:15 -0400 Received: from forward101b.mail.yandex.net (forward101b.mail.yandex.net [178.154.239.148]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B1C611B7; Wed, 31 May 2023 22:37:22 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-45.sas.yp-c.yandex.net [IPv6:2a02:6b8:c14:c83:0:640:84f9:0]) by forward101b.mail.yandex.net (Yandex) with ESMTP id 45ECA6003A; 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charset="utf-8" - find register range from the device tree - provide clock access via of - use_dma as a DT node Reviewed-by: Linus Walleij Signed-off-by: Nikita Shubin --- Notes: v0 -> v1: - dropped coma in ep93xx_spi_of_ids - renamed use_dma to "ep9301,use-dma" drivers/spi/spi-ep93xx.c | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-ep93xx.c b/drivers/spi/spi-ep93xx.c index 1615fd22f9a2..bd8049fe9c91 100644 --- a/drivers/spi/spi-ep93xx.c +++ b/drivers/spi/spi-ep93xx.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -644,6 +645,25 @@ static void ep93xx_spi_release_dma(struct ep93xx_spi *= espi) free_page((unsigned long)espi->zeropage); } =20 +#ifdef CONFIG_OF +static struct ep93xx_spi_info dt_spi_info; + +static struct ep93xx_spi_info *ep93xx_spi_get_platdata(struct platform_dev= ice *pdev) +{ + struct device_node *np =3D pdev->dev.of_node; + + if (np && of_property_read_bool(np, "ep9301,use-dma")) + dt_spi_info.use_dma =3D 1; + + return &dt_spi_info; +} +#else +static struct ep93xx_spi_info *ep93xx_spi_get_platdata(struct platform_dev= ice *pdev) +{ + return dev_get_platdata(&pdev->dev); +} +#endif + static int ep93xx_spi_probe(struct platform_device *pdev) { struct spi_master *master; @@ -653,7 +673,7 @@ static int ep93xx_spi_probe(struct platform_device *pde= v) int irq; int error; =20 - info =3D dev_get_platdata(&pdev->dev); + info =3D ep93xx_spi_get_platdata(pdev); if (!info) { dev_err(&pdev->dev, "missing platform data\n"); return -EINVAL; @@ -726,6 +746,8 @@ static int ep93xx_spi_probe(struct platform_device *pde= v) /* make sure that the hardware is disabled */ writel(0, espi->mmio + SSPCR1); =20 + master->dev.of_node =3D pdev->dev.of_node; + error =3D devm_spi_register_master(&pdev->dev, master); if (error) { dev_err(&pdev->dev, "failed to register SPI master\n"); @@ -753,9 +775,16 @@ static void ep93xx_spi_remove(struct platform_device *= pdev) ep93xx_spi_release_dma(espi); } =20 +static const struct of_device_id ep93xx_spi_of_ids[] =3D { + { .compatible =3D "cirrus,ep9301-spi" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ep93xx_spi_of_ids); + static struct platform_driver ep93xx_spi_driver =3D { .driver =3D { .name =3D "ep93xx-spi", + .of_match_table =3D ep93xx_spi_of_ids, }, .probe =3D ep93xx_spi_probe, .remove_new =3D ep93xx_spi_remove, --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5636C77B7A for ; Thu, 1 Jun 2023 05:46:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230472AbjFAFqA (ORCPT ); Thu, 1 Jun 2023 01:46:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230174AbjFAFp5 (ORCPT ); Thu, 1 Jun 2023 01:45:57 -0400 Received: from forward100a.mail.yandex.net (forward100a.mail.yandex.net [178.154.239.83]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 611759D; Wed, 31 May 2023 22:45:55 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net [IPv6:2a02:6b8:c1f:5e51:0:640:23ee:0]) by forward100a.mail.yandex.net (Yandex) with ESMTP id 528BA46CDA; Thu, 1 Jun 2023 08:45:53 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id pjGDMhnDduQ0-2mCnHApf; Thu, 01 Jun 2023 08:45:52 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1685598352; bh=0YJKTt4qnbyh+8Nwc8VCqPNAqMn97qfUdg5Z1sSgti8=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=E/qpELlmZlEJXkhHcS4wFmaVrPRw4CGI99dPGlmt8XyMZssVUPpqhtQs6llLjbzQu yodjbyrfBOMHRYJZ6amkIjNLiD9D9iLvk0OgcBtyLJiFfqf4Wid1bB5W4vhR9SvrJb mMsH4z75Gl2QMNUij4Wn9I38hWGLCyJNfAFfcIWU= Authentication-Results: mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Nikita Shubin Cc: Michael Peters , Kris Bahnsen , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 19/43] dt-bindings: net: Add Cirrus EP93xx Date: Thu, 1 Jun 2023 08:45:24 +0300 Message-Id: <20230601054549.10843-1-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add YAML bindings for ep93xx SoC Ethernet Controller. Signed-off-by: Nikita Shubin --- Notes: v0 -> v1: - replaced maintainers - fixed title =20 Rob Herring: - reference ethernet-controller.yaml - s/eth/ethernet/ =20 Andrew Lunn: - dropped copy_addr - use phy-handle instead of using non-conventional phy-id =20 Krzysztof Kozlowski: - removed wildcards - use fallback compatible and list all possible compatibles - dropped label - fix ident .../bindings/net/cirrus,ep9301-eth.yaml | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/cirrus,ep9301-eth= .yaml diff --git a/Documentation/devicetree/bindings/net/cirrus,ep9301-eth.yaml b= /Documentation/devicetree/bindings/net/cirrus,ep9301-eth.yaml new file mode 100644 index 000000000000..580316f33187 --- /dev/null +++ b/Documentation/devicetree/bindings/net/cirrus,ep9301-eth.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/cirrus,ep9301-eth.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EP93xx SoC Ethernet Controller + +maintainers: + - Alexander Sverdlin + - Nikita Shubin + +allOf: + - $ref: ethernet-controller.yaml# + +properties: + compatible: + oneOf: + - const: cirrus,ep9301-eth + - items: + - enum: + - cirrus,ep9302-eth + - cirrus,ep9307-eth + - cirrus,ep9312-eth + - cirrus,ep9315-eth + - const: cirrus,ep9301-eth + + reg: + items: + - description: The physical base address and size of IO range + + interrupts: + items: + - description: Combined signal for various interrupt events + + phy-handle: true + + mdio: + $ref: mdio.yaml# + unevaluatedProperties: false + description: optional node for embedded MDIO controller + +required: + - compatible + - reg + - interrupts + - phy-handle + +additionalProperties: false + +examples: + - | + ethernet@80010000 { + compatible =3D "cirrus,ep9301-eth"; + reg =3D <0x80010000 0x10000>; + interrupt-parent =3D <&vic1>; + interrupts =3D <7>; + phy-handle =3D <&phy0>; + }; + +... --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7174DC7618E for ; Mon, 24 Apr 2023 10:35:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231361AbjDXKfK (ORCPT ); Mon, 24 Apr 2023 06:35:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57590 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231223AbjDXKeq (ORCPT ); Mon, 24 Apr 2023 06:34:46 -0400 Received: from forward502c.mail.yandex.net (forward502c.mail.yandex.net [178.154.239.210]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E42C8E68; Mon, 24 Apr 2023 03:34:22 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net [IPv6:2a02:6b8:c12:261e:0:640:2e3d:0]) by forward502c.mail.yandex.net (Yandex) with ESMTP id 2A07A5ECF3; Mon, 24 Apr 2023 12:35:52 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id JZBb1pbWwKo0-bZjfcDZh; Mon, 24 Apr 2023 12:35:51 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1682328951; bh=H/MzURm8LBkdmNsr58WR1SK4CDr2JEUu6baOETb8+Wg=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=tYpH8otaP3x9f/8bRSAqZu82nnrxTEkZHlayhCB9QMaQcNZBH0DY//Dg5uGzu+1ns KYepJxdWKlIOUaF3KNmwGNqIfoWpcK2LJ+vK6ddbxRuwOghoWcuZzEEEjYOl3EjVFS 1YyW/N6nmcrttqIhmnf0ys65Wv67QgrP9FIDzwT4= Authentication-Results: mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , Hartley Sweeten , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 19/43] net: cirrus: add DT support for Cirrus EP93xx Date: Mon, 24 Apr 2023 15:34:35 +0300 Message-Id: <20230424123522.18302-20-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" - find register range from the device tree - get "copy_addr" from the device tree - get phy_id from the device tree Signed-off-by: Nikita Shubin --- Notes: rfc->v0 Fixed warnings on "(base_addr =3D=3D NULL)", pace required before the o= pen parenthesis '('. =20 Arnd Bergmann: - wildcards ep93xx to something meaningful, i.e. ep9301 - drop wrappers drivers/net/ethernet/cirrus/ep93xx_eth.c | 49 +++++++++++++++++++++--- 1 file changed, 43 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/cirrus/ep93xx_eth.c b/drivers/net/etherne= t/cirrus/ep93xx_eth.c index 8627ab19d470..b156cc75daad 100644 --- a/drivers/net/ethernet/cirrus/ep93xx_eth.c +++ b/drivers/net/ethernet/cirrus/ep93xx_eth.c @@ -17,6 +17,8 @@ #include #include #include +#include +#include #include #include #include @@ -792,6 +794,8 @@ static int ep93xx_eth_probe(struct platform_device *pde= v) struct net_device *dev; struct ep93xx_priv *ep; struct resource *mem; + void __iomem *base_addr; + struct device_node *np; int irq; int err; =20 @@ -804,6 +808,38 @@ static int ep93xx_eth_probe(struct platform_device *pd= ev) if (!mem || irq < 0) return -ENXIO; =20 + base_addr =3D ioremap(mem->start, resource_size(mem)); + if (!base_addr) { + dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n"); + return -EIO; + } + + if (!data) { + np =3D pdev->dev.of_node; + if (IS_ENABLED(CONFIG_OF) && np) { + u32 phy_id; + + data =3D devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + if (of_property_read_bool(np, "copy_addr")) { + memcpy_fromio(data->dev_addr, base_addr + 0x50, 6); + dev_info(&pdev->dev, "MAC=3D%pM\n", data->dev_addr); + } + + if (of_property_read_u32(np, "phy_id", &phy_id)) { + dev_err(&pdev->dev, "Failed to parse \"phy_id\"\n"); + return -ENOENT; + } + + data->phy_id =3D phy_id; + } + } + + if (!data) + return -ENOENT; + dev =3D ep93xx_dev_alloc(data); if (dev =3D=3D NULL) { err =3D -ENOMEM; @@ -824,12 +860,7 @@ static int ep93xx_eth_probe(struct platform_device *pd= ev) goto err_out; } =20 - ep->base_addr =3D ioremap(mem->start, resource_size(mem)); - if (ep->base_addr =3D=3D NULL) { - dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n"); - err =3D -EIO; - goto err_out; - } + ep->base_addr =3D base_addr; ep->irq =3D irq; =20 ep->mii.phy_id =3D data->phy_id; @@ -859,12 +890,18 @@ static int ep93xx_eth_probe(struct platform_device *p= dev) return err; } =20 +static const struct of_device_id ep93xx_eth_of_ids[] =3D { + { .compatible =3D "cirrus,ep9301-eth" }, + {}, +}; +MODULE_DEVICE_TABLE(of, ep93xx_eth_of_ids); =20 static struct platform_driver ep93xx_eth_driver =3D { .probe =3D ep93xx_eth_probe, .remove =3D ep93xx_eth_remove, .driver =3D { .name =3D "ep93xx-eth", + .of_match_table =3D ep93xx_eth_of_ids, }, }; =20 --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC0A5C77B7A for ; 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a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1685598354; bh=DFRrRs5yJB6I1NZ9/5/odctWMT+EMqwMMh4rTW/kIxM=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=q0FI6OYNleFFyvjkySIRTvmRWW9IGtRpLHzuEmzI9GViPQq+8NKNZ6J96pZ8RCtfm 3p2fbF3ouAKcm9U16K45Kuv5AMjYp5dNUUq4/Dyjn99yYcox4xq/fBaBjlNdpSJ+sH 9BLp1zEsFd729J3y5Iu7J2yIU+Qc8RmesCe01kyg= Authentication-Results: mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij , Hartley Sweeten , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni Cc: Nikita Shubin , Michael Peters , Kris Bahnsen , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: [PATCH v1 20/43] net: cirrus: add DT support for Cirrus EP93xx Date: Thu, 1 Jun 2023 08:45:25 +0300 Message-Id: <20230601054549.10843-2-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" - find register range from the device tree - get "copy_addr" from the device tree - get phy_id from the device tree Signed-off-by: Nikita Shubin Reviewed-by: Andrew Lunn Reviewed-by: Linus Walleij Tested-by: Alexander Sverdlin --- Notes: v0 -> v1: =20 - dropped platform data entirely - dropped copy_addr - use phy-handle instead of using non-conventional phy-id arch/arm/mach-ep93xx/platform.h | 2 +- drivers/net/ethernet/cirrus/ep93xx_eth.c | 67 +++++++++++++----------- 2 files changed, 37 insertions(+), 32 deletions(-) diff --git a/arch/arm/mach-ep93xx/platform.h b/arch/arm/mach-ep93xx/platfor= m.h index 5fb1b919133f..3cf2113491d8 100644 --- a/arch/arm/mach-ep93xx/platform.h +++ b/arch/arm/mach-ep93xx/platform.h @@ -5,8 +5,8 @@ =20 #ifndef __ASSEMBLY__ =20 -#include #include +#include =20 struct device; struct i2c_board_info; diff --git a/drivers/net/ethernet/cirrus/ep93xx_eth.c b/drivers/net/etherne= t/cirrus/ep93xx_eth.c index 8627ab19d470..41096d4830ff 100644 --- a/drivers/net/ethernet/cirrus/ep93xx_eth.c +++ b/drivers/net/ethernet/cirrus/ep93xx_eth.c @@ -17,12 +17,11 @@ #include #include #include +#include #include #include #include =20 -#include - #define DRV_MODULE_NAME "ep93xx-eth" =20 #define RX_QUEUE_ENTRIES 64 @@ -738,25 +737,6 @@ static const struct net_device_ops ep93xx_netdev_ops = =3D { .ndo_set_mac_address =3D eth_mac_addr, }; =20 -static struct net_device *ep93xx_dev_alloc(struct ep93xx_eth_data *data) -{ - struct net_device *dev; - - dev =3D alloc_etherdev(sizeof(struct ep93xx_priv)); - if (dev =3D=3D NULL) - return NULL; - - eth_hw_addr_set(dev, data->dev_addr); - - dev->ethtool_ops =3D &ep93xx_ethtool_ops; - dev->netdev_ops =3D &ep93xx_netdev_ops; - - dev->features |=3D NETIF_F_SG | NETIF_F_HW_CSUM; - - return dev; -} - - static int ep93xx_eth_remove(struct platform_device *pdev) { struct net_device *dev; @@ -788,27 +768,51 @@ static int ep93xx_eth_remove(struct platform_device *= pdev) =20 static int ep93xx_eth_probe(struct platform_device *pdev) { - struct ep93xx_eth_data *data; struct net_device *dev; struct ep93xx_priv *ep; struct resource *mem; + void __iomem *base_addr; + struct device_node *np; + u32 phy_id; int irq; int err; =20 if (pdev =3D=3D NULL) return -ENODEV; - data =3D dev_get_platdata(&pdev->dev); =20 mem =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); irq =3D platform_get_irq(pdev, 0); if (!mem || irq < 0) return -ENXIO; =20 - dev =3D ep93xx_dev_alloc(data); + base_addr =3D ioremap(mem->start, resource_size(mem)); + if (!base_addr) { + dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n"); + return -EIO; + } + + np =3D of_parse_phandle(pdev->dev.of_node, "phy-handle", 0); + if (!np) { + dev_err(&pdev->dev, "Please provide \"phy-handle\"\n"); + return -ENODEV; + } + + if (of_property_read_u32(np, "reg", &phy_id)) { + dev_err(&pdev->dev, "Failed to locate \"phy_id\"\n"); + return -ENOENT; + } + + dev =3D alloc_etherdev(sizeof(struct ep93xx_priv)); if (dev =3D=3D NULL) { err =3D -ENOMEM; goto err_out; } + + eth_hw_addr_set(dev, base_addr + 0x50); + dev->ethtool_ops =3D &ep93xx_ethtool_ops; + dev->netdev_ops =3D &ep93xx_netdev_ops; + dev->features |=3D NETIF_F_SG | NETIF_F_HW_CSUM; + ep =3D netdev_priv(dev); ep->dev =3D dev; SET_NETDEV_DEV(dev, &pdev->dev); @@ -824,15 +828,10 @@ static int ep93xx_eth_probe(struct platform_device *p= dev) goto err_out; } =20 - ep->base_addr =3D ioremap(mem->start, resource_size(mem)); - if (ep->base_addr =3D=3D NULL) { - dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n"); - err =3D -EIO; - goto err_out; - } + ep->base_addr =3D base_addr; ep->irq =3D irq; =20 - ep->mii.phy_id =3D data->phy_id; + ep->mii.phy_id =3D phy_id; ep->mii.phy_id_mask =3D 0x1f; ep->mii.reg_num_mask =3D 0x1f; ep->mii.dev =3D dev; @@ -859,12 +858,18 @@ static int ep93xx_eth_probe(struct platform_device *p= dev) return err; } =20 +static const struct of_device_id ep93xx_eth_of_ids[] =3D { + { .compatible =3D "cirrus,ep9301-eth" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ep93xx_eth_of_ids); =20 static struct platform_driver ep93xx_eth_driver =3D { .probe =3D ep93xx_eth_probe, .remove =3D ep93xx_eth_remove, .driver =3D { .name =3D "ep93xx-eth", + .of_match_table =3D ep93xx_eth_of_ids, }, }; =20 --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57A6CC77B7E for ; Mon, 24 Apr 2023 09:42:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230523AbjDXJmR (ORCPT ); Mon, 24 Apr 2023 05:42:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38820 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230235AbjDXJmP (ORCPT ); Mon, 24 Apr 2023 05:42:15 -0400 X-Greylist: delayed 394 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; 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dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , Vinod Koul , Rob Herring , Krzysztof Kozlowski , dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 20/43] dt-bindings: dma: Add DT bindings ep93xx dma Date: Mon, 24 Apr 2023 15:34:36 +0300 Message-Id: <20230424123522.18302-21-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add YAML bindings for ep93xx SoC. Signed-off-by: Nikita Shubin --- .../bindings/dma/cirrus,ep93xx-dma-m2m.yaml | 66 ++++++++++++ .../bindings/dma/cirrus,ep93xx-dma-m2p.yaml | 102 ++++++++++++++++++ 2 files changed, 168 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/cirrus,ep93xx-dma= -m2m.yaml create mode 100644 Documentation/devicetree/bindings/dma/cirrus,ep93xx-dma= -m2p.yaml diff --git a/Documentation/devicetree/bindings/dma/cirrus,ep93xx-dma-m2m.ya= ml b/Documentation/devicetree/bindings/dma/cirrus,ep93xx-dma-m2m.yaml new file mode 100644 index 000000000000..9a53ee9052a0 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/cirrus,ep93xx-dma-m2m.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/cirrus,ep93xx-dma-m2m.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logick ep93xx SoC DMA controller Device Tree Bindings + +maintainers: + - Vinod Koul + +properties: + compatible: + items: + - const: cirrus,ep9301-dma-m2m + + reg: + minItems: 2 + maxItems: 2 + + clocks: + items: + - description: m2m0 channel gate clock + - description: m2m1 channel gate clock + + clock-names: + items: + - const: m2m0 + - const: m2m1 + + interrupts: + minItems: 2 + maxItems: 2 + + dma-channels: + minimum: 2 + maximum: 2 + + '#dma-cells': false + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +additionalProperties: false + +examples: + - | + #include + dma1: dma-controller@80000100 { + compatible =3D "cirrus,ep9301-dma-m2m"; + reg =3D <0x80000100 0x0040>, + <0x80000140 0x0040>; + clocks =3D <&syscon EP93XX_CLK_M2M0>, + <&syscon EP93XX_CLK_M2M1>; + clock-names =3D "m2m0", "m2m1"; + dma-channels =3D <2>; + interrupt-parent =3D <&vic0>; + interrupts =3D <17>, <18>; + }; + +... + diff --git a/Documentation/devicetree/bindings/dma/cirrus,ep93xx-dma-m2p.ya= ml b/Documentation/devicetree/bindings/dma/cirrus,ep93xx-dma-m2p.yaml new file mode 100644 index 000000000000..51fd72b4e843 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/cirrus,ep93xx-dma-m2p.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/cirrus,ep93xx-dma-m2p.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logick ep93xx SoC M2P DMA controller Device Tree Bindings + +maintainers: + - Vinod Koul + +properties: + compatible: + items: + - const: cirrus,ep9301-dma-m2p + + reg: + minItems: 10 + maxItems: 10 + + clocks: + items: + - description: m2p0 channel gate clock + - description: m2p1 channel gate clock + - description: m2p2 channel gate clock + - description: m2p3 channel gate clock + - description: m2p4 channel gate clock + - description: m2p5 channel gate clock + - description: m2p6 channel gate clock + - description: m2p7 channel gate clock + - description: m2p8 channel gate clock + - description: m2p9 channel gate clock + + clock-names: + items: + - const: m2p0 + - const: m2p1 + - const: m2p2 + - const: m2p3 + - const: m2p4 + - const: m2p5 + - const: m2p6 + - const: m2p7 + - const: m2p8 + - const: m2p9 + + interrupts: + minItems: 10 + maxItems: 10 + + dma-channels: + minimum: 10 + maximum: 10 + + '#dma-cells': false + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +additionalProperties: false + +examples: + - | + #include + dma0: dma-controller@80000000 { + compatible =3D "cirrus,ep9301-dma-m2p"; + reg =3D <0x80000000 0x0040>, + <0x80000040 0x0040>, + <0x80000080 0x0040>, + <0x800000c0 0x0040>, + <0x80000240 0x0040>, + <0x80000200 0x0040>, + <0x800002c0 0x0040>, + <0x80000280 0x0040>, + <0x80000340 0x0040>, + <0x80000300 0x0040>; + clocks =3D <&syscon EP93XX_CLK_M2P0>, + <&syscon EP93XX_CLK_M2P1>, + <&syscon EP93XX_CLK_M2P2>, + <&syscon EP93XX_CLK_M2P3>, + <&syscon EP93XX_CLK_M2P4>, + <&syscon EP93XX_CLK_M2P5>, + <&syscon EP93XX_CLK_M2P6>, + <&syscon EP93XX_CLK_M2P7>, + <&syscon EP93XX_CLK_M2P8>, + <&syscon EP93XX_CLK_M2P9>; + clock-names =3D "m2p0", "m2p1", + "m2p2", "m2p3", + "m2p4", "m2p5", + "m2p6", "m2p7", + "m2p8", "m2p9"; + dma-channels =3D <10>; + interrupt-parent =3D <&vic0>; + interrupts =3D <7>, <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>, = <16>; + }; + +... + --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1925C77B7E for ; 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Thu, 01 Jun 2023 08:45:56 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1685598356; bh=1bDXVRXKM/tgJHSAAZWdj5rtWyNT0wihqHFmyX6zdO0=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=BS63bU9vkWL2D0xknjnAFd6ZNX+bpTaFbZFjz/OcVLvtithjXmQBlhHgZQt0MgOpx sH0+S6rHM7a0GjcVyVr0uD2X5V5VYiizh9U14mLfLWG6NufYfpgTZyJuAy0/PSrw7O L5IIrIG78FgxnxCZv6RwY+s2Ytt+AkPDwiQ3reQA= Authentication-Results: mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Nikita Shubin Cc: Michael Peters , Kris Bahnsen , dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 21/43] dt-bindings: dma: Add Cirrus EP93xx Date: Thu, 1 Jun 2023 08:45:26 +0300 Message-Id: <20230601054549.10843-3-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add YAML bindings for ep93xx SoC DMA. Signed-off-by: Nikita Shubin --- Notes: v0 -> v1: Rob Herring: - replaced maintainers - defined each entry in reg, interrupts - dropped dma-channels =20 Krzysztof Kozlowski: - fixed title - renamed files - use fallback compatible and list all possible compatibles - dropped label - fix ident .../bindings/dma/cirrus,ep9301-dma-m2m.yaml | 72 ++++++++++ .../bindings/dma/cirrus,ep9301-dma-m2p.yaml | 124 ++++++++++++++++++ 2 files changed, 196 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/cirrus,ep9301-dma= -m2m.yaml create mode 100644 Documentation/devicetree/bindings/dma/cirrus,ep9301-dma= -m2p.yaml diff --git a/Documentation/devicetree/bindings/dma/cirrus,ep9301-dma-m2m.ya= ml b/Documentation/devicetree/bindings/dma/cirrus,ep9301-dma-m2m.yaml new file mode 100644 index 000000000000..413492268bd7 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/cirrus,ep9301-dma-m2m.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/cirrus,ep9301-dma-m2m.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logick ep93xx SoC DMA controller + +maintainers: + - Alexander Sverdlin + - Nikita Shubin + +properties: + compatible: + oneOf: + - const: cirrus,ep9301-dma-m2m + - items: + - enum: + - cirrus,ep9302-dma-m2m + - cirrus,ep9307-dma-m2m + - cirrus,ep9312-dma-m2m + - cirrus,ep9315-dma-m2m + - const: cirrus,ep9301-dma-m2m + + reg: + items: + - description: m2m0 channel registers + - description: m2m1 channel registers + + clocks: + items: + - description: m2m0 channel gate clock + - description: m2m1 channel gate clock + + clock-names: + items: + - const: m2m0 + - const: m2m1 + + interrupts: + items: + - description: m2m0 channel interrupt + - description: m2m1 channel interrupt + + '#dma-cells': true + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +additionalProperties: false + +examples: + - | + #include + dma-controller@80000100 { + compatible =3D "cirrus,ep9301-dma-m2m"; + reg =3D <0x80000100 0x0040>, + <0x80000140 0x0040>; + clocks =3D <&syscon EP93XX_CLK_M2M0>, + <&syscon EP93XX_CLK_M2M1>; + clock-names =3D "m2m0", "m2m1"; + interrupt-parent =3D <&vic0>; + interrupts =3D <17>, <18>; + #dma-cells =3D <1>; + }; + +... + diff --git a/Documentation/devicetree/bindings/dma/cirrus,ep9301-dma-m2p.ya= ml b/Documentation/devicetree/bindings/dma/cirrus,ep9301-dma-m2p.yaml new file mode 100644 index 000000000000..79f2d61de6a3 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/cirrus,ep9301-dma-m2p.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/cirrus,ep9301-dma-m2p.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logick ep93xx SoC M2P DMA controller + +maintainers: + - Alexander Sverdlin + - Nikita Shubin + +properties: + compatible: + oneOf: + - const: cirrus,ep9301-dma-m2p + - items: + - enum: + - cirrus,ep9302-dma-m2p + - cirrus,ep9307-dma-m2p + - cirrus,ep9312-dma-m2p + - cirrus,ep9315-dma-m2p + - const: cirrus,ep9301-dma-m2p + + reg: + items: + - description: m2p0 channel registers + - description: m2p1 channel registers + - description: m2p2 channel registers + - description: m2p3 channel registers + - description: m2p4 channel registers + - description: m2p5 channel registers + - description: m2p6 channel registers + - description: m2p7 channel registers + - description: m2p8 channel registers + - description: m2p9 channel registers + + clocks: + items: + - description: m2p0 channel gate clock + - description: m2p1 channel gate clock + - description: m2p2 channel gate clock + - description: m2p3 channel gate clock + - description: m2p4 channel gate clock + - description: m2p5 channel gate clock + - description: m2p6 channel gate clock + - description: m2p7 channel gate clock + - description: m2p8 channel gate clock + - description: m2p9 channel gate clock + + clock-names: + items: + - const: m2p0 + - const: m2p1 + - const: m2p2 + - const: m2p3 + - const: m2p4 + - const: m2p5 + - const: m2p6 + - const: m2p7 + - const: m2p8 + - const: m2p9 + + interrupts: + items: + - description: m2p0 channel interrupt + - description: m2p1 channel interrupt + - description: m2p2 channel interrupt + - description: m2p3 channel interrupt + - description: m2p4 channel interrupt + - description: m2p5 channel interrupt + - description: m2p6 channel interrupt + - description: m2p7 channel interrupt + - description: m2p8 channel interrupt + - description: m2p9 channel interrupt + + '#dma-cells': true + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +additionalProperties: false + +examples: + - | + #include + dma-controller@80000000 { + compatible =3D "cirrus,ep9301-dma-m2p"; + reg =3D <0x80000000 0x0040>, + <0x80000040 0x0040>, + <0x80000080 0x0040>, + <0x800000c0 0x0040>, + <0x80000240 0x0040>, + <0x80000200 0x0040>, + <0x800002c0 0x0040>, + <0x80000280 0x0040>, + <0x80000340 0x0040>, + <0x80000300 0x0040>; + clocks =3D <&syscon EP93XX_CLK_M2P0>, + <&syscon EP93XX_CLK_M2P1>, + <&syscon EP93XX_CLK_M2P2>, + <&syscon EP93XX_CLK_M2P3>, + <&syscon EP93XX_CLK_M2P4>, + <&syscon EP93XX_CLK_M2P5>, + <&syscon EP93XX_CLK_M2P6>, + <&syscon EP93XX_CLK_M2P7>, + <&syscon EP93XX_CLK_M2P8>, + <&syscon EP93XX_CLK_M2P9>; + clock-names =3D "m2p0", "m2p1", + "m2p2", "m2p3", + "m2p4", "m2p5", + "m2p6", "m2p7", + "m2p8", "m2p9"; + interrupt-parent =3D <&vic0>; + interrupts =3D <7>, <8>, <9>, <10>, <11>, <12>, <13>, <14>, <15>, <1= 6>; + #dma-cells =3D <1>; + }; + +... + --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4778C7618E for ; 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a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1682328953; bh=VqfiwALsF03HPfSwF1n2+qvEWhTX1pcFlF7KBnRBI1M=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=r1YWhj6Re3tcztiNcfjIT5JWvetrei9XhHPcHmLkzP4kQTKoPi0o2ym7cX7c4GYU6 bGmMGcYvg5BjYMjmVsjAHIIF0PMY5c2rWG/UJY1FWBVuQTH6RNqQRU1tzBnROYIvn2 q0WQfNyz+8S5W6S8+K6/mQ5IHz/BpOAQ83ZAgdzs= Authentication-Results: mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , Vinod Koul , dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 21/43] dma: cirrus: add DT support for Cirrus EP93xx Date: Mon, 24 Apr 2023 15:34:37 +0300 Message-Id: <20230424123522.18302-22-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" - find register range from the device tree - get clocks, interrupts from device tree Co-developed-by: Alexander Sverdlin Signed-off-by: Alexander Sverdlin Signed-off-by: Nikita Shubin --- Notes: Arnd Bergmann: - wildcards ep93xx to something meaningful, i.e. ep9301 - drop wrappers =20 Changes by Alexander: - correct dma compatible checks - fix dma compatible namings drivers/dma/ep93xx_dma.c | 119 +++++++++++++++++++++-- include/linux/platform_data/dma-ep93xx.h | 3 + 2 files changed, 112 insertions(+), 10 deletions(-) diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c index d19ea885c63e..1da1e20a4d77 100644 --- a/drivers/dma/ep93xx_dma.c +++ b/drivers/dma/ep93xx_dma.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include =20 @@ -104,6 +105,11 @@ #define DMA_MAX_CHAN_BYTES 0xffff #define DMA_MAX_CHAN_DESCRIPTORS 32 =20 +enum ep93xx_dma_type { + M2P_DMA, + M2M_DMA, +}; + struct ep93xx_dma_engine; static int ep93xx_dma_slave_config_write(struct dma_chan *chan, enum dma_transfer_direction dir, @@ -213,7 +219,7 @@ struct ep93xx_dma_engine { #define INTERRUPT_NEXT_BUFFER 2 =20 size_t num_channels; - struct ep93xx_dma_chan channels[]; + struct ep93xx_dma_chan *channels; }; =20 static inline struct device *chan2dev(struct ep93xx_dma_chan *edmac) @@ -875,9 +881,11 @@ static int ep93xx_dma_alloc_chan_resources(struct dma_= chan *chan) if (!edmac->edma->m2m) { if (!data) return -EINVAL; + if (data->port < EP93XX_DMA_I2S1 || data->port > EP93XX_DMA_IRDA) return -EINVAL; + if (data->direction !=3D ep93xx_dma_chan_direction(chan)) return -EINVAL; } else { @@ -1315,20 +1323,88 @@ static void ep93xx_dma_issue_pending(struct dma_cha= n *chan) ep93xx_dma_advance_work(to_ep93xx_dma_chan(chan)); } =20 -static int __init ep93xx_dma_probe(struct platform_device *pdev) + +#ifdef CONFIG_OF +static const struct of_device_id ep93xx_dma_of_ids[] =3D { + { .compatible =3D "cirrus,ep9301-dma-m2p", .data =3D (const void *)M2P_DM= A }, + { .compatible =3D "cirrus,ep9301-dma-m2m", .data =3D (const void *)M2M_DM= A }, + {}, +}; +MODULE_DEVICE_TABLE(of, ep93xx_dma_of_ids); + +static int ep93xx_dma_of_probe(struct platform_device *pdev, + struct ep93xx_dma_engine *edma) +{ + struct device_node *np =3D pdev->dev.of_node; + const struct of_device_id *match =3D of_match_node(ep93xx_dma_of_ids, pde= v->dev.of_node); + struct dma_device *dma_dev =3D &edma->dma_dev; + int num_channels; + int i, ret; + + ret =3D of_property_read_u32(np, "dma-channels", &num_channels); + if (ret) { + dev_err(&pdev->dev, "failed to read dma-channels\n"); + return ret; + } + + edma->channels =3D devm_kzalloc(&pdev->dev, + num_channels * sizeof(struct ep93xx_dma_chan), + GFP_KERNEL); + if (!edma->channels) + return -ENOMEM; + + edma->num_channels =3D num_channels; + edma->m2m =3D match->data; + + INIT_LIST_HEAD(&dma_dev->channels); + for (i =3D 0; i < num_channels; i++) { + struct ep93xx_dma_chan *edmac =3D &edma->channels[i]; + + edmac->chan.device =3D dma_dev; + edmac->regs =3D devm_platform_ioremap_resource(pdev, i); + edmac->irq =3D platform_get_irq(pdev, i); + edmac->edma =3D edma; + + edmac->clk =3D of_clk_get(np, i); + + if (IS_ERR(edmac->clk)) { + dev_warn(&pdev->dev, "failed to get clock\n"); + continue; + } + + spin_lock_init(&edmac->lock); + INIT_LIST_HEAD(&edmac->active); + INIT_LIST_HEAD(&edmac->queue); + INIT_LIST_HEAD(&edmac->free_list); + tasklet_setup(&edmac->tasklet, ep93xx_dma_tasklet); + + list_add_tail(&edmac->chan.device_node, + &dma_dev->channels); + } + + return 0; +} +#else +static int ep93xx_dma_of_probe(struct platform_device *pdev, + struct ep93xx_dma_engine *edma) +{ + return -EINVAL; +} +#endif + +static int ep93xx_init_from_pdata(struct platform_device *pdev, + struct ep93xx_dma_engine *edma) { struct ep93xx_dma_platform_data *pdata =3D dev_get_platdata(&pdev->dev); - struct ep93xx_dma_engine *edma; - struct dma_device *dma_dev; - size_t edma_size; - int ret, i; + struct dma_device *dma_dev =3D &edma->dma_dev; + int i; =20 - edma_size =3D pdata->num_channels * sizeof(struct ep93xx_dma_chan); - edma =3D kzalloc(sizeof(*edma) + edma_size, GFP_KERNEL); - if (!edma) + edma->channels =3D devm_kzalloc(&pdev->dev, + pdata->num_channels * sizeof(struct ep93xx_dma_chan), + GFP_KERNEL); + if (!edma->channels) return -ENOMEM; =20 - dma_dev =3D &edma->dma_dev; edma->m2m =3D platform_get_device_id(pdev)->driver_data; edma->num_channels =3D pdata->num_channels; =20 @@ -1359,6 +1435,27 @@ static int __init ep93xx_dma_probe(struct platform_d= evice *pdev) &dma_dev->channels); } =20 + return 0; +} + +static int __init ep93xx_dma_probe(struct platform_device *pdev) +{ + struct ep93xx_dma_engine *edma; + struct dma_device *dma_dev; + int ret, i; + + edma =3D devm_kzalloc(&pdev->dev, sizeof(*edma), GFP_KERNEL); + + if (platform_get_device_id(pdev)) + ret =3D ep93xx_init_from_pdata(pdev, edma); + else + ret =3D ep93xx_dma_of_probe(pdev, edma); + + if (ret) + return ret; + + dma_dev =3D &edma->dma_dev; + dma_cap_zero(dma_dev->cap_mask); dma_cap_set(DMA_SLAVE, dma_dev->cap_mask); dma_cap_set(DMA_CYCLIC, dma_dev->cap_mask); @@ -1415,10 +1512,12 @@ static const struct platform_device_id ep93xx_dma_d= river_ids[] =3D { { "ep93xx-dma-m2m", 1 }, { }, }; +MODULE_DEVICE_TABLE(of, ep93xx_dma_driver_ids); =20 static struct platform_driver ep93xx_dma_driver =3D { .driver =3D { .name =3D "ep93xx-dma", + .of_match_table =3D ep93xx_dma_of_ids, }, .id_table =3D ep93xx_dma_driver_ids, }; diff --git a/include/linux/platform_data/dma-ep93xx.h b/include/linux/platf= orm_data/dma-ep93xx.h index eb9805bb3fe8..d485e3c21a3a 100644 --- a/include/linux/platform_data/dma-ep93xx.h +++ b/include/linux/platform_data/dma-ep93xx.h @@ -70,6 +70,9 @@ struct ep93xx_dma_platform_data { =20 static inline bool ep93xx_dma_chan_is_m2p(struct dma_chan *chan) { + if (of_device_is_compatible(dev_of_node(chan->device->dev), "cirrus,ep930= 1-dma-m2p")) + return true; + return !strcmp(dev_name(chan->device->dev), "ep93xx-dma-m2p"); } =20 --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15FA8C77B61 for ; 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a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1682328954; bh=gzZfNhCP4gLQxuxIz1zy8IGUwOFk5Um/gkdDTo4axVY=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=caqZCqDLVch5A8ypmNCfIAMmaENWkpVFbRauIda656kQ6KQThwDcE991Cawuw51ul AbXrWBNhpvkR7BsGW5b5ohmYThfKk4TDk4Qf5/3xZSL33tgiLyM+HtmaSe+33VREX1 /DbEUmHjj35NZzYFsT+cb1Zyn1hbCY231hA3Dpxg= Authentication-Results: mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Lukasz Majewski , linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 22/43] dt-bindings: mtd: add DT bindings for ts7250 nand Date: Mon, 24 Apr 2023 15:34:38 +0300 Message-Id: <20230424123522.18302-23-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add YAML bindings for ts7250 NAND. Signed-off-by: Nikita Shubin --- .../bindings/mtd/technologic,nand.yaml | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/technologic,nand.= yaml diff --git a/Documentation/devicetree/bindings/mtd/technologic,nand.yaml b/= Documentation/devicetree/bindings/mtd/technologic,nand.yaml new file mode 100644 index 000000000000..3234d93a1c21 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/technologic,nand.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/technologic,nand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Technologic Systems NAND controller + +maintainers: + - Lukasz Majewski + +properties: + compatible: + items: + - const: technologic,ts7200-nand + - const: gen_nand + + reg: + maxItems: 1 + + '#address-cells': true + '#size-cells': true + +required: + - compatible + - reg + +unevaluatedProperties: true + +examples: + - | + nand-parts@0 { + compatible =3D "technologic,ts7200-nand", "gen_nand"; + reg =3D <0x60000000 0x8000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "TS-BOOTROM"; + reg =3D <0x00000000 0x00020000>; + read-only; + }; + + partition@20000 { + label =3D "Linux"; + reg =3D <0x00020000 0x07d00000>; + }; + + partition@7d20000 { + label =3D "RedBoot"; + reg =3D <0x07d20000 0x002e0000>; + read-only; + }; + }; + +... --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5345C77B7E for ; Thu, 1 Jun 2023 05:46:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231559AbjFAFqT (ORCPT ); Thu, 1 Jun 2023 01:46:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53106 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231454AbjFAFqK (ORCPT ); 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dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij , Hartley Sweeten , Russell King , Vinod Koul , Nikita Shubin Cc: Michael Peters , Kris Bahnsen , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org Subject: [PATCH v1 22/43] dma: cirrus: add DT support for Cirrus EP93xx Date: Thu, 1 Jun 2023 08:45:27 +0300 Message-Id: <20230601054549.10843-4-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" - find register range from the device tree - get clocks, interrupts from device tree Co-developed-by: Alexander Sverdlin Signed-off-by: Alexander Sverdlin Signed-off-by: Nikita Shubin --- arch/arm/mach-ep93xx/dma.c | 1 + drivers/dma/ep93xx_dma.c | 136 +++++++++++++++++++++-- include/linux/platform_data/dma-ep93xx.h | 3 + 3 files changed, 130 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-ep93xx/dma.c b/arch/arm/mach-ep93xx/dma.c index 74515acab8ef..273954cbfced 100644 --- a/arch/arm/mach-ep93xx/dma.c +++ b/arch/arm/mach-ep93xx/dma.c @@ -19,6 +19,7 @@ #include #include #include +#include #include =20 #include diff --git a/drivers/dma/ep93xx_dma.c b/drivers/dma/ep93xx_dma.c index 5338a94f1a69..9f71e08ca380 100644 --- a/drivers/dma/ep93xx_dma.c +++ b/drivers/dma/ep93xx_dma.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include =20 @@ -104,6 +105,11 @@ #define DMA_MAX_CHAN_BYTES 0xffff #define DMA_MAX_CHAN_DESCRIPTORS 32 =20 +enum ep93xx_dma_type { + M2P_DMA, + M2M_DMA, +}; + struct ep93xx_dma_engine; static int ep93xx_dma_slave_config_write(struct dma_chan *chan, enum dma_transfer_direction dir, @@ -213,7 +219,7 @@ struct ep93xx_dma_engine { #define INTERRUPT_NEXT_BUFFER 2 =20 size_t num_channels; - struct ep93xx_dma_chan channels[]; + struct ep93xx_dma_chan *channels; }; =20 static inline struct device *chan2dev(struct ep93xx_dma_chan *edmac) @@ -875,9 +881,11 @@ static int ep93xx_dma_alloc_chan_resources(struct dma_= chan *chan) if (!edmac->edma->m2m) { if (!data) return -EINVAL; + if (data->port < EP93XX_DMA_I2S1 || data->port > EP93XX_DMA_IRDA) return -EINVAL; + if (data->direction !=3D ep93xx_dma_chan_direction(chan)) return -EINVAL; } else { @@ -1315,20 +1323,105 @@ static void ep93xx_dma_issue_pending(struct dma_ch= an *chan) ep93xx_dma_advance_work(to_ep93xx_dma_chan(chan)); } =20 -static int __init ep93xx_dma_probe(struct platform_device *pdev) + +#ifdef CONFIG_OF +struct ep93xx_edma_data { + u32 id; + size_t num_channels; +}; + +static const struct ep93xx_edma_data edma_m2p =3D { + .id =3D M2P_DMA, + .num_channels =3D 10, +}; + +static const struct ep93xx_edma_data edma_m2m =3D { + .id =3D M2M_DMA, + .num_channels =3D 2, +}; + +static const struct of_device_id ep93xx_dma_of_ids[] =3D { + { .compatible =3D "cirrus,ep9301-dma-m2p", .data =3D &edma_m2p }, + { .compatible =3D "cirrus,ep9301-dma-m2m", .data =3D &edma_m2m }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ep93xx_dma_of_ids); + +static int ep93xx_dma_of_probe(struct platform_device *pdev, + struct ep93xx_dma_engine *edma) +{ + struct device_node *np =3D pdev->dev.of_node; + const struct of_device_id *match =3D of_match_node(ep93xx_dma_of_ids, pde= v->dev.of_node); + const struct ep93xx_edma_data *data =3D match->data; + struct dma_device *dma_dev =3D &edma->dma_dev; + int num_channels; + int i; + + match =3D of_match_device((ep93xx_dma_of_ids), &pdev->dev); + if (!match || !match->data) { + dev_err(&pdev->dev, "No device match found\n"); + return -ENODEV; + } + + edma->m2m =3D data->id; + num_channels =3D data->num_channels; + edma->channels =3D devm_kzalloc(&pdev->dev, + num_channels * sizeof(struct ep93xx_dma_chan), + GFP_KERNEL); + if (!edma->channels) + return -ENOMEM; + + edma->num_channels =3D num_channels; + + INIT_LIST_HEAD(&dma_dev->channels); + for (i =3D 0; i < num_channels; i++) { + struct ep93xx_dma_chan *edmac =3D &edma->channels[i]; + + edmac->chan.device =3D dma_dev; + edmac->regs =3D devm_platform_ioremap_resource(pdev, i); + edmac->irq =3D platform_get_irq(pdev, i); + edmac->edma =3D edma; + + edmac->clk =3D of_clk_get(np, i); + + if (IS_ERR(edmac->clk)) { + dev_warn(&pdev->dev, "failed to get clock\n"); + continue; + } + + spin_lock_init(&edmac->lock); + INIT_LIST_HEAD(&edmac->active); + INIT_LIST_HEAD(&edmac->queue); + INIT_LIST_HEAD(&edmac->free_list); + tasklet_setup(&edmac->tasklet, ep93xx_dma_tasklet); + + list_add_tail(&edmac->chan.device_node, + &dma_dev->channels); + } + + return 0; +} +#else +static int ep93xx_dma_of_probe(struct platform_device *pdev, + struct ep93xx_dma_engine *edma) +{ + return -EINVAL; +} +#endif + +static int ep93xx_init_from_pdata(struct platform_device *pdev, + struct ep93xx_dma_engine *edma) { struct ep93xx_dma_platform_data *pdata =3D dev_get_platdata(&pdev->dev); - struct ep93xx_dma_engine *edma; - struct dma_device *dma_dev; - size_t edma_size; - int ret, i; + struct dma_device *dma_dev =3D &edma->dma_dev; + int i; =20 - edma_size =3D pdata->num_channels * sizeof(struct ep93xx_dma_chan); - edma =3D kzalloc(sizeof(*edma) + edma_size, GFP_KERNEL); - if (!edma) + edma->channels =3D devm_kzalloc(&pdev->dev, + pdata->num_channels * sizeof(struct ep93xx_dma_chan), + GFP_KERNEL); + if (!edma->channels) return -ENOMEM; =20 - dma_dev =3D &edma->dma_dev; edma->m2m =3D platform_get_device_id(pdev)->driver_data; edma->num_channels =3D pdata->num_channels; =20 @@ -1359,6 +1452,27 @@ static int __init ep93xx_dma_probe(struct platform_d= evice *pdev) &dma_dev->channels); } =20 + return 0; +} + +static int __init ep93xx_dma_probe(struct platform_device *pdev) +{ + struct ep93xx_dma_engine *edma; + struct dma_device *dma_dev; + int ret, i; + + edma =3D devm_kzalloc(&pdev->dev, sizeof(*edma), GFP_KERNEL); + + if (platform_get_device_id(pdev)) + ret =3D ep93xx_init_from_pdata(pdev, edma); + else + ret =3D ep93xx_dma_of_probe(pdev, edma); + + if (ret) + return ret; + + dma_dev =3D &edma->dma_dev; + dma_cap_zero(dma_dev->cap_mask); dma_cap_set(DMA_SLAVE, dma_dev->cap_mask); dma_cap_set(DMA_CYCLIC, dma_dev->cap_mask); @@ -1415,10 +1529,12 @@ static const struct platform_device_id ep93xx_dma_d= river_ids[] =3D { { "ep93xx-dma-m2m", 1 }, { }, }; +MODULE_DEVICE_TABLE(of, ep93xx_dma_driver_ids); =20 static struct platform_driver ep93xx_dma_driver =3D { .driver =3D { .name =3D "ep93xx-dma", + .of_match_table =3D ep93xx_dma_of_ids, }, .id_table =3D ep93xx_dma_driver_ids, }; diff --git a/include/linux/platform_data/dma-ep93xx.h b/include/linux/platf= orm_data/dma-ep93xx.h index eb9805bb3fe8..d485e3c21a3a 100644 --- a/include/linux/platform_data/dma-ep93xx.h +++ b/include/linux/platform_data/dma-ep93xx.h @@ -70,6 +70,9 @@ struct ep93xx_dma_platform_data { =20 static inline bool ep93xx_dma_chan_is_m2p(struct dma_chan *chan) { + if (of_device_is_compatible(dev_of_node(chan->device->dev), "cirrus,ep930= 1-dma-m2p")) + return true; + return !strcmp(dev_name(chan->device->dev), "ep93xx-dma-m2p"); } =20 --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD94AC77B7A for ; Thu, 1 Jun 2023 05:46:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231513AbjFAFqX (ORCPT ); Thu, 1 Jun 2023 01:46:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53120 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231466AbjFAFqK (ORCPT ); Thu, 1 Jun 2023 01:46:10 -0400 Received: from forward100a.mail.yandex.net (forward100a.mail.yandex.net [178.154.239.83]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C200139; Wed, 31 May 2023 22:46:03 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net [IPv6:2a02:6b8:c1f:5e51:0:640:23ee:0]) by forward100a.mail.yandex.net (Yandex) with ESMTP id 1C91A46CE9; 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charset="utf-8" Add YAML bindings for ts7250 NAND Controller. Signed-off-by: Nikita Shubin --- Notes: v0 -> v1: =20 make it a nand contoller .../bindings/mtd/technologic,nand.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/technologic,nand.= yaml diff --git a/Documentation/devicetree/bindings/mtd/technologic,nand.yaml b/= Documentation/devicetree/bindings/mtd/technologic,nand.yaml new file mode 100644 index 000000000000..26d1d9c3331d --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/technologic,nand.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/technologic,nand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Technologic Systems NAND controller + +maintainers: + - Nikita Shubin + +allOf: + - $ref: nand-controller.yaml + +properties: + compatible: + oneOf: + - const: technologic,ts7200-nand + - items: + - enum: + - technologic,ts7300-nand + - technologic,ts7260-nand + - technologic,ts7250-nand + - const: technologic,ts7200-nand + + reg: + maxItems: 1 + + '#address-cells': true + '#size-cells': true + +required: + - compatible + - reg + +unevaluatedProperties: true + +examples: + - | + nand-controller@60000000 { + compatible =3D "technologic,ts7200-nand"; + reg =3D <0x60000000 0x8000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + +... --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92F1BC77B61 for ; Mon, 24 Apr 2023 10:21:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231745AbjDXKVY (ORCPT ); Mon, 24 Apr 2023 06:21:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44416 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231672AbjDXKUr (ORCPT ); Mon, 24 Apr 2023 06:20:47 -0400 Received: from forward501c.mail.yandex.net (forward501c.mail.yandex.net [178.154.239.209]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BB46E18C for ; Mon, 24 Apr 2023 03:20:45 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net [IPv6:2a02:6b8:c12:261e:0:640:2e3d:0]) by forward501c.mail.yandex.net (Yandex) with ESMTP id 8845C5EBF7; Mon, 24 Apr 2023 12:35:58 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id JZBb1pbWwKo0-qs8Ysl2n; Mon, 24 Apr 2023 12:35:57 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1682328957; bh=26jP1z6kJxd8ER1tdQvbAbkoWyGDLjC4In1lvVJLLi0=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=sG8MZrtDcSveu1AzqOtwAzYRoYdrobB5Ta8zWmDhb+TvBCgPhPXlAoI1ia0VWrbgP DKobaaCytaGR+RiMIBK+PWCikaBjg1Ckrh8ML7KhQbPBo6XIRK8od48iHIZlYjSjyB LEQj79fbsT2LZiyJz3r7ghpUMR22Eh97qB5XqjCQ= Authentication-Results: mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Arnd Bergmann , Neil Armstrong , Chuanhong Guo , Liang Yang , Jean Delvare , Florian Fainelli , linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org Subject: [PATCH 23/43] mtd: ts72xx_nand: add platform helper Date: Mon, 24 Apr 2023 15:34:39 +0300 Message-Id: <20230424123522.18302-24-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The only purpose of this code to provide platform_nand_data to gen_nand driver which requires .cmd_ctrl and .dev_ready. Signed-off-by: Nikita Shubin --- Notes: rfc->v0 Alexander Sverdlin: - platfrom -> platform =20 Linus Walleij: - __raw_read/write[w|l] -> readb/writeb =20 Arnd Bergmann: - name match node ts7250 instead of wildcard drivers/mtd/nand/raw/Kconfig | 8 +++ drivers/mtd/nand/raw/Makefile | 1 + drivers/mtd/nand/raw/ts72xx_nand.c | 94 ++++++++++++++++++++++++++++++ 3 files changed, 103 insertions(+) create mode 100644 drivers/mtd/nand/raw/ts72xx_nand.c diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 170f1185ddc4..08f88c34ce53 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -456,6 +456,14 @@ config MTD_NAND_RENESAS Enables support for the NAND controller found on Renesas R-Car Gen3 and RZ/N1 SoC families. =20 +config MTD_NAND_TS72XX + bool "ts72xx NAND controller" + depends on ARCH_EP93XX && HAS_IOMEM + select MTD_NAND_PLATFORM + help + Enables support for NAND controller on ts72xx SBCs. + These only set's platform data. The real driver is gen_nand. + comment "Misc" =20 config MTD_SM_COMMON diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 917cdfb815b9..b1d5cec84519 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -23,6 +23,7 @@ omap2_nand-objs :=3D omap2.o obj-$(CONFIG_MTD_NAND_OMAP2) +=3D omap2_nand.o obj-$(CONFIG_MTD_NAND_OMAP_BCH_BUILD) +=3D omap_elm.o obj-$(CONFIG_MTD_NAND_MARVELL) +=3D marvell_nand.o +obj-$(CONFIG_MTD_NAND_TS72XX) +=3D ts72xx_nand.o obj-$(CONFIG_MTD_NAND_PLATFORM) +=3D plat_nand.o obj-$(CONFIG_MTD_NAND_PASEMI) +=3D pasemi_nand.o obj-$(CONFIG_MTD_NAND_ORION) +=3D orion_nand.o diff --git a/drivers/mtd/nand/raw/ts72xx_nand.c b/drivers/mtd/nand/raw/ts72= xx_nand.c new file mode 100644 index 000000000000..1c1c06c6e71a --- /dev/null +++ b/drivers/mtd/nand/raw/ts72xx_nand.c @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Technologic Systems TS72xx NAND driver platform code + * Copyright (C) 2021 Nikita Shubin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TS72XX_NAND_CONTROL_ADDR_LINE 22 /* 0xN0400000 */ +#define TS72XX_NAND_BUSY_ADDR_LINE 23 /* 0xN0800000 */ + +static void ts72xx_nand_hwcontrol(struct nand_chip *chip, + int cmd, unsigned int ctrl) +{ + if (ctrl & NAND_CTRL_CHANGE) { + void __iomem *addr =3D chip->legacy.IO_ADDR_R; + unsigned char bits; + + addr +=3D (1 << TS72XX_NAND_CONTROL_ADDR_LINE); + + bits =3D readb(addr) & ~0x07; + bits |=3D (ctrl & NAND_NCE) << 2; /* bit 0 -> bit 2 */ + bits |=3D (ctrl & NAND_CLE); /* bit 1 -> bit 1 */ + bits |=3D (ctrl & NAND_ALE) >> 2; /* bit 2 -> bit 0 */ + + writeb(bits, addr); + } + + if (cmd !=3D NAND_CMD_NONE) + writeb(cmd, chip->legacy.IO_ADDR_W); +} + +static int ts72xx_nand_device_ready(struct nand_chip *chip) +{ + void __iomem *addr =3D chip->legacy.IO_ADDR_R; + + addr +=3D (1 << TS72XX_NAND_BUSY_ADDR_LINE); + + return !!(readb(addr) & 0x20); +} + +static struct platform_nand_data ts72xx_nand_data =3D { + .chip =3D { + .nr_chips =3D 1, + .chip_offset =3D 0, + .chip_delay =3D 15, + }, + .ctrl =3D { + .cmd_ctrl =3D ts72xx_nand_hwcontrol, + .dev_ready =3D ts72xx_nand_device_ready, + }, +}; + +static int __init ts72xx_nand_setup(void) +{ + struct device_node *np; + struct platform_device *pdev; + + /* Multiplatform guard, only proceed on ts7250 */ + if (!of_machine_is_compatible("technologic,ts7250")) + return 0; + + np =3D of_find_compatible_node(NULL, NULL, "technologic,ts7200-nand"); + if (!np) { + pr_err("%s : nand device tree node not found.\n", __func__); + return -EINVAL; + } + + pdev =3D of_find_device_by_node(np); + if (!pdev) { + pr_err("%s : nand device not found.\n", __func__); + return -EINVAL; + } + + pdev->dev.platform_data =3D &ts72xx_nand_data; + put_device(&pdev->dev); + of_node_put(np); + + return 0; +} + +subsys_initcall(ts72xx_nand_setup); --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15BDBC7618E for ; Mon, 24 Apr 2023 10:22:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231837AbjDXKWj (ORCPT ); Mon, 24 Apr 2023 06:22:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46338 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231781AbjDXKVr (ORCPT ); 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dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , Damien Le Moal , Rob Herring , Krzysztof Kozlowski , Le Moal , linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 24/43] dt-bindings: ata: Add DT bindings ep93xx pata Date: Mon, 24 Apr 2023 15:34:40 +0300 Message-Id: <20230424123522.18302-25-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add YAML bindings ep93xx SoC. Signed-off-by: Nikita Shubin --- .../bindings/ata/cirrus,ep93xx-pata.yaml | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/ata/cirrus,ep93xx-pat= a.yaml diff --git a/Documentation/devicetree/bindings/ata/cirrus,ep93xx-pata.yaml = b/Documentation/devicetree/bindings/ata/cirrus,ep93xx-pata.yaml new file mode 100644 index 000000000000..24ed64cfa6d1 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/cirrus,ep93xx-pata.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/cirrus,ep93xx-pata.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EP9312 PATA controller driver + +maintainers: + - Damien Le Moal + +properties: + compatible: + const: cirrus,ep9312-pata + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + ide: ide@800a0000 { + compatible =3D "cirrus,ep9312-pata"; + reg =3D <0x800a0000 0x38>; + interrupt-parent =3D <&vic1>; + interrupts =3D <8>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ide_default_pins>; + }; + +... --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1EA0C77B7E for ; Thu, 1 Jun 2023 05:46:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231476AbjFAFqs (ORCPT ); Thu, 1 Jun 2023 01:46:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53232 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231474AbjFAFqb (ORCPT ); Thu, 1 Jun 2023 01:46:31 -0400 Received: from forward103a.mail.yandex.net (forward103a.mail.yandex.net [178.154.239.86]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 17853E5A for ; Wed, 31 May 2023 22:46:13 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net [IPv6:2a02:6b8:c1f:5e51:0:640:23ee:0]) by forward103a.mail.yandex.net (Yandex) with ESMTP id 7E8E646D04; Thu, 1 Jun 2023 08:46:11 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id pjGDMhnDduQ0-YQEzRG2A; Thu, 01 Jun 2023 08:46:10 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1685598370; bh=zUol15piszy0DpHFh7aq9OsjbFQ/XdK+rX3Y5m5Tct8=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=mNLMxmyvWOKZ1qbHS4LNUvJ9HpLHsCg2zDw9xBnBUM2prl7+02tLgazyiAj6qtR8W 7QWjP3jqwoaGL1EoSjIym8BNdAWIWKPR2pUSN8bdVVxtCnXKiyZ9i0h7B1zS+fBwr6 bMLabvG2S6I8UOuAk6y/SnBQtGjdPpiZKp+oAzvQ= Authentication-Results: mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Jonathan Cameron , Stephen Boyd , Christophe Kerello , Jean Delvare , Nikita Shubin , Liang Yang , Florian Fainelli Cc: Michael Peters , Kris Bahnsen , linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org Subject: [PATCH v1 24/43] mtd: nand: add support for ts72xx Date: Thu, 1 Jun 2023 08:45:29 +0300 Message-Id: <20230601054549.10843-6-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Technologic Systems has it's own nand controller implementation in CPLD. This patch adds support for TS-72XX boards family. Signed-off-by: Nikita Shubin --- drivers/mtd/nand/raw/Kconfig | 7 + drivers/mtd/nand/raw/Makefile | 1 + .../nand/raw/technologic-nand-controller.c | 151 ++++++++++++++++++ 3 files changed, 159 insertions(+) create mode 100644 drivers/mtd/nand/raw/technologic-nand-controller.c diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index b523354dfb00..94788da1a169 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -456,6 +456,13 @@ config MTD_NAND_RENESAS Enables support for the NAND controller found on Renesas R-Car Gen3 and RZ/N1 SoC families. =20 +config MTD_NAND_TS72XX + bool "ts72xx NAND controller" + depends on ARCH_EP93XX && HAS_IOMEM + help + Enables support for NAND controller on ts72xx SBCs. + This is a legacy driver based on gen_nand. + comment "Misc" =20 config MTD_SM_COMMON diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 917cdfb815b9..783e990a0078 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -23,6 +23,7 @@ omap2_nand-objs :=3D omap2.o obj-$(CONFIG_MTD_NAND_OMAP2) +=3D omap2_nand.o obj-$(CONFIG_MTD_NAND_OMAP_BCH_BUILD) +=3D omap_elm.o obj-$(CONFIG_MTD_NAND_MARVELL) +=3D marvell_nand.o +obj-$(CONFIG_MTD_NAND_TS72XX) +=3D technologic-nand-controller.o obj-$(CONFIG_MTD_NAND_PLATFORM) +=3D plat_nand.o obj-$(CONFIG_MTD_NAND_PASEMI) +=3D pasemi_nand.o obj-$(CONFIG_MTD_NAND_ORION) +=3D orion_nand.o diff --git a/drivers/mtd/nand/raw/technologic-nand-controller.c b/drivers/m= td/nand/raw/technologic-nand-controller.c new file mode 100644 index 000000000000..09aeada933a1 --- /dev/null +++ b/drivers/mtd/nand/raw/technologic-nand-controller.c @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Technologic Systems TS72xx NAND controller driver + * + * Copyright (C) 2023 Nikita Shubin + * + * derived: plat_nand.c + * Author: Vitaly Wool + */ + +#include +#include +#include +#include +#include +#include +#include + +#define TS72XX_NAND_CONTROL_ADDR_LINE 22 /* 0xN0400000 */ +#define TS72XX_NAND_BUSY_ADDR_LINE 23 /* 0xN0800000 */ + +struct ts72xx_nand_data { + struct nand_controller controller; + struct nand_chip chip; + void __iomem *io_base; +}; + +static int ts72xx_nand_attach_chip(struct nand_chip *chip) +{ + if (chip->ecc.engine_type =3D=3D NAND_ECC_ENGINE_TYPE_SOFT && + chip->ecc.algo =3D=3D NAND_ECC_ALGO_UNKNOWN) + chip->ecc.algo =3D NAND_ECC_ALGO_HAMMING; + + return 0; +} + +static const struct nand_controller_ops ts72xx_nand_ops =3D { + .attach_chip =3D ts72xx_nand_attach_chip, +}; + +static void ts72xx_nand_hwcontrol(struct nand_chip *chip, + int cmd, unsigned int ctrl) +{ + if (ctrl & NAND_CTRL_CHANGE) { + void __iomem *addr =3D chip->legacy.IO_ADDR_R; + unsigned char bits; + + addr +=3D (1 << TS72XX_NAND_CONTROL_ADDR_LINE); + + bits =3D readb(addr) & ~0x07; + bits |=3D (ctrl & NAND_NCE) << 2; /* bit 0 -> bit 2 */ + bits |=3D (ctrl & NAND_CLE); /* bit 1 -> bit 1 */ + bits |=3D (ctrl & NAND_ALE) >> 2; /* bit 2 -> bit 0 */ + + writeb(bits, addr); + } + + if (cmd !=3D NAND_CMD_NONE) + writeb(cmd, chip->legacy.IO_ADDR_W); +} + +static int ts72xx_nand_device_ready(struct nand_chip *chip) +{ + void __iomem *addr =3D chip->legacy.IO_ADDR_R; + + addr +=3D (1 << TS72XX_NAND_BUSY_ADDR_LINE); + + return !!(readb(addr) & 0x20); +} + +static int ts72xx_nand_probe(struct platform_device *pdev) +{ + struct ts72xx_nand_data *data; + struct mtd_info *mtd; + int err =3D 0; + + /* Allocate memory for the device structure (and zero it) */ + data =3D devm_kzalloc(&pdev->dev, sizeof(struct ts72xx_nand_data), + GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->controller.ops =3D &ts72xx_nand_ops; + nand_controller_init(&data->controller); + data->chip.controller =3D &data->controller; + + data->io_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(data->io_base)) + return PTR_ERR(data->io_base); + + nand_set_flash_node(&data->chip, pdev->dev.of_node); + mtd =3D nand_to_mtd(&data->chip); + mtd->dev.parent =3D &pdev->dev; + + data->chip.legacy.IO_ADDR_R =3D data->io_base; + data->chip.legacy.IO_ADDR_W =3D data->io_base; + data->chip.legacy.cmd_ctrl =3D ts72xx_nand_hwcontrol; + data->chip.legacy.dev_ready =3D ts72xx_nand_device_ready; + + platform_set_drvdata(pdev, data); + + /* + * This driver assumes that the default ECC engine should be TYPE_SOFT. + * Set ->engine_type before registering the NAND devices in order to + * provide a driver specific default value. + */ + data->chip.ecc.engine_type =3D NAND_ECC_ENGINE_TYPE_SOFT; + + /* Scan to find existence of the device */ + err =3D nand_scan(&data->chip, 1); + if (err) + return err; + + err =3D mtd_device_parse_register(mtd, NULL, NULL, + NULL, 0); + + if (!err) + return err; + + nand_cleanup(&data->chip); + + return 0; +} + +static void ts72xx_nand_remove(struct platform_device *pdev) +{ + struct ts72xx_nand_data *data =3D platform_get_drvdata(pdev); + struct nand_chip *chip =3D &data->chip; + int ret; + + ret =3D mtd_device_unregister(nand_to_mtd(chip)); + WARN_ON(ret); + nand_cleanup(chip); +} + +static const struct of_device_id ts72xx_id_table[] =3D { + { .compatible =3D "technologic,ts7200-nand" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ts72xx_id_table); + +static struct platform_driver ts72xx_nand_driver =3D { + .driver =3D { + .name =3D "ts72xx-nand", + .of_match_table =3D ts72xx_id_table, + }, + .probe =3D ts72xx_nand_probe, + .remove_new =3D ts72xx_nand_remove, +}; +module_platform_driver(ts72xx_nand_driver); + --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 813CEC77B61 for ; Mon, 24 Apr 2023 09:55:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231653AbjDXJz4 (ORCPT ); Mon, 24 Apr 2023 05:55:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54990 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231520AbjDXJzr (ORCPT ); Mon, 24 Apr 2023 05:55:47 -0400 Received: from forward502c.mail.yandex.net (forward502c.mail.yandex.net [178.154.239.210]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 60E8A40F0; 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(no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" - find register range from the device tree - get interrupts from device tree Signed-off-by: Nikita Shubin --- Notes: Arnd Bergmann: - wildcards ep93xx to something meaningful, i.e. ep9301 - drop wrappers drivers/ata/pata_ep93xx.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/ata/pata_ep93xx.c b/drivers/ata/pata_ep93xx.c index 47845d920075..09c95758389e 100644 --- a/drivers/ata/pata_ep93xx.c +++ b/drivers/ata/pata_ep93xx.c @@ -40,6 +40,8 @@ #include #include #include +#include +#include #include #include #include @@ -1016,9 +1018,16 @@ static int ep93xx_pata_remove(struct platform_device= *pdev) return 0; } =20 +static const struct of_device_id ep93xx_pata_of_ids[] =3D { + { .compatible =3D "cirrus,ep9312-pata" }, + {}, +}; +MODULE_DEVICE_TABLE(of, ep93xx_pata_of_ids); + static struct platform_driver ep93xx_pata_platform_driver =3D { .driver =3D { .name =3D DRV_NAME, + .of_match_table =3D ep93xx_pata_of_ids, }, .probe =3D ep93xx_pata_probe, .remove =3D ep93xx_pata_remove, --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B303AC77B7A for ; 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charset="utf-8" Add YAML bindings for ep93xx SoC PATA. Signed-off-by: Nikita Shubin Acked-by: Damien Le Moal --- Notes: v0 -> v1: =20 - renamed file to ep9312-pata - changed email to dlemoal@kernel.org - dropped label - fixed ident .../bindings/ata/cirrus,ep9312-pata.yaml | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/ata/cirrus,ep9312-pat= a.yaml diff --git a/Documentation/devicetree/bindings/ata/cirrus,ep9312-pata.yaml = b/Documentation/devicetree/bindings/ata/cirrus,ep9312-pata.yaml new file mode 100644 index 000000000000..3489be55a6fe --- /dev/null +++ b/Documentation/devicetree/bindings/ata/cirrus,ep9312-pata.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/cirrus,ep9312-pata.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic EP9312 PATA controller + +maintainers: + - Damien Le Moal + +properties: + compatible: + oneOf: + - const: cirrus,ep9312-pata + - items: + - const: cirrus,ep9315-pata + - const: cirrus,ep9312-pata + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + ide@800a0000 { + compatible =3D "cirrus,ep9312-pata"; + reg =3D <0x800a0000 0x38>; + interrupt-parent =3D <&vic1>; + interrupts =3D <8>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ide_default_pins>; + }; + +... --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EE62C7EE2C for ; Thu, 1 Jun 2023 05:46:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230410AbjFAFqx (ORCPT ); Thu, 1 Jun 2023 01:46:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53134 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231590AbjFAFqi (ORCPT ); Thu, 1 Jun 2023 01:46:38 -0400 Received: from forward100a.mail.yandex.net (forward100a.mail.yandex.net [178.154.239.83]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BDC69E6D; Wed, 31 May 2023 22:46:17 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net [IPv6:2a02:6b8:c1f:5e51:0:640:23ee:0]) by forward100a.mail.yandex.net (Yandex) with ESMTP id 570F341C76; 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charset="utf-8" - find register range from the device tree - get interrupts from device tree Signed-off-by: Nikita Shubin --- Notes: v0 -> v1: =20 - fixed headers - dropped coma in id table drivers/ata/pata_ep93xx.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/ata/pata_ep93xx.c b/drivers/ata/pata_ep93xx.c index c6e043e05d43..8d363bc71342 100644 --- a/drivers/ata/pata_ep93xx.c +++ b/drivers/ata/pata_ep93xx.c @@ -40,6 +40,7 @@ #include #include #include +#include #include #include #include @@ -1016,9 +1017,16 @@ static int ep93xx_pata_remove(struct platform_device= *pdev) return 0; } =20 +static const struct of_device_id ep93xx_pata_of_ids[] =3D { + { .compatible =3D "cirrus,ep9312-pata" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ep93xx_pata_of_ids); + static struct platform_driver ep93xx_pata_platform_driver =3D { .driver =3D { .name =3D DRV_NAME, + .of_match_table =3D ep93xx_pata_of_ids, }, .probe =3D ep93xx_pata_probe, .remove =3D ep93xx_pata_remove, --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3D35C7618E for ; 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a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1682328960; bh=qyIgOCdaAxA/ZmT6JZ72pRqNQLXvT4Bjw+nu8ZCSGLk=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=cji00OIAtPjo/9c1sBW5SB3NHMzdCY0u5pc2PqHE5ymJjgPE/p4wxBGzf53/9Del7 gV/Lc+k5xLLfAw3Q8poSd2dD0YnSdAyKzkfNvwMnwIOkVCdy5TZ5/TP3XzPVc3fZJz PcX5efJxRZNg4xE0W2Z5PoH5t483P48nUmmqXHVM= Authentication-Results: mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , Dmitry Torokhov , Rob Herring , Krzysztof Kozlowski , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 26/43] dt-bindings: input: Add DT bindings ep93xx keypad Date: Mon, 24 Apr 2023 15:34:42 +0300 Message-Id: <20230424123522.18302-27-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add YAML bindings ep93xx SoC. Signed-off-by: Nikita Shubin --- Notes: Linus Walleij: - replaced hex with proper , etc .../bindings/input/cirrus,ep93xx-keypad.yaml | 123 ++++++++++++++++++ 1 file changed, 123 insertions(+) create mode 100644 Documentation/devicetree/bindings/input/cirrus,ep93xx-k= eypad.yaml diff --git a/Documentation/devicetree/bindings/input/cirrus,ep93xx-keypad.y= aml b/Documentation/devicetree/bindings/input/cirrus,ep93xx-keypad.yaml new file mode 100644 index 000000000000..0310114de22e --- /dev/null +++ b/Documentation/devicetree/bindings/input/cirrus,ep93xx-keypad.yaml @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/cirrus,ep93xx-keypad.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus ep93xx keypad + +maintainers: + - Dmitry Torokhov + - Alexander Sverdlin + +allOf: + - $ref: "/schemas/input/matrix-keymap.yaml#" + +description: | + The KPP is designed to interface with a keypad matrix with 2-point conta= ct + or 3-point contact keys. The KPP is designed to simplify the software ta= sk + of scanning a keypad matrix. The KPP is capable of detecting, debouncing, + and decoding one or multiple keys pressed simultaneously on a keypad. + +properties: + compatible: + enum: + - cirrus,ep9301-keypad + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + enum: + - ep93xx-keypad + + debounce: + description: | + Time in microseconds that key must be pressed or + released for state change interrupt to trigger. + $ref: /schemas/types.yaml#/definitions/uint32 + + prescale: + description: row/column counter pre-scaler load value + $ref: /schemas/types.yaml#/definitions/uint32 + + clk-rate: + description: clock rate setting + $ref: /schemas/types.yaml#/definitions/uint32 + + disable-3-key: + type: boolean + description: + Disable 3 Key reset. Setting this disables the three key reset + output to the watchdog reset block. + + diag-mode: + type: boolean + description: + Key scan diagnostic mode. Setting this allows key scanning to be + directly controlled through the key register by writes from the + ARM Core. + + back-drive: + type: boolean + description: + Key scan back driving enable. Setting this enables the key + scanning logic to back drive the row and column pins of the + chip high during the first two column counts in the + row/column counter. + + test-mode: + type: boolean + description: + Test mode. When this is set, the counter RC_COUNT is advanced + by 8 counts when EN is active. The effect is that only column 0 + is checked in each row. This test mode allows a faster test + of the ROW pins. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - linux,keymap + +unevaluatedProperties: false + +examples: + - | + #include + #include + keypad@800f0000 { + compatible =3D "cirrus,ep9301-keypad"; + reg =3D <0x800f0000 0x0c>; + interrupt-parent =3D <&vic0>; + interrupts =3D <29>; + clocks =3D <&syscon EP93XX_CLK_KEYPAD>; + clock-names =3D "ep93xx-keypad"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&keypad_default_pins>; + linux,keymap =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E3AFC77B76 for ; Mon, 24 Apr 2023 10:22:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231843AbjDXKWx (ORCPT ); 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charset="utf-8" - get keymap from the device tree - find register range from the device tree - get interrupts from device tree Signed-off-by: Nikita Shubin --- Notes: Arnd Bergmann: - wildcards ep93xx to something meaningful, i.e. ep9301 - drop wrappers drivers/input/keyboard/ep93xx_keypad.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/input/keyboard/ep93xx_keypad.c b/drivers/input/keyboar= d/ep93xx_keypad.c index 55075addcac2..bf77754fa4c7 100644 --- a/drivers/input/keyboard/ep93xx_keypad.c +++ b/drivers/input/keyboard/ep93xx_keypad.c @@ -20,6 +20,8 @@ #include #include #include +#include +#include #include #include #include @@ -315,10 +317,17 @@ static int ep93xx_keypad_remove(struct platform_devic= e *pdev) return 0; } =20 +static const struct of_device_id ep93xx_keypad_of_ids[] =3D { + { .compatible =3D "cirrus,ep9301-keypad" }, + {}, +}; +MODULE_DEVICE_TABLE(of, ep93xx_keypad_of_ids); + static struct platform_driver ep93xx_keypad_driver =3D { .driver =3D { .name =3D "ep93xx-keypad", .pm =3D pm_sleep_ptr(&ep93xx_keypad_pm_ops), + .of_match_table =3D ep93xx_keypad_of_ids, }, .probe =3D ep93xx_keypad_probe, .remove =3D ep93xx_keypad_remove, --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77D4CC77B7E for ; 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charset="utf-8" Add YAML bindings for ep93xx SoC keypad. Signed-off-by: Nikita Shubin --- Notes: v0 -> v1: =20 - remove almost all but debounce-delay-ms and prescale - s/ep9301-keypad/ep9307-keypad/ it's actually only for ep9307, ep9312, ep9315 =20 Krzysztof Kozlowski: - renamed file - changed maintainers - dropped quotes - dropped clock-names - use fallback compatible and list all possible compatibles - fix ident .../bindings/input/cirrus,ep9307-keypad.yaml | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/input/cirrus,ep9307-k= eypad.yaml diff --git a/Documentation/devicetree/bindings/input/cirrus,ep9307-keypad.y= aml b/Documentation/devicetree/bindings/input/cirrus,ep9307-keypad.yaml new file mode 100644 index 000000000000..c7eb10a84a6b --- /dev/null +++ b/Documentation/devicetree/bindings/input/cirrus,ep9307-keypad.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/cirrus,ep9307-keypad.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus ep93xx keypad + +maintainers: + - Alexander Sverdlin + +allOf: + - $ref: /schemas/input/matrix-keymap.yaml# + +description: | + The KPP is designed to interface with a keypad matrix with 2-point conta= ct + or 3-point contact keys. The KPP is designed to simplify the software ta= sk + of scanning a keypad matrix. The KPP is capable of detecting, debouncing, + and decoding one or multiple keys pressed simultaneously on a keypad. + +properties: + compatible: + oneOf: + - const: cirrus,ep9307-keypad + - items: + - enum: + - cirrus,ep9312-keypad + - cirrus,ep9315-keypad + - const: cirrus,ep9307-keypad + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + cirrus,debounce-delay-ms: + description: | + Time in microseconds that key must be pressed or + released for state change interrupt to trigger. + + cirrus,prescale: + description: row/column counter pre-scaler load value + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - interrupts + - clocks + - linux,keymap + +unevaluatedProperties: false + +examples: + - | + #include + #include + keypad@800f0000 { + compatible =3D "cirrus,ep9301-keypad"; + reg =3D <0x800f0000 0x0c>; + interrupt-parent =3D <&vic0>; + interrupts =3D <29>; + clocks =3D <&syscon EP93XX_CLK_KEYPAD>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&keypad_default_pins>; + linux,keymap =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7CADC77B61 for ; Mon, 24 Apr 2023 10:22:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231547AbjDXKV6 (ORCPT ); Mon, 24 Apr 2023 06:21:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45278 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231600AbjDXKVG (ORCPT ); Mon, 24 Apr 2023 06:21:06 -0400 Received: from forward502b.mail.yandex.net (forward502b.mail.yandex.net [178.154.239.146]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2A8243C04; Mon, 24 Apr 2023 03:20:49 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net [IPv6:2a02:6b8:c12:261e:0:640:2e3d:0]) by forward502b.mail.yandex.net (Yandex) with ESMTP id 940275EDD8; Mon, 24 Apr 2023 12:36:02 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id JZBb1pbWwKo0-IWWSMic2; Mon, 24 Apr 2023 12:36:02 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1682328962; bh=d3R4SlbJR9GyKNTHeSNJIKou6BcJywQO8CN3xVIBaKM=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=OiJhIKfvqQJYJwfDut+7wSS0wQeQ/4nY/0VNMXXBNQ5ACuI91r7JkJ63nySQ+U8jJ 9hf8AEjul23/MMiL7ihkOAM11yFpF+/MoZYiqCd7Nz4TQHgcBv1ryTZBjbIQZxPbPQ IVQwaFRJTLeNVNrBPTudKgefHg3wI5T4wJ/2HUwg= Authentication-Results: mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , Alessandro Zummo , Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 28/43] dt-bindings: rtc: Add DT binding m48t86 rtc Date: Mon, 24 Apr 2023 15:34:44 +0300 Message-Id: <20230424123522.18302-29-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add YAML bindings for ST M48T86 / Dallas DS12887 RTC. Signed-off-by: Nikita Shubin --- .../bindings/rtc/dallas,rtc-m48t86.yaml | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/dallas,rtc-m48t86= .yaml diff --git a/Documentation/devicetree/bindings/rtc/dallas,rtc-m48t86.yaml b= /Documentation/devicetree/bindings/rtc/dallas,rtc-m48t86.yaml new file mode 100644 index 000000000000..51f98bdbc385 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/dallas,rtc-m48t86.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/dallas,rtc-m48t86.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ST M48T86 / Dallas DS12887 RTC bindings + +maintainers: + - Alessandro Zummo + +properties: + compatible: + const: dallas,rtc-m48t86 + + reg: + maxItems: 2 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + rtc1: rtc@10800000 { + compatible =3D "dallas,rtc-m48t86"; + reg =3D <0x10800000 0x1>, <0x11700000 0x1>; + }; + +... + --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C236C77B7A for ; Thu, 1 Jun 2023 05:47:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231674AbjFAFrY (ORCPT ); Thu, 1 Jun 2023 01:47:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53232 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231319AbjFAFqp (ORCPT ); Thu, 1 Jun 2023 01:46:45 -0400 Received: from forward102a.mail.yandex.net (forward102a.mail.yandex.net [178.154.239.85]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09392197; Wed, 31 May 2023 22:46:20 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net [IPv6:2a02:6b8:c1f:5e51:0:640:23ee:0]) by forward102a.mail.yandex.net (Yandex) with ESMTP id 3BEA346C8B; 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charset="utf-8" - get keymap from the device tree - find register range from the device tree - get interrupts from device tree Signed-off-by: Nikita Shubin --- Notes: v0 -> v1: =20 - fixed header - dropped coma in id table - take debounce, prescale from dt - remove ep93xx_keypad_platform_data - move flags to module params - drop setting clock rate, it's useless, as was never used, it seems we are okay with default clk rate used - move usefull defines from platform file here - drop platform header drivers/input/keyboard/ep93xx_keypad.c | 78 +++++++++++++------------- 1 file changed, 40 insertions(+), 38 deletions(-) diff --git a/drivers/input/keyboard/ep93xx_keypad.c b/drivers/input/keyboar= d/ep93xx_keypad.c index 55075addcac2..8b0e73f56216 100644 --- a/drivers/input/keyboard/ep93xx_keypad.c +++ b/drivers/input/keyboard/ep93xx_keypad.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -27,7 +28,6 @@ #include #include #include -#include #include =20 /* @@ -61,12 +61,18 @@ #define KEY_REG_KEY1_MASK GENMASK(5, 0) #define KEY_REG_KEY1_SHIFT 0 =20 +#define EP93XX_MATRIX_ROWS (8) +#define EP93XX_MATRIX_COLS (8) + #define EP93XX_MATRIX_SIZE (EP93XX_MATRIX_ROWS * EP93XX_MATRIX_COLS) =20 struct ep93xx_keypad { - struct ep93xx_keypad_platform_data *pdata; struct input_dev *input_dev; struct clk *clk; + unsigned int debounce; + unsigned int prescale; + unsigned int flags; + unsigned int clk_rate; =20 void __iomem *mmio_base; =20 @@ -80,6 +86,17 @@ struct ep93xx_keypad { bool enabled; }; =20 +/* flags for the ep93xx_keypad driver */ +#define EP93XX_KEYPAD_DISABLE_3_KEY (1<<0) /* disable 3-key reset */ +#define EP93XX_KEYPAD_DIAG_MODE (1<<1) /* diagnostic mode */ +#define EP93XX_KEYPAD_BACK_DRIVE (1<<2) /* back driving mode */ +#define EP93XX_KEYPAD_TEST_MODE (1<<3) /* scan only column 0 */ +#define EP93XX_KEYPAD_AUTOREPEAT (1<<4) /* enable key autorepeat */ + +static int ep93xx_keypad_flags; +module_param(ep93xx_keypad_flags, int, 0); +MODULE_PARM_DESC(ep93xx_keypad_flags, "EP93XX keypad flags."); + static irqreturn_t ep93xx_keypad_irq_handler(int irq, void *dev_id) { struct ep93xx_keypad *keypad =3D dev_id; @@ -133,23 +150,20 @@ static irqreturn_t ep93xx_keypad_irq_handler(int irq,= void *dev_id) =20 static void ep93xx_keypad_config(struct ep93xx_keypad *keypad) { - struct ep93xx_keypad_platform_data *pdata =3D keypad->pdata; unsigned int val =3D 0; =20 - clk_set_rate(keypad->clk, pdata->clk_rate); - - if (pdata->flags & EP93XX_KEYPAD_DISABLE_3_KEY) + if (keypad->flags & EP93XX_KEYPAD_DISABLE_3_KEY) val |=3D KEY_INIT_DIS3KY; - if (pdata->flags & EP93XX_KEYPAD_DIAG_MODE) + if (keypad->flags & EP93XX_KEYPAD_DIAG_MODE) val |=3D KEY_INIT_DIAG; - if (pdata->flags & EP93XX_KEYPAD_BACK_DRIVE) + if (keypad->flags & EP93XX_KEYPAD_BACK_DRIVE) val |=3D KEY_INIT_BACK; - if (pdata->flags & EP93XX_KEYPAD_TEST_MODE) + if (keypad->flags & EP93XX_KEYPAD_TEST_MODE) val |=3D KEY_INIT_T2; =20 - val |=3D ((pdata->debounce << KEY_INIT_DBNC_SHIFT) & KEY_INIT_DBNC_MASK); + val |=3D ((keypad->debounce << KEY_INIT_DBNC_SHIFT) & KEY_INIT_DBNC_MASK); =20 - val |=3D ((pdata->prescale << KEY_INIT_PRSCL_SHIFT) & KEY_INIT_PRSCL_MASK= ); + val |=3D ((keypad->prescale << KEY_INIT_PRSCL_SHIFT) & KEY_INIT_PRSCL_MAS= K); =20 __raw_writel(val, keypad->mmio_base + KEY_INIT); } @@ -220,17 +234,10 @@ static int ep93xx_keypad_resume(struct device *dev) static DEFINE_SIMPLE_DEV_PM_OPS(ep93xx_keypad_pm_ops, ep93xx_keypad_suspend, ep93xx_keypad_resume); =20 -static void ep93xx_keypad_release_gpio_action(void *_pdev) -{ - struct platform_device *pdev =3D _pdev; - - ep93xx_keypad_release_gpio(pdev); -} - static int ep93xx_keypad_probe(struct platform_device *pdev) { + struct device_node *np =3D pdev->dev.of_node; struct ep93xx_keypad *keypad; - const struct matrix_keymap_data *keymap_data; struct input_dev *input_dev; int err; =20 @@ -238,14 +245,6 @@ static int ep93xx_keypad_probe(struct platform_device = *pdev) if (!keypad) return -ENOMEM; =20 - keypad->pdata =3D dev_get_platdata(&pdev->dev); - if (!keypad->pdata) - return -EINVAL; - - keymap_data =3D keypad->pdata->keymap_data; - if (!keymap_data) - return -EINVAL; - keypad->irq =3D platform_get_irq(pdev, 0); if (keypad->irq < 0) return keypad->irq; @@ -254,19 +253,15 @@ static int ep93xx_keypad_probe(struct platform_device= *pdev) if (IS_ERR(keypad->mmio_base)) return PTR_ERR(keypad->mmio_base); =20 - err =3D ep93xx_keypad_acquire_gpio(pdev); - if (err) - return err; - - err =3D devm_add_action_or_reset(&pdev->dev, - ep93xx_keypad_release_gpio_action, pdev); - if (err) - return err; - keypad->clk =3D devm_clk_get(&pdev->dev, NULL); if (IS_ERR(keypad->clk)) return PTR_ERR(keypad->clk); =20 + keypad->flags =3D ep93xx_keypad_flags; + + of_property_read_u32(np, "cirrus,debounce-delay-ms", &keypad->debounce); + of_property_read_u32(np, "cirrus,prescale", &keypad->prescale); + input_dev =3D devm_input_allocate_device(&pdev->dev); if (!input_dev) return -ENOMEM; @@ -278,13 +273,13 @@ static int ep93xx_keypad_probe(struct platform_device= *pdev) input_dev->open =3D ep93xx_keypad_open; input_dev->close =3D ep93xx_keypad_close; =20 - err =3D matrix_keypad_build_keymap(keymap_data, NULL, + err =3D matrix_keypad_build_keymap(NULL, NULL, EP93XX_MATRIX_ROWS, EP93XX_MATRIX_COLS, keypad->keycodes, input_dev); if (err) return err; =20 - if (keypad->pdata->flags & EP93XX_KEYPAD_AUTOREPEAT) + if (keypad->flags & EP93XX_KEYPAD_AUTOREPEAT) __set_bit(EV_REP, input_dev->evbit); input_set_drvdata(input_dev, keypad); =20 @@ -315,10 +310,17 @@ static int ep93xx_keypad_remove(struct platform_devic= e *pdev) return 0; } =20 +static const struct of_device_id ep93xx_keypad_of_ids[] =3D { + { .compatible =3D "cirrus,ep9307-keypad" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ep93xx_keypad_of_ids); + static struct platform_driver ep93xx_keypad_driver =3D { .driver =3D { .name =3D "ep93xx-keypad", .pm =3D pm_sleep_ptr(&ep93xx_keypad_pm_ops), + .of_match_table =3D ep93xx_keypad_of_ids, }, .probe =3D ep93xx_keypad_probe, .remove =3D ep93xx_keypad_remove, --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53F23C77B7A for ; Thu, 1 Jun 2023 05:47:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231572AbjFAFra (ORCPT ); Thu, 1 Jun 2023 01:47:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53674 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231532AbjFAFqr (ORCPT ); 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dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij , Alessandro Zummo , Alexandre Belloni , Rob Herring , Krzysztof Kozlowski Cc: Nikita Shubin , Michael Peters , Kris Bahnsen , linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 29/43] dt-bindings: rtc: Add ST M48T86 Date: Thu, 1 Jun 2023 08:45:34 +0300 Message-Id: <20230601054549.10843-11-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add YAML bindings for ST M48T86 / Dallas DS12887 RTC. Signed-off-by: Nikita Shubin --- Notes: v0 -> v1: =20 - s/dallas/st/ - description for regs - s/additionalProperties/unevaluatedProperties/ - add ref rtc.yaml - changed compatible to st,m48t86 - dropped label in example - replaced Alessandro Alessandro to Alexandre Belloni .../bindings/rtc/st,m48t86-rtc.yaml | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/st,m48t86-rtc.yaml diff --git a/Documentation/devicetree/bindings/rtc/st,m48t86-rtc.yaml b/Doc= umentation/devicetree/bindings/rtc/st,m48t86-rtc.yaml new file mode 100644 index 000000000000..eb8e6451d7c8 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/st,m48t86-rtc.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/st,m48t86-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ST M48T86 / Dallas DS12887 RTC wirh SRAM + +maintainers: + - Alexandre Belloni + +properties: + compatible: + enum: + - st,m48t86 + + reg: + items: + - description: index register + - description: data register + +allOf: + - $ref: rtc.yaml + +unevaluatedProperties: false + +required: + - compatible + - reg + +examples: + - | + rtc@10800000 { + compatible =3D "st,m48t86"; + reg =3D <0x10800000 0x1>, <0x11700000 0x1>; + }; + +... --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8777EC77B7E for ; Mon, 24 Apr 2023 10:20:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231429AbjDXKU5 (ORCPT ); Mon, 24 Apr 2023 06:20:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231415AbjDXKUl (ORCPT ); Mon, 24 Apr 2023 06:20:41 -0400 Received: from forward501c.mail.yandex.net (forward501c.mail.yandex.net [IPv6:2a02:6b8:c03:500:1:45:d181:d501]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0BF2D1FE2 for ; Mon, 24 Apr 2023 03:20:39 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net [IPv6:2a02:6b8:c12:261e:0:640:2e3d:0]) by forward501c.mail.yandex.net (Yandex) with ESMTP id 0235D5EEC3; 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(no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" - get regs from device tree Signed-off-by: Nikita Shubin Acked-by: Arnd Bergmann --- drivers/rtc/rtc-m48t86.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/rtc/rtc-m48t86.c b/drivers/rtc/rtc-m48t86.c index 481c9525b1dd..d65727ac283a 100644 --- a/drivers/rtc/rtc-m48t86.c +++ b/drivers/rtc/rtc-m48t86.c @@ -15,6 +15,7 @@ #include #include #include +#include =20 #define M48T86_SEC 0x00 #define M48T86_SECALRM 0x01 @@ -269,9 +270,18 @@ static int m48t86_rtc_probe(struct platform_device *pd= ev) return 0; } =20 +#ifdef CONFIG_OF +static const struct of_device_id m48t86_rtc_of_ids[] =3D { + { .compatible =3D "dallas,rtc-m48t86" }, + { /* end of table */ }, +}; +MODULE_DEVICE_TABLE(of, m48t86_rtc_of_ids); +#endif + static struct platform_driver m48t86_rtc_platform_driver =3D { .driver =3D { .name =3D "rtc-m48t86", + .of_match_table =3D of_match_ptr(m48t86_rtc_of_ids), }, .probe =3D m48t86_rtc_probe, }; --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 984DBC7EE2C for ; Thu, 1 Jun 2023 05:47:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231658AbjFAFrH (ORCPT ); Thu, 1 Jun 2023 01:47:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231609AbjFAFqo (ORCPT ); Thu, 1 Jun 2023 01:46:44 -0400 Received: from forward103a.mail.yandex.net (forward103a.mail.yandex.net [178.154.239.86]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A7262195; Wed, 31 May 2023 22:46:20 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net [IPv6:2a02:6b8:c1f:5e51:0:640:23ee:0]) by forward103a.mail.yandex.net (Yandex) with ESMTP id 3723E46CCB; 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charset="utf-8" - get regs from device tree Signed-off-by: Nikita Shubin Reviewed-by: Linus Walleij --- Notes: v0 -> v1: =20 - dropped CONFIG_OF, of_match_ptr - dropped coma in id table - changed compatible from "dallas,rtc-m48t86" to "st,m48t86" drivers/rtc/rtc-m48t86.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/rtc/rtc-m48t86.c b/drivers/rtc/rtc-m48t86.c index 481c9525b1dd..b114796d4326 100644 --- a/drivers/rtc/rtc-m48t86.c +++ b/drivers/rtc/rtc-m48t86.c @@ -15,6 +15,7 @@ #include #include #include +#include =20 #define M48T86_SEC 0x00 #define M48T86_SECALRM 0x01 @@ -269,9 +270,16 @@ static int m48t86_rtc_probe(struct platform_device *pd= ev) return 0; } =20 +static const struct of_device_id m48t86_rtc_of_ids[] =3D { + { .compatible =3D "st,m48t86" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, m48t86_rtc_of_ids); + static struct platform_driver m48t86_rtc_platform_driver =3D { .driver =3D { .name =3D "rtc-m48t86", + .of_match_table =3D m48t86_rtc_of_ids, }, .probe =3D m48t86_rtc_probe, }; --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3624C7618E for ; Mon, 24 Apr 2023 09:51:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231593AbjDXJvr (ORCPT ); Mon, 24 Apr 2023 05:51:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49718 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231361AbjDXJvj (ORCPT ); Mon, 24 Apr 2023 05:51:39 -0400 X-Greylist: delayed 320 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Mon, 24 Apr 2023 02:51:33 PDT Received: from forward501b.mail.yandex.net (forward501b.mail.yandex.net [IPv6:2a02:6b8:c02:900:1:45:d181:d501]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A536A30ED; Mon, 24 Apr 2023 02:51:32 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net [IPv6:2a02:6b8:c12:261e:0:640:2e3d:0]) by forward501b.mail.yandex.net (Yandex) with ESMTP id EA3AB5EB34; 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(no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add DT binding for Technologic Systems TS-72xx watchdog. Signed-off-by: Nikita Shubin --- .../watchdog/technologic,ts72xx-wdt.yaml | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/technologic,= ts72xx-wdt.yaml diff --git a/Documentation/devicetree/bindings/watchdog/technologic,ts72xx-= wdt.yaml b/Documentation/devicetree/bindings/watchdog/technologic,ts72xx-wd= t.yaml new file mode 100644 index 000000000000..0e06dbaec85f --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/technologic,ts72xx-wdt.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/technologic,ts72xx-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Technologic Systems TS-72xx based SBCs watchdog bindings + +maintainers: + - Wim Van Sebroeck + - Guenter Roeck + +allOf: + - $ref: "watchdog.yaml#" + +properties: + compatible: + enum: + - technologic,ts7200-wdt + + reg: + maxItems: 2 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + watchdog0: watchdog@5a002000 { + compatible =3D "technologic,ts7200-wdt"; + reg =3D <0x23800000 0x01>, <0x23c00000 0x01>; + timeout-sec =3D <30>; + }; + +... + --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2801EC77B7A for ; Thu, 1 Jun 2023 05:47:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231628AbjFAFrl (ORCPT ); Thu, 1 Jun 2023 01:47:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53774 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231375AbjFAFqy (ORCPT ); Thu, 1 Jun 2023 01:46:54 -0400 Received: from forward100a.mail.yandex.net (forward100a.mail.yandex.net [178.154.239.83]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B35E710C4; Wed, 31 May 2023 22:46:24 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net [IPv6:2a02:6b8:c1f:5e51:0:640:23ee:0]) by forward100a.mail.yandex.net (Yandex) with ESMTP id 15877463C8; Thu, 1 Jun 2023 08:46:21 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id pjGDMhnDduQ0-singxOus; Thu, 01 Jun 2023 08:46:20 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1685598380; bh=rKLeo/d/8Wk8XKAwLVEqsT3NI7ElKFwC7e7Tg4clcm8=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=ckC3R7ZkEWFOO9/o9sMo2setllhfgcsZnGTp8OrocGoUBkZJd94PGDdmjzI3VS2Ox KxFNdtpylDHvWGl0mAX5IW0JQG6Hoh9TxmVUk5XbGVR9byBmECYMSmS+g7lzGUqjLv uZ/2BO0NXD0aERg9PVuHshMwoZmhmV9BkELe5oho= Authentication-Results: mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij , Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Nikita Shubin Cc: Michael Peters , Kris Bahnsen , linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 31/43] dt-bindings: wdt: Add ts72xx Date: Thu, 1 Jun 2023 08:45:36 +0300 Message-Id: <20230601054549.10843-13-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add DT binding for Technologic Systems TS-72xx watchdog. Signed-off-by: Nikita Shubin --- Notes: v0 -> v1: =20 - changed maintainers =20 Krzysztof Kozlowski: - renamed file - dropped quotes - added description for reg - dropped label - use fallback compatible and list all possible compatibles .../watchdog/technologic,ts7200-wdt.yaml | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/technologic,= ts7200-wdt.yaml diff --git a/Documentation/devicetree/bindings/watchdog/technologic,ts7200-= wdt.yaml b/Documentation/devicetree/bindings/watchdog/technologic,ts7200-wd= t.yaml new file mode 100644 index 000000000000..4f7f004ffdd3 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/technologic,ts7200-wdt.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/technologic,ts7200-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Technologic Systems TS-72xx based SBCs watchdog + +maintainers: + - Nikita Shubin + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + oneOf: + - const: technologic,ts7200-wdt + - items: + - enum: + - technologic,ts7300-wdt + - technologic,ts7260-wdt + - technologic,ts7250-wdt + - const: technologic,ts7200-wdt + + reg: + items: + - description: control register + - description: feed register + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + watchdog@23800000 { + compatible =3D "technologic,ts7200-wdt"; + reg =3D <0x23800000 0x01>, <0x23c00000 0x01>; + timeout-sec =3D <30>; + }; + +... + --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1444C7618E for ; Mon, 24 Apr 2023 09:57:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231520AbjDXJ5c (ORCPT ); Mon, 24 Apr 2023 05:57:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57120 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231133AbjDXJ51 (ORCPT ); Mon, 24 Apr 2023 05:57:27 -0400 Received: from forward502b.mail.yandex.net (forward502b.mail.yandex.net [IPv6:2a02:6b8:c02:900:1:45:d181:d502]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7CDB3196; Mon, 24 Apr 2023 02:57:26 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net [IPv6:2a02:6b8:c12:261e:0:640:2e3d:0]) by forward502b.mail.yandex.net (Yandex) with ESMTP id 920515EBE4; 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(no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" - get regs from device tree Signed-off-by: Nikita Shubin --- Notes: Arnd Bergmann: - wildcards ep93xx to something meaningful, i.e. ep9301 - drop wrappers drivers/watchdog/ts72xx_wdt.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/watchdog/ts72xx_wdt.c b/drivers/watchdog/ts72xx_wdt.c index bf918f5fa131..72bbb4db983e 100644 --- a/drivers/watchdog/ts72xx_wdt.c +++ b/drivers/watchdog/ts72xx_wdt.c @@ -13,6 +13,7 @@ * warranty of any kind, whether express or implied. */ =20 +#include #include #include #include @@ -162,10 +163,17 @@ static int ts72xx_wdt_probe(struct platform_device *p= dev) return 0; } =20 +static const struct of_device_id ts72xx_wdt_of_ids[] =3D { + { .compatible =3D "technologic,ts7200-wdt" }, + {}, +}; +MODULE_DEVICE_TABLE(of, ts72xx_wdt_of_ids); + static struct platform_driver ts72xx_wdt_driver =3D { .probe =3D ts72xx_wdt_probe, .driver =3D { .name =3D "ts72xx-wdt", + .of_match_table =3D ts72xx_wdt_of_ids, }, }; =20 --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C746CC77B7A for ; Thu, 1 Jun 2023 05:47:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231640AbjFAFro (ORCPT ); Thu, 1 Jun 2023 01:47:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53956 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231622AbjFAFqy (ORCPT ); Thu, 1 Jun 2023 01:46:54 -0400 Received: from forward100a.mail.yandex.net (forward100a.mail.yandex.net [178.154.239.83]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1BD4C10CA; Wed, 31 May 2023 22:46:24 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net [IPv6:2a02:6b8:c1f:5e51:0:640:23ee:0]) by forward100a.mail.yandex.net (Yandex) with ESMTP id A295346C98; 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charset="utf-8" - get regs from device tree Signed-off-by: Nikita Shubin --- Notes: v0 -> v1: =20 - dropped coma in id table drivers/watchdog/ts72xx_wdt.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/watchdog/ts72xx_wdt.c b/drivers/watchdog/ts72xx_wdt.c index bf918f5fa131..c3dbeffbb85d 100644 --- a/drivers/watchdog/ts72xx_wdt.c +++ b/drivers/watchdog/ts72xx_wdt.c @@ -13,6 +13,7 @@ * warranty of any kind, whether express or implied. */ =20 +#include #include #include #include @@ -162,10 +163,17 @@ static int ts72xx_wdt_probe(struct platform_device *p= dev) return 0; } =20 +static const struct of_device_id ts72xx_wdt_of_ids[] =3D { + { .compatible =3D "technologic,ts7200-wdt" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ts72xx_wdt_of_ids); + static struct platform_driver ts72xx_wdt_driver =3D { .probe =3D ts72xx_wdt_probe, .driver =3D { .name =3D "ts72xx-wdt", + .of_match_table =3D ts72xx_wdt_of_ids, }, }; =20 --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21F71C77B7E for ; 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a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1682328965; bh=C6LBzQtuPvxvqnaOXftP/JvtH1Yc+ydDMGhI/tFJ394=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=s+QToJQjYNoRrTvzrx/bGkiIodhjzt9ryaOtaq3pomjJ9zpDRY5b530Uq9S6ScElD uDbR/uVybBjmW5gErNzwWB+k9PnOnRnxBGqtILpqkhhOYrN83x8CQhAK7zGFQ/Q2tn An2G6QRjuzRb1BAR2f/mODb2JlLV87wTE123xNDg= Authentication-Results: mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 32/43] dt-bindings: gpio: Add DT bindings ep93xx gpio Date: Mon, 24 Apr 2023 15:34:48 +0300 Message-Id: <20230424123522.18302-33-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add YAML bindings for ep93xx SoC. Signed-off-by: Nikita Shubin --- .../devicetree/bindings/gpio/gpio-ep93xx.yaml | 161 ++++++++++++++++++ 1 file changed, 161 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-ep93xx.yaml diff --git a/Documentation/devicetree/bindings/gpio/gpio-ep93xx.yaml b/Docu= mentation/devicetree/bindings/gpio/gpio-ep93xx.yaml new file mode 100644 index 000000000000..4cf03c325d39 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-ep93xx.yaml @@ -0,0 +1,161 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/gpio-ep93xx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EP93xx GPIO controller + +maintainers: + - Linus Walleij + - Bartosz Golaszewski + - Nikita Shubin + +properties: + compatible: + const: cirrus,ep9301-gpio + + chip-label: + maxItems: 1 + description: human readable name. + + reg: + minItems: 2 + items: + - description: data register + - description: direction register + - description: interrupt registers base + + reg-names: + minItems: 2 + items: + - const: data + - const: dir + - const: intr + + gpio-controller: true + + gpio-ranges: true + + "#gpio-cells": + const: 2 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + interrupts: + items: + - const: 27 + + interrupts-extended: + minItems: 8 + maxItems: 8 + description: port F has dedicated irq line for each gpio line. + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + +additionalProperties: false + +examples: + - | + gpio0: gpio@80840000 { + compatible =3D "cirrus,ep9301-gpio"; + chip-label =3D "A"; + reg =3D <0x80840000 0x04>, + <0x80840010 0x04>, + <0x80840090 0x1c>; + reg-names =3D "data", "dir", "intr"; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + interrupt-parent =3D <&vic1>; + interrupts =3D <27>; + }; + + gpio1: gpio@80840004 { + compatible =3D "cirrus,ep9301-gpio"; + chip-label =3D "B"; + reg =3D <0x80840004 0x04>, + <0x80840014 0x04>, + <0x808400ac 0x1c>; + reg-names =3D "data", "dir", "intr"; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + interrupt-parent =3D <&vic1>; + interrupts =3D <27>; + }; + + gpio2: gpio@80840008 { + compatible =3D "cirrus,ep9301-gpio"; + chip-label =3D "C"; + reg =3D <0x80840008 0x04>, + <0x80840018 0x04>; + reg-names =3D "data", "dir"; + gpio-controller; + #gpio-cells =3D <2>; + }; + + gpio3: gpio@8084000c { + compatible =3D "cirrus,ep9301-gpio"; + chip-label =3D "D"; + reg =3D <0x8084000c 0x04>, + <0x8084001c 0x04>; + reg-names =3D "data", "dir"; + gpio-controller; + #gpio-cells =3D <2>; + }; + + gpio4: gpio@80840020 { + compatible =3D "cirrus,ep9301-gpio"; + chip-label =3D "E"; + reg =3D <0x80840020 0x04>, + <0x80840024 0x04>; + reg-names =3D "data", "dir"; + gpio-controller; + #gpio-cells =3D <2>; + }; + + gpio5: gpio@80840030 { + compatible =3D "cirrus,ep9301-gpio"; + chip-label =3D "F"; + reg =3D <0x80840030 0x04>, + <0x80840034 0x04>, + <0x8084004c 0x1c>; + reg-names =3D "data", "dir", "intr"; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D <&vic0 19>, <&vic0 20>, + <&vic0 21>, <&vic0 22>, + <&vic1 15>, <&vic1 16>, + <&vic1 17>, <&vic1 18>; + }; + + gpio6: gpio@80840038 { + compatible =3D "cirrus,ep9301-gpio"; + chip-label =3D "G"; + reg =3D <0x80840038 0x04>, + <0x8084003c 0x04>; + reg-names =3D "data", "dir"; + gpio-controller; + #gpio-cells =3D <2>; + }; + + gpio7: gpio@80840040 { + compatible =3D "cirrus,ep9301-gpio"; + chip-label =3D "H"; + reg =3D <0x80840040 0x04>, + <0x80840044 0x04>; + reg-names =3D "data", "dir"; + gpio-controller; + #gpio-cells =3D <2>; + }; + +... --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53C8AC77B76 for ; Mon, 24 Apr 2023 10:22:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231810AbjDXKWK (ORCPT ); Mon, 24 Apr 2023 06:22:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45506 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231738AbjDXKVT (ORCPT ); Mon, 24 Apr 2023 06:21:19 -0400 Received: from forward502b.mail.yandex.net (forward502b.mail.yandex.net [178.154.239.146]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8EAB2421D; Mon, 24 Apr 2023 03:20:51 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net [IPv6:2a02:6b8:c12:261e:0:640:2e3d:0]) by forward502b.mail.yandex.net (Yandex) with ESMTP id D17C55EBE5; Mon, 24 Apr 2023 12:36:05 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id JZBb1pbWwKo0-lLqFUc6B; Mon, 24 Apr 2023 12:36:05 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1682328965; bh=SSxwu9lthPZqqdCdgmUMEpmuMngqWwft96CtvBOzvls=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=IuJ/8EyOB6yEznRSkx495zMeYi3Zv5PWv9VH+KP2hzAdLbpnvPj54Wuy/8PEFl4DX W5suv33jnqg0C4wohVHpD0vAaziUKEpEoNSblbyTPCjjtw+LGKFizw80DJb4gpav9h R/WqKa+yioPnhnOU7RHbH0ZIWkja/2ofEOfxd/0g= Authentication-Results: mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , Linus Walleij , Bartosz Golaszewski , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 33/43] gpio: ep93xx: add DT support for gpio-ep93xx Date: Mon, 24 Apr 2023 15:34:49 +0300 Message-Id: <20230424123522.18302-34-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add match table. Signed-off-by: Nikita Shubin --- drivers/gpio/gpio-ep93xx.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index ca508c7c4f2f..4e3d01fab012 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -363,9 +363,15 @@ static int ep93xx_gpio_probe(struct platform_device *p= dev) return devm_gpiochip_add_data(&pdev->dev, gc, egc); } =20 +static const struct of_device_id ep93xx_gpio_match[] =3D { + { .compatible =3D "cirrus,ep9301-gpio" }, + { /* end of table */ }, +}; + static struct platform_driver ep93xx_gpio_driver =3D { .driver =3D { .name =3D "gpio-ep93xx", + .of_match_table =3D ep93xx_gpio_match, }, .probe =3D ep93xx_gpio_probe, }; --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CA1BC77B7E for ; Thu, 1 Jun 2023 05:47:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231726AbjFAFrw (ORCPT ); Thu, 1 Jun 2023 01:47:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54032 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231635AbjFAFq6 (ORCPT ); Thu, 1 Jun 2023 01:46:58 -0400 Received: from forward102a.mail.yandex.net (forward102a.mail.yandex.net [178.154.239.85]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E8BA10D7; Wed, 31 May 2023 22:46:26 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net [IPv6:2a02:6b8:c1f:5e51:0:640:23ee:0]) by forward102a.mail.yandex.net (Yandex) with ESMTP id 30B0746C97; Thu, 1 Jun 2023 08:46:23 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id pjGDMhnDduQ0-IRRIO8Qs; Thu, 01 Jun 2023 08:46:22 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1685598382; bh=y5M8VTUW3Md/hfd4UTZu0tzO/lLbxF8tmPlhgvZrA64=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=c3PRzP6xMt4i1Mcj+rmou0EgPPmFR1bcDTSBPXpHdSwpw3+jRImJuAWDO2i9BfriS 8jW/btdn/W7mOVSE3DIV9XNgxpQO05wXTcv3CM0RPvhdCJPVUx67kN8+ZP+B6Urf6m NzZgNvHv+x9IDbWph43D1mF2XsR+a6NhRrIgLv1E= Authentication-Results: mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Nikita Shubin Cc: Michael Peters , Kris Bahnsen , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 33/43] dt-bindings: gpio: Add Cirrus EP93xx Date: Thu, 1 Jun 2023 08:45:38 +0300 Message-Id: <20230601054549.10843-15-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add YAML bindings for ep93xx SoC gpio controller. Signed-off-by: Nikita Shubin --- .../devicetree/bindings/gpio/gpio-ep9301.yaml | 154 ++++++++++++++++++ 1 file changed, 154 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-ep9301.yaml diff --git a/Documentation/devicetree/bindings/gpio/gpio-ep9301.yaml b/Docu= mentation/devicetree/bindings/gpio/gpio-ep9301.yaml new file mode 100644 index 000000000000..daadfb4926c3 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-ep9301.yaml @@ -0,0 +1,154 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/gpio-ep9301.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EP93xx GPIO controller + +maintainers: + - Linus Walleij + - Bartosz Golaszewski + - Nikita Shubin + +properties: + compatible: + oneOf: + - const: cirrus,ep9301-gpio + - items: + - enum: + - cirrus,ep9302-gpio + - cirrus,ep9307-gpio + - cirrus,ep9312-gpio + - cirrus,ep9315-gpio + - const: cirrus,ep9301-gpio + + reg: + minItems: 2 + items: + - description: data register + - description: direction register + - description: interrupt registers base + + reg-names: + minItems: 2 + items: + - const: data + - const: dir + - const: intr + + gpio-controller: true + + gpio-ranges: true + + "#gpio-cells": + const: 2 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + interrupts: + oneOf: + - maxItems: 1 + - description: port F has dedicated irq line for each gpio line + maxItems: 8 + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + +additionalProperties: false + +examples: + - | + gpio@80840000 { + compatible =3D "cirrus,ep9301-gpio"; + reg =3D <0x80840000 0x04>, + <0x80840010 0x04>, + <0x80840090 0x1c>; + reg-names =3D "data", "dir", "intr"; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + interrupt-parent =3D <&vic1>; + interrupts =3D <27>; + }; + + gpio@80840004 { + compatible =3D "cirrus,ep9301-gpio"; + reg =3D <0x80840004 0x04>, + <0x80840014 0x04>, + <0x808400ac 0x1c>; + reg-names =3D "data", "dir", "intr"; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + interrupt-parent =3D <&vic1>; + interrupts =3D <27>; + }; + + gpio@80840008 { + compatible =3D "cirrus,ep9301-gpio"; + reg =3D <0x80840008 0x04>, + <0x80840018 0x04>; + reg-names =3D "data", "dir"; + gpio-controller; + #gpio-cells =3D <2>; + }; + + gpio@8084000c { + compatible =3D "cirrus,ep9301-gpio"; + reg =3D <0x8084000c 0x04>, + <0x8084001c 0x04>; + reg-names =3D "data", "dir"; + gpio-controller; + #gpio-cells =3D <2>; + }; + + gpio@80840020 { + compatible =3D "cirrus,ep9301-gpio"; + reg =3D <0x80840020 0x04>, + <0x80840024 0x04>; + reg-names =3D "data", "dir"; + gpio-controller; + #gpio-cells =3D <2>; + }; + + gpio@80840030 { + compatible =3D "cirrus,ep9301-gpio"; + reg =3D <0x80840030 0x04>, + <0x80840034 0x04>, + <0x8084004c 0x1c>; + reg-names =3D "data", "dir", "intr"; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D <&vic0 19>, <&vic0 20>, + <&vic0 21>, <&vic0 22>, + <&vic1 15>, <&vic1 16>, + <&vic1 17>, <&vic1 18>; + }; + + gpio@80840038 { + compatible =3D "cirrus,ep9301-gpio"; + reg =3D <0x80840038 0x04>, + <0x8084003c 0x04>; + reg-names =3D "data", "dir"; + gpio-controller; + #gpio-cells =3D <2>; + }; + + gpio@80840040 { + compatible =3D "cirrus,ep9301-gpio"; + reg =3D <0x80840040 0x04>, + <0x80840044 0x04>; + reg-names =3D "data", "dir"; + gpio-controller; + #gpio-cells =3D <2>; + }; + +... --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDD06C7618E for ; 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a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1682328966; bh=3iuf6Lu4e4rU6W7xqwd01nAFp6flexA2feuwpF6CHwI=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=D0cHGQmGLD1meQvV1cZnshNgsjk0GeBqIuVmUaYpiDazZt3eoih7cevkvmh+KlcBJ CS6McGhLwFUyTPHA0XbVl1y9xLSdfnQHb31VMeOi8frDz9L4cubjJRx5wGfPEgXTjG tFccZMiiDu4FgUm4aG7GwMQ4He4sFVdwYV1UIL4I= Authentication-Results: mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , Arnd Bergmann , Olof Johansson , soc@kernel.org, Rob Herring , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 34/43] ARM: dts: add device tree for ep93xx Soc Date: Mon, 24 Apr 2023 15:34:50 +0300 Message-Id: <20230424123522.18302-35-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds a divice for Cirrus ep93xx SoC amd ts7250 board that has been my testing target for ep93xx device support. Also inluded device tree for Liebherr BK3.1 board through it's not a complete support. Signed-off-by: Nikita Shubin Reviewed-by: Kris Bahnsen Tested-by: Michael Peters --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/ep93xx-bk3.dts | 96 ++++++ arch/arm/boot/dts/ep93xx-ts7250.dts | 113 ++++++++ arch/arm/boot/dts/ep93xx.dtsi | 433 ++++++++++++++++++++++++++++ 4 files changed, 643 insertions(+) create mode 100644 arch/arm/boot/dts/ep93xx-bk3.dts create mode 100644 arch/arm/boot/dts/ep93xx-ts7250.dts create mode 100644 arch/arm/boot/dts/ep93xx.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index efe4152e5846..e6f48deeabed 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1653,3 +1653,4 @@ dtb-$(CONFIG_ARCH_ASPEED) +=3D \ aspeed-bmc-vegman-n110.dtb \ aspeed-bmc-vegman-rx20.dtb \ aspeed-bmc-vegman-sx20.dtb +dtb-$(CONFIG_ARCH_EP93XX) +=3D ep93xx-ts7250.dtb diff --git a/arch/arm/boot/dts/ep93xx-bk3.dts b/arch/arm/boot/dts/ep93xx-bk= 3.dts new file mode 100644 index 000000000000..c477af54ab56 --- /dev/null +++ b/arch/arm/boot/dts/ep93xx-bk3.dts @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for Liebherr controller BK3.1 based on Cirrus EP9302 S= oC + */ +/dts-v1/; +#include "ep93xx.dtsi" + +/ { + model =3D "Liebherr controller BK3.1"; + compatible =3D "liebherr,bk3", "cirrus,ep93xx"; + + memory { + device_type =3D "memory"; + }; + + soc { + nand-parts@0 { + compatible =3D "technologic,ts7200-nand", "gen_nand"; + reg =3D <0x60000000 0x8000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "System"; + reg =3D <0x00000000 0x01e00000>; + read-only; + }; + + partition@20000 { + label =3D "Data"; + reg =3D <0x01e00000 0x05f20000>; + }; + + partition@7d20000 { + label =3D "RedBoot"; + reg =3D <0x07d20000 0x002e0000>; + read-only; + }; + }; + + syscon: syscon@80930000 { + pinctrl: pinctrl { + compatible =3D "cirrus,ep9301-pinctrl"; + }; + }; + + gpio1: gpio@80840004 { + /* PWM */ + gpio-ranges =3D <&pinctrl 6 163 1>; + }; + }; +}; + +&gpio1 { + /* PWM */ + gpio-ranges =3D <&pinctrl 6 163 1>; +}; + +&gpio4 { + gpio-ranges =3D <&pinctrl 0 97 2>; + status =3D "okay"; +}; + +&gpio6 { + gpio-ranges =3D <&pinctrl 0 87 2>; + status =3D "okay"; +}; + +&gpio7 { + gpio-ranges =3D <&pinctrl 2 199 4>; + status =3D "okay"; +}; + +&i2c { + status =3D "okay"; +}; + +&spi0: spi@808a0000 { + cs-gpios =3D <&gpio5 3 0>; + use_dma; + status =3D "okay"; +}; + +ð0 { + copy_addr; + phy_id =3D < 1 >; +}; + +&uart0 { + status =3D "okay"; +}; + +&uart1 { + status =3D "okay"; +}; + diff --git a/arch/arm/boot/dts/ep93xx-ts7250.dts b/arch/arm/boot/dts/ep93xx= -ts7250.dts new file mode 100644 index 000000000000..6562780333a3 --- /dev/null +++ b/arch/arm/boot/dts/ep93xx-ts7250.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for Technologic Systems ts7250 board based on Cirrus E= P9302 SoC + */ +/dts-v1/; +#include "ep93xx.dtsi" + +/ { + compatible =3D "technologic,ts7250", "cirrus,ep9301"; + model =3D "TS-7250 SBC"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + memory@0 { + device_type =3D "memory"; + /* should be set from ATAGS */ + reg =3D <0x00000000 0x02000000>, + <0x000530c0 0x01fdd000>; + }; + + soc { + nand-parts@0 { + compatible =3D "technologic,ts7200-nand", "gen_nand"; + reg =3D <0x60000000 0x8000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "TS-BOOTROM"; + reg =3D <0x00000000 0x00020000>; + read-only; + }; + + partition@20000 { + label =3D "Linux"; + reg =3D <0x00020000 0x07d00000>; + }; + + partition@7d20000 { + label =3D "RedBoot"; + reg =3D <0x07d20000 0x002e0000>; + read-only; + }; + }; + + syscon: syscon@80930000 { + pinctrl: pinctrl { + compatible =3D "cirrus,ep9301-pinctrl"; + }; + }; + + rtc1: rtc@10800000 { + compatible =3D "dallas,rtc-m48t86"; + reg =3D <0x10800000 0x1>, + <0x11700000 0x1>; + }; + + watchdog1: watchdog@23800000 { + compatible =3D "technologic,ts7200-wdt"; + reg =3D <0x23800000 0x01>, + <0x23c00000 0x01>; + timeout-sec =3D <30>; + }; + }; +}; + +&gpio1 { + /* PWM */ + gpio-ranges =3D <&pinctrl 6 163 1>; +}; + +&gpio4 { + gpio-ranges =3D <&pinctrl 0 97 2>; + status =3D "okay"; +}; + +&gpio6 { + gpio-ranges =3D <&pinctrl 0 87 2>; + status =3D "okay"; +}; + +&gpio7 { + gpio-ranges =3D <&pinctrl 2 199 4>; + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; +}; + +&spi0 { + cs-gpios =3D <&gpio5 2 0>; + status =3D "okay"; + + tmp122_spi: tmp122@0 { + compatible =3D "ti,tmp122"; + reg =3D <0>; + spi-max-frequency =3D <2000000>; + }; +}; + +ð0 { + copy_addr; + phy_id =3D < 1 >; +}; + +&uart0 { + status =3D "okay"; +}; + +&uart1 { + status =3D "okay"; +}; diff --git a/arch/arm/boot/dts/ep93xx.dtsi b/arch/arm/boot/dts/ep93xx.dtsi new file mode 100644 index 000000000000..67ecfde539af --- /dev/null +++ b/arch/arm/boot/dts/ep93xx.dtsi @@ -0,0 +1,433 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for Cirrus Logic systems EP93XX SoC + */ +#include +#include +#include +#include +/ { + soc { + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + compatible =3D "simple-bus"; + + syscon: syscon@80930000 { + compatible =3D "cirrus,ep9301-syscon", + "syscon", "simple-mfd"; + reg =3D <0x80930000 0x1000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + + ep9301-reboot { + compatible =3D "cirrus,ep9301-reboot"; + }; + + pinctrl: pinctrl { + regmap =3D <&syscon>; + + spi_default_pins: pinctrl-spi { + function =3D "spi"; + groups =3D "ssp"; + }; + + ac97_default_pins: pinctrl-ac97 { + function =3D "ac97"; + groups =3D "ac97"; + }; + + i2s_on_ssp_pins: pinctrl-i2sonssp { + function =3D "i2s"; + groups =3D "i2s_on_ssp"; + }; + + i2s_on_ac97_pins: pinctrl-i2sonac97 { + function =3D "i2s"; + groups =3D "i2s_on_ac97"; + }; + + gpio1_default_pins: pinctrl-gpio1 { + function =3D "gpio1"; + groups =3D "gpio1agrp"; + }; + + pwm1_default_pins: pinctrl-pwm1 { + function =3D "pwm"; + groups =3D "pwm1"; + }; + + gpio2_default_pins: pinctrl-gpio2 { + function =3D "gpio2"; + groups =3D "gpio2agrp"; + }; + + gpio3_default_pins: pinctrl-gpio3 { + function =3D "gpio3"; + groups =3D "gpio3agrp"; + }; + + keypad_default_pins: pinctrl-keypad { + function =3D "keypad"; + groups =3D "keypadgrp"; + }; + + gpio4_default_pins: pinctrl-gpio4 { + function =3D "gpio4"; + groups =3D "gpio4agrp"; + }; + + gpio6_default_pins: pinctrl-gpio6 { + function =3D "gpio6"; + groups =3D "gpio6agrp"; + }; + + gpio7_default_pins: pinctrl-gpio7 { + function =3D "gpio7"; + groups =3D "gpio7agrp"; + }; + + ide_default_pins: pinctrl-ide { + function =3D "pata"; + groups =3D "idegrp"; + }; + + lcd_on_dram0_pins: pinctrl-rasteronsdram0 { + function =3D "lcd"; + groups =3D "rasteronsdram0grp"; + }; + + lcd_on_dram3_pins: pinctrl-rasteronsdram3 { + function =3D "lcd"; + groups =3D "rasteronsdram3grp"; + }; + }; + }; + + vic0: interrupt-controller@800b0000 { + compatible =3D "arm,pl192-vic"; + interrupt-controller; + reg =3D <0x800b0000 0x1000>; + #interrupt-cells =3D <1>; + valid-mask =3D <0x7ffffffc>; + valid-wakeup-mask =3D <0x0>; + }; + + vic1: interrupt-controller@800c0000 { + compatible =3D "arm,pl192-vic"; + interrupt-controller; + reg =3D <0x800c0000 0x1000>; + #interrupt-cells =3D <1>; + valid-mask =3D <0x1fffffff>; + valid-wakeup-mask =3D <0x0>; + }; + + timer: timer@80810000 { + compatible =3D "cirrus,ep9301-timer"; + reg =3D <0x80810000 0x100>; + interrupt-parent =3D <&vic1>; + interrupts =3D <19>; + }; + + dma0: dma-controller@80000000 { + compatible =3D "cirrus,ep9301-dma-m2p"; + reg =3D <0x80000000 0x0040>, + <0x80000040 0x0040>, + <0x80000080 0x0040>, + <0x800000c0 0x0040>, + <0x80000240 0x0040>, + <0x80000200 0x0040>, + <0x800002c0 0x0040>, + <0x80000280 0x0040>, + <0x80000340 0x0040>, + <0x80000300 0x0040>; + clocks =3D <&syscon EP93XX_CLK_M2P0>, + <&syscon EP93XX_CLK_M2P1>, + <&syscon EP93XX_CLK_M2P2>, + <&syscon EP93XX_CLK_M2P3>, + <&syscon EP93XX_CLK_M2P4>, + <&syscon EP93XX_CLK_M2P5>, + <&syscon EP93XX_CLK_M2P6>, + <&syscon EP93XX_CLK_M2P7>, + <&syscon EP93XX_CLK_M2P8>, + <&syscon EP93XX_CLK_M2P9>; + clock-names =3D "m2p0", "m2p1", + "m2p2", "m2p3", + "m2p4", "m2p5", + "m2p6", "m2p7", + "m2p8", "m2p9"; + dma-channels =3D <10>; + interrupt-parent =3D <&vic0>; + interrupts =3D <7>, <8>, <9>, <10>, <11>, + <12>, <13>, <14>, <15>, <16>; + }; + + dma1: dma-controller@80000100 { + compatible =3D "cirrus,ep9301-dma-m2m"; + reg =3D <0x80000100 0x0040>, + <0x80000140 0x0040>; + clocks =3D <&syscon EP93XX_CLK_M2M0>, + <&syscon EP93XX_CLK_M2M1>; + clock-names =3D "m2m0", "m2m1"; + dma-channels =3D <2>; + interrupt-parent =3D <&vic0>; + interrupts =3D <17>, <18>; + }; + + gpio0: gpio@80840000 { + compatible =3D "cirrus,ep9301-gpio"; + chip-label =3D "A"; + reg =3D <0x80840000 0x04>, + <0x80840010 0x04>, + <0x80840090 0x1c>; + reg-names =3D "data", "dir", "intr"; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + interrupt-parent =3D <&vic1>; + interrupts =3D <27>; + }; + + gpio1: gpio@80840004 { + compatible =3D "cirrus,ep9301-gpio"; + chip-label =3D "B"; + reg =3D <0x80840004 0x04>, + <0x80840014 0x04>, + <0x808400ac 0x1c>; + reg-names =3D "data", "dir", "intr"; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + interrupt-parent =3D <&vic1>; + interrupts =3D <27>; + }; + + gpio2: gpio@80840008 { + compatible =3D "cirrus,ep9301-gpio"; + chip-label =3D "C"; + reg =3D <0x80840008 0x04>, + <0x80840018 0x04>; + reg-names =3D "data", "dir"; + gpio-controller; + #gpio-cells =3D <2>; + status =3D "disabled"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gpio2_default_pins>; + }; + + gpio3: gpio@8084000c { + compatible =3D "cirrus,ep9301-gpio"; + chip-label =3D "D"; + reg =3D <0x8084000c 0x04>, + <0x8084001c 0x04>; + reg-names =3D "data", "dir"; + gpio-controller; + #gpio-cells =3D <2>; + status =3D "disabled"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gpio3_default_pins>; + }; + + gpio4: gpio@80840020 { + compatible =3D "cirrus,ep9301-gpio"; + chip-label =3D "E"; + reg =3D <0x80840020 0x04>, + <0x80840024 0x04>; + reg-names =3D "data", "dir"; + gpio-controller; + #gpio-cells =3D <2>; + status =3D "disabled"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gpio4_default_pins>; + }; + + gpio5: gpio@80840030 { + compatible =3D "cirrus,ep9301-gpio"; + chip-label =3D "F"; + reg =3D <0x80840030 0x04>, + <0x80840034 0x04>, + <0x8084004c 0x1c>; + reg-names =3D "data", "dir", "intr"; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D <&vic0 19>, <&vic0 20>, + <&vic0 21>, <&vic0 22>, + <&vic1 15>, <&vic1 16>, + <&vic1 17>, <&vic1 18>; + }; + + gpio6: gpio@80840038 { + compatible =3D "cirrus,ep9301-gpio"; + chip-label =3D "G"; + reg =3D <0x80840038 0x04>, + <0x8084003c 0x04>; + reg-names =3D "data", "dir"; + gpio-controller; + #gpio-cells =3D <2>; + status =3D "disabled"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gpio6_default_pins>; + }; + + gpio7: gpio@80840040 { + compatible =3D "cirrus,ep9301-gpio"; + chip-label =3D "H"; + reg =3D <0x80840040 0x04>, + <0x80840044 0x04>; + reg-names =3D "data", "dir"; + gpio-controller; + #gpio-cells =3D <2>; + status =3D "disabled"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gpio7_default_pins>; + }; + + ide: ide@800a0000 { + compatible =3D "cirrus,ep9312-pata"; + reg =3D <0x800a0000 0x38>; + interrupt-parent =3D <&vic1>; + interrupts =3D <8>; + status =3D "disabled"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ide_default_pins>; + }; + + uart0: uart@808c0000 { + compatible =3D "arm,primecell"; + reg =3D <0x808c0000 0x1000>; + arm,primecell-periphid =3D <0x00041010>; + clocks =3D <&syscon EP93XX_CLK_UART1>, <&syscon EP93XX_CLK_UART>; + clock-names =3D "apb:uart1", "apb_pclk"; + interrupt-parent =3D <&vic1>; + interrupts =3D <20>; + status =3D "disabled"; + }; + + uart1: uart@808d0000 { + compatible =3D "arm,primecell"; + reg =3D <0x808d0000 0x1000>; + arm,primecell-periphid =3D <0x00041010>; + clocks =3D <&syscon EP93XX_CLK_UART2>, <&syscon EP93XX_CLK_UART>; + clock-names =3D "apb:uart2", "apb_pclk"; + interrupt-parent =3D <&vic1>; + interrupts =3D <22>; + status =3D "disabled"; + }; + + uart2: uart@808b0000 { + compatible =3D "arm,primecell"; + reg =3D <0x808b0000 0x1000>; + arm,primecell-periphid =3D <0x00041010>; + clocks =3D <&syscon EP93XX_CLK_UART3>, <&syscon EP93XX_CLK_UART>; + clock-names =3D "apb:uart3", "apb_pclk"; + interrupt-parent =3D <&vic1>; + interrupts =3D <23>; + status =3D "disabled"; + }; + + eth0: eth@80010000 { + compatible =3D "cirrus,ep9301-eth"; + reg =3D <0x80010000 0x10000>; + interrupt-parent =3D <&vic1>; + interrupts =3D <7>; + }; + + rtc0: rtc@80920000 { + compatible =3D "cirrus,ep9301-rtc"; + reg =3D <0x80920000 0x100>; + }; + + spi0: spi@808a0000 { + compatible =3D "cirrus,ep9301-spi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x808a0000 0x18>; + interrupt-parent =3D <&vic1>; + interrupts =3D <21>; + clocks =3D <&syscon EP93XX_CLK_SPI>; + clock-names =3D "ep93xx-spi.0"; + cs-gpios =3D <&gpio5 2 0>; + use_dma; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi_default_pins>; + status =3D "disabled"; + }; + + watchdog0: watchdog@80940000 { + compatible =3D "cirrus,ep9301-wdt"; + reg =3D <0x80940000 0x08>; + }; + + pwm0: pwm@80910000 { + compatible =3D "cirrus,ep9301-pwm"; + reg =3D <0x80910000 0x10>; + clocks =3D <&syscon EP93XX_CLK_PWM>; + clock-names =3D "pwm_clk"; + status =3D "disabled"; + }; + + pwm1: pwm@80910020 { + compatible =3D "cirrus,ep9301-pwm"; + reg =3D <0x80910020 0x10>; + clocks =3D <&syscon EP93XX_CLK_PWM>; + clock-names =3D "pwm_clk"; + status =3D "disabled"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm1_default_pins>; + }; + + keypad: keypad@800f0000 { + compatible =3D "cirrus,ep9301-keypad"; + reg =3D <0x800f0000 0x0c>; + interrupt-parent =3D <&vic0>; + interrupts =3D <29>; + clocks =3D <&syscon EP93XX_CLK_KEYPAD>; + clock-names =3D "ep93xx-keypad"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&keypad_default_pins>; + linux,keymap =3D + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + + i2c0: i2c0 { + compatible =3D "i2c-gpio"; + sda-gpios =3D <&gpio6 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios =3D <&gpio6 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + leds { + compatible =3D "gpio-leds"; + led0 { + label =3D "grled"; + gpios =3D <&gpio4 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + function =3D LED_FUNCTION_HEARTBEAT; + }; + + led1 { + label =3D "rdled"; + gpios =3D <&gpio4 1 GPIO_ACTIVE_HIGH>; + function =3D LED_FUNCTION_FAULT; + }; + }; +}; --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC0EFC77B7A for ; Thu, 1 Jun 2023 05:47:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231720AbjFAFrs (ORCPT ); Thu, 1 Jun 2023 01:47:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54028 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231634AbjFAFq6 (ORCPT ); Thu, 1 Jun 2023 01:46:58 -0400 Received: from forward100a.mail.yandex.net (forward100a.mail.yandex.net [178.154.239.83]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 92B3A10DD; Wed, 31 May 2023 22:46:27 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net [IPv6:2a02:6b8:c1f:5e51:0:640:23ee:0]) by forward100a.mail.yandex.net (Yandex) with ESMTP id B2EE546CDA; Thu, 1 Jun 2023 08:46:23 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id pjGDMhnDduQ0-zieECyhD; Thu, 01 Jun 2023 08:46:23 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1685598383; bh=A2FiCkys0aL7RsfnhMzn1bmYZGGoisuSld30oU2VX3Y=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=EGnOrp8PGQbb0MIsNhPKsLwLUhMbmVl3+0qqeLSb8CnN70PT7cedgH9vXG3cUAy5S ywUAmMZmEPQRyKd/YdocZXnzEhbhpxWbex5FH1v66MQRNg5Gt43OgJhnios1RHqtDU EgOEazSLyLprVQ4MLtjcEKXoR34rnUWr85ExNwTk= Authentication-Results: mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij , Bartosz Golaszewski Cc: Nikita Shubin , Michael Peters , Kris Bahnsen , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 34/43] gpio: ep93xx: add DT support for gpio-ep93xx Date: Thu, 1 Jun 2023 08:45:39 +0300 Message-Id: <20230601054549.10843-16-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add match table. Signed-off-by: Nikita Shubin Reviewed-by: Andy Shevchenko Reviewed-by: Linus Walleij --- Notes: v0 -> v1: =20 - dropped coma in id table drivers/gpio/gpio-ep93xx.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index ca508c7c4f2f..5e328e4411cc 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -363,9 +363,15 @@ static int ep93xx_gpio_probe(struct platform_device *p= dev) return devm_gpiochip_add_data(&pdev->dev, gc, egc); } =20 +static const struct of_device_id ep93xx_gpio_match[] =3D { + { .compatible =3D "cirrus,ep9301-gpio" }, + { /* sentinel */ } +}; + static struct platform_driver ep93xx_gpio_driver =3D { .driver =3D { .name =3D "gpio-ep93xx", + .of_match_table =3D ep93xx_gpio_match, }, .probe =3D ep93xx_gpio_probe, }; --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0AEA4C7EE21 for ; Mon, 24 Apr 2023 09:51:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231546AbjDXJvm (ORCPT ); Mon, 24 Apr 2023 05:51:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49700 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231156AbjDXJvj (ORCPT ); Mon, 24 Apr 2023 05:51:39 -0400 Received: from forward501b.mail.yandex.net (forward501b.mail.yandex.net [178.154.239.145]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A562B30F4 for ; Mon, 24 Apr 2023 02:51:32 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net [IPv6:2a02:6b8:c12:261e:0:640:2e3d:0]) by forward501b.mail.yandex.net (Yandex) with ESMTP id E94C85EB39; Mon, 24 Apr 2023 12:36:08 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id JZBb1pbWwKo0-7EvCIZZi; Mon, 24 Apr 2023 12:36:08 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1682328968; bh=K0s3KX6GF6McSsZMczUuy8UP6UIYgxJXDX0bg9N6kp0=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=dupjRkbZ0vNSlMnwgp9Div0rlFnF/JtZmoUZp22nuI0n/s1QpK9kUuJsnB+7Nl1pS izTx810GWSRVg2aUJXiKnXr8GGeWXrx/pZv36sxy2VRBiiCwW90ZdjTkyExsexXOvZ mNA0wUpaI3r5I3/zcjWVQvQ/pqlA8kjDO/NowDfM= Authentication-Results: mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , Russell King , Hartley Sweeten , Arnd Bergmann , "Russell King (Oracle)" , Nick Desaulniers , Nathan Chancellor , Masahiro Yamada , Nick Hawkins , Nicolas Saenz Julienne , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 35/43] ARM: ep93xx: DT for the Cirrus ep93xx SoC platforms Date: Mon, 24 Apr 2023 15:34:51 +0300 Message-Id: <20230424123522.18302-36-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds compulsory device tree support to the Cirrus ep93xx ARMv4 platform. - We select PINCTRL_EP93xx - We select COMMON_CLK_EP93XX, as clock driver moved out of platform code - We select ARCH_HAS_RESET_CONTROLLER And also we need ARM_ATAG_DTB_COMPAT to update device tree with information about memory passed from bootloader. We have to leave all MACH options as they are used for board checking before decomp, to turn off watchdog and ethernet DMA. Signed-off-by: Nikita Shubin --- Notes: rfc->v0 - fixed typo - removed board-dt.c completely =20 Alexander Sverdlin: - platfrom -> platform arch/arm/Makefile | 1 - arch/arm/mach-ep93xx/Kconfig | 20 ++++++++++---------- arch/arm/mach-ep93xx/Makefile | 11 ----------- 3 files changed, 10 insertions(+), 22 deletions(-) delete mode 100644 arch/arm/mach-ep93xx/Makefile diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 485a439e22ca..8ad844ba777e 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -179,7 +179,6 @@ machine-$(CONFIG_ARCH_CLPS711X) +=3D clps711x machine-$(CONFIG_ARCH_DAVINCI) +=3D davinci machine-$(CONFIG_ARCH_DIGICOLOR) +=3D digicolor machine-$(CONFIG_ARCH_DOVE) +=3D dove -machine-$(CONFIG_ARCH_EP93XX) +=3D ep93xx machine-$(CONFIG_ARCH_EXYNOS) +=3D exynos machine-$(CONFIG_ARCH_FOOTBRIDGE) +=3D footbridge machine-$(CONFIG_ARCH_GEMINI) +=3D gemini diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig index 703f3d232a60..812b71dcf60e 100644 --- a/arch/arm/mach-ep93xx/Kconfig +++ b/arch/arm/mach-ep93xx/Kconfig @@ -3,27 +3,27 @@ menuconfig ARCH_EP93XX bool "EP93xx-based" depends on ATAGS depends on ARCH_MULTI_V4T + # CONFIG_ARCH_MULTI_V7 is not set depends on CPU_LITTLE_ENDIAN + select ARCH_HAS_RESET_CONTROLLER select ARCH_SPARSEMEM_ENABLE select ARM_AMBA select ARM_VIC + select ARM_APPENDED_DTB # Old Redboot bootloaders deployed + select ARM_ATAG_DTB_COMPAT # we need this to update dt memory node + select COMMON_CLK_EP93XX + select EP93XX_TIMER select CLKSRC_MMIO select CPU_ARM920T select GPIOLIB + select PINCTRL + select PINCTRL_EP93XX help This enables support for the Cirrus EP93xx series of CPUs. =20 if ARCH_EP93XX =20 -menu "Cirrus EP93xx Implementation Options" - -config EP93XX_SOC_COMMON - bool - default y - select SOC_BUS - select LEDS_GPIO_REGISTER - -comment "EP93xx Platforms" +# menu "EP93xx Platforms" =20 config MACH_BK3 bool "Support Liebherr BK3.1" @@ -103,6 +103,6 @@ config MACH_VISION_EP9307 Say 'Y' here if you want your kernel to support the Vision Engraving Systems EP9307 SoM. =20 -endmenu +# endmenu =20 endif diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile deleted file mode 100644 index 62e37403df14..000000000000 --- a/arch/arm/mach-ep93xx/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Makefile for the linux kernel. -# -obj-y :=3D core.o clock.o timer-ep93xx.o - -obj-$(CONFIG_EP93XX_DMA) +=3D dma.o - -obj-$(CONFIG_MACH_EDB93XX) +=3D edb93xx.o -obj-$(CONFIG_MACH_TS72XX) +=3D ts72xx.o -obj-$(CONFIG_MACH_VISION_EP9307)+=3D vision_ep9307.o --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61A41C77B7A for ; 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a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1685598385; bh=+Af/E/LQ4oF+374jObA9aIKb9X64urspTEK5lWR7h1Q=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=ebH1jb+PzJ6epde43rG4/iUbUJlTlgyTodVv4PhvFXzGIRYCCEUUYTyYUcx3PPHdn 3rGunkhYoX/zkvSljZenf0bE7x+cjY2XqrTygs5fJobQT/uPa9OU3OpXEpJHpoMAKz 8N32TfudlT54A0V4YVTbbzaEsfjxabnymsU81sfs= Authentication-Results: mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij , Olof Johansson , soc@kernel.org, Rob Herring , Krzysztof Kozlowski Cc: Nikita Shubin , Michael Peters , Kris Bahnsen , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 35/43] ARM: dts: add device tree for ep93xx Soc Date: Thu, 1 Jun 2023 08:45:40 +0300 Message-Id: <20230601054549.10843-17-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds a divice for Cirrus ep93xx SoC amd ts7250 board that has been my testing target for ep93xx device support. Also inluded device tree for Liebherr BK3.1 board through it's not a complete support. Signed-off-by: Nikita Shubin --- Notes: v0 -> v1: =20 - add empty chosen node - s/dallas,rtc-m48t86/st,m48t86/ - changed phy_id to phy-handle - dropped gpio chip-label's - s/eth@80010000/ethernet@80010000 - s/use_dma/ep9301,use-dma - added i2s to bk3 arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/ep93xx-bk3.dts | 119 +++++++ arch/arm/boot/dts/ep93xx-ts7250.dts | 132 ++++++++ arch/arm/boot/dts/ep93xx.dtsi | 466 ++++++++++++++++++++++++++++ 4 files changed, 718 insertions(+) create mode 100644 arch/arm/boot/dts/ep93xx-bk3.dts create mode 100644 arch/arm/boot/dts/ep93xx-ts7250.dts create mode 100644 arch/arm/boot/dts/ep93xx.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 59829fc90315..a68f868fffe7 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1670,3 +1670,4 @@ dtb-$(CONFIG_ARCH_ASPEED) +=3D \ aspeed-bmc-vegman-n110.dtb \ aspeed-bmc-vegman-rx20.dtb \ aspeed-bmc-vegman-sx20.dtb +dtb-$(CONFIG_ARCH_EP93XX) +=3D ep93xx-ts7250.dtb diff --git a/arch/arm/boot/dts/ep93xx-bk3.dts b/arch/arm/boot/dts/ep93xx-bk= 3.dts new file mode 100644 index 000000000000..215587c498e6 --- /dev/null +++ b/arch/arm/boot/dts/ep93xx-bk3.dts @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for Liebherr controller BK3.1 based on Cirrus EP9302 S= oC + */ +/dts-v1/; +#include "ep93xx.dtsi" + +/ { + model =3D "Liebherr controller BK3.1"; + compatible =3D "liebherr,bk3", "cirrus,ep9301"; + + chosen { + }; + + memory { + device_type =3D "memory"; + }; + + soc { + nand-controller@60000000 { + compatible =3D "technologic,ts7200-nand"; + reg =3D <0x60000000 0x8000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "System"; + reg =3D <0x00000000 0x01e00000>; + read-only; + }; + + partition@1e00000 { + label =3D "Data"; + reg =3D <0x01e00000 0x05f20000>; + }; + + partition@7d20000 { + label =3D "RedBoot"; + reg =3D <0x07d20000 0x002e0000>; + read-only; + }; + }; + }; + + syscon: syscon@80930000 { + pinctrl: pinctrl { + compatible =3D "cirrus,ep9301-pinctrl"; + }; + }; + + gpio1: gpio@80840004 { + /* PWM */ + gpio-ranges =3D <&pinctrl 6 163 1>; + }; + }; +}; + +&gpio1 { + /* PWM */ + gpio-ranges =3D <&pinctrl 6 163 1>; +}; + +&gpio4 { + gpio-ranges =3D <&pinctrl 0 97 2>; + status =3D "okay"; +}; + +&gpio6 { + gpio-ranges =3D <&pinctrl 0 87 2>; + status =3D "okay"; +}; + +&gpio7 { + gpio-ranges =3D <&pinctrl 2 199 4>; + status =3D "okay"; +}; + +&i2c { + status =3D "okay"; +}; + +&spi0: spi@808a0000 { + cs-gpios =3D <&gpio5 3 0>; + status =3D "okay"; +}; + +ð0 { + phy-handle =3D <&phy0>; +}; + +&mdio0 { + phy0: ethernet-phy@1 { + reg =3D <1>; + device_type =3D "ethernet-phy"; + }; +}; + +&uart0 { + status =3D "okay"; +}; + +&uart1 { + status =3D "okay"; +}; + +&usb { + status =3D "okay"; +}; + +&i2s { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2s_on_ac97_pins>; + /delete-property/ status; +}; diff --git a/arch/arm/boot/dts/ep93xx-ts7250.dts b/arch/arm/boot/dts/ep93xx= -ts7250.dts new file mode 100644 index 000000000000..40290e3cb9b3 --- /dev/null +++ b/arch/arm/boot/dts/ep93xx-ts7250.dts @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for Technologic Systems ts7250 board based on Cirrus E= P9302 SoC + */ +/dts-v1/; +#include "ep93xx.dtsi" + +/ { + compatible =3D "technologic,ts7250", "cirrus,ep9301"; + model =3D "TS-7250 SBC"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + chosen { + }; + + memory@0 { + device_type =3D "memory"; + /* should be set from ATAGS */ + reg =3D <0x00000000 0x02000000>, + <0x000530c0 0x01fdd000>; + }; + + soc { + nand-controller@60000000 { + compatible =3D "technologic,ts7200-nand"; + reg =3D <0x60000000 0x8000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "TS-BOOTROM"; + reg =3D <0x00000000 0x00020000>; + read-only; + }; + + partition@20000 { + label =3D "Linux"; + reg =3D <0x00020000 0x07d00000>; + }; + + partition@7d20000 { + label =3D "RedBoot"; + reg =3D <0x07d20000 0x002e0000>; + read-only; + }; + }; + }; + + syscon: syscon@80930000 { + pinctrl: pinctrl { + compatible =3D "cirrus,ep9301-pinctrl"; + }; + }; + + rtc1: rtc@10800000 { + compatible =3D "st,m48t86"; + reg =3D <0x10800000 0x1>, + <0x11700000 0x1>; + }; + + watchdog1: watchdog@23800000 { + compatible =3D "technologic,ts7200-wdt"; + reg =3D <0x23800000 0x01>, + <0x23c00000 0x01>; + timeout-sec =3D <30>; + }; + }; +}; + +&gpio1 { + /* PWM */ + gpio-ranges =3D <&pinctrl 6 163 1>; +}; + +&gpio4 { + gpio-ranges =3D <&pinctrl 0 97 2>; + status =3D "okay"; +}; + +&gpio6 { + gpio-ranges =3D <&pinctrl 0 87 2>; + status =3D "okay"; +}; + +&gpio7 { + gpio-ranges =3D <&pinctrl 2 199 4>; + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; +}; + +&spi0 { + cs-gpios =3D <&gpio5 2 0>; + status =3D "okay"; + + tmp122_spi: tmp122@0 { + compatible =3D "ti,tmp122"; + reg =3D <0>; + spi-max-frequency =3D <2000000>; + }; +}; + +ð0 { + phy-handle =3D <&phy0>; +}; + +&mdio0 { + phy0: ethernet-phy@1 { + reg =3D <1>; + device_type =3D "ethernet-phy"; + }; +}; + +&uart0 { + status =3D "okay"; +}; + +&uart1 { + status =3D "okay"; +}; + +&usb0 { + status =3D "okay"; +}; diff --git a/arch/arm/boot/dts/ep93xx.dtsi b/arch/arm/boot/dts/ep93xx.dtsi new file mode 100644 index 000000000000..6da556ceaf04 --- /dev/null +++ b/arch/arm/boot/dts/ep93xx.dtsi @@ -0,0 +1,466 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for Cirrus Logic systems EP93XX SoC + */ +#include +#include +#include +#include +/ { + soc { + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + compatible =3D "simple-bus"; + + syscon: syscon@80930000 { + compatible =3D "cirrus,ep9301-syscon", + "syscon", "simple-mfd"; + reg =3D <0x80930000 0x1000>; + + ep9301-reboot { + compatible =3D "cirrus,ep9301-reboot"; + }; + + eclk: clock-controller { + #clock-cells =3D <1>; + compatible =3D "cirrus,ep9301-clk"; + status =3D "okay"; + clocks =3D <&xtali>; + }; + + pinctrl: pinctrl { + spi_default_pins: pins-spi { + function =3D "spi"; + groups =3D "ssp"; + }; + + ac97_default_pins: pins-ac97 { + function =3D "ac97"; + groups =3D "ac97"; + }; + + i2s_on_ssp_pins: pins-i2sonssp { + function =3D "i2s"; + groups =3D "i2s_on_ssp"; + }; + + i2s_on_ac97_pins: pins-i2sonac97 { + function =3D "i2s"; + groups =3D "i2s_on_ac97"; + }; + + gpio1_default_pins: pins-gpio1 { + function =3D "gpio"; + groups =3D "gpio1agrp"; + }; + + pwm1_default_pins: pins-pwm1 { + function =3D "pwm"; + groups =3D "pwm1"; + }; + + gpio2_default_pins: pins-gpio2 { + function =3D "gpio"; + groups =3D "gpio2agrp"; + }; + + gpio3_default_pins: pins-gpio3 { + function =3D "gpio"; + groups =3D "gpio3agrp"; + }; + + keypad_default_pins: pins-keypad { + function =3D "keypad"; + groups =3D "keypadgrp"; + }; + + gpio4_default_pins: pins-gpio4 { + function =3D "gpio"; + groups =3D "gpio4agrp"; + }; + + gpio6_default_pins: pins-gpio6 { + function =3D "gpio"; + groups =3D "gpio6agrp"; + }; + + gpio7_default_pins: pins-gpio7 { + function =3D "gpio"; + groups =3D "gpio7agrp"; + }; + + ide_default_pins: pins-ide { + function =3D "pata"; + groups =3D "idegrp"; + }; + + lcd_on_dram0_pins: pins-rasteronsdram0 { + function =3D "lcd"; + groups =3D "rasteronsdram0grp"; + }; + + lcd_on_dram3_pins: pins-rasteronsdram3 { + function =3D "lcd"; + groups =3D "rasteronsdram3grp"; + }; + }; + }; + + vic0: interrupt-controller@800b0000 { + compatible =3D "arm,pl192-vic"; + interrupt-controller; + reg =3D <0x800b0000 0x1000>; + #interrupt-cells =3D <1>; + valid-mask =3D <0x7ffffffc>; + valid-wakeup-mask =3D <0x0>; + }; + + vic1: interrupt-controller@800c0000 { + compatible =3D "arm,pl192-vic"; + interrupt-controller; + reg =3D <0x800c0000 0x1000>; + #interrupt-cells =3D <1>; + valid-mask =3D <0x1fffffff>; + valid-wakeup-mask =3D <0x0>; + }; + + timer: timer@80810000 { + compatible =3D "cirrus,ep9301-timer"; + reg =3D <0x80810000 0x100>; + interrupt-parent =3D <&vic1>; + interrupts =3D <19>; + }; + + dma0: dma-controller@80000000 { + compatible =3D "cirrus,ep9301-dma-m2p"; + reg =3D <0x80000000 0x0040>, + <0x80000040 0x0040>, + <0x80000080 0x0040>, + <0x800000c0 0x0040>, + <0x80000240 0x0040>, + <0x80000200 0x0040>, + <0x800002c0 0x0040>, + <0x80000280 0x0040>, + <0x80000340 0x0040>, + <0x80000300 0x0040>; + clocks =3D <&eclk EP93XX_CLK_M2P0>, + <&eclk EP93XX_CLK_M2P1>, + <&eclk EP93XX_CLK_M2P2>, + <&eclk EP93XX_CLK_M2P3>, + <&eclk EP93XX_CLK_M2P4>, + <&eclk EP93XX_CLK_M2P5>, + <&eclk EP93XX_CLK_M2P6>, + <&eclk EP93XX_CLK_M2P7>, + <&eclk EP93XX_CLK_M2P8>, + <&eclk EP93XX_CLK_M2P9>; + clock-names =3D "m2p0", "m2p1", + "m2p2", "m2p3", + "m2p4", "m2p5", + "m2p6", "m2p7", + "m2p8", "m2p9"; + interrupt-parent =3D <&vic0>; + interrupts =3D <7>, <8>, <9>, <10>, <11>, + <12>, <13>, <14>, <15>, <16>; + #dma-cells =3D <1>; + }; + + dma1: dma-controller@80000100 { + compatible =3D "cirrus,ep9301-dma-m2m"; + reg =3D <0x80000100 0x0040>, + <0x80000140 0x0040>; + clocks =3D <&eclk EP93XX_CLK_M2M0>, + <&eclk EP93XX_CLK_M2M1>; + clock-names =3D "m2m0", "m2m1"; + interrupt-parent =3D <&vic0>; + interrupts =3D <17>, <18>; + #dma-cells =3D <1>; + }; + + i2s: i2s@80820000 { + compatible =3D "cirrus,ep9301-i2s"; + #sound-dai-cells =3D <0>; + reg =3D <0x80820000 0x100>; + interrupt-parent =3D <&vic1>; + interrupts =3D <28>; + clocks =3D <&eclk EP93XX_CLK_I2S_MCLK + &eclk EP93XX_CLK_I2S_SCLK + &eclk EP93XX_CLK_I2S_LRCLK>; + clock-names =3D "mclk", "sclk", "lrclk"; + status =3D "disabled"; + }; + + gpio0: gpio@80840000 { + compatible =3D "cirrus,ep9301-gpio"; + reg =3D <0x80840000 0x04>, + <0x80840010 0x04>, + <0x80840090 0x1c>; + reg-names =3D "data", "dir", "intr"; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + interrupt-parent =3D <&vic1>; + interrupts =3D <27>; + }; + + gpio1: gpio@80840004 { + compatible =3D "cirrus,ep9301-gpio"; + reg =3D <0x80840004 0x04>, + <0x80840014 0x04>, + <0x808400ac 0x1c>; + reg-names =3D "data", "dir", "intr"; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + interrupt-parent =3D <&vic1>; + interrupts =3D <27>; + }; + + gpio2: gpio@80840008 { + compatible =3D "cirrus,ep9301-gpio"; + reg =3D <0x80840008 0x04>, + <0x80840018 0x04>; + reg-names =3D "data", "dir"; + gpio-controller; + #gpio-cells =3D <2>; + status =3D "disabled"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gpio2_default_pins>; + }; + + gpio3: gpio@8084000c { + compatible =3D "cirrus,ep9301-gpio"; + reg =3D <0x8084000c 0x04>, + <0x8084001c 0x04>; + reg-names =3D "data", "dir"; + gpio-controller; + #gpio-cells =3D <2>; + status =3D "disabled"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gpio3_default_pins>; + }; + + gpio4: gpio@80840020 { + compatible =3D "cirrus,ep9301-gpio"; + reg =3D <0x80840020 0x04>, + <0x80840024 0x04>; + reg-names =3D "data", "dir"; + gpio-controller; + #gpio-cells =3D <2>; + status =3D "disabled"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gpio4_default_pins>; + }; + + gpio5: gpio@80840030 { + compatible =3D "cirrus,ep9301-gpio"; + reg =3D <0x80840030 0x04>, + <0x80840034 0x04>, + <0x8084004c 0x1c>; + reg-names =3D "data", "dir", "intr"; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D <&vic0 19>, <&vic0 20>, + <&vic0 21>, <&vic0 22>, + <&vic1 15>, <&vic1 16>, + <&vic1 17>, <&vic1 18>; + }; + + gpio6: gpio@80840038 { + compatible =3D "cirrus,ep9301-gpio"; + reg =3D <0x80840038 0x04>, + <0x8084003c 0x04>; + reg-names =3D "data", "dir"; + gpio-controller; + #gpio-cells =3D <2>; + status =3D "disabled"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gpio6_default_pins>; + }; + + gpio7: gpio@80840040 { + compatible =3D "cirrus,ep9301-gpio"; + reg =3D <0x80840040 0x04>, + <0x80840044 0x04>; + reg-names =3D "data", "dir"; + gpio-controller; + #gpio-cells =3D <2>; + status =3D "disabled"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gpio7_default_pins>; + }; + + ide: ide@800a0000 { + compatible =3D "cirrus,ep9312-pata"; + reg =3D <0x800a0000 0x38>; + interrupt-parent =3D <&vic1>; + interrupts =3D <8>; + status =3D "disabled"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ide_default_pins>; + }; + + uart0: uart@808c0000 { + compatible =3D "arm,primecell"; + reg =3D <0x808c0000 0x1000>; + arm,primecell-periphid =3D <0x00041010>; + clocks =3D <&eclk EP93XX_CLK_UART1>, <&eclk EP93XX_CLK_UART>; + clock-names =3D "apb:uart1", "apb_pclk"; + interrupt-parent =3D <&vic1>; + interrupts =3D <20>; + status =3D "disabled"; + }; + + uart1: uart@808d0000 { + compatible =3D "arm,primecell"; + reg =3D <0x808d0000 0x1000>; + arm,primecell-periphid =3D <0x00041010>; + clocks =3D <&eclk EP93XX_CLK_UART2>, <&eclk EP93XX_CLK_UART>; + clock-names =3D "apb:uart2", "apb_pclk"; + interrupt-parent =3D <&vic1>; + interrupts =3D <22>; + status =3D "disabled"; + }; + + uart2: uart@808b0000 { + compatible =3D "arm,primecell"; + reg =3D <0x808b0000 0x1000>; + arm,primecell-periphid =3D <0x00041010>; + clocks =3D <&eclk EP93XX_CLK_UART3>, <&eclk EP93XX_CLK_UART>; + clock-names =3D "apb:uart3", "apb_pclk"; + interrupt-parent =3D <&vic1>; + interrupts =3D <23>; + status =3D "disabled"; + }; + + usb0: usb@80020000 { + compatible =3D "generic-ohci"; + reg =3D <0x80020000 0x10000>; + interrupt-parent =3D <&vic1>; + interrupts =3D <24>; + clocks =3D <&eclk EP93XX_CLK_USB>; + status =3D "disabled"; + }; + + eth0: ethernet@80010000 { + compatible =3D "cirrus,ep9301-eth"; + reg =3D <0x80010000 0x10000>; + interrupt-parent =3D <&vic1>; + interrupts =3D <7>; + mdio0: mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + rtc0: rtc@80920000 { + compatible =3D "cirrus,ep9301-rtc"; + reg =3D <0x80920000 0x100>; + }; + + spi0: spi@808a0000 { + compatible =3D "cirrus,ep9301-spi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x808a0000 0x18>; + interrupt-parent =3D <&vic1>; + interrupts =3D <21>; + clocks =3D <&eclk EP93XX_CLK_SPI>; + cs-gpios =3D <&gpio5 2 0>; + cirrus,ep9301-use-dma; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi_default_pins>; + status =3D "disabled"; + }; + + adc: adc@80900000 { + compatible =3D "cirrus,ep9301-adc"; + reg =3D <0x80900000 0x28>; + clocks =3D <&eclk EP93XX_CLK_ADC>; + interrupt-parent =3D <&vic0>; + interrupts =3D <30>; + status =3D "disabled"; + }; + + watchdog0: watchdog@80940000 { + compatible =3D "cirrus,ep9301-wdt"; + reg =3D <0x80940000 0x08>; + }; + + pwm0: pwm@80910000 { + compatible =3D "cirrus,ep9301-pwm"; + reg =3D <0x80910000 0x10>; + clocks =3D <&eclk EP93XX_CLK_PWM>; + status =3D "disabled"; + }; + + pwm1: pwm@80910020 { + compatible =3D "cirrus,ep9301-pwm"; + reg =3D <0x80910020 0x10>; + clocks =3D <&eclk EP93XX_CLK_PWM>; + status =3D "disabled"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm1_default_pins>; + }; + + keypad: keypad@800f0000 { + compatible =3D "cirrus,ep9307-keypad"; + reg =3D <0x800f0000 0x0c>; + interrupt-parent =3D <&vic0>; + interrupts =3D <29>; + clocks =3D <&eclk EP93XX_CLK_KEYPAD>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&keypad_default_pins>; + linux,keymap =3D + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + + xtali: oscillator { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <14745600>; + clock-output-names =3D "xtali"; + }; + + i2c0: i2c0 { + compatible =3D "i2c-gpio"; + sda-gpios =3D <&gpio6 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios =3D <&gpio6 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + leds { + compatible =3D "gpio-leds"; + led0 { + label =3D "grled"; + gpios =3D <&gpio4 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + function =3D LED_FUNCTION_HEARTBEAT; + }; + + led1 { + label =3D "rdled"; + gpios =3D <&gpio4 1 GPIO_ACTIVE_HIGH>; + function =3D LED_FUNCTION_FAULT; + }; + }; +}; --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2C12C77B7E for ; Mon, 24 Apr 2023 10:35:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231630AbjDXKfU (ORCPT ); Mon, 24 Apr 2023 06:35:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57590 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231255AbjDXKer (ORCPT ); Mon, 24 Apr 2023 06:34:47 -0400 X-Greylist: delayed 2343 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Mon, 24 Apr 2023 03:34:24 PDT Received: from forward502c.mail.yandex.net (forward502c.mail.yandex.net [IPv6:2a02:6b8:c03:500:1:45:d181:d502]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 53956E42; 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(no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Drop legacy gpio request/free since we are using pinctrl for this now. Signed-off-by: Nikita Shubin Acked-by: Uwe Kleine-K=C3=B6nig --- drivers/pwm/pwm-ep93xx.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/drivers/pwm/pwm-ep93xx.c b/drivers/pwm/pwm-ep93xx.c index 8bfe6cfbb3db..657adb011aeb 100644 --- a/drivers/pwm/pwm-ep93xx.c +++ b/drivers/pwm/pwm-ep93xx.c @@ -45,20 +45,6 @@ static inline struct ep93xx_pwm *to_ep93xx_pwm(struct pw= m_chip *chip) return container_of(chip, struct ep93xx_pwm, chip); } =20 -static int ep93xx_pwm_request(struct pwm_chip *chip, struct pwm_device *pw= m) -{ - struct platform_device *pdev =3D to_platform_device(chip->dev); - - return ep93xx_pwm_acquire_gpio(pdev); -} - -static void ep93xx_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) -{ - struct platform_device *pdev =3D to_platform_device(chip->dev); - - ep93xx_pwm_release_gpio(pdev); -} - static int ep93xx_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, const struct pwm_state *state) { @@ -157,8 +143,6 @@ static int ep93xx_pwm_apply(struct pwm_chip *chip, stru= ct pwm_device *pwm, } =20 static const struct pwm_ops ep93xx_pwm_ops =3D { - .request =3D ep93xx_pwm_request, - .free =3D ep93xx_pwm_free, .apply =3D ep93xx_pwm_apply, .owner =3D THIS_MODULE, }; --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9EB5C77B7E for ; Thu, 1 Jun 2023 05:48:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231749AbjFAFr6 (ORCPT ); Thu, 1 Jun 2023 01:47:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53790 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231410AbjFAFrD (ORCPT ); Thu, 1 Jun 2023 01:47:03 -0400 Received: from forward100a.mail.yandex.net (forward100a.mail.yandex.net [IPv6:2a02:6b8:c0e:500:1:45:d181:d100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9CA001AB for ; Wed, 31 May 2023 22:46:30 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net [IPv6:2a02:6b8:c1f:5e51:0:640:23ee:0]) by forward100a.mail.yandex.net (Yandex) with ESMTP id 4991E46CD6; Thu, 1 Jun 2023 08:46:28 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id pjGDMhnDduQ0-AwSLvKHg; Thu, 01 Jun 2023 08:46:28 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1685598388; bh=cfidUNhLl2ben6D10QceNGfJXqqis/yhEUlfiH2umJA=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=PttJ9OBEfFdKwvbjEM1czzrbr0lztNbJWlD8+v0b+E01iXu6iHwTVQqR3LHrFdtaC Szu+6P7ynK9fjBfOWy2pZl/4WQHpyKlDXMUALI4/y/dCYv2xiYzLFQARFkXP7HAeev F4tuJjp+TX0KVZiGQrEQRA6nwSLmO7E6SEV80z3Y= Authentication-Results: mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij , Russell King , Hartley Sweeten , "Russell King (Oracle)" , Nathan Chancellor , Nick Desaulniers , Masahiro Yamada , Nicolas Saenz Julienne Cc: Nikita Shubin , Michael Peters , Kris Bahnsen , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 36/43] ARM: ep93xx: DT for the Cirrus ep93xx SoC platforms Date: Thu, 1 Jun 2023 08:45:41 +0300 Message-Id: <20230601054549.10843-18-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds compulsory device tree support to the Cirrus ep93xx ARMv4 platform. - We select PINCTRL_EP93xx - We select COMMON_CLK_EP93XX, as clock driver moved out of platform code - We select ARCH_HAS_RESET_CONTROLLER And also we need ARM_ATAG_DTB_COMPAT to update device tree with information about memory passed from bootloader. We have to leave all MACH options as they are used for board checking before decomp, to turn off watchdog and ethernet DMA. Signed-off-by: Nikita Shubin --- arch/arm/Makefile | 1 - arch/arm/mach-ep93xx/Kconfig | 20 ++++++++++---------- arch/arm/mach-ep93xx/Makefile | 11 ----------- 3 files changed, 10 insertions(+), 22 deletions(-) delete mode 100644 arch/arm/mach-ep93xx/Makefile diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 547e5856eaa0..0e3d637cae6c 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -179,7 +179,6 @@ machine-$(CONFIG_ARCH_CLPS711X) +=3D clps711x machine-$(CONFIG_ARCH_DAVINCI) +=3D davinci machine-$(CONFIG_ARCH_DIGICOLOR) +=3D digicolor machine-$(CONFIG_ARCH_DOVE) +=3D dove -machine-$(CONFIG_ARCH_EP93XX) +=3D ep93xx machine-$(CONFIG_ARCH_EXYNOS) +=3D exynos machine-$(CONFIG_ARCH_FOOTBRIDGE) +=3D footbridge machine-$(CONFIG_ARCH_GEMINI) +=3D gemini diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig index 703f3d232a60..812b71dcf60e 100644 --- a/arch/arm/mach-ep93xx/Kconfig +++ b/arch/arm/mach-ep93xx/Kconfig @@ -3,27 +3,27 @@ menuconfig ARCH_EP93XX bool "EP93xx-based" depends on ATAGS depends on ARCH_MULTI_V4T + # CONFIG_ARCH_MULTI_V7 is not set depends on CPU_LITTLE_ENDIAN + select ARCH_HAS_RESET_CONTROLLER select ARCH_SPARSEMEM_ENABLE select ARM_AMBA select ARM_VIC + select ARM_APPENDED_DTB # Old Redboot bootloaders deployed + select ARM_ATAG_DTB_COMPAT # we need this to update dt memory node + select COMMON_CLK_EP93XX + select EP93XX_TIMER select CLKSRC_MMIO select CPU_ARM920T select GPIOLIB + select PINCTRL + select PINCTRL_EP93XX help This enables support for the Cirrus EP93xx series of CPUs. =20 if ARCH_EP93XX =20 -menu "Cirrus EP93xx Implementation Options" - -config EP93XX_SOC_COMMON - bool - default y - select SOC_BUS - select LEDS_GPIO_REGISTER - -comment "EP93xx Platforms" +# menu "EP93xx Platforms" =20 config MACH_BK3 bool "Support Liebherr BK3.1" @@ -103,6 +103,6 @@ config MACH_VISION_EP9307 Say 'Y' here if you want your kernel to support the Vision Engraving Systems EP9307 SoM. =20 -endmenu +# endmenu =20 endif diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile deleted file mode 100644 index 62e37403df14..000000000000 --- a/arch/arm/mach-ep93xx/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Makefile for the linux kernel. -# -obj-y :=3D core.o clock.o timer-ep93xx.o - -obj-$(CONFIG_EP93XX_DMA) +=3D dma.o - -obj-$(CONFIG_MACH_EDB93XX) +=3D edb93xx.o -obj-$(CONFIG_MACH_TS72XX) +=3D ts72xx.o -obj-$(CONFIG_MACH_VISION_EP9307)+=3D vision_ep9307.o --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 625E3C7EE21 for ; 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a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1682328970; bh=ILW7HQf2U6XIRRdddf7sXhZXt2NIlcnnFnvadaw+a9k=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=j5UN+nR4GxEPvjO303ZhccRQk/FFjdl6xNS8wrHhKOIAVHUoBwMU6Gx7cYyymH9yq hJqGkbWtQthzZTOLoCE75g/B4AUQtHYHOGc2luGeBAkiA/wps5ntf+0E7BNwgrmBRG uNmRACHMKjVHOO0DJo3RxdCYjDOByFIfLZp0PMG0= Authentication-Results: mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , Dmitry Torokhov , Andy Shevchenko , Jonathan Cameron , Lv Ruyi , linux-input@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 37/43] input: keypad: ep93xx: drop legacy pinctrl Date: Mon, 24 Apr 2023 15:34:53 +0300 Message-Id: <20230424123522.18302-38-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Drop legacy acquire/release since we are using pinctrl for this now. Signed-off-by: Nikita Shubin --- drivers/input/keyboard/ep93xx_keypad.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/drivers/input/keyboard/ep93xx_keypad.c b/drivers/input/keyboar= d/ep93xx_keypad.c index bf77754fa4c7..a5f5d7d453e7 100644 --- a/drivers/input/keyboard/ep93xx_keypad.c +++ b/drivers/input/keyboard/ep93xx_keypad.c @@ -222,13 +222,6 @@ static int ep93xx_keypad_resume(struct device *dev) static DEFINE_SIMPLE_DEV_PM_OPS(ep93xx_keypad_pm_ops, ep93xx_keypad_suspend, ep93xx_keypad_resume); =20 -static void ep93xx_keypad_release_gpio_action(void *_pdev) -{ - struct platform_device *pdev =3D _pdev; - - ep93xx_keypad_release_gpio(pdev); -} - static int ep93xx_keypad_probe(struct platform_device *pdev) { struct ep93xx_keypad *keypad; @@ -256,15 +249,6 @@ static int ep93xx_keypad_probe(struct platform_device = *pdev) if (IS_ERR(keypad->mmio_base)) return PTR_ERR(keypad->mmio_base); =20 - err =3D ep93xx_keypad_acquire_gpio(pdev); - if (err) - return err; - - err =3D devm_add_action_or_reset(&pdev->dev, - ep93xx_keypad_release_gpio_action, pdev); - if (err) - return err; - keypad->clk =3D devm_clk_get(&pdev->dev, NULL); if (IS_ERR(keypad->clk)) return PTR_ERR(keypad->clk); --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42C7AC77B7A for ; Thu, 1 Jun 2023 05:48:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231757AbjFAFsC (ORCPT ); Thu, 1 Jun 2023 01:48:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231602AbjFAFrE (ORCPT ); Thu, 1 Jun 2023 01:47:04 -0400 Received: from forward100a.mail.yandex.net (forward100a.mail.yandex.net [178.154.239.83]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0540D10EC; Wed, 31 May 2023 22:46:30 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net [IPv6:2a02:6b8:c1f:5e51:0:640:23ee:0]) by forward100a.mail.yandex.net (Yandex) with ESMTP id 37FD046CD1; Thu, 1 Jun 2023 08:46:29 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id pjGDMhnDduQ0-g8stdGLu; Thu, 01 Jun 2023 08:46:28 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1685598388; bh=EOmo+RE2lmZbsgHFDMmAtXJCZ5Gk2K8xR39C2HP8i6U=; h=Cc:Message-Id:References:Date:In-Reply-To:Subject:To:From; b=VdnyYB/VNrOd+qfrFT1H4Id+8uaguK42lktXQ2n82X1822UuFEV66jyQl/8cAvFvT zc6ol3NJhdpumMgNgS+vGH9LgISgn+Eu/XLS1aqDEGovd92q2Drdo4PREXBCyf8pEB CTcBI91a+WZbwYnhK5lLp18OLCcBpZ8pHgmPNdmw= Authentication-Results: mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij , Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Nikita Shubin , Michael Peters , Kris Bahnsen , linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 37/43] pwm: ep93xx: drop legacy pinctrl Date: Thu, 1 Jun 2023 08:45:42 +0300 Message-Id: <20230601054549.10843-19-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Drop legacy gpio request/free since we are using pinctrl for this now. Signed-off-by: Nikita Shubin Acked-by: Uwe Kleine-K=C3=B6nig --- Notes: v0 -> v1: =20 - dropped leagcy soc header drivers/pwm/pwm-ep93xx.c | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/drivers/pwm/pwm-ep93xx.c b/drivers/pwm/pwm-ep93xx.c index 361984ef4c0b..ac08bd0e7572 100644 --- a/drivers/pwm/pwm-ep93xx.c +++ b/drivers/pwm/pwm-ep93xx.c @@ -27,8 +27,6 @@ =20 #include =20 -#include /* for ep93xx_pwm_{acquire,release}_g= pio() */ - #define EP93XX_PWMx_TERM_COUNT 0x00 #define EP93XX_PWMx_DUTY_CYCLE 0x04 #define EP93XX_PWMx_ENABLE 0x08 @@ -45,20 +43,6 @@ static inline struct ep93xx_pwm *to_ep93xx_pwm(struct pw= m_chip *chip) return container_of(chip, struct ep93xx_pwm, chip); } =20 -static int ep93xx_pwm_request(struct pwm_chip *chip, struct pwm_device *pw= m) -{ - struct platform_device *pdev =3D to_platform_device(chip->dev); - - return ep93xx_pwm_acquire_gpio(pdev); -} - -static void ep93xx_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) -{ - struct platform_device *pdev =3D to_platform_device(chip->dev); - - ep93xx_pwm_release_gpio(pdev); -} - static int ep93xx_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, const struct pwm_state *state) { @@ -157,8 +141,6 @@ static int ep93xx_pwm_apply(struct pwm_chip *chip, stru= ct pwm_device *pwm, } =20 static const struct pwm_ops ep93xx_pwm_ops =3D { - .request =3D ep93xx_pwm_request, - .free =3D ep93xx_pwm_free, .apply =3D ep93xx_pwm_apply, .owner =3D THIS_MODULE, }; --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61E0CC77B61 for ; Mon, 24 Apr 2023 09:51:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231599AbjDXJvw (ORCPT ); Mon, 24 Apr 2023 05:51:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230504AbjDXJvj (ORCPT ); Mon, 24 Apr 2023 05:51:39 -0400 Received: from forward501b.mail.yandex.net (forward501b.mail.yandex.net [178.154.239.145]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A5A1930FF for ; Mon, 24 Apr 2023 02:51:32 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net [IPv6:2a02:6b8:c12:261e:0:640:2e3d:0]) by forward501b.mail.yandex.net (Yandex) with ESMTP id 49E9E5EB14; Mon, 24 Apr 2023 12:36:12 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id JZBb1pbWwKo0-sRmf96JB; Mon, 24 Apr 2023 12:36:12 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1682328972; bh=Ti4rmk9GtD+fdUS3cXOpHQKoJb3lg100jXiX2vylp5A=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=f+2TuJ4q7vopWgrQYEdbOHo5PlYImRqhUgnB8d6vd6ffvEptPbYF0vq61RH4v+phm lP9auUVDmh9yJohjldy73bMbEKO0eXtMLtH1ty2dIwvZ5mHYp8GhRbyl1YVlfZ5Xbh ZxrQymSyC+5EpXqfd9iC3SrV7UOANPc1g5wlgRv4= Authentication-Results: mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , Linus Walleij , linux-kernel@vger.kernel.org Subject: [PATCH 38/43] ARM: ep93xx: soc: drop defines Date: Mon, 24 Apr 2023 15:34:54 +0300 Message-Id: <20230424123522.18302-39-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Remove unnecessary defines, as we dropped board files. Signed-off-by: Nikita Shubin --- include/linux/soc/cirrus/ep93xx.h | 22 ---------------------- 1 file changed, 22 deletions(-) diff --git a/include/linux/soc/cirrus/ep93xx.h b/include/linux/soc/cirrus/e= p93xx.h index f0f770a103be..bba0a5ca4335 100644 --- a/include/linux/soc/cirrus/ep93xx.h +++ b/include/linux/soc/cirrus/ep93xx.h @@ -2,34 +2,12 @@ #ifndef _SOC_EP93XX_H #define _SOC_EP93XX_H =20 -struct platform_device; - #define EP93XX_CHIP_REV_D0 3 #define EP93XX_CHIP_REV_D1 4 #define EP93XX_CHIP_REV_E0 5 #define EP93XX_CHIP_REV_E1 6 #define EP93XX_CHIP_REV_E2 7 =20 -#if defined(CONFIG_ARCH_EP93XX) && !defined(CONFIG_OF) -int ep93xx_pwm_acquire_gpio(struct platform_device *pdev); -void ep93xx_pwm_release_gpio(struct platform_device *pdev); -int ep93xx_ide_acquire_gpio(struct platform_device *pdev); -void ep93xx_ide_release_gpio(struct platform_device *pdev); -int ep93xx_keypad_acquire_gpio(struct platform_device *pdev); -void ep93xx_keypad_release_gpio(struct platform_device *pdev); -int ep93xx_i2s_acquire(void); -void ep93xx_i2s_release(void); -#else -static inline int ep93xx_pwm_acquire_gpio(struct platform_device *pdev) { = return 0; } -static inline void ep93xx_pwm_release_gpio(struct platform_device *pdev) {} -static inline int ep93xx_ide_acquire_gpio(struct platform_device *pdev) { = return 0; } -static inline void ep93xx_ide_release_gpio(struct platform_device *pdev) {} -static inline int ep93xx_keypad_acquire_gpio(struct platform_device *pdev)= { return 0; } -static inline void ep93xx_keypad_release_gpio(struct platform_device *pdev= ) {} -static inline int ep93xx_i2s_acquire(void) { return 0; } -static inline void ep93xx_i2s_release(void) {} -#endif - #if defined(CONFIG_ARCH_EP93XX) unsigned int ep93xx_chip_revision(void); #ifdef CONFIG_SOC_EP93XX --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6EF1C77B7A for ; Thu, 1 Jun 2023 05:48:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231768AbjFAFsF (ORCPT ); Thu, 1 Jun 2023 01:48:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231650AbjFAFrF (ORCPT ); Thu, 1 Jun 2023 01:47:05 -0400 Received: from forward100a.mail.yandex.net (forward100a.mail.yandex.net [178.154.239.83]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4D6DD1AD; Wed, 31 May 2023 22:46:32 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net [IPv6:2a02:6b8:c1f:5e51:0:640:23ee:0]) by forward100a.mail.yandex.net (Yandex) with ESMTP id CA84046D03; Thu, 1 Jun 2023 08:46:29 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id pjGDMhnDduQ0-Nb8XSMqX; Thu, 01 Jun 2023 08:46:29 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1685598389; bh=y+tFOwGnvCdi8X4QhhgzSNJA5jm6cyNcwe8cwo1VMts=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=cQb3tKUQqQU70xbxwmnmHG4A8rwFZcyB9S41GD/gqX9V1JYWmr0e4eDLzjCRc3uhf in1wAxUUNe/s5ISLN4iPYu6wEn6nhKUU024TIpY4YMAyOjdHC0xUMb2g1JSUj84Nnx bi6bkoJVdtByTvFxiQFLSu1UfOuNn0TZMbBRMxgo= Authentication-Results: mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij , Sergey Shtylyov , Damien Le Moal Cc: Nikita Shubin , Michael Peters , Kris Bahnsen , linux-ide@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 38/43] pata: cirrus: drop legacy pinctrl Date: Thu, 1 Jun 2023 08:45:43 +0300 Message-Id: <20230601054549.10843-20-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Drop legacy acquire/release since we are using pinctrl for this now. Signed-off-by: Nikita Shubin Reviewed-by: Sergey Shtylyov --- drivers/ata/pata_ep93xx.c | 25 ++++++------------------- 1 file changed, 6 insertions(+), 19 deletions(-) diff --git a/drivers/ata/pata_ep93xx.c b/drivers/ata/pata_ep93xx.c index 8d363bc71342..88cf31000000 100644 --- a/drivers/ata/pata_ep93xx.c +++ b/drivers/ata/pata_ep93xx.c @@ -921,28 +921,18 @@ static int ep93xx_pata_probe(struct platform_device *= pdev) void __iomem *ide_base; int err; =20 - err =3D ep93xx_ide_acquire_gpio(pdev); - if (err) - return err; - /* INT[3] (IRQ_EP93XX_EXT3) line connected as pull down */ irq =3D platform_get_irq(pdev, 0); - if (irq < 0) { - err =3D irq; - goto err_rel_gpio; - } + if (irq < 0) + return irq; =20 ide_base =3D devm_platform_get_and_ioremap_resource(pdev, 0, &mem_res); - if (IS_ERR(ide_base)) { - err =3D PTR_ERR(ide_base); - goto err_rel_gpio; - } + if (IS_ERR(ide_base)) + return PTR_ERR(ide_base); =20 drv_data =3D devm_kzalloc(&pdev->dev, sizeof(*drv_data), GFP_KERNEL); - if (!drv_data) { - err =3D -ENXIO; - goto err_rel_gpio; - } + if (!drv_data) + return -ENXIO; =20 drv_data->pdev =3D pdev; drv_data->ide_base =3D ide_base; @@ -1000,8 +990,6 @@ static int ep93xx_pata_probe(struct platform_device *p= dev) =20 err_rel_dma: ep93xx_pata_release_dma(drv_data); -err_rel_gpio: - ep93xx_ide_release_gpio(pdev); return err; } =20 @@ -1013,7 +1001,6 @@ static int ep93xx_pata_remove(struct platform_device = *pdev) ata_host_detach(host); ep93xx_pata_release_dma(drv_data); ep93xx_pata_clear_regs(drv_data->ide_base); - ep93xx_ide_release_gpio(pdev); return 0; } =20 --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C9E5C77B61 for ; Mon, 24 Apr 2023 10:22:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231495AbjDXKWO (ORCPT ); Mon, 24 Apr 2023 06:22:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45050 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231754AbjDXKV3 (ORCPT ); Mon, 24 Apr 2023 06:21:29 -0400 Received: from forward502b.mail.yandex.net (forward502b.mail.yandex.net [178.154.239.146]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 599D4420C for ; Mon, 24 Apr 2023 03:20:50 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net [IPv6:2a02:6b8:c12:261e:0:640:2e3d:0]) by forward502b.mail.yandex.net (Yandex) with ESMTP id 6AE815EDF0; Mon, 24 Apr 2023 12:36:14 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id JZBb1pbWwKo0-XtsvvIDr; Mon, 24 Apr 2023 12:36:13 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1682328973; bh=+kl+HXYBpYyocWP0e7VBjw9iIwYge0UxFQHTIULPdrg=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=EJt9Y9Wia4GfrS7fwWwLydlU7y2KsHmI7nVep8+L1eDH6igoouKb/aNa32jV6xE9A 0PzqVEs/tsR/0J0GlNGUXad0m9pRB8z7JhreG6plQHci5r97MZx6yVyWjIQNEfaUqa Gmer++jPGbsGB0nE5GeFnusw9QwxHDx2FDOaPiy0= Authentication-Results: mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , Hartley Sweeten , Russell King , Lukasz Majewski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 39/43] ARM: ep93xx: delete all boardfiles Date: Mon, 24 Apr 2023 15:34:55 +0300 Message-Id: <20230424123522.18302-40-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Delete the ep93xx board files. Signed-off-by: Nikita Shubin --- arch/arm/mach-ep93xx/clock.c | 733 ----------------- arch/arm/mach-ep93xx/core.c | 1114 -------------------------- arch/arm/mach-ep93xx/dma.c | 114 --- arch/arm/mach-ep93xx/edb93xx.c | 344 -------- arch/arm/mach-ep93xx/ep93xx-regs.h | 38 - arch/arm/mach-ep93xx/gpio-ep93xx.h | 111 --- arch/arm/mach-ep93xx/hardware.h | 25 - arch/arm/mach-ep93xx/irqs.h | 76 -- arch/arm/mach-ep93xx/platform.h | 42 - arch/arm/mach-ep93xx/soc.h | 212 ----- arch/arm/mach-ep93xx/timer-ep93xx.c | 142 ---- arch/arm/mach-ep93xx/ts72xx.c | 422 ---------- arch/arm/mach-ep93xx/ts72xx.h | 94 --- arch/arm/mach-ep93xx/vision_ep9307.c | 311 ------- 14 files changed, 3778 deletions(-) delete mode 100644 arch/arm/mach-ep93xx/clock.c delete mode 100644 arch/arm/mach-ep93xx/core.c delete mode 100644 arch/arm/mach-ep93xx/dma.c delete mode 100644 arch/arm/mach-ep93xx/edb93xx.c delete mode 100644 arch/arm/mach-ep93xx/ep93xx-regs.h delete mode 100644 arch/arm/mach-ep93xx/gpio-ep93xx.h delete mode 100644 arch/arm/mach-ep93xx/hardware.h delete mode 100644 arch/arm/mach-ep93xx/irqs.h delete mode 100644 arch/arm/mach-ep93xx/platform.h delete mode 100644 arch/arm/mach-ep93xx/soc.h delete mode 100644 arch/arm/mach-ep93xx/timer-ep93xx.c delete mode 100644 arch/arm/mach-ep93xx/ts72xx.c delete mode 100644 arch/arm/mach-ep93xx/ts72xx.h delete mode 100644 arch/arm/mach-ep93xx/vision_ep9307.c diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c deleted file mode 100644 index 85a496ddc619..000000000000 --- a/arch/arm/mach-ep93xx/clock.c +++ /dev/null @@ -1,733 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-ep93xx/clock.c - * Clock control for Cirrus EP93xx chips. - * - * Copyright (C) 2006 Lennert Buytenhek - */ - -#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "hardware.h" - -#include - -#include "soc.h" - -static DEFINE_SPINLOCK(clk_lock); - -static char fclk_divisors[] =3D { 1, 2, 4, 8, 16, 1, 1, 1 }; -static char hclk_divisors[] =3D { 1, 2, 4, 5, 6, 8, 16, 32 }; -static char pclk_divisors[] =3D { 1, 2, 4, 8 }; - -static char adc_divisors[] =3D { 16, 4 }; -static char sclk_divisors[] =3D { 2, 4 }; -static char lrclk_divisors[] =3D { 32, 64, 128 }; - -static const char * const mux_parents[] =3D { - "xtali", - "pll1", - "pll2" -}; - -/* - * PLL rate =3D 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^= PS - */ -static unsigned long calc_pll_rate(unsigned long long rate, u32 config_wor= d) -{ - int i; - - rate *=3D ((config_word >> 11) & 0x1f) + 1; /* X1FBD */ - rate *=3D ((config_word >> 5) & 0x3f) + 1; /* X2FBD */ - do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */ - for (i =3D 0; i < ((config_word >> 16) & 3); i++) /* PS */ - rate >>=3D 1; - - return (unsigned long)rate; -} - -struct clk_psc { - struct clk_hw hw; - void __iomem *reg; - u8 bit_idx; - u32 mask; - u8 shift; - u8 width; - char *div; - u8 num_div; - spinlock_t *lock; -}; - -#define to_clk_psc(_hw) container_of(_hw, struct clk_psc, hw) - -static int ep93xx_clk_is_enabled(struct clk_hw *hw) -{ - struct clk_psc *psc =3D to_clk_psc(hw); - u32 val =3D readl(psc->reg); - - return (val & BIT(psc->bit_idx)) ? 1 : 0; -} - -static int ep93xx_clk_enable(struct clk_hw *hw) -{ - struct clk_psc *psc =3D to_clk_psc(hw); - unsigned long flags =3D 0; - u32 val; - - if (psc->lock) - spin_lock_irqsave(psc->lock, flags); - - val =3D __raw_readl(psc->reg); - val |=3D BIT(psc->bit_idx); - - ep93xx_syscon_swlocked_write(val, psc->reg); - - if (psc->lock) - spin_unlock_irqrestore(psc->lock, flags); - - return 0; -} - -static void ep93xx_clk_disable(struct clk_hw *hw) -{ - struct clk_psc *psc =3D to_clk_psc(hw); - unsigned long flags =3D 0; - u32 val; - - if (psc->lock) - spin_lock_irqsave(psc->lock, flags); - - val =3D __raw_readl(psc->reg); - val &=3D ~BIT(psc->bit_idx); - - ep93xx_syscon_swlocked_write(val, psc->reg); - - if (psc->lock) - spin_unlock_irqrestore(psc->lock, flags); -} - -static const struct clk_ops clk_ep93xx_gate_ops =3D { - .enable =3D ep93xx_clk_enable, - .disable =3D ep93xx_clk_disable, - .is_enabled =3D ep93xx_clk_is_enabled, -}; - -static struct clk_hw *ep93xx_clk_register_gate(const char *name, - const char *parent_name, - void __iomem *reg, - u8 bit_idx) -{ - struct clk_init_data init; - struct clk_psc *psc; - struct clk *clk; - - psc =3D kzalloc(sizeof(*psc), GFP_KERNEL); - if (!psc) - return ERR_PTR(-ENOMEM); - - init.name =3D name; - init.ops =3D &clk_ep93xx_gate_ops; - init.flags =3D CLK_SET_RATE_PARENT; - init.parent_names =3D (parent_name ? &parent_name : NULL); - init.num_parents =3D (parent_name ? 1 : 0); - - psc->reg =3D reg; - psc->bit_idx =3D bit_idx; - psc->hw.init =3D &init; - psc->lock =3D &clk_lock; - - clk =3D clk_register(NULL, &psc->hw); - if (IS_ERR(clk)) { - kfree(psc); - return ERR_CAST(clk); - } - - return &psc->hw; -} - -static u8 ep93xx_mux_get_parent(struct clk_hw *hw) -{ - struct clk_psc *psc =3D to_clk_psc(hw); - u32 val =3D __raw_readl(psc->reg); - - if (!(val & EP93XX_SYSCON_CLKDIV_ESEL)) - return 0; - - if (!(val & EP93XX_SYSCON_CLKDIV_PSEL)) - return 1; - - return 2; -} - -static int ep93xx_mux_set_parent_lock(struct clk_hw *hw, u8 index) -{ - struct clk_psc *psc =3D to_clk_psc(hw); - unsigned long flags =3D 0; - u32 val; - - if (index >=3D ARRAY_SIZE(mux_parents)) - return -EINVAL; - - if (psc->lock) - spin_lock_irqsave(psc->lock, flags); - - val =3D __raw_readl(psc->reg); - val &=3D ~(EP93XX_SYSCON_CLKDIV_ESEL | EP93XX_SYSCON_CLKDIV_PSEL); - - - if (index !=3D 0) { - val |=3D EP93XX_SYSCON_CLKDIV_ESEL; - val |=3D (index - 1) ? EP93XX_SYSCON_CLKDIV_PSEL : 0; - } - - ep93xx_syscon_swlocked_write(val, psc->reg); - - if (psc->lock) - spin_unlock_irqrestore(psc->lock, flags); - - return 0; -} - -static bool is_best(unsigned long rate, unsigned long now, - unsigned long best) -{ - return abs(rate - now) < abs(rate - best); -} - -static int ep93xx_mux_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) -{ - unsigned long rate =3D req->rate; - struct clk *best_parent =3D NULL; - unsigned long __parent_rate; - unsigned long best_rate =3D 0, actual_rate, mclk_rate; - unsigned long best_parent_rate; - int __div =3D 0, __pdiv =3D 0; - int i; - - /* - * Try the two pll's and the external clock - * Because the valid predividers are 2, 2.5 and 3, we multiply - * all the clocks by 2 to avoid floating point math. - * - * This is based on the algorithm in the ep93xx raster guide: - * http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf - * - */ - for (i =3D 0; i < ARRAY_SIZE(mux_parents); i++) { - struct clk *parent =3D clk_get_sys(mux_parents[i], NULL); - - __parent_rate =3D clk_get_rate(parent); - mclk_rate =3D __parent_rate * 2; - - /* Try each predivider value */ - for (__pdiv =3D 4; __pdiv <=3D 6; __pdiv++) { - __div =3D mclk_rate / (rate * __pdiv); - if (__div < 2 || __div > 127) - continue; - - actual_rate =3D mclk_rate / (__pdiv * __div); - if (is_best(rate, actual_rate, best_rate)) { - best_rate =3D actual_rate; - best_parent_rate =3D __parent_rate; - best_parent =3D parent; - } - } - } - - if (!best_parent) - return -EINVAL; - - req->best_parent_rate =3D best_parent_rate; - req->best_parent_hw =3D __clk_get_hw(best_parent); - req->rate =3D best_rate; - - return 0; -} - -static unsigned long ep93xx_ddiv_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_psc *psc =3D to_clk_psc(hw); - unsigned long rate =3D 0; - u32 val =3D __raw_readl(psc->reg); - int __pdiv =3D ((val >> EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) & 0x03); - int __div =3D val & 0x7f; - - if (__div > 0) - rate =3D (parent_rate * 2) / ((__pdiv + 3) * __div); - - return rate; -} - -static int ep93xx_ddiv_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_psc *psc =3D to_clk_psc(hw); - int pdiv =3D 0, div =3D 0; - unsigned long best_rate =3D 0, actual_rate, mclk_rate; - int __div =3D 0, __pdiv =3D 0; - u32 val; - - mclk_rate =3D parent_rate * 2; - - for (__pdiv =3D 4; __pdiv <=3D 6; __pdiv++) { - __div =3D mclk_rate / (rate * __pdiv); - if (__div < 2 || __div > 127) - continue; - - actual_rate =3D mclk_rate / (__pdiv * __div); - if (is_best(rate, actual_rate, best_rate)) { - pdiv =3D __pdiv - 3; - div =3D __div; - best_rate =3D actual_rate; - } - } - - if (!best_rate) - return -EINVAL; - - val =3D __raw_readl(psc->reg); - - /* Clear old dividers */ - val &=3D ~0x37f; - - /* Set the new pdiv and div bits for the new clock rate */ - val |=3D (pdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | div; - ep93xx_syscon_swlocked_write(val, psc->reg); - - return 0; -} - -static const struct clk_ops clk_ddiv_ops =3D { - .enable =3D ep93xx_clk_enable, - .disable =3D ep93xx_clk_disable, - .is_enabled =3D ep93xx_clk_is_enabled, - .get_parent =3D ep93xx_mux_get_parent, - .set_parent =3D ep93xx_mux_set_parent_lock, - .determine_rate =3D ep93xx_mux_determine_rate, - .recalc_rate =3D ep93xx_ddiv_recalc_rate, - .set_rate =3D ep93xx_ddiv_set_rate, -}; - -static struct clk_hw *clk_hw_register_ddiv(const char *name, - void __iomem *reg, - u8 bit_idx) -{ - struct clk_init_data init; - struct clk_psc *psc; - struct clk *clk; - - psc =3D kzalloc(sizeof(*psc), GFP_KERNEL); - if (!psc) - return ERR_PTR(-ENOMEM); - - init.name =3D name; - init.ops =3D &clk_ddiv_ops; - init.flags =3D 0; - init.parent_names =3D mux_parents; - init.num_parents =3D ARRAY_SIZE(mux_parents); - - psc->reg =3D reg; - psc->bit_idx =3D bit_idx; - psc->lock =3D &clk_lock; - psc->hw.init =3D &init; - - clk =3D clk_register(NULL, &psc->hw); - if (IS_ERR(clk)) { - kfree(psc); - return ERR_CAST(clk); - } - return &psc->hw; -} - -static unsigned long ep93xx_div_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_psc *psc =3D to_clk_psc(hw); - u32 val =3D __raw_readl(psc->reg); - u8 index =3D (val & psc->mask) >> psc->shift; - - if (index > psc->num_div) - return 0; - - return DIV_ROUND_UP_ULL(parent_rate, psc->div[index]); -} - -static long ep93xx_div_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) -{ - struct clk_psc *psc =3D to_clk_psc(hw); - unsigned long best =3D 0, now, maxdiv; - int i; - - maxdiv =3D psc->div[psc->num_div - 1]; - - for (i =3D 0; i < psc->num_div; i++) { - if ((rate * psc->div[i]) =3D=3D *parent_rate) - return DIV_ROUND_UP_ULL((u64)*parent_rate, psc->div[i]); - - now =3D DIV_ROUND_UP_ULL((u64)*parent_rate, psc->div[i]); - - if (is_best(rate, now, best)) - best =3D now; - } - - if (!best) - best =3D DIV_ROUND_UP_ULL(*parent_rate, maxdiv); - - return best; -} - -static int ep93xx_div_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_psc *psc =3D to_clk_psc(hw); - u32 val =3D __raw_readl(psc->reg) & ~psc->mask; - int i; - - for (i =3D 0; i < psc->num_div; i++) - if (rate =3D=3D parent_rate / psc->div[i]) { - val |=3D i << psc->shift; - break; - } - - if (i =3D=3D psc->num_div) - return -EINVAL; - - ep93xx_syscon_swlocked_write(val, psc->reg); - - return 0; -} - -static const struct clk_ops ep93xx_div_ops =3D { - .enable =3D ep93xx_clk_enable, - .disable =3D ep93xx_clk_disable, - .is_enabled =3D ep93xx_clk_is_enabled, - .recalc_rate =3D ep93xx_div_recalc_rate, - .round_rate =3D ep93xx_div_round_rate, - .set_rate =3D ep93xx_div_set_rate, -}; - -static struct clk_hw *clk_hw_register_div(const char *name, - const char *parent_name, - void __iomem *reg, - u8 enable_bit, - u8 shift, - u8 width, - char *clk_divisors, - u8 num_div) -{ - struct clk_init_data init; - struct clk_psc *psc; - struct clk *clk; - - psc =3D kzalloc(sizeof(*psc), GFP_KERNEL); - if (!psc) - return ERR_PTR(-ENOMEM); - - init.name =3D name; - init.ops =3D &ep93xx_div_ops; - init.flags =3D 0; - init.parent_names =3D (parent_name ? &parent_name : NULL); - init.num_parents =3D 1; - - psc->reg =3D reg; - psc->bit_idx =3D enable_bit; - psc->mask =3D GENMASK(shift + width - 1, shift); - psc->shift =3D shift; - psc->div =3D clk_divisors; - psc->num_div =3D num_div; - psc->lock =3D &clk_lock; - psc->hw.init =3D &init; - - clk =3D clk_register(NULL, &psc->hw); - if (IS_ERR(clk)) { - kfree(psc); - return ERR_CAST(clk); - } - return &psc->hw; -} - -struct ep93xx_gate { - unsigned int bit; - const char *dev_id; - const char *con_id; -}; - -static struct ep93xx_gate ep93xx_uarts[] =3D { - {EP93XX_SYSCON_DEVCFG_U1EN, "apb:uart1", NULL}, - {EP93XX_SYSCON_DEVCFG_U2EN, "apb:uart2", NULL}, - {EP93XX_SYSCON_DEVCFG_U3EN, "apb:uart3", NULL}, -}; - -static void __init ep93xx_uart_clock_init(void) -{ - unsigned int i; - struct clk_hw *hw; - u32 value; - unsigned int clk_uart_div; - - value =3D __raw_readl(EP93XX_SYSCON_PWRCNT); - if (value & EP93XX_SYSCON_PWRCNT_UARTBAUD) - clk_uart_div =3D 1; - else - clk_uart_div =3D 2; - - hw =3D clk_hw_register_fixed_factor(NULL, "uart", "xtali", 0, 1, clk_uart= _div); - - /* parenting uart gate clocks to uart clock */ - for (i =3D 0; i < ARRAY_SIZE(ep93xx_uarts); i++) { - hw =3D ep93xx_clk_register_gate(ep93xx_uarts[i].dev_id, - "uart", - EP93XX_SYSCON_DEVCFG, - ep93xx_uarts[i].bit); - - clk_hw_register_clkdev(hw, NULL, ep93xx_uarts[i].dev_id); - } -} - -static struct ep93xx_gate ep93xx_dmas[] =3D { - {EP93XX_SYSCON_PWRCNT_DMA_M2P0, NULL, "m2p0"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2P1, NULL, "m2p1"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2P2, NULL, "m2p2"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2P3, NULL, "m2p3"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2P4, NULL, "m2p4"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2P5, NULL, "m2p5"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2P6, NULL, "m2p6"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2P7, NULL, "m2p7"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2P8, NULL, "m2p8"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2P9, NULL, "m2p9"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2M0, NULL, "m2m0"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2M1, NULL, "m2m1"}, -}; - -static void __init ep93xx_dma_clock_init(void) -{ - unsigned int i; - struct clk_hw *hw; - int ret; - - for (i =3D 0; i < ARRAY_SIZE(ep93xx_dmas); i++) { - hw =3D clk_hw_register_gate(NULL, ep93xx_dmas[i].con_id, - "hclk", 0, - EP93XX_SYSCON_PWRCNT, - ep93xx_dmas[i].bit, - 0, - &clk_lock); - - ret =3D clk_hw_register_clkdev(hw, ep93xx_dmas[i].con_id, NULL); - if (ret) - pr_err("%s: failed to register lookup %s\n", - __func__, ep93xx_dmas[i].con_id); - } -} - -static int __init ep93xx_clock_init(void) -{ - u32 value; - struct clk_hw *hw; - unsigned long clk_pll1_rate; - unsigned long clk_f_rate; - unsigned long clk_h_rate; - unsigned long clk_p_rate; - unsigned long clk_pll2_rate; - unsigned int clk_f_div; - unsigned int clk_h_div; - unsigned int clk_p_div; - unsigned int clk_usb_div; - unsigned long clk_spi_div; - - hw =3D clk_hw_register_fixed_rate(NULL, "xtali", NULL, 0, EP93XX_EXT_CLK_= RATE); - clk_hw_register_clkdev(hw, NULL, "xtali"); - - /* Determine the bootloader configured pll1 rate */ - value =3D __raw_readl(EP93XX_SYSCON_CLKSET1); - if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1)) - clk_pll1_rate =3D EP93XX_EXT_CLK_RATE; - else - clk_pll1_rate =3D calc_pll_rate(EP93XX_EXT_CLK_RATE, value); - - hw =3D clk_hw_register_fixed_rate(NULL, "pll1", "xtali", 0, clk_pll1_rate= ); - clk_hw_register_clkdev(hw, NULL, "pll1"); - - /* Initialize the pll1 derived clocks */ - clk_f_div =3D fclk_divisors[(value >> 25) & 0x7]; - clk_h_div =3D hclk_divisors[(value >> 20) & 0x7]; - clk_p_div =3D pclk_divisors[(value >> 18) & 0x3]; - - hw =3D clk_hw_register_fixed_factor(NULL, "fclk", "pll1", 0, 1, clk_f_div= ); - clk_f_rate =3D clk_get_rate(hw->clk); - hw =3D clk_hw_register_fixed_factor(NULL, "hclk", "pll1", 0, 1, clk_h_div= ); - clk_h_rate =3D clk_get_rate(hw->clk); - hw =3D clk_hw_register_fixed_factor(NULL, "pclk", "hclk", 0, 1, clk_p_div= ); - clk_p_rate =3D clk_get_rate(hw->clk); - - clk_hw_register_clkdev(hw, "apb_pclk", NULL); - - ep93xx_dma_clock_init(); - - /* Determine the bootloader configured pll2 rate */ - value =3D __raw_readl(EP93XX_SYSCON_CLKSET2); - if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2)) - clk_pll2_rate =3D EP93XX_EXT_CLK_RATE; - else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN) - clk_pll2_rate =3D calc_pll_rate(EP93XX_EXT_CLK_RATE, value); - else - clk_pll2_rate =3D 0; - - hw =3D clk_hw_register_fixed_rate(NULL, "pll2", "xtali", 0, clk_pll2_rate= ); - clk_hw_register_clkdev(hw, NULL, "pll2"); - - /* Initialize the pll2 derived clocks */ - /* - * These four bits set the divide ratio between the PLL2 - * output and the USB clock. - * 0000 - Divide by 1 - * 0001 - Divide by 2 - * 0010 - Divide by 3 - * 0011 - Divide by 4 - * 0100 - Divide by 5 - * 0101 - Divide by 6 - * 0110 - Divide by 7 - * 0111 - Divide by 8 - * 1000 - Divide by 9 - * 1001 - Divide by 10 - * 1010 - Divide by 11 - * 1011 - Divide by 12 - * 1100 - Divide by 13 - * 1101 - Divide by 14 - * 1110 - Divide by 15 - * 1111 - Divide by 1 - * On power-on-reset these bits are reset to 0000b. - */ - clk_usb_div =3D (((value >> 28) & 0xf) + 1); - hw =3D clk_hw_register_fixed_factor(NULL, "usb_clk", "pll2", 0, 1, clk_us= b_div); - hw =3D clk_hw_register_gate(NULL, "ohci-platform", - "usb_clk", 0, - EP93XX_SYSCON_PWRCNT, - EP93XX_SYSCON_PWRCNT_USH_EN, - 0, - &clk_lock); - clk_hw_register_clkdev(hw, NULL, "ohci-platform"); - - /* - * EP93xx SSP clock rate was doubled in version E2. For more information - * see: - * http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf - */ - clk_spi_div =3D 1; - if (ep93xx_chip_revision() < EP93XX_CHIP_REV_E2) - clk_spi_div =3D 2; - hw =3D clk_hw_register_fixed_factor(NULL, "ep93xx-spi.0", "xtali", 0, 1, = clk_spi_div); - clk_hw_register_clkdev(hw, NULL, "ep93xx-spi.0"); - - /* pwm clock */ - hw =3D clk_hw_register_fixed_factor(NULL, "pwm_clk", "xtali", 0, 1, 1); - clk_hw_register_clkdev(hw, "pwm_clk", NULL); - - pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n", - clk_pll1_rate / 1000000, clk_pll2_rate / 1000000); - pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n", - clk_f_rate / 1000000, clk_h_rate / 1000000, - clk_p_rate / 1000000); - - ep93xx_uart_clock_init(); - - /* touchscreen/adc clock */ - hw =3D clk_hw_register_div("ep93xx-adc", - "xtali", - EP93XX_SYSCON_KEYTCHCLKDIV, - EP93XX_SYSCON_KEYTCHCLKDIV_TSEN, - EP93XX_SYSCON_KEYTCHCLKDIV_ADIV, - 1, - adc_divisors, - ARRAY_SIZE(adc_divisors)); - - clk_hw_register_clkdev(hw, NULL, "ep93xx-adc"); - - /* keypad clock */ - hw =3D clk_hw_register_div("ep93xx-keypad", - "xtali", - EP93XX_SYSCON_KEYTCHCLKDIV, - EP93XX_SYSCON_KEYTCHCLKDIV_KEN, - EP93XX_SYSCON_KEYTCHCLKDIV_KDIV, - 1, - adc_divisors, - ARRAY_SIZE(adc_divisors)); - - clk_hw_register_clkdev(hw, NULL, "ep93xx-keypad"); - - /* On reset PDIV and VDIV is set to zero, while PDIV zero - * means clock disable, VDIV shouldn't be zero. - * So i set both dividers to minimum. - */ - /* ENA - Enable CLK divider. */ - /* PDIV - 00 - Disable clock */ - /* VDIV - at least 2 */ - /* Check and enable video clk registers */ - value =3D __raw_readl(EP93XX_SYSCON_VIDCLKDIV); - value |=3D (1 << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | 2; - ep93xx_syscon_swlocked_write(value, EP93XX_SYSCON_VIDCLKDIV); - - /* check and enable i2s clk registers */ - value =3D __raw_readl(EP93XX_SYSCON_I2SCLKDIV); - value |=3D (1 << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | 2; - ep93xx_syscon_swlocked_write(value, EP93XX_SYSCON_I2SCLKDIV); - - /* video clk */ - hw =3D clk_hw_register_ddiv("ep93xx-fb", - EP93XX_SYSCON_VIDCLKDIV, - EP93XX_SYSCON_CLKDIV_ENABLE); - - clk_hw_register_clkdev(hw, NULL, "ep93xx-fb"); - - /* i2s clk */ - hw =3D clk_hw_register_ddiv("mclk", - EP93XX_SYSCON_I2SCLKDIV, - EP93XX_SYSCON_CLKDIV_ENABLE); - - clk_hw_register_clkdev(hw, "mclk", "ep93xx-i2s"); - - /* i2s sclk */ -#define EP93XX_I2SCLKDIV_SDIV_SHIFT 16 -#define EP93XX_I2SCLKDIV_SDIV_WIDTH 1 - hw =3D clk_hw_register_div("sclk", - "mclk", - EP93XX_SYSCON_I2SCLKDIV, - EP93XX_SYSCON_I2SCLKDIV_SENA, - EP93XX_I2SCLKDIV_SDIV_SHIFT, - EP93XX_I2SCLKDIV_SDIV_WIDTH, - sclk_divisors, - ARRAY_SIZE(sclk_divisors)); - - clk_hw_register_clkdev(hw, "sclk", "ep93xx-i2s"); - - /* i2s lrclk */ -#define EP93XX_I2SCLKDIV_LRDIV32_SHIFT 17 -#define EP93XX_I2SCLKDIV_LRDIV32_WIDTH 3 - hw =3D clk_hw_register_div("lrclk", - "sclk", - EP93XX_SYSCON_I2SCLKDIV, - EP93XX_SYSCON_I2SCLKDIV_SENA, - EP93XX_I2SCLKDIV_LRDIV32_SHIFT, - EP93XX_I2SCLKDIV_LRDIV32_WIDTH, - lrclk_divisors, - ARRAY_SIZE(lrclk_divisors)); - - clk_hw_register_clkdev(hw, "lrclk", "ep93xx-i2s"); - - return 0; -} -postcore_initcall(ep93xx_clock_init); diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c deleted file mode 100644 index d61c1d2a0843..000000000000 --- a/arch/arm/mach-ep93xx/core.c +++ /dev/null @@ -1,1114 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-ep93xx/core.c - * Core routines for Cirrus EP93xx chips. - * - * Copyright (C) 2006 Lennert Buytenhek - * Copyright (C) 2007 Herbert Valerio Riedel - * - * Thanks go to Michael Burian and Ray Lehtiniemi for their key - * role in the ep93xx linux community. - */ - -#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "hardware.h" -#include -#include -#include -#include - -#include "gpio-ep93xx.h" - -#include -#include - -#include "soc.h" -#include "irqs.h" - -/************************************************************************* - * Static I/O mappings that are needed for all EP93xx platforms - *************************************************************************/ -static struct map_desc ep93xx_io_desc[] __initdata =3D { - { - .virtual =3D EP93XX_AHB_VIRT_BASE, - .pfn =3D __phys_to_pfn(EP93XX_AHB_PHYS_BASE), - .length =3D EP93XX_AHB_SIZE, - .type =3D MT_DEVICE, - }, { - .virtual =3D EP93XX_APB_VIRT_BASE, - .pfn =3D __phys_to_pfn(EP93XX_APB_PHYS_BASE), - .length =3D EP93XX_APB_SIZE, - .type =3D MT_DEVICE, - }, -}; - -void __init ep93xx_map_io(void) -{ - iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc)); -} - -/************************************************************************* - * EP93xx IRQ handling - *************************************************************************/ -void __init ep93xx_init_irq(void) -{ - vic_init(EP93XX_VIC1_BASE, IRQ_EP93XX_VIC0, EP93XX_VIC1_VALID_IRQ_MASK, 0= ); - vic_init(EP93XX_VIC2_BASE, IRQ_EP93XX_VIC1, EP93XX_VIC2_VALID_IRQ_MASK, 0= ); -} - - -/************************************************************************* - * EP93xx System Controller Software Locked register handling - *************************************************************************/ - -/* - * syscon_swlock prevents anything else from writing to the syscon - * block while a software locked register is being written. - */ -static DEFINE_SPINLOCK(syscon_swlock); - -void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg) -{ - unsigned long flags; - - spin_lock_irqsave(&syscon_swlock, flags); - - __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); - __raw_writel(val, reg); - - spin_unlock_irqrestore(&syscon_swlock, flags); -} - -void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bit= s) -{ - unsigned long flags; - unsigned int val; - - spin_lock_irqsave(&syscon_swlock, flags); - - val =3D __raw_readl(EP93XX_SYSCON_DEVCFG); - val &=3D ~clear_bits; - val |=3D set_bits; - __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); - __raw_writel(val, EP93XX_SYSCON_DEVCFG); - - spin_unlock_irqrestore(&syscon_swlock, flags); -} - -/** - * ep93xx_chip_revision() - returns the EP93xx chip revision - * - * See "platform.h" for more information. - */ -unsigned int ep93xx_chip_revision(void) -{ - unsigned int v; - - v =3D __raw_readl(EP93XX_SYSCON_SYSCFG); - v &=3D EP93XX_SYSCON_SYSCFG_REV_MASK; - v >>=3D EP93XX_SYSCON_SYSCFG_REV_SHIFT; - return v; -} -EXPORT_SYMBOL_GPL(ep93xx_chip_revision); - -/************************************************************************* - * EP93xx GPIO - *************************************************************************/ -/* port A */ -static struct resource ep93xx_a_gpio_resources[] =3D { - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE, 0x04, "data"), - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x10, 0x04, "dir"), - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x90, 0x1c, "intr"), - DEFINE_RES_IRQ(IRQ_EP93XX_GPIO_AB), -}; - -static struct platform_device ep93xx_a_gpio =3D { - .name =3D "gpio-ep93xx", - .id =3D 0, - .num_resources =3D ARRAY_SIZE(ep93xx_a_gpio_resources), - .resource =3D ep93xx_a_gpio_resources, -}; - -/* port B */ -static struct resource ep93xx_b_gpio_resources[] =3D { - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x04, 0x04, "data"), - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x14, 0x04, "dir"), - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0xac, 0x1c, "intr"), - DEFINE_RES_IRQ(IRQ_EP93XX_GPIO_AB), -}; - -static struct platform_device ep93xx_b_gpio =3D { - .name =3D "gpio-ep93xx", - .id =3D 1, - .num_resources =3D ARRAY_SIZE(ep93xx_b_gpio_resources), - .resource =3D ep93xx_b_gpio_resources, -}; - -/* port C */ -static struct resource ep93xx_c_gpio_resources[] =3D { - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x08, 0x04, "data"), - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x18, 0x04, "dir"), -}; - -static struct platform_device ep93xx_c_gpio =3D { - .name =3D "gpio-ep93xx", - .id =3D 2, - .num_resources =3D ARRAY_SIZE(ep93xx_c_gpio_resources), - .resource =3D ep93xx_c_gpio_resources, -}; - -/* port D */ -static struct resource ep93xx_d_gpio_resources[] =3D { - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x0c, 0x04, "data"), - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x1c, 0x04, "dir"), -}; - -static struct platform_device ep93xx_d_gpio =3D { - .name =3D "gpio-ep93xx", - .id =3D 3, - .num_resources =3D ARRAY_SIZE(ep93xx_d_gpio_resources), - .resource =3D ep93xx_d_gpio_resources, -}; - -/* port E */ -static struct resource ep93xx_e_gpio_resources[] =3D { - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x20, 0x04, "data"), - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x24, 0x04, "dir"), -}; - -static struct platform_device ep93xx_e_gpio =3D { - .name =3D "gpio-ep93xx", - .id =3D 4, - .num_resources =3D ARRAY_SIZE(ep93xx_e_gpio_resources), - .resource =3D ep93xx_e_gpio_resources, -}; - -/* port F */ -static struct resource ep93xx_f_gpio_resources[] =3D { - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x30, 0x04, "data"), - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x34, 0x04, "dir"), - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x4c, 0x1c, "intr"), - DEFINE_RES_IRQ(IRQ_EP93XX_GPIO0MUX), - DEFINE_RES_IRQ(IRQ_EP93XX_GPIO1MUX), - DEFINE_RES_IRQ(IRQ_EP93XX_GPIO2MUX), - DEFINE_RES_IRQ(IRQ_EP93XX_GPIO3MUX), - DEFINE_RES_IRQ(IRQ_EP93XX_GPIO4MUX), - DEFINE_RES_IRQ(IRQ_EP93XX_GPIO5MUX), - DEFINE_RES_IRQ(IRQ_EP93XX_GPIO6MUX), - DEFINE_RES_IRQ(IRQ_EP93XX_GPIO7MUX), -}; - -static struct platform_device ep93xx_f_gpio =3D { - .name =3D "gpio-ep93xx", - .id =3D 5, - .num_resources =3D ARRAY_SIZE(ep93xx_f_gpio_resources), - .resource =3D ep93xx_f_gpio_resources, -}; - -/* port G */ -static struct resource ep93xx_g_gpio_resources[] =3D { - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x38, 0x04, "data"), - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x3c, 0x04, "dir"), -}; - -static struct platform_device ep93xx_g_gpio =3D { - .name =3D "gpio-ep93xx", - .id =3D 6, - .num_resources =3D ARRAY_SIZE(ep93xx_g_gpio_resources), - .resource =3D ep93xx_g_gpio_resources, -}; - -static struct platform_device *ep93xx_gpio_device[] __initdata =3D { - &ep93xx_a_gpio, - &ep93xx_b_gpio, - &ep93xx_c_gpio, - &ep93xx_d_gpio, - &ep93xx_e_gpio, - &ep93xx_f_gpio, - &ep93xx_g_gpio, -}; - -/************************************************************************* - * EP93xx peripheral handling - *************************************************************************/ -#define EP93XX_UART_MCR_OFFSET (0x0100) - -static void ep93xx_uart_set_mctrl(struct amba_device *dev, - void __iomem *base, unsigned int mctrl) -{ - unsigned int mcr; - - mcr =3D 0; - if (mctrl & TIOCM_RTS) - mcr |=3D 2; - if (mctrl & TIOCM_DTR) - mcr |=3D 1; - - __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET); -} - -static struct amba_pl010_data ep93xx_uart_data =3D { - .set_mctrl =3D ep93xx_uart_set_mctrl, -}; - -static AMBA_APB_DEVICE(uart1, "apb:uart1", 0x00041010, EP93XX_UART1_PHYS_B= ASE, - { IRQ_EP93XX_UART1 }, &ep93xx_uart_data); - -static AMBA_APB_DEVICE(uart2, "apb:uart2", 0x00041010, EP93XX_UART2_PHYS_B= ASE, - { IRQ_EP93XX_UART2 }, NULL); - -static AMBA_APB_DEVICE(uart3, "apb:uart3", 0x00041010, EP93XX_UART3_PHYS_B= ASE, - { IRQ_EP93XX_UART3 }, &ep93xx_uart_data); - -static struct resource ep93xx_rtc_resource[] =3D { - DEFINE_RES_MEM(EP93XX_RTC_PHYS_BASE, 0x10c), -}; - -static struct platform_device ep93xx_rtc_device =3D { - .name =3D "ep93xx-rtc", - .id =3D -1, - .num_resources =3D ARRAY_SIZE(ep93xx_rtc_resource), - .resource =3D ep93xx_rtc_resource, -}; - -/************************************************************************* - * EP93xx OHCI USB Host - *************************************************************************/ - -static struct clk *ep93xx_ohci_host_clock; - -static int ep93xx_ohci_power_on(struct platform_device *pdev) -{ - if (!ep93xx_ohci_host_clock) { - ep93xx_ohci_host_clock =3D devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(ep93xx_ohci_host_clock)) - return PTR_ERR(ep93xx_ohci_host_clock); - } - - return clk_prepare_enable(ep93xx_ohci_host_clock); -} - -static void ep93xx_ohci_power_off(struct platform_device *pdev) -{ - clk_disable(ep93xx_ohci_host_clock); -} - -static struct usb_ohci_pdata ep93xx_ohci_pdata =3D { - .power_on =3D ep93xx_ohci_power_on, - .power_off =3D ep93xx_ohci_power_off, - .power_suspend =3D ep93xx_ohci_power_off, -}; - -static struct resource ep93xx_ohci_resources[] =3D { - DEFINE_RES_MEM(EP93XX_USB_PHYS_BASE, 0x1000), - DEFINE_RES_IRQ(IRQ_EP93XX_USB), -}; - -static u64 ep93xx_ohci_dma_mask =3D DMA_BIT_MASK(32); - -static struct platform_device ep93xx_ohci_device =3D { - .name =3D "ohci-platform", - .id =3D -1, - .num_resources =3D ARRAY_SIZE(ep93xx_ohci_resources), - .resource =3D ep93xx_ohci_resources, - .dev =3D { - .dma_mask =3D &ep93xx_ohci_dma_mask, - .coherent_dma_mask =3D DMA_BIT_MASK(32), - .platform_data =3D &ep93xx_ohci_pdata, - }, -}; - -/************************************************************************* - * EP93xx physmap'ed flash - *************************************************************************/ -static struct physmap_flash_data ep93xx_flash_data; - -static struct resource ep93xx_flash_resource =3D { - .flags =3D IORESOURCE_MEM, -}; - -static struct platform_device ep93xx_flash =3D { - .name =3D "physmap-flash", - .id =3D 0, - .dev =3D { - .platform_data =3D &ep93xx_flash_data, - }, - .num_resources =3D 1, - .resource =3D &ep93xx_flash_resource, -}; - -/** - * ep93xx_register_flash() - Register the external flash device. - * @width: bank width in octets - * @start: resource start address - * @size: resource size - */ -void __init ep93xx_register_flash(unsigned int width, - resource_size_t start, resource_size_t size) -{ - ep93xx_flash_data.width =3D width; - - ep93xx_flash_resource.start =3D start; - ep93xx_flash_resource.end =3D start + size - 1; - - platform_device_register(&ep93xx_flash); -} - - -/************************************************************************* - * EP93xx ethernet peripheral handling - *************************************************************************/ -static struct ep93xx_eth_data ep93xx_eth_data; - -static struct resource ep93xx_eth_resource[] =3D { - DEFINE_RES_MEM(EP93XX_ETHERNET_PHYS_BASE, 0x10000), - DEFINE_RES_IRQ(IRQ_EP93XX_ETHERNET), -}; - -static u64 ep93xx_eth_dma_mask =3D DMA_BIT_MASK(32); - -static struct platform_device ep93xx_eth_device =3D { - .name =3D "ep93xx-eth", - .id =3D -1, - .dev =3D { - .platform_data =3D &ep93xx_eth_data, - .coherent_dma_mask =3D DMA_BIT_MASK(32), - .dma_mask =3D &ep93xx_eth_dma_mask, - }, - .num_resources =3D ARRAY_SIZE(ep93xx_eth_resource), - .resource =3D ep93xx_eth_resource, -}; - -/** - * ep93xx_register_eth - Register the built-in ethernet platform device. - * @data: platform specific ethernet configuration (__initdata) - * @copy_addr: flag indicating that the MAC address should be copied - * from the IndAd registers (as programmed by the bootloader) - */ -void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_add= r) -{ - if (copy_addr) - memcpy_fromio(data->dev_addr, EP93XX_ETHERNET_BASE + 0x50, 6); - - ep93xx_eth_data =3D *data; - platform_device_register(&ep93xx_eth_device); -} - - -/************************************************************************* - * EP93xx i2c peripheral handling - *************************************************************************/ - -/* All EP93xx devices use the same two GPIO pins for I2C bit-banging */ -static struct gpiod_lookup_table ep93xx_i2c_gpiod_table =3D { - .dev_id =3D "i2c-gpio.0", - .table =3D { - /* Use local offsets on gpiochip/port "G" */ - GPIO_LOOKUP_IDX("gpio-ep93xx.6", 1, NULL, 0, - GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - GPIO_LOOKUP_IDX("gpio-ep93xx.6", 0, NULL, 1, - GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - }, -}; - -static struct platform_device ep93xx_i2c_device =3D { - .name =3D "i2c-gpio", - .id =3D 0, - .dev =3D { - .platform_data =3D NULL, - }, -}; - -/** - * ep93xx_register_i2c - Register the i2c platform device. - * @devices: platform specific i2c bus device information (__initdata) - * @num: the number of devices on the i2c bus - */ -void __init ep93xx_register_i2c(struct i2c_board_info *devices, int num) -{ - /* - * FIXME: this just sets the two pins as non-opendrain, as no - * platforms tries to do that anyway. Flag the applicable lines - * as open drain in the GPIO_LOOKUP above and the driver or - * gpiolib will handle open drain/open drain emulation as need - * be. Right now i2c-gpio emulates open drain which is not - * optimal. - */ - __raw_writel((0 << 1) | (0 << 0), - EP93XX_GPIO_EEDRIVE); - - i2c_register_board_info(0, devices, num); - gpiod_add_lookup_table(&ep93xx_i2c_gpiod_table); - platform_device_register(&ep93xx_i2c_device); -} - -/************************************************************************* - * EP93xx SPI peripheral handling - *************************************************************************/ -static struct ep93xx_spi_info ep93xx_spi_master_data; - -static struct resource ep93xx_spi_resources[] =3D { - DEFINE_RES_MEM(EP93XX_SPI_PHYS_BASE, 0x18), - DEFINE_RES_IRQ(IRQ_EP93XX_SSP), -}; - -static u64 ep93xx_spi_dma_mask =3D DMA_BIT_MASK(32); - -static struct platform_device ep93xx_spi_device =3D { - .name =3D "ep93xx-spi", - .id =3D 0, - .dev =3D { - .platform_data =3D &ep93xx_spi_master_data, - .coherent_dma_mask =3D DMA_BIT_MASK(32), - .dma_mask =3D &ep93xx_spi_dma_mask, - }, - .num_resources =3D ARRAY_SIZE(ep93xx_spi_resources), - .resource =3D ep93xx_spi_resources, -}; - -/** - * ep93xx_register_spi() - registers spi platform device - * @info: ep93xx board specific spi master info (__initdata) - * @devices: SPI devices to register (__initdata) - * @num: number of SPI devices to register - * - * This function registers platform device for the EP93xx SPI controller a= nd - * also makes sure that SPI pins are muxed so that I2S is not using those = pins. - */ -void __init ep93xx_register_spi(struct ep93xx_spi_info *info, - struct spi_board_info *devices, int num) -{ - /* - * When SPI is used, we need to make sure that I2S is muxed off from - * SPI pins. - */ - ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONSSP); - - ep93xx_spi_master_data =3D *info; - spi_register_board_info(devices, num); - platform_device_register(&ep93xx_spi_device); -} - -/************************************************************************* - * EP93xx LEDs - *************************************************************************/ -static const struct gpio_led ep93xx_led_pins[] __initconst =3D { - { - .name =3D "platform:grled", - }, { - .name =3D "platform:rdled", - }, -}; - -static const struct gpio_led_platform_data ep93xx_led_data __initconst =3D= { - .num_leds =3D ARRAY_SIZE(ep93xx_led_pins), - .leds =3D ep93xx_led_pins, -}; - -static struct gpiod_lookup_table ep93xx_leds_gpio_table =3D { - .dev_id =3D "leds-gpio", - .table =3D { - /* Use local offsets on gpiochip/port "E" */ - GPIO_LOOKUP_IDX("gpio-ep93xx.4", 0, NULL, 0, GPIO_ACTIVE_HIGH), - GPIO_LOOKUP_IDX("gpio-ep93xx.4", 1, NULL, 1, GPIO_ACTIVE_HIGH), - { } - }, -}; - -/************************************************************************* - * EP93xx pwm peripheral handling - *************************************************************************/ -static struct resource ep93xx_pwm0_resource[] =3D { - DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE, 0x10), -}; - -static struct platform_device ep93xx_pwm0_device =3D { - .name =3D "ep93xx-pwm", - .id =3D 0, - .num_resources =3D ARRAY_SIZE(ep93xx_pwm0_resource), - .resource =3D ep93xx_pwm0_resource, -}; - -static struct resource ep93xx_pwm1_resource[] =3D { - DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE + 0x20, 0x10), -}; - -static struct platform_device ep93xx_pwm1_device =3D { - .name =3D "ep93xx-pwm", - .id =3D 1, - .num_resources =3D ARRAY_SIZE(ep93xx_pwm1_resource), - .resource =3D ep93xx_pwm1_resource, -}; - -void __init ep93xx_register_pwm(int pwm0, int pwm1) -{ - if (pwm0) - platform_device_register(&ep93xx_pwm0_device); - - /* NOTE: EP9307 does not have PWMOUT1 (pin EGPIO14) */ - if (pwm1) - platform_device_register(&ep93xx_pwm1_device); -} - -int ep93xx_pwm_acquire_gpio(struct platform_device *pdev) -{ - int err; - - if (pdev->id =3D=3D 0) { - err =3D 0; - } else if (pdev->id =3D=3D 1) { - err =3D gpio_request(EP93XX_GPIO_LINE_EGPIO14, - dev_name(&pdev->dev)); - if (err) - return err; - err =3D gpio_direction_output(EP93XX_GPIO_LINE_EGPIO14, 0); - if (err) - goto fail; - - /* PWM 1 output on EGPIO[14] */ - ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_PONG); - } else { - err =3D -ENODEV; - } - - return err; - -fail: - gpio_free(EP93XX_GPIO_LINE_EGPIO14); - return err; -} -EXPORT_SYMBOL(ep93xx_pwm_acquire_gpio); - -void ep93xx_pwm_release_gpio(struct platform_device *pdev) -{ - if (pdev->id =3D=3D 1) { - gpio_direction_input(EP93XX_GPIO_LINE_EGPIO14); - gpio_free(EP93XX_GPIO_LINE_EGPIO14); - - /* EGPIO[14] used for GPIO */ - ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_PONG); - } -} -EXPORT_SYMBOL(ep93xx_pwm_release_gpio); - - -/************************************************************************* - * EP93xx video peripheral handling - *************************************************************************/ -static struct ep93xxfb_mach_info ep93xxfb_data; - -static struct resource ep93xx_fb_resource[] =3D { - DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE, 0x800), -}; - -static struct platform_device ep93xx_fb_device =3D { - .name =3D "ep93xx-fb", - .id =3D -1, - .dev =3D { - .platform_data =3D &ep93xxfb_data, - .coherent_dma_mask =3D DMA_BIT_MASK(32), - .dma_mask =3D &ep93xx_fb_device.dev.coherent_dma_mask, - }, - .num_resources =3D ARRAY_SIZE(ep93xx_fb_resource), - .resource =3D ep93xx_fb_resource, -}; - -/* The backlight use a single register in the framebuffer's register space= */ -#define EP93XX_RASTER_REG_BRIGHTNESS 0x20 - -static struct resource ep93xx_bl_resources[] =3D { - DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE + - EP93XX_RASTER_REG_BRIGHTNESS, 0x04), -}; - -static struct platform_device ep93xx_bl_device =3D { - .name =3D "ep93xx-bl", - .id =3D -1, - .num_resources =3D ARRAY_SIZE(ep93xx_bl_resources), - .resource =3D ep93xx_bl_resources, -}; - -/** - * ep93xx_register_fb - Register the framebuffer platform device. - * @data: platform specific framebuffer configuration (__initdata) - */ -void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data) -{ - ep93xxfb_data =3D *data; - platform_device_register(&ep93xx_fb_device); - platform_device_register(&ep93xx_bl_device); -} - - -/************************************************************************* - * EP93xx matrix keypad peripheral handling - *************************************************************************/ -static struct ep93xx_keypad_platform_data ep93xx_keypad_data; - -static struct resource ep93xx_keypad_resource[] =3D { - DEFINE_RES_MEM(EP93XX_KEY_MATRIX_PHYS_BASE, 0x0c), - DEFINE_RES_IRQ(IRQ_EP93XX_KEY), -}; - -static struct platform_device ep93xx_keypad_device =3D { - .name =3D "ep93xx-keypad", - .id =3D -1, - .dev =3D { - .platform_data =3D &ep93xx_keypad_data, - }, - .num_resources =3D ARRAY_SIZE(ep93xx_keypad_resource), - .resource =3D ep93xx_keypad_resource, -}; - -/** - * ep93xx_register_keypad - Register the keypad platform device. - * @data: platform specific keypad configuration (__initdata) - */ -void __init ep93xx_register_keypad(struct ep93xx_keypad_platform_data *dat= a) -{ - ep93xx_keypad_data =3D *data; - platform_device_register(&ep93xx_keypad_device); -} - -int ep93xx_keypad_acquire_gpio(struct platform_device *pdev) -{ - int err; - int i; - - for (i =3D 0; i < 8; i++) { - err =3D gpio_request(EP93XX_GPIO_LINE_C(i), dev_name(&pdev->dev)); - if (err) - goto fail_gpio_c; - err =3D gpio_request(EP93XX_GPIO_LINE_D(i), dev_name(&pdev->dev)); - if (err) - goto fail_gpio_d; - } - - /* Enable the keypad controller; GPIO ports C and D used for keypad */ - ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_KEYS | - EP93XX_SYSCON_DEVCFG_GONK); - - return 0; - -fail_gpio_d: - gpio_free(EP93XX_GPIO_LINE_C(i)); -fail_gpio_c: - for (--i; i >=3D 0; --i) { - gpio_free(EP93XX_GPIO_LINE_C(i)); - gpio_free(EP93XX_GPIO_LINE_D(i)); - } - return err; -} -EXPORT_SYMBOL(ep93xx_keypad_acquire_gpio); - -void ep93xx_keypad_release_gpio(struct platform_device *pdev) -{ - int i; - - for (i =3D 0; i < 8; i++) { - gpio_free(EP93XX_GPIO_LINE_C(i)); - gpio_free(EP93XX_GPIO_LINE_D(i)); - } - - /* Disable the keypad controller; GPIO ports C and D used for GPIO */ - ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS | - EP93XX_SYSCON_DEVCFG_GONK); -} -EXPORT_SYMBOL(ep93xx_keypad_release_gpio); - -/************************************************************************* - * EP93xx I2S audio peripheral handling - *************************************************************************/ -static struct resource ep93xx_i2s_resource[] =3D { - DEFINE_RES_MEM(EP93XX_I2S_PHYS_BASE, 0x100), - DEFINE_RES_IRQ(IRQ_EP93XX_SAI), -}; - -static struct platform_device ep93xx_i2s_device =3D { - .name =3D "ep93xx-i2s", - .id =3D -1, - .num_resources =3D ARRAY_SIZE(ep93xx_i2s_resource), - .resource =3D ep93xx_i2s_resource, -}; - -static struct platform_device ep93xx_pcm_device =3D { - .name =3D "ep93xx-pcm-audio", - .id =3D -1, -}; - -void __init ep93xx_register_i2s(void) -{ - platform_device_register(&ep93xx_i2s_device); - platform_device_register(&ep93xx_pcm_device); -} - -#define EP93XX_SYSCON_DEVCFG_I2S_MASK (EP93XX_SYSCON_DEVCFG_I2SONSSP | \ - EP93XX_SYSCON_DEVCFG_I2SONAC97) - -#define EP93XX_I2SCLKDIV_MASK (EP93XX_SYSCON_I2SCLKDIV_ORIDE | \ - EP93XX_SYSCON_I2SCLKDIV_SPOL) - -int ep93xx_i2s_acquire(void) -{ - unsigned val; - - ep93xx_devcfg_set_clear(EP93XX_SYSCON_DEVCFG_I2SONAC97, - EP93XX_SYSCON_DEVCFG_I2S_MASK); - - /* - * This is potentially racy with the clock api for i2s_mclk, sclk and=20 - * lrclk. Since the i2s driver is the only user of those clocks we - * rely on it to prevent parallel use of this function and the=20 - * clock api for the i2s clocks. - */ - val =3D __raw_readl(EP93XX_SYSCON_I2SCLKDIV); - val &=3D ~EP93XX_I2SCLKDIV_MASK; - val |=3D EP93XX_SYSCON_I2SCLKDIV_ORIDE | EP93XX_SYSCON_I2SCLKDIV_SPOL; - ep93xx_syscon_swlocked_write(val, EP93XX_SYSCON_I2SCLKDIV); - - return 0; -} -EXPORT_SYMBOL(ep93xx_i2s_acquire); - -void ep93xx_i2s_release(void) -{ - ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2S_MASK); -} -EXPORT_SYMBOL(ep93xx_i2s_release); - -/************************************************************************* - * EP93xx AC97 audio peripheral handling - *************************************************************************/ -static struct resource ep93xx_ac97_resources[] =3D { - DEFINE_RES_MEM(EP93XX_AAC_PHYS_BASE, 0xac), - DEFINE_RES_IRQ(IRQ_EP93XX_AACINTR), -}; - -static struct platform_device ep93xx_ac97_device =3D { - .name =3D "ep93xx-ac97", - .id =3D -1, - .num_resources =3D ARRAY_SIZE(ep93xx_ac97_resources), - .resource =3D ep93xx_ac97_resources, -}; - -void __init ep93xx_register_ac97(void) -{ - /* - * Make sure that the AC97 pins are not used by I2S. - */ - ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONAC97); - - platform_device_register(&ep93xx_ac97_device); - platform_device_register(&ep93xx_pcm_device); -} - -/************************************************************************* - * EP93xx Watchdog - *************************************************************************/ -static struct resource ep93xx_wdt_resources[] =3D { - DEFINE_RES_MEM(EP93XX_WATCHDOG_PHYS_BASE, 0x08), -}; - -static struct platform_device ep93xx_wdt_device =3D { - .name =3D "ep93xx-wdt", - .id =3D -1, - .num_resources =3D ARRAY_SIZE(ep93xx_wdt_resources), - .resource =3D ep93xx_wdt_resources, -}; - -/************************************************************************* - * EP93xx IDE - *************************************************************************/ -static struct resource ep93xx_ide_resources[] =3D { - DEFINE_RES_MEM(EP93XX_IDE_PHYS_BASE, 0x38), - DEFINE_RES_IRQ(IRQ_EP93XX_EXT3), -}; - -static struct platform_device ep93xx_ide_device =3D { - .name =3D "ep93xx-ide", - .id =3D -1, - .dev =3D { - .dma_mask =3D &ep93xx_ide_device.dev.coherent_dma_mask, - .coherent_dma_mask =3D DMA_BIT_MASK(32), - }, - .num_resources =3D ARRAY_SIZE(ep93xx_ide_resources), - .resource =3D ep93xx_ide_resources, -}; - -void __init ep93xx_register_ide(void) -{ - platform_device_register(&ep93xx_ide_device); -} - -int ep93xx_ide_acquire_gpio(struct platform_device *pdev) -{ - int err; - int i; - - err =3D gpio_request(EP93XX_GPIO_LINE_EGPIO2, dev_name(&pdev->dev)); - if (err) - return err; - err =3D gpio_request(EP93XX_GPIO_LINE_EGPIO15, dev_name(&pdev->dev)); - if (err) - goto fail_egpio15; - for (i =3D 2; i < 8; i++) { - err =3D gpio_request(EP93XX_GPIO_LINE_E(i), dev_name(&pdev->dev)); - if (err) - goto fail_gpio_e; - } - for (i =3D 4; i < 8; i++) { - err =3D gpio_request(EP93XX_GPIO_LINE_G(i), dev_name(&pdev->dev)); - if (err) - goto fail_gpio_g; - } - for (i =3D 0; i < 8; i++) { - err =3D gpio_request(EP93XX_GPIO_LINE_H(i), dev_name(&pdev->dev)); - if (err) - goto fail_gpio_h; - } - - /* GPIO ports E[7:2], G[7:4] and H used by IDE */ - ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_EONIDE | - EP93XX_SYSCON_DEVCFG_GONIDE | - EP93XX_SYSCON_DEVCFG_HONIDE); - return 0; - -fail_gpio_h: - for (--i; i >=3D 0; --i) - gpio_free(EP93XX_GPIO_LINE_H(i)); - i =3D 8; -fail_gpio_g: - for (--i; i >=3D 4; --i) - gpio_free(EP93XX_GPIO_LINE_G(i)); - i =3D 8; -fail_gpio_e: - for (--i; i >=3D 2; --i) - gpio_free(EP93XX_GPIO_LINE_E(i)); - gpio_free(EP93XX_GPIO_LINE_EGPIO15); -fail_egpio15: - gpio_free(EP93XX_GPIO_LINE_EGPIO2); - return err; -} -EXPORT_SYMBOL(ep93xx_ide_acquire_gpio); - -void ep93xx_ide_release_gpio(struct platform_device *pdev) -{ - int i; - - for (i =3D 2; i < 8; i++) - gpio_free(EP93XX_GPIO_LINE_E(i)); - for (i =3D 4; i < 8; i++) - gpio_free(EP93XX_GPIO_LINE_G(i)); - for (i =3D 0; i < 8; i++) - gpio_free(EP93XX_GPIO_LINE_H(i)); - gpio_free(EP93XX_GPIO_LINE_EGPIO15); - gpio_free(EP93XX_GPIO_LINE_EGPIO2); - - - /* GPIO ports E[7:2], G[7:4] and H used by GPIO */ - ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_EONIDE | - EP93XX_SYSCON_DEVCFG_GONIDE | - EP93XX_SYSCON_DEVCFG_HONIDE); -} -EXPORT_SYMBOL(ep93xx_ide_release_gpio); - -/************************************************************************* - * EP93xx ADC - *************************************************************************/ -static struct resource ep93xx_adc_resources[] =3D { - DEFINE_RES_MEM(EP93XX_ADC_PHYS_BASE, 0x28), - DEFINE_RES_IRQ(IRQ_EP93XX_TOUCH), -}; - -static struct platform_device ep93xx_adc_device =3D { - .name =3D "ep93xx-adc", - .id =3D -1, - .num_resources =3D ARRAY_SIZE(ep93xx_adc_resources), - .resource =3D ep93xx_adc_resources, -}; - -void __init ep93xx_register_adc(void) -{ - /* Power up ADC, deactivate Touch Screen Controller */ - ep93xx_devcfg_set_clear(EP93XX_SYSCON_DEVCFG_TIN, - EP93XX_SYSCON_DEVCFG_ADCPD); - - platform_device_register(&ep93xx_adc_device); -} - -/************************************************************************* - * EP93xx Security peripheral - *************************************************************************/ - -/* - * The Maverick Key is 256 bits of micro fuses blown at the factory during - * manufacturing to uniquely identify a part. - * - * See: http://arm.cirrus.com/forum/viewtopic.php?t=3D486&highlight=3Dmave= rick+key - */ -#define EP93XX_SECURITY_REG(x) (EP93XX_SECURITY_BASE + (x)) -#define EP93XX_SECURITY_SECFLG EP93XX_SECURITY_REG(0x2400) -#define EP93XX_SECURITY_FUSEFLG EP93XX_SECURITY_REG(0x2410) -#define EP93XX_SECURITY_UNIQID EP93XX_SECURITY_REG(0x2440) -#define EP93XX_SECURITY_UNIQCHK EP93XX_SECURITY_REG(0x2450) -#define EP93XX_SECURITY_UNIQVAL EP93XX_SECURITY_REG(0x2460) -#define EP93XX_SECURITY_SECID1 EP93XX_SECURITY_REG(0x2500) -#define EP93XX_SECURITY_SECID2 EP93XX_SECURITY_REG(0x2504) -#define EP93XX_SECURITY_SECCHK1 EP93XX_SECURITY_REG(0x2520) -#define EP93XX_SECURITY_SECCHK2 EP93XX_SECURITY_REG(0x2524) -#define EP93XX_SECURITY_UNIQID2 EP93XX_SECURITY_REG(0x2700) -#define EP93XX_SECURITY_UNIQID3 EP93XX_SECURITY_REG(0x2704) -#define EP93XX_SECURITY_UNIQID4 EP93XX_SECURITY_REG(0x2708) -#define EP93XX_SECURITY_UNIQID5 EP93XX_SECURITY_REG(0x270c) - -static char ep93xx_soc_id[33]; - -static const char __init *ep93xx_get_soc_id(void) -{ - unsigned int id, id2, id3, id4, id5; - - if (__raw_readl(EP93XX_SECURITY_UNIQVAL) !=3D 1) - return "bad Hamming code"; - - id =3D __raw_readl(EP93XX_SECURITY_UNIQID); - id2 =3D __raw_readl(EP93XX_SECURITY_UNIQID2); - id3 =3D __raw_readl(EP93XX_SECURITY_UNIQID3); - id4 =3D __raw_readl(EP93XX_SECURITY_UNIQID4); - id5 =3D __raw_readl(EP93XX_SECURITY_UNIQID5); - - if (id !=3D id2) - return "invalid"; - - /* Toss the unique ID into the entropy pool */ - add_device_randomness(&id2, 4); - add_device_randomness(&id3, 4); - add_device_randomness(&id4, 4); - add_device_randomness(&id5, 4); - - snprintf(ep93xx_soc_id, sizeof(ep93xx_soc_id), - "%08x%08x%08x%08x", id2, id3, id4, id5); - - return ep93xx_soc_id; -} - -static const char __init *ep93xx_get_soc_rev(void) -{ - int rev =3D ep93xx_chip_revision(); - - switch (rev) { - case EP93XX_CHIP_REV_D0: - return "D0"; - case EP93XX_CHIP_REV_D1: - return "D1"; - case EP93XX_CHIP_REV_E0: - return "E0"; - case EP93XX_CHIP_REV_E1: - return "E1"; - case EP93XX_CHIP_REV_E2: - return "E2"; - default: - return "unknown"; - } -} - -static const char __init *ep93xx_get_machine_name(void) -{ - return kasprintf(GFP_KERNEL,"%s", machine_desc->name); -} - -static struct device __init *ep93xx_init_soc(void) -{ - struct soc_device_attribute *soc_dev_attr; - struct soc_device *soc_dev; - - soc_dev_attr =3D kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); - if (!soc_dev_attr) - return NULL; - - soc_dev_attr->machine =3D ep93xx_get_machine_name(); - soc_dev_attr->family =3D "Cirrus Logic EP93xx"; - soc_dev_attr->revision =3D ep93xx_get_soc_rev(); - soc_dev_attr->soc_id =3D ep93xx_get_soc_id(); - - soc_dev =3D soc_device_register(soc_dev_attr); - if (IS_ERR(soc_dev)) { - kfree(soc_dev_attr->machine); - kfree(soc_dev_attr); - return NULL; - } - - return soc_device_to_device(soc_dev); -} - -struct device __init *ep93xx_init_devices(void) -{ - struct device *parent; - int i; - - /* Disallow access to MaverickCrunch initially */ - ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA); - - /* Default all ports to GPIO */ - ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS | - EP93XX_SYSCON_DEVCFG_GONK | - EP93XX_SYSCON_DEVCFG_EONIDE | - EP93XX_SYSCON_DEVCFG_GONIDE | - EP93XX_SYSCON_DEVCFG_HONIDE); - - parent =3D ep93xx_init_soc(); - - /* Get the GPIO working early, other devices need it */ - for (i =3D 0; i < ARRAY_SIZE(ep93xx_gpio_device); i++) - platform_device_register(ep93xx_gpio_device[i]); - - amba_device_register(&uart1_device, &iomem_resource); - amba_device_register(&uart2_device, &iomem_resource); - amba_device_register(&uart3_device, &iomem_resource); - - platform_device_register(&ep93xx_rtc_device); - platform_device_register(&ep93xx_ohci_device); - platform_device_register(&ep93xx_wdt_device); - - gpiod_add_lookup_table(&ep93xx_leds_gpio_table); - gpio_led_register_device(-1, &ep93xx_led_data); - - return parent; -} - -void ep93xx_restart(enum reboot_mode mode, const char *cmd) -{ - /* - * Set then clear the SWRST bit to initiate a software reset - */ - ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_SWRST); - ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_SWRST); - - while (1) - ; -} diff --git a/arch/arm/mach-ep93xx/dma.c b/arch/arm/mach-ep93xx/dma.c deleted file mode 100644 index 74515acab8ef..000000000000 --- a/arch/arm/mach-ep93xx/dma.c +++ /dev/null @@ -1,114 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-ep93xx/dma.c - * - * Platform support code for the EP93xx dmaengine driver. - * - * Copyright (C) 2011 Mika Westerberg - * - * This work is based on the original dma-m2p implementation with - * following copyrights: - * - * Copyright (C) 2006 Lennert Buytenhek - * Copyright (C) 2006 Applied Data Systems - * Copyright (C) 2009 Ryan Mallon - */ - -#include -#include -#include -#include -#include -#include - -#include -#include "hardware.h" - -#include "soc.h" - -#define DMA_CHANNEL(_name, _base, _irq) \ - { .name =3D (_name), .base =3D (_base), .irq =3D (_irq) } - -/* - * DMA M2P channels. - * - * On the EP93xx chip the following peripherals my be allocated to the 10 - * Memory to Internal Peripheral (M2P) channels (5 transmit + 5 receive). - * - * I2S contains 3 Tx and 3 Rx DMA Channels - * AAC contains 3 Tx and 3 Rx DMA Channels - * UART1 contains 1 Tx and 1 Rx DMA Channels - * UART2 contains 1 Tx and 1 Rx DMA Channels - * UART3 contains 1 Tx and 1 Rx DMA Channels - * IrDA contains 1 Tx and 1 Rx DMA Channels - * - * Registers are mapped statically in ep93xx_map_io(). - */ -static struct ep93xx_dma_chan_data ep93xx_dma_m2p_channels[] =3D { - DMA_CHANNEL("m2p0", EP93XX_DMA_BASE + 0x0000, IRQ_EP93XX_DMAM2P0), - DMA_CHANNEL("m2p1", EP93XX_DMA_BASE + 0x0040, IRQ_EP93XX_DMAM2P1), - DMA_CHANNEL("m2p2", EP93XX_DMA_BASE + 0x0080, IRQ_EP93XX_DMAM2P2), - DMA_CHANNEL("m2p3", EP93XX_DMA_BASE + 0x00c0, IRQ_EP93XX_DMAM2P3), - DMA_CHANNEL("m2p4", EP93XX_DMA_BASE + 0x0240, IRQ_EP93XX_DMAM2P4), - DMA_CHANNEL("m2p5", EP93XX_DMA_BASE + 0x0200, IRQ_EP93XX_DMAM2P5), - DMA_CHANNEL("m2p6", EP93XX_DMA_BASE + 0x02c0, IRQ_EP93XX_DMAM2P6), - DMA_CHANNEL("m2p7", EP93XX_DMA_BASE + 0x0280, IRQ_EP93XX_DMAM2P7), - DMA_CHANNEL("m2p8", EP93XX_DMA_BASE + 0x0340, IRQ_EP93XX_DMAM2P8), - DMA_CHANNEL("m2p9", EP93XX_DMA_BASE + 0x0300, IRQ_EP93XX_DMAM2P9), -}; - -static struct ep93xx_dma_platform_data ep93xx_dma_m2p_data =3D { - .channels =3D ep93xx_dma_m2p_channels, - .num_channels =3D ARRAY_SIZE(ep93xx_dma_m2p_channels), -}; - -static u64 ep93xx_dma_m2p_mask =3D DMA_BIT_MASK(32); - -static struct platform_device ep93xx_dma_m2p_device =3D { - .name =3D "ep93xx-dma-m2p", - .id =3D -1, - .dev =3D { - .platform_data =3D &ep93xx_dma_m2p_data, - .dma_mask =3D &ep93xx_dma_m2p_mask, - .coherent_dma_mask =3D DMA_BIT_MASK(32), - }, -}; - -/* - * DMA M2M channels. - * - * There are 2 M2M channels which support memcpy/memset and in addition si= mple - * hardware requests from/to SSP and IDE. We do not implement an external - * hardware requests. - * - * Registers are mapped statically in ep93xx_map_io(). - */ -static struct ep93xx_dma_chan_data ep93xx_dma_m2m_channels[] =3D { - DMA_CHANNEL("m2m0", EP93XX_DMA_BASE + 0x0100, IRQ_EP93XX_DMAM2M0), - DMA_CHANNEL("m2m1", EP93XX_DMA_BASE + 0x0140, IRQ_EP93XX_DMAM2M1), -}; - -static struct ep93xx_dma_platform_data ep93xx_dma_m2m_data =3D { - .channels =3D ep93xx_dma_m2m_channels, - .num_channels =3D ARRAY_SIZE(ep93xx_dma_m2m_channels), -}; - -static u64 ep93xx_dma_m2m_mask =3D DMA_BIT_MASK(32); - -static struct platform_device ep93xx_dma_m2m_device =3D { - .name =3D "ep93xx-dma-m2m", - .id =3D -1, - .dev =3D { - .platform_data =3D &ep93xx_dma_m2m_data, - .dma_mask =3D &ep93xx_dma_m2m_mask, - .coherent_dma_mask =3D DMA_BIT_MASK(32), - }, -}; - -static int __init ep93xx_dma_init(void) -{ - platform_device_register(&ep93xx_dma_m2p_device); - platform_device_register(&ep93xx_dma_m2m_device); - return 0; -} -arch_initcall(ep93xx_dma_init); diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c deleted file mode 100644 index c1e880946f72..000000000000 --- a/arch/arm/mach-ep93xx/edb93xx.c +++ /dev/null @@ -1,344 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-ep93xx/edb93xx.c - * Cirrus Logic EDB93xx Development Board support. - * - * EDB93XX, EDB9301, EDB9307A - * Copyright (C) 2008-2009 H Hartley Sweeten - * - * EDB9302 - * Copyright (C) 2006 George Kashperko - * - * EDB9302A, EDB9315, EDB9315A - * Copyright (C) 2006 Lennert Buytenhek - * - * EDB9307 - * Copyright (C) 2007 Herbert Valerio Riedel - * - * EDB9312 - * Copyright (C) 2006 Infosys Technologies Limited - * Toufeeq Hussain - */ - -#include -#include -#include -#include -#include -#include - -#include - -#include "hardware.h" -#include -#include -#include "gpio-ep93xx.h" - -#include -#include - -#include "soc.h" - -static void __init edb93xx_register_flash(void) -{ - if (machine_is_edb9307() || machine_is_edb9312() || - machine_is_edb9315()) { - ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M); - } else { - ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M); - } -} - -static struct ep93xx_eth_data __initdata edb93xx_eth_data =3D { - .phy_id =3D 1, -}; - - -/************************************************************************* - * EDB93xx i2c peripheral handling - *************************************************************************/ - -static struct i2c_board_info __initdata edb93xxa_i2c_board_info[] =3D { - { - I2C_BOARD_INFO("isl1208", 0x6f), - }, -}; - -static struct i2c_board_info __initdata edb93xx_i2c_board_info[] =3D { - { - I2C_BOARD_INFO("ds1337", 0x68), - }, -}; - -static void __init edb93xx_register_i2c(void) -{ - if (machine_is_edb9302a() || machine_is_edb9307a() || - machine_is_edb9315a()) { - ep93xx_register_i2c(edb93xxa_i2c_board_info, - ARRAY_SIZE(edb93xxa_i2c_board_info)); - } else if (machine_is_edb9302() || machine_is_edb9307() - || machine_is_edb9312() || machine_is_edb9315()) { - ep93xx_register_i2c(edb93xx_i2c_board_info, - ARRAY_SIZE(edb93xx_i2c_board_info)); - } -} - - -/************************************************************************* - * EDB93xx SPI peripheral handling - *************************************************************************/ -static struct cs4271_platform_data edb93xx_cs4271_data =3D { - .gpio_nreset =3D -EINVAL, /* filled in later */ -}; - -static struct spi_board_info edb93xx_spi_board_info[] __initdata =3D { - { - .modalias =3D "cs4271", - .platform_data =3D &edb93xx_cs4271_data, - .max_speed_hz =3D 6000000, - .bus_num =3D 0, - .chip_select =3D 0, - .mode =3D SPI_MODE_3, - }, -}; - -static struct gpiod_lookup_table edb93xx_spi_cs_gpio_table =3D { - .dev_id =3D "spi0", - .table =3D { - GPIO_LOOKUP("gpio-ep93xx.0", 6, "cs", GPIO_ACTIVE_LOW), - { }, - }, -}; - -static struct ep93xx_spi_info edb93xx_spi_info __initdata =3D { - /* Intentionally left blank */ -}; - -static void __init edb93xx_register_spi(void) -{ - if (machine_is_edb9301() || machine_is_edb9302()) - edb93xx_cs4271_data.gpio_nreset =3D EP93XX_GPIO_LINE_EGPIO1; - else if (machine_is_edb9302a() || machine_is_edb9307a()) - edb93xx_cs4271_data.gpio_nreset =3D EP93XX_GPIO_LINE_H(2); - else if (machine_is_edb9315a()) - edb93xx_cs4271_data.gpio_nreset =3D EP93XX_GPIO_LINE_EGPIO14; - - gpiod_add_lookup_table(&edb93xx_spi_cs_gpio_table); - ep93xx_register_spi(&edb93xx_spi_info, edb93xx_spi_board_info, - ARRAY_SIZE(edb93xx_spi_board_info)); -} - - -/************************************************************************* - * EDB93xx I2S - *************************************************************************/ -static struct platform_device edb93xx_audio_device =3D { - .name =3D "edb93xx-audio", - .id =3D -1, -}; - -static int __init edb93xx_has_audio(void) -{ - return (machine_is_edb9301() || machine_is_edb9302() || - machine_is_edb9302a() || machine_is_edb9307a() || - machine_is_edb9315a()); -} - -static void __init edb93xx_register_i2s(void) -{ - if (edb93xx_has_audio()) { - ep93xx_register_i2s(); - platform_device_register(&edb93xx_audio_device); - } -} - - -/************************************************************************* - * EDB93xx pwm - *************************************************************************/ -static void __init edb93xx_register_pwm(void) -{ - if (machine_is_edb9301() || - machine_is_edb9302() || machine_is_edb9302a()) { - /* EP9301 and EP9302 only have pwm.1 (EGPIO14) */ - ep93xx_register_pwm(0, 1); - } else if (machine_is_edb9307() || machine_is_edb9307a()) { - /* EP9307 only has pwm.0 (PWMOUT) */ - ep93xx_register_pwm(1, 0); - } else { - /* EP9312 and EP9315 have both */ - ep93xx_register_pwm(1, 1); - } -} - - -/************************************************************************* - * EDB93xx framebuffer - *************************************************************************/ -static struct ep93xxfb_mach_info __initdata edb93xxfb_info =3D { - .flags =3D 0, -}; - -static int __init edb93xx_has_fb(void) -{ - /* These platforms have an ep93xx with video capability */ - return machine_is_edb9307() || machine_is_edb9307a() || - machine_is_edb9312() || machine_is_edb9315() || - machine_is_edb9315a(); -} - -static void __init edb93xx_register_fb(void) -{ - if (!edb93xx_has_fb()) - return; - - if (machine_is_edb9307a() || machine_is_edb9315a()) - edb93xxfb_info.flags |=3D EP93XXFB_USE_SDCSN0; - else - edb93xxfb_info.flags |=3D EP93XXFB_USE_SDCSN3; - - ep93xx_register_fb(&edb93xxfb_info); -} - - -/************************************************************************* - * EDB93xx IDE - *************************************************************************/ -static int __init edb93xx_has_ide(void) -{ - /* - * Although EDB9312 and EDB9315 do have IDE capability, they have - * INTRQ line wired as pull-up, which makes using IDE interface - * problematic. - */ - return machine_is_edb9312() || machine_is_edb9315() || - machine_is_edb9315a(); -} - -static void __init edb93xx_register_ide(void) -{ - if (!edb93xx_has_ide()) - return; - - ep93xx_register_ide(); -} - - -static void __init edb93xx_init_machine(void) -{ - ep93xx_init_devices(); - edb93xx_register_flash(); - ep93xx_register_eth(&edb93xx_eth_data, 1); - edb93xx_register_i2c(); - edb93xx_register_spi(); - edb93xx_register_i2s(); - edb93xx_register_pwm(); - edb93xx_register_fb(); - edb93xx_register_ide(); - ep93xx_register_adc(); -} - - -#ifdef CONFIG_MACH_EDB9301 -MACHINE_START(EDB9301, "Cirrus Logic EDB9301 Evaluation Board") - /* Maintainer: H Hartley Sweeten */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS, - .map_io =3D ep93xx_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D edb93xx_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_EDB9302 -MACHINE_START(EDB9302, "Cirrus Logic EDB9302 Evaluation Board") - /* Maintainer: George Kashperko */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS, - .map_io =3D ep93xx_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D edb93xx_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_EDB9302A -MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board") - /* Maintainer: Lennert Buytenhek */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS, - .map_io =3D ep93xx_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D edb93xx_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_EDB9307 -MACHINE_START(EDB9307, "Cirrus Logic EDB9307 Evaluation Board") - /* Maintainer: Herbert Valerio Riedel */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS, - .map_io =3D ep93xx_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D edb93xx_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_EDB9307A -MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board") - /* Maintainer: H Hartley Sweeten */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS, - .map_io =3D ep93xx_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D edb93xx_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_EDB9312 -MACHINE_START(EDB9312, "Cirrus Logic EDB9312 Evaluation Board") - /* Maintainer: Toufeeq Hussain */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS, - .map_io =3D ep93xx_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D edb93xx_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_EDB9315 -MACHINE_START(EDB9315, "Cirrus Logic EDB9315 Evaluation Board") - /* Maintainer: Lennert Buytenhek */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS, - .map_io =3D ep93xx_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D edb93xx_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_EDB9315A -MACHINE_START(EDB9315A, "Cirrus Logic EDB9315A Evaluation Board") - /* Maintainer: Lennert Buytenhek */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS, - .map_io =3D ep93xx_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D edb93xx_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END -#endif diff --git a/arch/arm/mach-ep93xx/ep93xx-regs.h b/arch/arm/mach-ep93xx/ep93= xx-regs.h deleted file mode 100644 index 8fa3646de0a4..000000000000 --- a/arch/arm/mach-ep93xx/ep93xx-regs.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_ARCH_EP93XX_REGS_H -#define __ASM_ARCH_EP93XX_REGS_H - -/* - * EP93xx linux memory map: - * - * virt phys size - * fe800000 5M per-platform mappings - * fed00000 80800000 2M APB - * fef00000 80000000 1M AHB - */ - -#define EP93XX_AHB_PHYS_BASE 0x80000000 -#define EP93XX_AHB_VIRT_BASE 0xfef00000 -#define EP93XX_AHB_SIZE 0x00100000 - -#define EP93XX_AHB_PHYS(x) (EP93XX_AHB_PHYS_BASE + (x)) -#define EP93XX_AHB_IOMEM(x) IOMEM(EP93XX_AHB_VIRT_BASE + (x)) - -#define EP93XX_APB_PHYS_BASE 0x80800000 -#define EP93XX_APB_VIRT_BASE 0xfed00000 -#define EP93XX_APB_SIZE 0x00200000 - -#define EP93XX_APB_PHYS(x) (EP93XX_APB_PHYS_BASE + (x)) -#define EP93XX_APB_IOMEM(x) IOMEM(EP93XX_APB_VIRT_BASE + (x)) - -/* APB UARTs */ -#define EP93XX_UART1_PHYS_BASE EP93XX_APB_PHYS(0x000c0000) -#define EP93XX_UART1_BASE EP93XX_APB_IOMEM(0x000c0000) - -#define EP93XX_UART2_PHYS_BASE EP93XX_APB_PHYS(0x000d0000) -#define EP93XX_UART2_BASE EP93XX_APB_IOMEM(0x000d0000) - -#define EP93XX_UART3_PHYS_BASE EP93XX_APB_PHYS(0x000e0000) -#define EP93XX_UART3_BASE EP93XX_APB_IOMEM(0x000e0000) - -#endif diff --git a/arch/arm/mach-ep93xx/gpio-ep93xx.h b/arch/arm/mach-ep93xx/gpio= -ep93xx.h deleted file mode 100644 index 7b46eb7e5507..000000000000 --- a/arch/arm/mach-ep93xx/gpio-ep93xx.h +++ /dev/null @@ -1,111 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Include file for the EP93XX GPIO controller machine specifics */ - -#ifndef __GPIO_EP93XX_H -#define __GPIO_EP93XX_H - -#include "ep93xx-regs.h" - -#define EP93XX_GPIO_PHYS_BASE EP93XX_APB_PHYS(0x00040000) -#define EP93XX_GPIO_BASE EP93XX_APB_IOMEM(0x00040000) -#define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x)) -#define EP93XX_GPIO_F_INT_STATUS EP93XX_GPIO_REG(0x5c) -#define EP93XX_GPIO_A_INT_STATUS EP93XX_GPIO_REG(0xa0) -#define EP93XX_GPIO_B_INT_STATUS EP93XX_GPIO_REG(0xbc) -#define EP93XX_GPIO_EEDRIVE EP93XX_GPIO_REG(0xc8) - -/* GPIO port A. */ -#define EP93XX_GPIO_LINE_A(x) ((x) + 0) -#define EP93XX_GPIO_LINE_EGPIO0 EP93XX_GPIO_LINE_A(0) -#define EP93XX_GPIO_LINE_EGPIO1 EP93XX_GPIO_LINE_A(1) -#define EP93XX_GPIO_LINE_EGPIO2 EP93XX_GPIO_LINE_A(2) -#define EP93XX_GPIO_LINE_EGPIO3 EP93XX_GPIO_LINE_A(3) -#define EP93XX_GPIO_LINE_EGPIO4 EP93XX_GPIO_LINE_A(4) -#define EP93XX_GPIO_LINE_EGPIO5 EP93XX_GPIO_LINE_A(5) -#define EP93XX_GPIO_LINE_EGPIO6 EP93XX_GPIO_LINE_A(6) -#define EP93XX_GPIO_LINE_EGPIO7 EP93XX_GPIO_LINE_A(7) - -/* GPIO port B. */ -#define EP93XX_GPIO_LINE_B(x) ((x) + 8) -#define EP93XX_GPIO_LINE_EGPIO8 EP93XX_GPIO_LINE_B(0) -#define EP93XX_GPIO_LINE_EGPIO9 EP93XX_GPIO_LINE_B(1) -#define EP93XX_GPIO_LINE_EGPIO10 EP93XX_GPIO_LINE_B(2) -#define EP93XX_GPIO_LINE_EGPIO11 EP93XX_GPIO_LINE_B(3) -#define EP93XX_GPIO_LINE_EGPIO12 EP93XX_GPIO_LINE_B(4) -#define EP93XX_GPIO_LINE_EGPIO13 EP93XX_GPIO_LINE_B(5) -#define EP93XX_GPIO_LINE_EGPIO14 EP93XX_GPIO_LINE_B(6) -#define EP93XX_GPIO_LINE_EGPIO15 EP93XX_GPIO_LINE_B(7) - -/* GPIO port C. */ -#define EP93XX_GPIO_LINE_C(x) ((x) + 40) -#define EP93XX_GPIO_LINE_ROW0 EP93XX_GPIO_LINE_C(0) -#define EP93XX_GPIO_LINE_ROW1 EP93XX_GPIO_LINE_C(1) -#define EP93XX_GPIO_LINE_ROW2 EP93XX_GPIO_LINE_C(2) -#define EP93XX_GPIO_LINE_ROW3 EP93XX_GPIO_LINE_C(3) -#define EP93XX_GPIO_LINE_ROW4 EP93XX_GPIO_LINE_C(4) -#define EP93XX_GPIO_LINE_ROW5 EP93XX_GPIO_LINE_C(5) -#define EP93XX_GPIO_LINE_ROW6 EP93XX_GPIO_LINE_C(6) -#define EP93XX_GPIO_LINE_ROW7 EP93XX_GPIO_LINE_C(7) - -/* GPIO port D. */ -#define EP93XX_GPIO_LINE_D(x) ((x) + 24) -#define EP93XX_GPIO_LINE_COL0 EP93XX_GPIO_LINE_D(0) -#define EP93XX_GPIO_LINE_COL1 EP93XX_GPIO_LINE_D(1) -#define EP93XX_GPIO_LINE_COL2 EP93XX_GPIO_LINE_D(2) -#define EP93XX_GPIO_LINE_COL3 EP93XX_GPIO_LINE_D(3) -#define EP93XX_GPIO_LINE_COL4 EP93XX_GPIO_LINE_D(4) -#define EP93XX_GPIO_LINE_COL5 EP93XX_GPIO_LINE_D(5) -#define EP93XX_GPIO_LINE_COL6 EP93XX_GPIO_LINE_D(6) -#define EP93XX_GPIO_LINE_COL7 EP93XX_GPIO_LINE_D(7) - -/* GPIO port E. */ -#define EP93XX_GPIO_LINE_E(x) ((x) + 32) -#define EP93XX_GPIO_LINE_GRLED EP93XX_GPIO_LINE_E(0) -#define EP93XX_GPIO_LINE_RDLED EP93XX_GPIO_LINE_E(1) -#define EP93XX_GPIO_LINE_DIORn EP93XX_GPIO_LINE_E(2) -#define EP93XX_GPIO_LINE_IDECS1n EP93XX_GPIO_LINE_E(3) -#define EP93XX_GPIO_LINE_IDECS2n EP93XX_GPIO_LINE_E(4) -#define EP93XX_GPIO_LINE_IDEDA0 EP93XX_GPIO_LINE_E(5) -#define EP93XX_GPIO_LINE_IDEDA1 EP93XX_GPIO_LINE_E(6) -#define EP93XX_GPIO_LINE_IDEDA2 EP93XX_GPIO_LINE_E(7) - -/* GPIO port F. */ -#define EP93XX_GPIO_LINE_F(x) ((x) + 16) -#define EP93XX_GPIO_LINE_WP EP93XX_GPIO_LINE_F(0) -#define EP93XX_GPIO_LINE_MCCD1 EP93XX_GPIO_LINE_F(1) -#define EP93XX_GPIO_LINE_MCCD2 EP93XX_GPIO_LINE_F(2) -#define EP93XX_GPIO_LINE_MCBVD1 EP93XX_GPIO_LINE_F(3) -#define EP93XX_GPIO_LINE_MCBVD2 EP93XX_GPIO_LINE_F(4) -#define EP93XX_GPIO_LINE_VS1 EP93XX_GPIO_LINE_F(5) -#define EP93XX_GPIO_LINE_READY EP93XX_GPIO_LINE_F(6) -#define EP93XX_GPIO_LINE_VS2 EP93XX_GPIO_LINE_F(7) - -/* GPIO port G. */ -#define EP93XX_GPIO_LINE_G(x) ((x) + 48) -#define EP93XX_GPIO_LINE_EECLK EP93XX_GPIO_LINE_G(0) -#define EP93XX_GPIO_LINE_EEDAT EP93XX_GPIO_LINE_G(1) -#define EP93XX_GPIO_LINE_SLA0 EP93XX_GPIO_LINE_G(2) -#define EP93XX_GPIO_LINE_SLA1 EP93XX_GPIO_LINE_G(3) -#define EP93XX_GPIO_LINE_DD12 EP93XX_GPIO_LINE_G(4) -#define EP93XX_GPIO_LINE_DD13 EP93XX_GPIO_LINE_G(5) -#define EP93XX_GPIO_LINE_DD14 EP93XX_GPIO_LINE_G(6) -#define EP93XX_GPIO_LINE_DD15 EP93XX_GPIO_LINE_G(7) - -/* GPIO port H. */ -#define EP93XX_GPIO_LINE_H(x) ((x) + 56) -#define EP93XX_GPIO_LINE_DD0 EP93XX_GPIO_LINE_H(0) -#define EP93XX_GPIO_LINE_DD1 EP93XX_GPIO_LINE_H(1) -#define EP93XX_GPIO_LINE_DD2 EP93XX_GPIO_LINE_H(2) -#define EP93XX_GPIO_LINE_DD3 EP93XX_GPIO_LINE_H(3) -#define EP93XX_GPIO_LINE_DD4 EP93XX_GPIO_LINE_H(4) -#define EP93XX_GPIO_LINE_DD5 EP93XX_GPIO_LINE_H(5) -#define EP93XX_GPIO_LINE_DD6 EP93XX_GPIO_LINE_H(6) -#define EP93XX_GPIO_LINE_DD7 EP93XX_GPIO_LINE_H(7) - -/* maximum value for gpio line identifiers */ -#define EP93XX_GPIO_LINE_MAX EP93XX_GPIO_LINE_H(7) - -/* maximum value for irq capable line identifiers */ -#define EP93XX_GPIO_LINE_MAX_IRQ EP93XX_GPIO_LINE_F(7) - -#endif /* __GPIO_EP93XX_H */ diff --git a/arch/arm/mach-ep93xx/hardware.h b/arch/arm/mach-ep93xx/hardwar= e.h deleted file mode 100644 index e7d850e04782..000000000000 --- a/arch/arm/mach-ep93xx/hardware.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * arch/arm/mach-ep93xx/include/mach/hardware.h - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include "platform.h" - -/* - * The EP93xx has two external crystal oscillators. To generate the - * required high-frequency clocks, the processor uses two phase-locked- - * loops (PLLs) to multiply the incoming external clock signal to much - * higher frequencies that are then divided down by programmable dividers - * to produce the needed clocks. The PLLs operate independently of one - * another. - */ -#define EP93XX_EXT_CLK_RATE 14745600 -#define EP93XX_EXT_RTC_RATE 32768 - -#define EP93XX_KEYTCHCLK_DIV4 (EP93XX_EXT_CLK_RATE / 4) -#define EP93XX_KEYTCHCLK_DIV16 (EP93XX_EXT_CLK_RATE / 16) - -#endif diff --git a/arch/arm/mach-ep93xx/irqs.h b/arch/arm/mach-ep93xx/irqs.h deleted file mode 100644 index 353201b90c66..000000000000 --- a/arch/arm/mach-ep93xx/irqs.h +++ /dev/null @@ -1,76 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - -#define IRQ_EP93XX_VIC0 1 - -#define IRQ_EP93XX_COMMRX (IRQ_EP93XX_VIC0 + 2) -#define IRQ_EP93XX_COMMTX (IRQ_EP93XX_VIC0 + 3) -#define IRQ_EP93XX_TIMER1 (IRQ_EP93XX_VIC0 + 4) -#define IRQ_EP93XX_TIMER2 (IRQ_EP93XX_VIC0 + 5) -#define IRQ_EP93XX_AACINTR (IRQ_EP93XX_VIC0 + 6) -#define IRQ_EP93XX_DMAM2P0 (IRQ_EP93XX_VIC0 + 7) -#define IRQ_EP93XX_DMAM2P1 (IRQ_EP93XX_VIC0 + 8) -#define IRQ_EP93XX_DMAM2P2 (IRQ_EP93XX_VIC0 + 9) -#define IRQ_EP93XX_DMAM2P3 (IRQ_EP93XX_VIC0 + 10) -#define IRQ_EP93XX_DMAM2P4 (IRQ_EP93XX_VIC0 + 11) -#define IRQ_EP93XX_DMAM2P5 (IRQ_EP93XX_VIC0 + 12) -#define IRQ_EP93XX_DMAM2P6 (IRQ_EP93XX_VIC0 + 13) -#define IRQ_EP93XX_DMAM2P7 (IRQ_EP93XX_VIC0 + 14) -#define IRQ_EP93XX_DMAM2P8 (IRQ_EP93XX_VIC0 + 15) -#define IRQ_EP93XX_DMAM2P9 (IRQ_EP93XX_VIC0 + 16) -#define IRQ_EP93XX_DMAM2M0 (IRQ_EP93XX_VIC0 + 17) -#define IRQ_EP93XX_DMAM2M1 (IRQ_EP93XX_VIC0 + 18) -#define IRQ_EP93XX_GPIO0MUX (IRQ_EP93XX_VIC0 + 19) -#define IRQ_EP93XX_GPIO1MUX (IRQ_EP93XX_VIC0 + 20) -#define IRQ_EP93XX_GPIO2MUX (IRQ_EP93XX_VIC0 + 21) -#define IRQ_EP93XX_GPIO3MUX (IRQ_EP93XX_VIC0 + 22) -#define IRQ_EP93XX_UART1RX (IRQ_EP93XX_VIC0 + 23) -#define IRQ_EP93XX_UART1TX (IRQ_EP93XX_VIC0 + 24) -#define IRQ_EP93XX_UART2RX (IRQ_EP93XX_VIC0 + 25) -#define IRQ_EP93XX_UART2TX (IRQ_EP93XX_VIC0 + 26) -#define IRQ_EP93XX_UART3RX (IRQ_EP93XX_VIC0 + 27) -#define IRQ_EP93XX_UART3TX (IRQ_EP93XX_VIC0 + 28) -#define IRQ_EP93XX_KEY (IRQ_EP93XX_VIC0 + 29) -#define IRQ_EP93XX_TOUCH (IRQ_EP93XX_VIC0 + 30) -#define EP93XX_VIC1_VALID_IRQ_MASK 0x7ffffffc - -#define IRQ_EP93XX_VIC1 (IRQ_EP93XX_VIC0 + 32) - -#define IRQ_EP93XX_EXT0 (IRQ_EP93XX_VIC1 + 0) -#define IRQ_EP93XX_EXT1 (IRQ_EP93XX_VIC1 + 1) -#define IRQ_EP93XX_EXT2 (IRQ_EP93XX_VIC1 + 2) -#define IRQ_EP93XX_64HZ (IRQ_EP93XX_VIC1 + 3) -#define IRQ_EP93XX_WATCHDOG (IRQ_EP93XX_VIC1 + 4) -#define IRQ_EP93XX_RTC (IRQ_EP93XX_VIC1 + 5) -#define IRQ_EP93XX_IRDA (IRQ_EP93XX_VIC1 + 6) -#define IRQ_EP93XX_ETHERNET (IRQ_EP93XX_VIC1 + 7) -#define IRQ_EP93XX_EXT3 (IRQ_EP93XX_VIC1 + 8) -#define IRQ_EP93XX_PROG (IRQ_EP93XX_VIC1 + 9) -#define IRQ_EP93XX_1HZ (IRQ_EP93XX_VIC1 + 10) -#define IRQ_EP93XX_VSYNC (IRQ_EP93XX_VIC1 + 11) -#define IRQ_EP93XX_VIDEO_FIFO (IRQ_EP93XX_VIC1 + 12) -#define IRQ_EP93XX_SSP1RX (IRQ_EP93XX_VIC1 + 13) -#define IRQ_EP93XX_SSP1TX (IRQ_EP93XX_VIC1 + 14) -#define IRQ_EP93XX_GPIO4MUX (IRQ_EP93XX_VIC1 + 15) -#define IRQ_EP93XX_GPIO5MUX (IRQ_EP93XX_VIC1 + 16) -#define IRQ_EP93XX_GPIO6MUX (IRQ_EP93XX_VIC1 + 17) -#define IRQ_EP93XX_GPIO7MUX (IRQ_EP93XX_VIC1 + 18) -#define IRQ_EP93XX_TIMER3 (IRQ_EP93XX_VIC1 + 19) -#define IRQ_EP93XX_UART1 (IRQ_EP93XX_VIC1 + 20) -#define IRQ_EP93XX_SSP (IRQ_EP93XX_VIC1 + 21) -#define IRQ_EP93XX_UART2 (IRQ_EP93XX_VIC1 + 22) -#define IRQ_EP93XX_UART3 (IRQ_EP93XX_VIC1 + 23) -#define IRQ_EP93XX_USB (IRQ_EP93XX_VIC1 + 24) -#define IRQ_EP93XX_ETHERNET_PME (IRQ_EP93XX_VIC1 + 25) -#define IRQ_EP93XX_DSP (IRQ_EP93XX_VIC1 + 26) -#define IRQ_EP93XX_GPIO_AB (IRQ_EP93XX_VIC1 + 27) -#define IRQ_EP93XX_SAI (IRQ_EP93XX_VIC1 + 28) -#define EP93XX_VIC2_VALID_IRQ_MASK 0x1fffffff - -#define NR_EP93XX_IRQS (IRQ_EP93XX_VIC1 + 32 + 24) - -#define EP93XX_BOARD_IRQ(x) (NR_EP93XX_IRQS + (x)) -#define EP93XX_BOARD_IRQS 32 - -#endif diff --git a/arch/arm/mach-ep93xx/platform.h b/arch/arm/mach-ep93xx/platfor= m.h deleted file mode 100644 index 5fb1b919133f..000000000000 --- a/arch/arm/mach-ep93xx/platform.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * arch/arm/mach-ep93xx/include/mach/platform.h - */ - -#ifndef __ASSEMBLY__ - -#include -#include - -struct device; -struct i2c_board_info; -struct spi_board_info; -struct platform_device; -struct ep93xxfb_mach_info; -struct ep93xx_keypad_platform_data; -struct ep93xx_spi_info; - -void ep93xx_map_io(void); -void ep93xx_init_irq(void); - -void ep93xx_register_flash(unsigned int width, - resource_size_t start, resource_size_t size); - -void ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr); -void ep93xx_register_i2c(struct i2c_board_info *devices, int num); -void ep93xx_register_spi(struct ep93xx_spi_info *info, - struct spi_board_info *devices, int num); -void ep93xx_register_fb(struct ep93xxfb_mach_info *data); -void ep93xx_register_pwm(int pwm0, int pwm1); -void ep93xx_register_keypad(struct ep93xx_keypad_platform_data *data); -void ep93xx_register_i2s(void); -void ep93xx_register_ac97(void); -void ep93xx_register_ide(void); -void ep93xx_register_adc(void); - -struct device *ep93xx_init_devices(void); -extern void ep93xx_timer_init(void); - -void ep93xx_restart(enum reboot_mode, const char *); - -#endif diff --git a/arch/arm/mach-ep93xx/soc.h b/arch/arm/mach-ep93xx/soc.h deleted file mode 100644 index 3245ebbd5069..000000000000 --- a/arch/arm/mach-ep93xx/soc.h +++ /dev/null @@ -1,212 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * arch/arm/mach-ep93xx/soc.h - * - * Copyright (C) 2012 Open Kernel Labs - * Copyright (C) 2012 Ryan Mallon - */ - -#ifndef _EP93XX_SOC_H -#define _EP93XX_SOC_H - -#include "ep93xx-regs.h" -#include "irqs.h" - -/* - * EP93xx Physical Memory Map: - * - * The ASDO pin is sampled at system reset to select a synchronous or - * asynchronous boot configuration. When ASDO is "1" (i.e. pulled-up) - * the synchronous boot mode is selected. When ASDO is "0" (i.e - * pulled-down) the asynchronous boot mode is selected. - * - * In synchronous boot mode nSDCE3 is decoded starting at physical address - * 0x00000000 and nCS0 is decoded starting at 0xf0000000. For asynchronous - * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3 - * decoded at 0xf0000000. - * - * There is known errata for the EP93xx dealing with External Memory - * Configurations. Please refer to "AN273: EP93xx Silicon Rev E Design - * Guidelines" for more information. This document can be found at: - * - * http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf - */ - -#define EP93XX_CS0_PHYS_BASE_ASYNC 0x00000000 /* ASDO Pin =3D 0 */ -#define EP93XX_SDCE3_PHYS_BASE_SYNC 0x00000000 /* ASDO Pin =3D 1 */ -#define EP93XX_CS1_PHYS_BASE 0x10000000 -#define EP93XX_CS2_PHYS_BASE 0x20000000 -#define EP93XX_CS3_PHYS_BASE 0x30000000 -#define EP93XX_PCMCIA_PHYS_BASE 0x40000000 -#define EP93XX_CS6_PHYS_BASE 0x60000000 -#define EP93XX_CS7_PHYS_BASE 0x70000000 -#define EP93XX_SDCE0_PHYS_BASE 0xc0000000 -#define EP93XX_SDCE1_PHYS_BASE 0xd0000000 -#define EP93XX_SDCE2_PHYS_BASE 0xe0000000 -#define EP93XX_SDCE3_PHYS_BASE_ASYNC 0xf0000000 /* ASDO Pin =3D 0 */ -#define EP93XX_CS0_PHYS_BASE_SYNC 0xf0000000 /* ASDO Pin =3D 1 */ - -/* AHB peripherals */ -#define EP93XX_DMA_BASE EP93XX_AHB_IOMEM(0x00000000) - -#define EP93XX_ETHERNET_PHYS_BASE EP93XX_AHB_PHYS(0x00010000) -#define EP93XX_ETHERNET_BASE EP93XX_AHB_IOMEM(0x00010000) - -#define EP93XX_USB_PHYS_BASE EP93XX_AHB_PHYS(0x00020000) -#define EP93XX_USB_BASE EP93XX_AHB_IOMEM(0x00020000) - -#define EP93XX_RASTER_PHYS_BASE EP93XX_AHB_PHYS(0x00030000) -#define EP93XX_RASTER_BASE EP93XX_AHB_IOMEM(0x00030000) - -#define EP93XX_GRAPHICS_ACCEL_BASE EP93XX_AHB_IOMEM(0x00040000) - -#define EP93XX_SDRAM_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00060000) - -#define EP93XX_PCMCIA_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00080000) - -#define EP93XX_BOOT_ROM_BASE EP93XX_AHB_IOMEM(0x00090000) - -#define EP93XX_IDE_PHYS_BASE EP93XX_AHB_PHYS(0x000a0000) -#define EP93XX_IDE_BASE EP93XX_AHB_IOMEM(0x000a0000) - -#define EP93XX_VIC1_BASE EP93XX_AHB_IOMEM(0x000b0000) - -#define EP93XX_VIC2_BASE EP93XX_AHB_IOMEM(0x000c0000) - -/* APB peripherals */ -#define EP93XX_TIMER_BASE EP93XX_APB_IOMEM(0x00010000) - -#define EP93XX_I2S_PHYS_BASE EP93XX_APB_PHYS(0x00020000) -#define EP93XX_I2S_BASE EP93XX_APB_IOMEM(0x00020000) - -#define EP93XX_SECURITY_BASE EP93XX_APB_IOMEM(0x00030000) - -#define EP93XX_AAC_PHYS_BASE EP93XX_APB_PHYS(0x00080000) -#define EP93XX_AAC_BASE EP93XX_APB_IOMEM(0x00080000) - -#define EP93XX_SPI_PHYS_BASE EP93XX_APB_PHYS(0x000a0000) -#define EP93XX_SPI_BASE EP93XX_APB_IOMEM(0x000a0000) - -#define EP93XX_IRDA_BASE EP93XX_APB_IOMEM(0x000b0000) - -#define EP93XX_KEY_MATRIX_PHYS_BASE EP93XX_APB_PHYS(0x000f0000) -#define EP93XX_KEY_MATRIX_BASE EP93XX_APB_IOMEM(0x000f0000) - -#define EP93XX_ADC_PHYS_BASE EP93XX_APB_PHYS(0x00100000) -#define EP93XX_ADC_BASE EP93XX_APB_IOMEM(0x00100000) -#define EP93XX_TOUCHSCREEN_BASE EP93XX_APB_IOMEM(0x00100000) - -#define EP93XX_PWM_PHYS_BASE EP93XX_APB_PHYS(0x00110000) -#define EP93XX_PWM_BASE EP93XX_APB_IOMEM(0x00110000) - -#define EP93XX_RTC_PHYS_BASE EP93XX_APB_PHYS(0x00120000) -#define EP93XX_RTC_BASE EP93XX_APB_IOMEM(0x00120000) - -#define EP93XX_WATCHDOG_PHYS_BASE EP93XX_APB_PHYS(0x00140000) -#define EP93XX_WATCHDOG_BASE EP93XX_APB_IOMEM(0x00140000) - -/* System controller */ -#define EP93XX_SYSCON_BASE EP93XX_APB_IOMEM(0x00130000) -#define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x)) -#define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00) -#define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04) -#define EP93XX_SYSCON_PWRCNT_FIR_EN (1<<31) -#define EP93XX_SYSCON_PWRCNT_UARTBAUD (1<<29) -#define EP93XX_SYSCON_PWRCNT_USH_EN 28 -#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 27 -#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 26 -#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 25 -#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 24 -#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 23 -#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 22 -#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 21 -#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 20 -#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 19 -#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 18 -#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 17 -#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 16 -#define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08) -#define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c) -#define EP93XX_SYSCON_CLKSET1 EP93XX_SYSCON_REG(0x20) -#define EP93XX_SYSCON_CLKSET1_NBYP1 (1<<23) -#define EP93XX_SYSCON_CLKSET2 EP93XX_SYSCON_REG(0x24) -#define EP93XX_SYSCON_CLKSET2_NBYP2 (1<<19) -#define EP93XX_SYSCON_CLKSET2_PLL2_EN (1<<18) -#define EP93XX_SYSCON_DEVCFG EP93XX_SYSCON_REG(0x80) -#define EP93XX_SYSCON_DEVCFG_SWRST (1<<31) -#define EP93XX_SYSCON_DEVCFG_D1ONG (1<<30) -#define EP93XX_SYSCON_DEVCFG_D0ONG (1<<29) -#define EP93XX_SYSCON_DEVCFG_IONU2 (1<<28) -#define EP93XX_SYSCON_DEVCFG_GONK (1<<27) -#define EP93XX_SYSCON_DEVCFG_TONG (1<<26) -#define EP93XX_SYSCON_DEVCFG_MONG (1<<25) -#define EP93XX_SYSCON_DEVCFG_U3EN 24 -#define EP93XX_SYSCON_DEVCFG_CPENA (1<<23) -#define EP93XX_SYSCON_DEVCFG_A2ONG (1<<22) -#define EP93XX_SYSCON_DEVCFG_A1ONG (1<<21) -#define EP93XX_SYSCON_DEVCFG_U2EN 20 -#define EP93XX_SYSCON_DEVCFG_EXVC (1<<19) -#define EP93XX_SYSCON_DEVCFG_U1EN 18 -#define EP93XX_SYSCON_DEVCFG_TIN (1<<17) -#define EP93XX_SYSCON_DEVCFG_HC3IN (1<<15) -#define EP93XX_SYSCON_DEVCFG_HC3EN (1<<14) -#define EP93XX_SYSCON_DEVCFG_HC1IN (1<<13) -#define EP93XX_SYSCON_DEVCFG_HC1EN (1<<12) -#define EP93XX_SYSCON_DEVCFG_HONIDE (1<<11) -#define EP93XX_SYSCON_DEVCFG_GONIDE (1<<10) -#define EP93XX_SYSCON_DEVCFG_PONG (1<<9) -#define EP93XX_SYSCON_DEVCFG_EONIDE (1<<8) -#define EP93XX_SYSCON_DEVCFG_I2SONSSP (1<<7) -#define EP93XX_SYSCON_DEVCFG_I2SONAC97 (1<<6) -#define EP93XX_SYSCON_DEVCFG_RASONP3 (1<<4) -#define EP93XX_SYSCON_DEVCFG_RAS (1<<3) -#define EP93XX_SYSCON_DEVCFG_ADCPD (1<<2) -#define EP93XX_SYSCON_DEVCFG_KEYS (1<<1) -#define EP93XX_SYSCON_DEVCFG_SHENA (1<<0) -#define EP93XX_SYSCON_VIDCLKDIV EP93XX_SYSCON_REG(0x84) -#define EP93XX_SYSCON_CLKDIV_ENABLE 15 -#define EP93XX_SYSCON_CLKDIV_ESEL (1<<14) -#define EP93XX_SYSCON_CLKDIV_PSEL (1<<13) -#define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8 -#define EP93XX_SYSCON_I2SCLKDIV EP93XX_SYSCON_REG(0x8c) -#define EP93XX_SYSCON_I2SCLKDIV_SENA 31 -#define EP93XX_SYSCON_I2SCLKDIV_ORIDE (1<<29) -#define EP93XX_SYSCON_I2SCLKDIV_SPOL (1<<19) -#define EP93XX_I2SCLKDIV_SDIV (1 << 16) -#define EP93XX_I2SCLKDIV_LRDIV32 (0 << 17) -#define EP93XX_I2SCLKDIV_LRDIV64 (1 << 17) -#define EP93XX_I2SCLKDIV_LRDIV128 (2 << 17) -#define EP93XX_I2SCLKDIV_LRDIV_MASK (3 << 17) -#define EP93XX_SYSCON_KEYTCHCLKDIV EP93XX_SYSCON_REG(0x90) -#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN 31 -#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV 16 -#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN 15 -#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0) -#define EP93XX_SYSCON_SYSCFG EP93XX_SYSCON_REG(0x9c) -#define EP93XX_SYSCON_SYSCFG_REV_MASK (0xf0000000) -#define EP93XX_SYSCON_SYSCFG_REV_SHIFT (28) -#define EP93XX_SYSCON_SYSCFG_SBOOT (1<<8) -#define EP93XX_SYSCON_SYSCFG_LCSN7 (1<<7) -#define EP93XX_SYSCON_SYSCFG_LCSN6 (1<<6) -#define EP93XX_SYSCON_SYSCFG_LASDO (1<<5) -#define EP93XX_SYSCON_SYSCFG_LEEDA (1<<4) -#define EP93XX_SYSCON_SYSCFG_LEECLK (1<<3) -#define EP93XX_SYSCON_SYSCFG_LCSN2 (1<<1) -#define EP93XX_SYSCON_SYSCFG_LCSN1 (1<<0) -#define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0) - -/* EP93xx System Controller software locked register write */ -void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg); -void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bit= s); - -static inline void ep93xx_devcfg_set_bits(unsigned int bits) -{ - ep93xx_devcfg_set_clear(bits, 0x00); -} - -static inline void ep93xx_devcfg_clear_bits(unsigned int bits) -{ - ep93xx_devcfg_set_clear(0x00, bits); -} - -#endif /* _EP93XX_SOC_H */ diff --git a/arch/arm/mach-ep93xx/timer-ep93xx.c b/arch/arm/mach-ep93xx/tim= er-ep93xx.c deleted file mode 100644 index dd4b164d1831..000000000000 --- a/arch/arm/mach-ep93xx/timer-ep93xx.c +++ /dev/null @@ -1,142 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "soc.h" - -/************************************************************************* - * Timer handling for EP93xx - ************************************************************************* - * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and - * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate - * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz, - * is free-running, and can't generate interrupts. - * - * The 508 kHz timers are ideal for use for the timer interrupt, as the - * most common values of HZ divide 508 kHz nicely. We pick the 32 bit - * timer (timer 3) to get as long sleep intervals as possible when using - * CONFIG_NO_HZ. - * - * The higher clock rate of timer 4 makes it a better choice than the - * other timers for use as clock source and for sched_clock(), providing - * a stable 40 bit time base. - ************************************************************************* - */ -#define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x)) -#define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00) -#define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04) -#define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08) -#define EP93XX_TIMER123_CONTROL_ENABLE (1 << 7) -#define EP93XX_TIMER123_CONTROL_MODE (1 << 6) -#define EP93XX_TIMER123_CONTROL_CLKSEL (1 << 3) -#define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c) -#define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20) -#define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24) -#define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28) -#define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c) -#define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60) -#define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64) -#define EP93XX_TIMER4_VALUE_HIGH_ENABLE (1 << 8) -#define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80) -#define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84) -#define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88) -#define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c) - -#define EP93XX_TIMER123_RATE 508469 -#define EP93XX_TIMER4_RATE 983040 - -static u64 notrace ep93xx_read_sched_clock(void) -{ - u64 ret; - - ret =3D readl(EP93XX_TIMER4_VALUE_LOW); - ret |=3D ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32); - return ret; -} - -u64 ep93xx_clocksource_read(struct clocksource *c) -{ - u64 ret; - - ret =3D readl(EP93XX_TIMER4_VALUE_LOW); - ret |=3D ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32); - return (u64) ret; -} - -static int ep93xx_clkevt_set_next_event(unsigned long next, - struct clock_event_device *evt) -{ - /* Default mode: periodic, off, 508 kHz */ - u32 tmode =3D EP93XX_TIMER123_CONTROL_MODE | - EP93XX_TIMER123_CONTROL_CLKSEL; - - /* Clear timer */ - writel(tmode, EP93XX_TIMER3_CONTROL); - - /* Set next event */ - writel(next, EP93XX_TIMER3_LOAD); - writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE, - EP93XX_TIMER3_CONTROL); - return 0; -} - - -static int ep93xx_clkevt_shutdown(struct clock_event_device *evt) -{ - /* Disable timer */ - writel(0, EP93XX_TIMER3_CONTROL); - - return 0; -} - -static struct clock_event_device ep93xx_clockevent =3D { - .name =3D "timer1", - .features =3D CLOCK_EVT_FEAT_ONESHOT, - .set_state_shutdown =3D ep93xx_clkevt_shutdown, - .set_state_oneshot =3D ep93xx_clkevt_shutdown, - .tick_resume =3D ep93xx_clkevt_shutdown, - .set_next_event =3D ep93xx_clkevt_set_next_event, - .rating =3D 300, -}; - -static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt =3D dev_id; - - /* Writing any value clears the timer interrupt */ - writel(1, EP93XX_TIMER3_CLEAR); - - evt->event_handler(evt); - - return IRQ_HANDLED; -} - -void __init ep93xx_timer_init(void) -{ - int irq =3D IRQ_EP93XX_TIMER3; - unsigned long flags =3D IRQF_TIMER | IRQF_IRQPOLL; - - /* Enable and register clocksource and sched_clock on timer 4 */ - writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE, - EP93XX_TIMER4_VALUE_HIGH); - clocksource_mmio_init(NULL, "timer4", - EP93XX_TIMER4_RATE, 200, 40, - ep93xx_clocksource_read); - sched_clock_register(ep93xx_read_sched_clock, 40, - EP93XX_TIMER4_RATE); - - /* Set up clockevent on timer 3 */ - if (request_irq(irq, ep93xx_timer_interrupt, flags, "ep93xx timer", - &ep93xx_clockevent)) - pr_err("Failed to request irq %d (ep93xx timer)\n", irq); - clockevents_config_and_register(&ep93xx_clockevent, - EP93XX_TIMER123_RATE, - 1, - 0xffffffffU); -} diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c deleted file mode 100644 index 0bbdf587c685..000000000000 --- a/arch/arm/mach-ep93xx/ts72xx.c +++ /dev/null @@ -1,422 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-ep93xx/ts72xx.c - * Technologic Systems TS72xx SBC support. - * - * Copyright (C) 2006 Lennert Buytenhek - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "gpio-ep93xx.h" -#include "hardware.h" - -#include -#include -#include - -#include "soc.h" -#include "ts72xx.h" - -/************************************************************************* - * IO map - *************************************************************************/ -static struct map_desc ts72xx_io_desc[] __initdata =3D { - { - .virtual =3D (unsigned long)TS72XX_MODEL_VIRT_BASE, - .pfn =3D __phys_to_pfn(TS72XX_MODEL_PHYS_BASE), - .length =3D TS72XX_MODEL_SIZE, - .type =3D MT_DEVICE, - }, { - .virtual =3D (unsigned long)TS72XX_OPTIONS_VIRT_BASE, - .pfn =3D __phys_to_pfn(TS72XX_OPTIONS_PHYS_BASE), - .length =3D TS72XX_OPTIONS_SIZE, - .type =3D MT_DEVICE, - }, { - .virtual =3D (unsigned long)TS72XX_OPTIONS2_VIRT_BASE, - .pfn =3D __phys_to_pfn(TS72XX_OPTIONS2_PHYS_BASE), - .length =3D TS72XX_OPTIONS2_SIZE, - .type =3D MT_DEVICE, - }, { - .virtual =3D (unsigned long)TS72XX_CPLDVER_VIRT_BASE, - .pfn =3D __phys_to_pfn(TS72XX_CPLDVER_PHYS_BASE), - .length =3D TS72XX_CPLDVER_SIZE, - .type =3D MT_DEVICE, - } -}; - -static void __init ts72xx_map_io(void) -{ - ep93xx_map_io(); - iotable_init(ts72xx_io_desc, ARRAY_SIZE(ts72xx_io_desc)); -} - - -/************************************************************************* - * NAND flash - *************************************************************************/ -#define TS72XX_NAND_CONTROL_ADDR_LINE 22 /* 0xN0400000 */ -#define TS72XX_NAND_BUSY_ADDR_LINE 23 /* 0xN0800000 */ - -static void ts72xx_nand_hwcontrol(struct nand_chip *chip, - int cmd, unsigned int ctrl) -{ - if (ctrl & NAND_CTRL_CHANGE) { - void __iomem *addr =3D chip->legacy.IO_ADDR_R; - unsigned char bits; - - addr +=3D (1 << TS72XX_NAND_CONTROL_ADDR_LINE); - - bits =3D __raw_readb(addr) & ~0x07; - bits |=3D (ctrl & NAND_NCE) << 2; /* bit 0 -> bit 2 */ - bits |=3D (ctrl & NAND_CLE); /* bit 1 -> bit 1 */ - bits |=3D (ctrl & NAND_ALE) >> 2; /* bit 2 -> bit 0 */ - - __raw_writeb(bits, addr); - } - - if (cmd !=3D NAND_CMD_NONE) - __raw_writeb(cmd, chip->legacy.IO_ADDR_W); -} - -static int ts72xx_nand_device_ready(struct nand_chip *chip) -{ - void __iomem *addr =3D chip->legacy.IO_ADDR_R; - - addr +=3D (1 << TS72XX_NAND_BUSY_ADDR_LINE); - - return !!(__raw_readb(addr) & 0x20); -} - -#define TS72XX_BOOTROM_PART_SIZE (SZ_16K) -#define TS72XX_REDBOOT_PART_SIZE (SZ_2M + SZ_1M) - -static struct mtd_partition ts72xx_nand_parts[] =3D { - { - .name =3D "TS-BOOTROM", - .offset =3D 0, - .size =3D TS72XX_BOOTROM_PART_SIZE, - .mask_flags =3D MTD_WRITEABLE, /* force read-only */ - }, { - .name =3D "Linux", - .offset =3D MTDPART_OFS_RETAIN, - .size =3D TS72XX_REDBOOT_PART_SIZE, - /* leave so much for last partition */ - }, { - .name =3D "RedBoot", - .offset =3D MTDPART_OFS_APPEND, - .size =3D MTDPART_SIZ_FULL, - .mask_flags =3D MTD_WRITEABLE, /* force read-only */ - }, -}; - -static struct platform_nand_data ts72xx_nand_data =3D { - .chip =3D { - .nr_chips =3D 1, - .chip_offset =3D 0, - .chip_delay =3D 15, - }, - .ctrl =3D { - .cmd_ctrl =3D ts72xx_nand_hwcontrol, - .dev_ready =3D ts72xx_nand_device_ready, - }, -}; - -static struct resource ts72xx_nand_resource[] =3D { - { - .start =3D 0, /* filled in later */ - .end =3D 0, /* filled in later */ - .flags =3D IORESOURCE_MEM, - }, -}; - -static struct platform_device ts72xx_nand_flash =3D { - .name =3D "gen_nand", - .id =3D -1, - .dev.platform_data =3D &ts72xx_nand_data, - .resource =3D ts72xx_nand_resource, - .num_resources =3D ARRAY_SIZE(ts72xx_nand_resource), -}; - -static void __init ts72xx_register_flash(struct mtd_partition *parts, int = n, - resource_size_t start) -{ - /* - * TS7200 has NOR flash all other TS72xx board have NAND flash. - */ - if (board_is_ts7200()) { - ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M); - } else { - ts72xx_nand_resource[0].start =3D start; - ts72xx_nand_resource[0].end =3D start + SZ_16M - 1; - - ts72xx_nand_data.chip.partitions =3D parts; - ts72xx_nand_data.chip.nr_partitions =3D n; - - platform_device_register(&ts72xx_nand_flash); - } -} - -/************************************************************************* - * RTC M48T86 - *************************************************************************/ -#define TS72XX_RTC_INDEX_PHYS_BASE (EP93XX_CS1_PHYS_BASE + 0x00800000) -#define TS72XX_RTC_DATA_PHYS_BASE (EP93XX_CS1_PHYS_BASE + 0x01700000) - -static struct resource ts72xx_rtc_resources[] =3D { - DEFINE_RES_MEM(TS72XX_RTC_INDEX_PHYS_BASE, 0x01), - DEFINE_RES_MEM(TS72XX_RTC_DATA_PHYS_BASE, 0x01), -}; - -static struct platform_device ts72xx_rtc_device =3D { - .name =3D "rtc-m48t86", - .id =3D -1, - .resource =3D ts72xx_rtc_resources, - .num_resources =3D ARRAY_SIZE(ts72xx_rtc_resources), -}; - -/************************************************************************* - * Watchdog (in CPLD) - *************************************************************************/ -#define TS72XX_WDT_CONTROL_PHYS_BASE (EP93XX_CS2_PHYS_BASE + 0x03800000) -#define TS72XX_WDT_FEED_PHYS_BASE (EP93XX_CS2_PHYS_BASE + 0x03c00000) - -static struct resource ts72xx_wdt_resources[] =3D { - DEFINE_RES_MEM(TS72XX_WDT_CONTROL_PHYS_BASE, 0x01), - DEFINE_RES_MEM(TS72XX_WDT_FEED_PHYS_BASE, 0x01), -}; - -static struct platform_device ts72xx_wdt_device =3D { - .name =3D "ts72xx-wdt", - .id =3D -1, - .resource =3D ts72xx_wdt_resources, - .num_resources =3D ARRAY_SIZE(ts72xx_wdt_resources), -}; - -/************************************************************************* - * ETH - *************************************************************************/ -static struct ep93xx_eth_data __initdata ts72xx_eth_data =3D { - .phy_id =3D 1, -}; - -/************************************************************************* - * SPI SD/MMC host - *************************************************************************/ -#define BK3_EN_SDCARD_PHYS_BASE 0x12400000 -#define BK3_EN_SDCARD_PWR 0x0 -#define BK3_DIS_SDCARD_PWR 0x0C -static void bk3_mmc_spi_setpower(struct device *dev, unsigned int vdd) -{ - void __iomem *pwr_sd =3D ioremap(BK3_EN_SDCARD_PHYS_BASE, SZ_4K); - - if (!pwr_sd) { - pr_err("Failed to enable SD card power!"); - return; - } - - pr_debug("%s: SD card pwr %s VDD:0x%x\n", __func__, - !!vdd ? "ON" : "OFF", vdd); - - if (!!vdd) - __raw_writeb(BK3_EN_SDCARD_PWR, pwr_sd); - else - __raw_writeb(BK3_DIS_SDCARD_PWR, pwr_sd); - - iounmap(pwr_sd); -} - -static struct mmc_spi_platform_data bk3_spi_mmc_data =3D { - .detect_delay =3D 500, - .powerup_msecs =3D 100, - .ocr_mask =3D MMC_VDD_32_33 | MMC_VDD_33_34, - .caps =3D MMC_CAP_NONREMOVABLE, - .setpower =3D bk3_mmc_spi_setpower, -}; - -/************************************************************************* - * SPI Bus - SD card access - *************************************************************************/ -static struct spi_board_info bk3_spi_board_info[] __initdata =3D { - { - .modalias =3D "mmc_spi", - .platform_data =3D &bk3_spi_mmc_data, - .max_speed_hz =3D 7.4E6, - .bus_num =3D 0, - .chip_select =3D 0, - .mode =3D SPI_MODE_0, - }, -}; - -/* - * This is a stub -> the FGPIO[3] pin is not connected on the schematic - * The all work is performed automatically by !SPI_FRAME (SFRM1) and - * goes through CPLD - */ -static struct gpiod_lookup_table bk3_spi_cs_gpio_table =3D { - .dev_id =3D "spi0", - .table =3D { - GPIO_LOOKUP("gpio-ep93xx.5", 3, "cs", GPIO_ACTIVE_LOW), - { }, - }, -}; - -static struct ep93xx_spi_info bk3_spi_master __initdata =3D { - .use_dma =3D 1, -}; - -/************************************************************************* - * TS72XX support code - *************************************************************************/ -#if IS_ENABLED(CONFIG_FPGA_MGR_TS73XX) - -/* Relative to EP93XX_CS1_PHYS_BASE */ -#define TS73XX_FPGA_LOADER_BASE 0x03c00000 - -static struct resource ts73xx_fpga_resources[] =3D { - { - .start =3D EP93XX_CS1_PHYS_BASE + TS73XX_FPGA_LOADER_BASE, - .end =3D EP93XX_CS1_PHYS_BASE + TS73XX_FPGA_LOADER_BASE + 1, - .flags =3D IORESOURCE_MEM, - }, -}; - -static struct platform_device ts73xx_fpga_device =3D { - .name =3D "ts73xx-fpga-mgr", - .id =3D -1, - .resource =3D ts73xx_fpga_resources, - .num_resources =3D ARRAY_SIZE(ts73xx_fpga_resources), -}; - -#endif - -/************************************************************************* - * SPI Bus - *************************************************************************/ -static struct spi_board_info ts72xx_spi_devices[] __initdata =3D { - { - .modalias =3D "tmp122", - .max_speed_hz =3D 2 * 1000 * 1000, - .bus_num =3D 0, - .chip_select =3D 0, - }, -}; - -static struct gpiod_lookup_table ts72xx_spi_cs_gpio_table =3D { - .dev_id =3D "spi0", - .table =3D { - /* DIO_17 */ - GPIO_LOOKUP("gpio-ep93xx.5", 2, "cs", GPIO_ACTIVE_LOW), - { }, - }, -}; - -static struct ep93xx_spi_info ts72xx_spi_info __initdata =3D { - /* Intentionally left blank */ -}; - -static void __init ts72xx_init_machine(void) -{ - ep93xx_init_devices(); - ts72xx_register_flash(ts72xx_nand_parts, ARRAY_SIZE(ts72xx_nand_parts), - is_ts9420_installed() ? - EP93XX_CS7_PHYS_BASE : EP93XX_CS6_PHYS_BASE); - platform_device_register(&ts72xx_rtc_device); - platform_device_register(&ts72xx_wdt_device); - - ep93xx_register_eth(&ts72xx_eth_data, 1); -#if IS_ENABLED(CONFIG_FPGA_MGR_TS73XX) - if (board_is_ts7300()) - platform_device_register(&ts73xx_fpga_device); -#endif - gpiod_add_lookup_table(&ts72xx_spi_cs_gpio_table); - ep93xx_register_spi(&ts72xx_spi_info, ts72xx_spi_devices, - ARRAY_SIZE(ts72xx_spi_devices)); -} - -MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC") - /* Maintainer: Lennert Buytenhek */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS, - .map_io =3D ts72xx_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D ts72xx_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END - -/************************************************************************* - * EP93xx I2S audio peripheral handling - *************************************************************************/ -static struct resource ep93xx_i2s_resource[] =3D { - DEFINE_RES_MEM(EP93XX_I2S_PHYS_BASE, 0x100), - DEFINE_RES_IRQ_NAMED(IRQ_EP93XX_SAI, "spilink i2s slave"), -}; - -static struct platform_device ep93xx_i2s_device =3D { - .name =3D "ep93xx-spilink-i2s", - .id =3D -1, - .num_resources =3D ARRAY_SIZE(ep93xx_i2s_resource), - .resource =3D ep93xx_i2s_resource, -}; - -/************************************************************************* - * BK3 support code - *************************************************************************/ -static struct mtd_partition bk3_nand_parts[] =3D { - { - .name =3D "System", - .offset =3D 0x00000000, - .size =3D 0x01e00000, - }, { - .name =3D "Data", - .offset =3D 0x01e00000, - .size =3D 0x05f20000 - }, { - .name =3D "RedBoot", - .offset =3D 0x07d20000, - .size =3D 0x002e0000, - .mask_flags =3D MTD_WRITEABLE, /* force RO */ - }, -}; - -static void __init bk3_init_machine(void) -{ - ep93xx_init_devices(); - - ts72xx_register_flash(bk3_nand_parts, ARRAY_SIZE(bk3_nand_parts), - EP93XX_CS6_PHYS_BASE); - - ep93xx_register_eth(&ts72xx_eth_data, 1); - - gpiod_add_lookup_table(&bk3_spi_cs_gpio_table); - ep93xx_register_spi(&bk3_spi_master, bk3_spi_board_info, - ARRAY_SIZE(bk3_spi_board_info)); - - /* Configure ep93xx's I2S to use AC97 pins */ - ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_I2SONAC97); - platform_device_register(&ep93xx_i2s_device); -} - -MACHINE_START(BK3, "Liebherr controller BK3.1") - /* Maintainer: Lukasz Majewski */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS, - .map_io =3D ts72xx_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D bk3_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END diff --git a/arch/arm/mach-ep93xx/ts72xx.h b/arch/arm/mach-ep93xx/ts72xx.h deleted file mode 100644 index 00b4941d29c9..000000000000 --- a/arch/arm/mach-ep93xx/ts72xx.h +++ /dev/null @@ -1,94 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * arch/arm/mach-ep93xx/include/mach/ts72xx.h - */ - -/* - * TS72xx memory map: - * - * virt phys size - * febff000 22000000 4K model number register (bits 0-2) - * febfe000 22400000 4K options register - * febfd000 22800000 4K options register #2 - * febfc000 23400000 4K CPLD version register - */ - -#ifndef __TS72XX_H_ -#define __TS72XX_H_ - -#define TS72XX_MODEL_PHYS_BASE 0x22000000 -#define TS72XX_MODEL_VIRT_BASE IOMEM(0xfebff000) -#define TS72XX_MODEL_SIZE 0x00001000 - -#define TS72XX_MODEL_TS7200 0x00 -#define TS72XX_MODEL_TS7250 0x01 -#define TS72XX_MODEL_TS7260 0x02 -#define TS72XX_MODEL_TS7300 0x03 -#define TS72XX_MODEL_TS7400 0x04 -#define TS72XX_MODEL_MASK 0x07 - - -#define TS72XX_OPTIONS_PHYS_BASE 0x22400000 -#define TS72XX_OPTIONS_VIRT_BASE IOMEM(0xfebfe000) -#define TS72XX_OPTIONS_SIZE 0x00001000 - -#define TS72XX_OPTIONS_COM2_RS485 0x02 -#define TS72XX_OPTIONS_MAX197 0x01 - - -#define TS72XX_OPTIONS2_PHYS_BASE 0x22800000 -#define TS72XX_OPTIONS2_VIRT_BASE IOMEM(0xfebfd000) -#define TS72XX_OPTIONS2_SIZE 0x00001000 - -#define TS72XX_OPTIONS2_TS9420 0x04 -#define TS72XX_OPTIONS2_TS9420_BOOT 0x02 - -#define TS72XX_CPLDVER_PHYS_BASE 0x23400000 -#define TS72XX_CPLDVER_VIRT_BASE IOMEM(0xfebfc000) -#define TS72XX_CPLDVER_SIZE 0x00001000 - -#ifndef __ASSEMBLY__ - -static inline int ts72xx_model(void) -{ - return __raw_readb(TS72XX_MODEL_VIRT_BASE) & TS72XX_MODEL_MASK; -} - -static inline int board_is_ts7200(void) -{ - return ts72xx_model() =3D=3D TS72XX_MODEL_TS7200; -} - -static inline int board_is_ts7250(void) -{ - return ts72xx_model() =3D=3D TS72XX_MODEL_TS7250; -} - -static inline int board_is_ts7260(void) -{ - return ts72xx_model() =3D=3D TS72XX_MODEL_TS7260; -} - -static inline int board_is_ts7300(void) -{ - return ts72xx_model() =3D=3D TS72XX_MODEL_TS7300; -} - -static inline int board_is_ts7400(void) -{ - return ts72xx_model() =3D=3D TS72XX_MODEL_TS7400; -} - -static inline int is_max197_installed(void) -{ - return !!(__raw_readb(TS72XX_OPTIONS_VIRT_BASE) & - TS72XX_OPTIONS_MAX197); -} - -static inline int is_ts9420_installed(void) -{ - return !!(__raw_readb(TS72XX_OPTIONS2_VIRT_BASE) & - TS72XX_OPTIONS2_TS9420); -} -#endif -#endif /* __TS72XX_H_ */ diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vi= sion_ep9307.c deleted file mode 100644 index 020223b0be2b..000000000000 --- a/arch/arm/mach-ep93xx/vision_ep9307.c +++ /dev/null @@ -1,311 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-ep93xx/vision_ep9307.c - * Vision Engraving Systems EP9307 SoM support. - * - * Copyright (C) 2008-2011 Vision Engraving Systems - * H Hartley Sweeten - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "hardware.h" -#include -#include -#include "gpio-ep93xx.h" - -#include -#include -#include - -#include "soc.h" - -/************************************************************************* - * Static I/O mappings for the FPGA - *************************************************************************/ -#define VISION_PHYS_BASE EP93XX_CS7_PHYS_BASE -#define VISION_VIRT_BASE 0xfebff000 - -static struct map_desc vision_io_desc[] __initdata =3D { - { - .virtual =3D VISION_VIRT_BASE, - .pfn =3D __phys_to_pfn(VISION_PHYS_BASE), - .length =3D SZ_4K, - .type =3D MT_DEVICE, - }, -}; - -static void __init vision_map_io(void) -{ - ep93xx_map_io(); - - iotable_init(vision_io_desc, ARRAY_SIZE(vision_io_desc)); -} - -/************************************************************************* - * Ethernet - *************************************************************************/ -static struct ep93xx_eth_data vision_eth_data __initdata =3D { - .phy_id =3D 1, -}; - -/************************************************************************* - * Framebuffer - *************************************************************************/ -#define VISION_LCD_ENABLE EP93XX_GPIO_LINE_EGPIO1 - -static int vision_lcd_setup(struct platform_device *pdev) -{ - int err; - - err =3D gpio_request_one(VISION_LCD_ENABLE, GPIOF_INIT_HIGH, - dev_name(&pdev->dev)); - if (err) - return err; - - ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_RAS | - EP93XX_SYSCON_DEVCFG_RASONP3 | - EP93XX_SYSCON_DEVCFG_EXVC); - - return 0; -} - -static void vision_lcd_teardown(struct platform_device *pdev) -{ - gpio_free(VISION_LCD_ENABLE); -} - -static void vision_lcd_blank(int blank_mode, struct fb_info *info) -{ - if (blank_mode) - gpio_set_value(VISION_LCD_ENABLE, 0); - else - gpio_set_value(VISION_LCD_ENABLE, 1); -} - -static struct ep93xxfb_mach_info ep93xxfb_info __initdata =3D { - .flags =3D EP93XXFB_USE_SDCSN0 | EP93XXFB_PCLK_FALLING, - .setup =3D vision_lcd_setup, - .teardown =3D vision_lcd_teardown, - .blank =3D vision_lcd_blank, -}; - - -/************************************************************************* - * GPIO Expanders - *************************************************************************/ -#define PCA9539_74_GPIO_BASE (EP93XX_GPIO_LINE_MAX + 1) -#define PCA9539_75_GPIO_BASE (PCA9539_74_GPIO_BASE + 16) -#define PCA9539_76_GPIO_BASE (PCA9539_75_GPIO_BASE + 16) -#define PCA9539_77_GPIO_BASE (PCA9539_76_GPIO_BASE + 16) - -static struct pca953x_platform_data pca953x_74_gpio_data =3D { - .gpio_base =3D PCA9539_74_GPIO_BASE, - .irq_base =3D EP93XX_BOARD_IRQ(0), -}; - -static struct pca953x_platform_data pca953x_75_gpio_data =3D { - .gpio_base =3D PCA9539_75_GPIO_BASE, - .irq_base =3D -1, -}; - -static struct pca953x_platform_data pca953x_76_gpio_data =3D { - .gpio_base =3D PCA9539_76_GPIO_BASE, - .irq_base =3D -1, -}; - -static struct pca953x_platform_data pca953x_77_gpio_data =3D { - .gpio_base =3D PCA9539_77_GPIO_BASE, - .irq_base =3D -1, -}; - -/************************************************************************* - * I2C Bus - *************************************************************************/ - -static struct i2c_board_info vision_i2c_info[] __initdata =3D { - { - I2C_BOARD_INFO("isl1208", 0x6f), - .irq =3D IRQ_EP93XX_EXT1, - }, { - I2C_BOARD_INFO("pca9539", 0x74), - .platform_data =3D &pca953x_74_gpio_data, - }, { - I2C_BOARD_INFO("pca9539", 0x75), - .platform_data =3D &pca953x_75_gpio_data, - }, { - I2C_BOARD_INFO("pca9539", 0x76), - .platform_data =3D &pca953x_76_gpio_data, - }, { - I2C_BOARD_INFO("pca9539", 0x77), - .platform_data =3D &pca953x_77_gpio_data, - }, -}; - -/************************************************************************* - * SPI CS4271 Audio Codec - *************************************************************************/ -static struct cs4271_platform_data vision_cs4271_data =3D { - .gpio_nreset =3D EP93XX_GPIO_LINE_H(2), -}; - -/************************************************************************* - * SPI Flash - *************************************************************************/ -static struct mtd_partition vision_spi_flash_partitions[] =3D { - { - .name =3D "SPI bootstrap", - .offset =3D 0, - .size =3D SZ_4K, - }, { - .name =3D "Bootstrap config", - .offset =3D MTDPART_OFS_APPEND, - .size =3D SZ_4K, - }, { - .name =3D "System config", - .offset =3D MTDPART_OFS_APPEND, - .size =3D MTDPART_SIZ_FULL, - }, -}; - -static struct flash_platform_data vision_spi_flash_data =3D { - .name =3D "SPI Flash", - .parts =3D vision_spi_flash_partitions, - .nr_parts =3D ARRAY_SIZE(vision_spi_flash_partitions), -}; - -/************************************************************************* - * SPI SD/MMC host - *************************************************************************/ -static struct mmc_spi_platform_data vision_spi_mmc_data =3D { - .detect_delay =3D 100, - .powerup_msecs =3D 100, - .ocr_mask =3D MMC_VDD_32_33 | MMC_VDD_33_34, - .caps2 =3D MMC_CAP2_RO_ACTIVE_HIGH, -}; - -static struct gpiod_lookup_table vision_spi_mmc_gpio_table =3D { - .dev_id =3D "mmc_spi.2", /* "mmc_spi @ CS2 */ - .table =3D { - /* Card detect */ - GPIO_LOOKUP_IDX("gpio-ep93xx.1", 7, NULL, 0, GPIO_ACTIVE_LOW), - /* Write protect */ - GPIO_LOOKUP_IDX("gpio-ep93xx.5", 0, NULL, 1, GPIO_ACTIVE_HIGH), - { }, - }, -}; - -/************************************************************************* - * SPI Bus - *************************************************************************/ -static struct spi_board_info vision_spi_board_info[] __initdata =3D { - { - .modalias =3D "cs4271", - .platform_data =3D &vision_cs4271_data, - .max_speed_hz =3D 6000000, - .bus_num =3D 0, - .chip_select =3D 0, - .mode =3D SPI_MODE_3, - }, { - .modalias =3D "sst25l", - .platform_data =3D &vision_spi_flash_data, - .max_speed_hz =3D 20000000, - .bus_num =3D 0, - .chip_select =3D 1, - .mode =3D SPI_MODE_3, - }, { - .modalias =3D "mmc_spi", - .platform_data =3D &vision_spi_mmc_data, - .max_speed_hz =3D 20000000, - .bus_num =3D 0, - .chip_select =3D 2, - .mode =3D SPI_MODE_3, - }, -}; - -static struct gpiod_lookup_table vision_spi_cs_gpio_table =3D { - .dev_id =3D "spi0", - .table =3D { - GPIO_LOOKUP_IDX("gpio-ep93xx.0", 6, "cs", 0, GPIO_ACTIVE_LOW), - GPIO_LOOKUP_IDX("gpio-ep93xx.0", 7, "cs", 1, GPIO_ACTIVE_LOW), - GPIO_LOOKUP_IDX("gpio-ep93xx.6", 2, "cs", 2, GPIO_ACTIVE_LOW), - { }, - }, -}; - -static struct ep93xx_spi_info vision_spi_master __initdata =3D { - .use_dma =3D 1, -}; - -/************************************************************************* - * I2S Audio - *************************************************************************/ -static struct platform_device vision_audio_device =3D { - .name =3D "edb93xx-audio", - .id =3D -1, -}; - -static void __init vision_register_i2s(void) -{ - ep93xx_register_i2s(); - platform_device_register(&vision_audio_device); -} - -/************************************************************************* - * Machine Initialization - *************************************************************************/ -static void __init vision_init_machine(void) -{ - ep93xx_init_devices(); - ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_64M); - ep93xx_register_eth(&vision_eth_data, 1); - ep93xx_register_fb(&ep93xxfb_info); - ep93xx_register_pwm(1, 0); - - /* - * Request the gpio expander's interrupt gpio line now to prevent - * the kernel from doing a WARN in gpiolib:gpio_ensure_requested(). - */ - if (gpio_request_one(EP93XX_GPIO_LINE_F(7), GPIOF_DIR_IN, - "pca9539:74")) - pr_warn("cannot request interrupt gpio for pca9539:74\n"); - - vision_i2c_info[1].irq =3D gpio_to_irq(EP93XX_GPIO_LINE_F(7)); - - ep93xx_register_i2c(vision_i2c_info, - ARRAY_SIZE(vision_i2c_info)); - gpiod_add_lookup_table(&vision_spi_mmc_gpio_table); - gpiod_add_lookup_table(&vision_spi_cs_gpio_table); - ep93xx_register_spi(&vision_spi_master, vision_spi_board_info, - ARRAY_SIZE(vision_spi_board_info)); - vision_register_i2s(); -} - -MACHINE_START(VISION_EP9307, "Vision Engraving Systems EP9307") - /* Maintainer: H Hartley Sweeten */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS + EP93XX_BOARD_IRQS, - .map_io =3D vision_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D vision_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4F39C77B7E for ; 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a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1685598393; bh=GJa091ZEIb0nAmNL8fwvAkv4qM1TXqxWM9hEZutyZdI=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=ERa/ZqNLyx0ecVtcjznshaStyF2fznOOqGBqyFiiNdsUUSPO+yQkjwKSqpp+7AXRR 4JO3Td06wrfafdRP9PdIMQGmHuXaUNc6PTnx9ksXksdScQbKygq7fZzYMibU85CxZV 7Tp/lxvpJq12ImZDfrjW73805bjV/NFz0prKhNFs= Authentication-Results: mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij , Hartley Sweeten , Russell King , Lukasz Majewski Cc: Nikita Shubin , Michael Peters , Kris Bahnsen , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 39/43] ARM: ep93xx: delete all boardfiles Date: Thu, 1 Jun 2023 08:45:44 +0300 Message-Id: <20230601054549.10843-21-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Delete the ep93xx board files. Signed-off-by: Nikita Shubin --- arch/arm/mach-ep93xx/clock.c | 733 ----------------- arch/arm/mach-ep93xx/core.c | 1114 -------------------------- arch/arm/mach-ep93xx/dma.c | 115 --- arch/arm/mach-ep93xx/edb93xx.c | 344 -------- arch/arm/mach-ep93xx/ep93xx-regs.h | 38 - arch/arm/mach-ep93xx/gpio-ep93xx.h | 111 --- arch/arm/mach-ep93xx/hardware.h | 25 - arch/arm/mach-ep93xx/irqs.h | 76 -- arch/arm/mach-ep93xx/platform.h | 42 - arch/arm/mach-ep93xx/soc.h | 212 ----- arch/arm/mach-ep93xx/timer-ep93xx.c | 142 ---- arch/arm/mach-ep93xx/ts72xx.c | 422 ---------- arch/arm/mach-ep93xx/ts72xx.h | 94 --- arch/arm/mach-ep93xx/vision_ep9307.c | 311 ------- 14 files changed, 3779 deletions(-) delete mode 100644 arch/arm/mach-ep93xx/clock.c delete mode 100644 arch/arm/mach-ep93xx/core.c delete mode 100644 arch/arm/mach-ep93xx/dma.c delete mode 100644 arch/arm/mach-ep93xx/edb93xx.c delete mode 100644 arch/arm/mach-ep93xx/ep93xx-regs.h delete mode 100644 arch/arm/mach-ep93xx/gpio-ep93xx.h delete mode 100644 arch/arm/mach-ep93xx/hardware.h delete mode 100644 arch/arm/mach-ep93xx/irqs.h delete mode 100644 arch/arm/mach-ep93xx/platform.h delete mode 100644 arch/arm/mach-ep93xx/soc.h delete mode 100644 arch/arm/mach-ep93xx/timer-ep93xx.c delete mode 100644 arch/arm/mach-ep93xx/ts72xx.c delete mode 100644 arch/arm/mach-ep93xx/ts72xx.h delete mode 100644 arch/arm/mach-ep93xx/vision_ep9307.c diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c deleted file mode 100644 index 85a496ddc619..000000000000 --- a/arch/arm/mach-ep93xx/clock.c +++ /dev/null @@ -1,733 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-ep93xx/clock.c - * Clock control for Cirrus EP93xx chips. - * - * Copyright (C) 2006 Lennert Buytenhek - */ - -#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "hardware.h" - -#include - -#include "soc.h" - -static DEFINE_SPINLOCK(clk_lock); - -static char fclk_divisors[] =3D { 1, 2, 4, 8, 16, 1, 1, 1 }; -static char hclk_divisors[] =3D { 1, 2, 4, 5, 6, 8, 16, 32 }; -static char pclk_divisors[] =3D { 1, 2, 4, 8 }; - -static char adc_divisors[] =3D { 16, 4 }; -static char sclk_divisors[] =3D { 2, 4 }; -static char lrclk_divisors[] =3D { 32, 64, 128 }; - -static const char * const mux_parents[] =3D { - "xtali", - "pll1", - "pll2" -}; - -/* - * PLL rate =3D 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^= PS - */ -static unsigned long calc_pll_rate(unsigned long long rate, u32 config_wor= d) -{ - int i; - - rate *=3D ((config_word >> 11) & 0x1f) + 1; /* X1FBD */ - rate *=3D ((config_word >> 5) & 0x3f) + 1; /* X2FBD */ - do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */ - for (i =3D 0; i < ((config_word >> 16) & 3); i++) /* PS */ - rate >>=3D 1; - - return (unsigned long)rate; -} - -struct clk_psc { - struct clk_hw hw; - void __iomem *reg; - u8 bit_idx; - u32 mask; - u8 shift; - u8 width; - char *div; - u8 num_div; - spinlock_t *lock; -}; - -#define to_clk_psc(_hw) container_of(_hw, struct clk_psc, hw) - -static int ep93xx_clk_is_enabled(struct clk_hw *hw) -{ - struct clk_psc *psc =3D to_clk_psc(hw); - u32 val =3D readl(psc->reg); - - return (val & BIT(psc->bit_idx)) ? 1 : 0; -} - -static int ep93xx_clk_enable(struct clk_hw *hw) -{ - struct clk_psc *psc =3D to_clk_psc(hw); - unsigned long flags =3D 0; - u32 val; - - if (psc->lock) - spin_lock_irqsave(psc->lock, flags); - - val =3D __raw_readl(psc->reg); - val |=3D BIT(psc->bit_idx); - - ep93xx_syscon_swlocked_write(val, psc->reg); - - if (psc->lock) - spin_unlock_irqrestore(psc->lock, flags); - - return 0; -} - -static void ep93xx_clk_disable(struct clk_hw *hw) -{ - struct clk_psc *psc =3D to_clk_psc(hw); - unsigned long flags =3D 0; - u32 val; - - if (psc->lock) - spin_lock_irqsave(psc->lock, flags); - - val =3D __raw_readl(psc->reg); - val &=3D ~BIT(psc->bit_idx); - - ep93xx_syscon_swlocked_write(val, psc->reg); - - if (psc->lock) - spin_unlock_irqrestore(psc->lock, flags); -} - -static const struct clk_ops clk_ep93xx_gate_ops =3D { - .enable =3D ep93xx_clk_enable, - .disable =3D ep93xx_clk_disable, - .is_enabled =3D ep93xx_clk_is_enabled, -}; - -static struct clk_hw *ep93xx_clk_register_gate(const char *name, - const char *parent_name, - void __iomem *reg, - u8 bit_idx) -{ - struct clk_init_data init; - struct clk_psc *psc; - struct clk *clk; - - psc =3D kzalloc(sizeof(*psc), GFP_KERNEL); - if (!psc) - return ERR_PTR(-ENOMEM); - - init.name =3D name; - init.ops =3D &clk_ep93xx_gate_ops; - init.flags =3D CLK_SET_RATE_PARENT; - init.parent_names =3D (parent_name ? &parent_name : NULL); - init.num_parents =3D (parent_name ? 1 : 0); - - psc->reg =3D reg; - psc->bit_idx =3D bit_idx; - psc->hw.init =3D &init; - psc->lock =3D &clk_lock; - - clk =3D clk_register(NULL, &psc->hw); - if (IS_ERR(clk)) { - kfree(psc); - return ERR_CAST(clk); - } - - return &psc->hw; -} - -static u8 ep93xx_mux_get_parent(struct clk_hw *hw) -{ - struct clk_psc *psc =3D to_clk_psc(hw); - u32 val =3D __raw_readl(psc->reg); - - if (!(val & EP93XX_SYSCON_CLKDIV_ESEL)) - return 0; - - if (!(val & EP93XX_SYSCON_CLKDIV_PSEL)) - return 1; - - return 2; -} - -static int ep93xx_mux_set_parent_lock(struct clk_hw *hw, u8 index) -{ - struct clk_psc *psc =3D to_clk_psc(hw); - unsigned long flags =3D 0; - u32 val; - - if (index >=3D ARRAY_SIZE(mux_parents)) - return -EINVAL; - - if (psc->lock) - spin_lock_irqsave(psc->lock, flags); - - val =3D __raw_readl(psc->reg); - val &=3D ~(EP93XX_SYSCON_CLKDIV_ESEL | EP93XX_SYSCON_CLKDIV_PSEL); - - - if (index !=3D 0) { - val |=3D EP93XX_SYSCON_CLKDIV_ESEL; - val |=3D (index - 1) ? EP93XX_SYSCON_CLKDIV_PSEL : 0; - } - - ep93xx_syscon_swlocked_write(val, psc->reg); - - if (psc->lock) - spin_unlock_irqrestore(psc->lock, flags); - - return 0; -} - -static bool is_best(unsigned long rate, unsigned long now, - unsigned long best) -{ - return abs(rate - now) < abs(rate - best); -} - -static int ep93xx_mux_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) -{ - unsigned long rate =3D req->rate; - struct clk *best_parent =3D NULL; - unsigned long __parent_rate; - unsigned long best_rate =3D 0, actual_rate, mclk_rate; - unsigned long best_parent_rate; - int __div =3D 0, __pdiv =3D 0; - int i; - - /* - * Try the two pll's and the external clock - * Because the valid predividers are 2, 2.5 and 3, we multiply - * all the clocks by 2 to avoid floating point math. - * - * This is based on the algorithm in the ep93xx raster guide: - * http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf - * - */ - for (i =3D 0; i < ARRAY_SIZE(mux_parents); i++) { - struct clk *parent =3D clk_get_sys(mux_parents[i], NULL); - - __parent_rate =3D clk_get_rate(parent); - mclk_rate =3D __parent_rate * 2; - - /* Try each predivider value */ - for (__pdiv =3D 4; __pdiv <=3D 6; __pdiv++) { - __div =3D mclk_rate / (rate * __pdiv); - if (__div < 2 || __div > 127) - continue; - - actual_rate =3D mclk_rate / (__pdiv * __div); - if (is_best(rate, actual_rate, best_rate)) { - best_rate =3D actual_rate; - best_parent_rate =3D __parent_rate; - best_parent =3D parent; - } - } - } - - if (!best_parent) - return -EINVAL; - - req->best_parent_rate =3D best_parent_rate; - req->best_parent_hw =3D __clk_get_hw(best_parent); - req->rate =3D best_rate; - - return 0; -} - -static unsigned long ep93xx_ddiv_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_psc *psc =3D to_clk_psc(hw); - unsigned long rate =3D 0; - u32 val =3D __raw_readl(psc->reg); - int __pdiv =3D ((val >> EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) & 0x03); - int __div =3D val & 0x7f; - - if (__div > 0) - rate =3D (parent_rate * 2) / ((__pdiv + 3) * __div); - - return rate; -} - -static int ep93xx_ddiv_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_psc *psc =3D to_clk_psc(hw); - int pdiv =3D 0, div =3D 0; - unsigned long best_rate =3D 0, actual_rate, mclk_rate; - int __div =3D 0, __pdiv =3D 0; - u32 val; - - mclk_rate =3D parent_rate * 2; - - for (__pdiv =3D 4; __pdiv <=3D 6; __pdiv++) { - __div =3D mclk_rate / (rate * __pdiv); - if (__div < 2 || __div > 127) - continue; - - actual_rate =3D mclk_rate / (__pdiv * __div); - if (is_best(rate, actual_rate, best_rate)) { - pdiv =3D __pdiv - 3; - div =3D __div; - best_rate =3D actual_rate; - } - } - - if (!best_rate) - return -EINVAL; - - val =3D __raw_readl(psc->reg); - - /* Clear old dividers */ - val &=3D ~0x37f; - - /* Set the new pdiv and div bits for the new clock rate */ - val |=3D (pdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | div; - ep93xx_syscon_swlocked_write(val, psc->reg); - - return 0; -} - -static const struct clk_ops clk_ddiv_ops =3D { - .enable =3D ep93xx_clk_enable, - .disable =3D ep93xx_clk_disable, - .is_enabled =3D ep93xx_clk_is_enabled, - .get_parent =3D ep93xx_mux_get_parent, - .set_parent =3D ep93xx_mux_set_parent_lock, - .determine_rate =3D ep93xx_mux_determine_rate, - .recalc_rate =3D ep93xx_ddiv_recalc_rate, - .set_rate =3D ep93xx_ddiv_set_rate, -}; - -static struct clk_hw *clk_hw_register_ddiv(const char *name, - void __iomem *reg, - u8 bit_idx) -{ - struct clk_init_data init; - struct clk_psc *psc; - struct clk *clk; - - psc =3D kzalloc(sizeof(*psc), GFP_KERNEL); - if (!psc) - return ERR_PTR(-ENOMEM); - - init.name =3D name; - init.ops =3D &clk_ddiv_ops; - init.flags =3D 0; - init.parent_names =3D mux_parents; - init.num_parents =3D ARRAY_SIZE(mux_parents); - - psc->reg =3D reg; - psc->bit_idx =3D bit_idx; - psc->lock =3D &clk_lock; - psc->hw.init =3D &init; - - clk =3D clk_register(NULL, &psc->hw); - if (IS_ERR(clk)) { - kfree(psc); - return ERR_CAST(clk); - } - return &psc->hw; -} - -static unsigned long ep93xx_div_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_psc *psc =3D to_clk_psc(hw); - u32 val =3D __raw_readl(psc->reg); - u8 index =3D (val & psc->mask) >> psc->shift; - - if (index > psc->num_div) - return 0; - - return DIV_ROUND_UP_ULL(parent_rate, psc->div[index]); -} - -static long ep93xx_div_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) -{ - struct clk_psc *psc =3D to_clk_psc(hw); - unsigned long best =3D 0, now, maxdiv; - int i; - - maxdiv =3D psc->div[psc->num_div - 1]; - - for (i =3D 0; i < psc->num_div; i++) { - if ((rate * psc->div[i]) =3D=3D *parent_rate) - return DIV_ROUND_UP_ULL((u64)*parent_rate, psc->div[i]); - - now =3D DIV_ROUND_UP_ULL((u64)*parent_rate, psc->div[i]); - - if (is_best(rate, now, best)) - best =3D now; - } - - if (!best) - best =3D DIV_ROUND_UP_ULL(*parent_rate, maxdiv); - - return best; -} - -static int ep93xx_div_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_psc *psc =3D to_clk_psc(hw); - u32 val =3D __raw_readl(psc->reg) & ~psc->mask; - int i; - - for (i =3D 0; i < psc->num_div; i++) - if (rate =3D=3D parent_rate / psc->div[i]) { - val |=3D i << psc->shift; - break; - } - - if (i =3D=3D psc->num_div) - return -EINVAL; - - ep93xx_syscon_swlocked_write(val, psc->reg); - - return 0; -} - -static const struct clk_ops ep93xx_div_ops =3D { - .enable =3D ep93xx_clk_enable, - .disable =3D ep93xx_clk_disable, - .is_enabled =3D ep93xx_clk_is_enabled, - .recalc_rate =3D ep93xx_div_recalc_rate, - .round_rate =3D ep93xx_div_round_rate, - .set_rate =3D ep93xx_div_set_rate, -}; - -static struct clk_hw *clk_hw_register_div(const char *name, - const char *parent_name, - void __iomem *reg, - u8 enable_bit, - u8 shift, - u8 width, - char *clk_divisors, - u8 num_div) -{ - struct clk_init_data init; - struct clk_psc *psc; - struct clk *clk; - - psc =3D kzalloc(sizeof(*psc), GFP_KERNEL); - if (!psc) - return ERR_PTR(-ENOMEM); - - init.name =3D name; - init.ops =3D &ep93xx_div_ops; - init.flags =3D 0; - init.parent_names =3D (parent_name ? &parent_name : NULL); - init.num_parents =3D 1; - - psc->reg =3D reg; - psc->bit_idx =3D enable_bit; - psc->mask =3D GENMASK(shift + width - 1, shift); - psc->shift =3D shift; - psc->div =3D clk_divisors; - psc->num_div =3D num_div; - psc->lock =3D &clk_lock; - psc->hw.init =3D &init; - - clk =3D clk_register(NULL, &psc->hw); - if (IS_ERR(clk)) { - kfree(psc); - return ERR_CAST(clk); - } - return &psc->hw; -} - -struct ep93xx_gate { - unsigned int bit; - const char *dev_id; - const char *con_id; -}; - -static struct ep93xx_gate ep93xx_uarts[] =3D { - {EP93XX_SYSCON_DEVCFG_U1EN, "apb:uart1", NULL}, - {EP93XX_SYSCON_DEVCFG_U2EN, "apb:uart2", NULL}, - {EP93XX_SYSCON_DEVCFG_U3EN, "apb:uart3", NULL}, -}; - -static void __init ep93xx_uart_clock_init(void) -{ - unsigned int i; - struct clk_hw *hw; - u32 value; - unsigned int clk_uart_div; - - value =3D __raw_readl(EP93XX_SYSCON_PWRCNT); - if (value & EP93XX_SYSCON_PWRCNT_UARTBAUD) - clk_uart_div =3D 1; - else - clk_uart_div =3D 2; - - hw =3D clk_hw_register_fixed_factor(NULL, "uart", "xtali", 0, 1, clk_uart= _div); - - /* parenting uart gate clocks to uart clock */ - for (i =3D 0; i < ARRAY_SIZE(ep93xx_uarts); i++) { - hw =3D ep93xx_clk_register_gate(ep93xx_uarts[i].dev_id, - "uart", - EP93XX_SYSCON_DEVCFG, - ep93xx_uarts[i].bit); - - clk_hw_register_clkdev(hw, NULL, ep93xx_uarts[i].dev_id); - } -} - -static struct ep93xx_gate ep93xx_dmas[] =3D { - {EP93XX_SYSCON_PWRCNT_DMA_M2P0, NULL, "m2p0"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2P1, NULL, "m2p1"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2P2, NULL, "m2p2"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2P3, NULL, "m2p3"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2P4, NULL, "m2p4"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2P5, NULL, "m2p5"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2P6, NULL, "m2p6"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2P7, NULL, "m2p7"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2P8, NULL, "m2p8"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2P9, NULL, "m2p9"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2M0, NULL, "m2m0"}, - {EP93XX_SYSCON_PWRCNT_DMA_M2M1, NULL, "m2m1"}, -}; - -static void __init ep93xx_dma_clock_init(void) -{ - unsigned int i; - struct clk_hw *hw; - int ret; - - for (i =3D 0; i < ARRAY_SIZE(ep93xx_dmas); i++) { - hw =3D clk_hw_register_gate(NULL, ep93xx_dmas[i].con_id, - "hclk", 0, - EP93XX_SYSCON_PWRCNT, - ep93xx_dmas[i].bit, - 0, - &clk_lock); - - ret =3D clk_hw_register_clkdev(hw, ep93xx_dmas[i].con_id, NULL); - if (ret) - pr_err("%s: failed to register lookup %s\n", - __func__, ep93xx_dmas[i].con_id); - } -} - -static int __init ep93xx_clock_init(void) -{ - u32 value; - struct clk_hw *hw; - unsigned long clk_pll1_rate; - unsigned long clk_f_rate; - unsigned long clk_h_rate; - unsigned long clk_p_rate; - unsigned long clk_pll2_rate; - unsigned int clk_f_div; - unsigned int clk_h_div; - unsigned int clk_p_div; - unsigned int clk_usb_div; - unsigned long clk_spi_div; - - hw =3D clk_hw_register_fixed_rate(NULL, "xtali", NULL, 0, EP93XX_EXT_CLK_= RATE); - clk_hw_register_clkdev(hw, NULL, "xtali"); - - /* Determine the bootloader configured pll1 rate */ - value =3D __raw_readl(EP93XX_SYSCON_CLKSET1); - if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1)) - clk_pll1_rate =3D EP93XX_EXT_CLK_RATE; - else - clk_pll1_rate =3D calc_pll_rate(EP93XX_EXT_CLK_RATE, value); - - hw =3D clk_hw_register_fixed_rate(NULL, "pll1", "xtali", 0, clk_pll1_rate= ); - clk_hw_register_clkdev(hw, NULL, "pll1"); - - /* Initialize the pll1 derived clocks */ - clk_f_div =3D fclk_divisors[(value >> 25) & 0x7]; - clk_h_div =3D hclk_divisors[(value >> 20) & 0x7]; - clk_p_div =3D pclk_divisors[(value >> 18) & 0x3]; - - hw =3D clk_hw_register_fixed_factor(NULL, "fclk", "pll1", 0, 1, clk_f_div= ); - clk_f_rate =3D clk_get_rate(hw->clk); - hw =3D clk_hw_register_fixed_factor(NULL, "hclk", "pll1", 0, 1, clk_h_div= ); - clk_h_rate =3D clk_get_rate(hw->clk); - hw =3D clk_hw_register_fixed_factor(NULL, "pclk", "hclk", 0, 1, clk_p_div= ); - clk_p_rate =3D clk_get_rate(hw->clk); - - clk_hw_register_clkdev(hw, "apb_pclk", NULL); - - ep93xx_dma_clock_init(); - - /* Determine the bootloader configured pll2 rate */ - value =3D __raw_readl(EP93XX_SYSCON_CLKSET2); - if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2)) - clk_pll2_rate =3D EP93XX_EXT_CLK_RATE; - else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN) - clk_pll2_rate =3D calc_pll_rate(EP93XX_EXT_CLK_RATE, value); - else - clk_pll2_rate =3D 0; - - hw =3D clk_hw_register_fixed_rate(NULL, "pll2", "xtali", 0, clk_pll2_rate= ); - clk_hw_register_clkdev(hw, NULL, "pll2"); - - /* Initialize the pll2 derived clocks */ - /* - * These four bits set the divide ratio between the PLL2 - * output and the USB clock. - * 0000 - Divide by 1 - * 0001 - Divide by 2 - * 0010 - Divide by 3 - * 0011 - Divide by 4 - * 0100 - Divide by 5 - * 0101 - Divide by 6 - * 0110 - Divide by 7 - * 0111 - Divide by 8 - * 1000 - Divide by 9 - * 1001 - Divide by 10 - * 1010 - Divide by 11 - * 1011 - Divide by 12 - * 1100 - Divide by 13 - * 1101 - Divide by 14 - * 1110 - Divide by 15 - * 1111 - Divide by 1 - * On power-on-reset these bits are reset to 0000b. - */ - clk_usb_div =3D (((value >> 28) & 0xf) + 1); - hw =3D clk_hw_register_fixed_factor(NULL, "usb_clk", "pll2", 0, 1, clk_us= b_div); - hw =3D clk_hw_register_gate(NULL, "ohci-platform", - "usb_clk", 0, - EP93XX_SYSCON_PWRCNT, - EP93XX_SYSCON_PWRCNT_USH_EN, - 0, - &clk_lock); - clk_hw_register_clkdev(hw, NULL, "ohci-platform"); - - /* - * EP93xx SSP clock rate was doubled in version E2. For more information - * see: - * http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf - */ - clk_spi_div =3D 1; - if (ep93xx_chip_revision() < EP93XX_CHIP_REV_E2) - clk_spi_div =3D 2; - hw =3D clk_hw_register_fixed_factor(NULL, "ep93xx-spi.0", "xtali", 0, 1, = clk_spi_div); - clk_hw_register_clkdev(hw, NULL, "ep93xx-spi.0"); - - /* pwm clock */ - hw =3D clk_hw_register_fixed_factor(NULL, "pwm_clk", "xtali", 0, 1, 1); - clk_hw_register_clkdev(hw, "pwm_clk", NULL); - - pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n", - clk_pll1_rate / 1000000, clk_pll2_rate / 1000000); - pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n", - clk_f_rate / 1000000, clk_h_rate / 1000000, - clk_p_rate / 1000000); - - ep93xx_uart_clock_init(); - - /* touchscreen/adc clock */ - hw =3D clk_hw_register_div("ep93xx-adc", - "xtali", - EP93XX_SYSCON_KEYTCHCLKDIV, - EP93XX_SYSCON_KEYTCHCLKDIV_TSEN, - EP93XX_SYSCON_KEYTCHCLKDIV_ADIV, - 1, - adc_divisors, - ARRAY_SIZE(adc_divisors)); - - clk_hw_register_clkdev(hw, NULL, "ep93xx-adc"); - - /* keypad clock */ - hw =3D clk_hw_register_div("ep93xx-keypad", - "xtali", - EP93XX_SYSCON_KEYTCHCLKDIV, - EP93XX_SYSCON_KEYTCHCLKDIV_KEN, - EP93XX_SYSCON_KEYTCHCLKDIV_KDIV, - 1, - adc_divisors, - ARRAY_SIZE(adc_divisors)); - - clk_hw_register_clkdev(hw, NULL, "ep93xx-keypad"); - - /* On reset PDIV and VDIV is set to zero, while PDIV zero - * means clock disable, VDIV shouldn't be zero. - * So i set both dividers to minimum. - */ - /* ENA - Enable CLK divider. */ - /* PDIV - 00 - Disable clock */ - /* VDIV - at least 2 */ - /* Check and enable video clk registers */ - value =3D __raw_readl(EP93XX_SYSCON_VIDCLKDIV); - value |=3D (1 << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | 2; - ep93xx_syscon_swlocked_write(value, EP93XX_SYSCON_VIDCLKDIV); - - /* check and enable i2s clk registers */ - value =3D __raw_readl(EP93XX_SYSCON_I2SCLKDIV); - value |=3D (1 << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | 2; - ep93xx_syscon_swlocked_write(value, EP93XX_SYSCON_I2SCLKDIV); - - /* video clk */ - hw =3D clk_hw_register_ddiv("ep93xx-fb", - EP93XX_SYSCON_VIDCLKDIV, - EP93XX_SYSCON_CLKDIV_ENABLE); - - clk_hw_register_clkdev(hw, NULL, "ep93xx-fb"); - - /* i2s clk */ - hw =3D clk_hw_register_ddiv("mclk", - EP93XX_SYSCON_I2SCLKDIV, - EP93XX_SYSCON_CLKDIV_ENABLE); - - clk_hw_register_clkdev(hw, "mclk", "ep93xx-i2s"); - - /* i2s sclk */ -#define EP93XX_I2SCLKDIV_SDIV_SHIFT 16 -#define EP93XX_I2SCLKDIV_SDIV_WIDTH 1 - hw =3D clk_hw_register_div("sclk", - "mclk", - EP93XX_SYSCON_I2SCLKDIV, - EP93XX_SYSCON_I2SCLKDIV_SENA, - EP93XX_I2SCLKDIV_SDIV_SHIFT, - EP93XX_I2SCLKDIV_SDIV_WIDTH, - sclk_divisors, - ARRAY_SIZE(sclk_divisors)); - - clk_hw_register_clkdev(hw, "sclk", "ep93xx-i2s"); - - /* i2s lrclk */ -#define EP93XX_I2SCLKDIV_LRDIV32_SHIFT 17 -#define EP93XX_I2SCLKDIV_LRDIV32_WIDTH 3 - hw =3D clk_hw_register_div("lrclk", - "sclk", - EP93XX_SYSCON_I2SCLKDIV, - EP93XX_SYSCON_I2SCLKDIV_SENA, - EP93XX_I2SCLKDIV_LRDIV32_SHIFT, - EP93XX_I2SCLKDIV_LRDIV32_WIDTH, - lrclk_divisors, - ARRAY_SIZE(lrclk_divisors)); - - clk_hw_register_clkdev(hw, "lrclk", "ep93xx-i2s"); - - return 0; -} -postcore_initcall(ep93xx_clock_init); diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c deleted file mode 100644 index d61c1d2a0843..000000000000 --- a/arch/arm/mach-ep93xx/core.c +++ /dev/null @@ -1,1114 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-ep93xx/core.c - * Core routines for Cirrus EP93xx chips. - * - * Copyright (C) 2006 Lennert Buytenhek - * Copyright (C) 2007 Herbert Valerio Riedel - * - * Thanks go to Michael Burian and Ray Lehtiniemi for their key - * role in the ep93xx linux community. - */ - -#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "hardware.h" -#include -#include -#include -#include - -#include "gpio-ep93xx.h" - -#include -#include - -#include "soc.h" -#include "irqs.h" - -/************************************************************************* - * Static I/O mappings that are needed for all EP93xx platforms - *************************************************************************/ -static struct map_desc ep93xx_io_desc[] __initdata =3D { - { - .virtual =3D EP93XX_AHB_VIRT_BASE, - .pfn =3D __phys_to_pfn(EP93XX_AHB_PHYS_BASE), - .length =3D EP93XX_AHB_SIZE, - .type =3D MT_DEVICE, - }, { - .virtual =3D EP93XX_APB_VIRT_BASE, - .pfn =3D __phys_to_pfn(EP93XX_APB_PHYS_BASE), - .length =3D EP93XX_APB_SIZE, - .type =3D MT_DEVICE, - }, -}; - -void __init ep93xx_map_io(void) -{ - iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc)); -} - -/************************************************************************* - * EP93xx IRQ handling - *************************************************************************/ -void __init ep93xx_init_irq(void) -{ - vic_init(EP93XX_VIC1_BASE, IRQ_EP93XX_VIC0, EP93XX_VIC1_VALID_IRQ_MASK, 0= ); - vic_init(EP93XX_VIC2_BASE, IRQ_EP93XX_VIC1, EP93XX_VIC2_VALID_IRQ_MASK, 0= ); -} - - -/************************************************************************* - * EP93xx System Controller Software Locked register handling - *************************************************************************/ - -/* - * syscon_swlock prevents anything else from writing to the syscon - * block while a software locked register is being written. - */ -static DEFINE_SPINLOCK(syscon_swlock); - -void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg) -{ - unsigned long flags; - - spin_lock_irqsave(&syscon_swlock, flags); - - __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); - __raw_writel(val, reg); - - spin_unlock_irqrestore(&syscon_swlock, flags); -} - -void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bit= s) -{ - unsigned long flags; - unsigned int val; - - spin_lock_irqsave(&syscon_swlock, flags); - - val =3D __raw_readl(EP93XX_SYSCON_DEVCFG); - val &=3D ~clear_bits; - val |=3D set_bits; - __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); - __raw_writel(val, EP93XX_SYSCON_DEVCFG); - - spin_unlock_irqrestore(&syscon_swlock, flags); -} - -/** - * ep93xx_chip_revision() - returns the EP93xx chip revision - * - * See "platform.h" for more information. - */ -unsigned int ep93xx_chip_revision(void) -{ - unsigned int v; - - v =3D __raw_readl(EP93XX_SYSCON_SYSCFG); - v &=3D EP93XX_SYSCON_SYSCFG_REV_MASK; - v >>=3D EP93XX_SYSCON_SYSCFG_REV_SHIFT; - return v; -} -EXPORT_SYMBOL_GPL(ep93xx_chip_revision); - -/************************************************************************* - * EP93xx GPIO - *************************************************************************/ -/* port A */ -static struct resource ep93xx_a_gpio_resources[] =3D { - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE, 0x04, "data"), - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x10, 0x04, "dir"), - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x90, 0x1c, "intr"), - DEFINE_RES_IRQ(IRQ_EP93XX_GPIO_AB), -}; - -static struct platform_device ep93xx_a_gpio =3D { - .name =3D "gpio-ep93xx", - .id =3D 0, - .num_resources =3D ARRAY_SIZE(ep93xx_a_gpio_resources), - .resource =3D ep93xx_a_gpio_resources, -}; - -/* port B */ -static struct resource ep93xx_b_gpio_resources[] =3D { - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x04, 0x04, "data"), - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x14, 0x04, "dir"), - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0xac, 0x1c, "intr"), - DEFINE_RES_IRQ(IRQ_EP93XX_GPIO_AB), -}; - -static struct platform_device ep93xx_b_gpio =3D { - .name =3D "gpio-ep93xx", - .id =3D 1, - .num_resources =3D ARRAY_SIZE(ep93xx_b_gpio_resources), - .resource =3D ep93xx_b_gpio_resources, -}; - -/* port C */ -static struct resource ep93xx_c_gpio_resources[] =3D { - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x08, 0x04, "data"), - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x18, 0x04, "dir"), -}; - -static struct platform_device ep93xx_c_gpio =3D { - .name =3D "gpio-ep93xx", - .id =3D 2, - .num_resources =3D ARRAY_SIZE(ep93xx_c_gpio_resources), - .resource =3D ep93xx_c_gpio_resources, -}; - -/* port D */ -static struct resource ep93xx_d_gpio_resources[] =3D { - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x0c, 0x04, "data"), - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x1c, 0x04, "dir"), -}; - -static struct platform_device ep93xx_d_gpio =3D { - .name =3D "gpio-ep93xx", - .id =3D 3, - .num_resources =3D ARRAY_SIZE(ep93xx_d_gpio_resources), - .resource =3D ep93xx_d_gpio_resources, -}; - -/* port E */ -static struct resource ep93xx_e_gpio_resources[] =3D { - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x20, 0x04, "data"), - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x24, 0x04, "dir"), -}; - -static struct platform_device ep93xx_e_gpio =3D { - .name =3D "gpio-ep93xx", - .id =3D 4, - .num_resources =3D ARRAY_SIZE(ep93xx_e_gpio_resources), - .resource =3D ep93xx_e_gpio_resources, -}; - -/* port F */ -static struct resource ep93xx_f_gpio_resources[] =3D { - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x30, 0x04, "data"), - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x34, 0x04, "dir"), - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x4c, 0x1c, "intr"), - DEFINE_RES_IRQ(IRQ_EP93XX_GPIO0MUX), - DEFINE_RES_IRQ(IRQ_EP93XX_GPIO1MUX), - DEFINE_RES_IRQ(IRQ_EP93XX_GPIO2MUX), - DEFINE_RES_IRQ(IRQ_EP93XX_GPIO3MUX), - DEFINE_RES_IRQ(IRQ_EP93XX_GPIO4MUX), - DEFINE_RES_IRQ(IRQ_EP93XX_GPIO5MUX), - DEFINE_RES_IRQ(IRQ_EP93XX_GPIO6MUX), - DEFINE_RES_IRQ(IRQ_EP93XX_GPIO7MUX), -}; - -static struct platform_device ep93xx_f_gpio =3D { - .name =3D "gpio-ep93xx", - .id =3D 5, - .num_resources =3D ARRAY_SIZE(ep93xx_f_gpio_resources), - .resource =3D ep93xx_f_gpio_resources, -}; - -/* port G */ -static struct resource ep93xx_g_gpio_resources[] =3D { - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x38, 0x04, "data"), - DEFINE_RES_MEM_NAMED(EP93XX_GPIO_PHYS_BASE + 0x3c, 0x04, "dir"), -}; - -static struct platform_device ep93xx_g_gpio =3D { - .name =3D "gpio-ep93xx", - .id =3D 6, - .num_resources =3D ARRAY_SIZE(ep93xx_g_gpio_resources), - .resource =3D ep93xx_g_gpio_resources, -}; - -static struct platform_device *ep93xx_gpio_device[] __initdata =3D { - &ep93xx_a_gpio, - &ep93xx_b_gpio, - &ep93xx_c_gpio, - &ep93xx_d_gpio, - &ep93xx_e_gpio, - &ep93xx_f_gpio, - &ep93xx_g_gpio, -}; - -/************************************************************************* - * EP93xx peripheral handling - *************************************************************************/ -#define EP93XX_UART_MCR_OFFSET (0x0100) - -static void ep93xx_uart_set_mctrl(struct amba_device *dev, - void __iomem *base, unsigned int mctrl) -{ - unsigned int mcr; - - mcr =3D 0; - if (mctrl & TIOCM_RTS) - mcr |=3D 2; - if (mctrl & TIOCM_DTR) - mcr |=3D 1; - - __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET); -} - -static struct amba_pl010_data ep93xx_uart_data =3D { - .set_mctrl =3D ep93xx_uart_set_mctrl, -}; - -static AMBA_APB_DEVICE(uart1, "apb:uart1", 0x00041010, EP93XX_UART1_PHYS_B= ASE, - { IRQ_EP93XX_UART1 }, &ep93xx_uart_data); - -static AMBA_APB_DEVICE(uart2, "apb:uart2", 0x00041010, EP93XX_UART2_PHYS_B= ASE, - { IRQ_EP93XX_UART2 }, NULL); - -static AMBA_APB_DEVICE(uart3, "apb:uart3", 0x00041010, EP93XX_UART3_PHYS_B= ASE, - { IRQ_EP93XX_UART3 }, &ep93xx_uart_data); - -static struct resource ep93xx_rtc_resource[] =3D { - DEFINE_RES_MEM(EP93XX_RTC_PHYS_BASE, 0x10c), -}; - -static struct platform_device ep93xx_rtc_device =3D { - .name =3D "ep93xx-rtc", - .id =3D -1, - .num_resources =3D ARRAY_SIZE(ep93xx_rtc_resource), - .resource =3D ep93xx_rtc_resource, -}; - -/************************************************************************* - * EP93xx OHCI USB Host - *************************************************************************/ - -static struct clk *ep93xx_ohci_host_clock; - -static int ep93xx_ohci_power_on(struct platform_device *pdev) -{ - if (!ep93xx_ohci_host_clock) { - ep93xx_ohci_host_clock =3D devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(ep93xx_ohci_host_clock)) - return PTR_ERR(ep93xx_ohci_host_clock); - } - - return clk_prepare_enable(ep93xx_ohci_host_clock); -} - -static void ep93xx_ohci_power_off(struct platform_device *pdev) -{ - clk_disable(ep93xx_ohci_host_clock); -} - -static struct usb_ohci_pdata ep93xx_ohci_pdata =3D { - .power_on =3D ep93xx_ohci_power_on, - .power_off =3D ep93xx_ohci_power_off, - .power_suspend =3D ep93xx_ohci_power_off, -}; - -static struct resource ep93xx_ohci_resources[] =3D { - DEFINE_RES_MEM(EP93XX_USB_PHYS_BASE, 0x1000), - DEFINE_RES_IRQ(IRQ_EP93XX_USB), -}; - -static u64 ep93xx_ohci_dma_mask =3D DMA_BIT_MASK(32); - -static struct platform_device ep93xx_ohci_device =3D { - .name =3D "ohci-platform", - .id =3D -1, - .num_resources =3D ARRAY_SIZE(ep93xx_ohci_resources), - .resource =3D ep93xx_ohci_resources, - .dev =3D { - .dma_mask =3D &ep93xx_ohci_dma_mask, - .coherent_dma_mask =3D DMA_BIT_MASK(32), - .platform_data =3D &ep93xx_ohci_pdata, - }, -}; - -/************************************************************************* - * EP93xx physmap'ed flash - *************************************************************************/ -static struct physmap_flash_data ep93xx_flash_data; - -static struct resource ep93xx_flash_resource =3D { - .flags =3D IORESOURCE_MEM, -}; - -static struct platform_device ep93xx_flash =3D { - .name =3D "physmap-flash", - .id =3D 0, - .dev =3D { - .platform_data =3D &ep93xx_flash_data, - }, - .num_resources =3D 1, - .resource =3D &ep93xx_flash_resource, -}; - -/** - * ep93xx_register_flash() - Register the external flash device. - * @width: bank width in octets - * @start: resource start address - * @size: resource size - */ -void __init ep93xx_register_flash(unsigned int width, - resource_size_t start, resource_size_t size) -{ - ep93xx_flash_data.width =3D width; - - ep93xx_flash_resource.start =3D start; - ep93xx_flash_resource.end =3D start + size - 1; - - platform_device_register(&ep93xx_flash); -} - - -/************************************************************************* - * EP93xx ethernet peripheral handling - *************************************************************************/ -static struct ep93xx_eth_data ep93xx_eth_data; - -static struct resource ep93xx_eth_resource[] =3D { - DEFINE_RES_MEM(EP93XX_ETHERNET_PHYS_BASE, 0x10000), - DEFINE_RES_IRQ(IRQ_EP93XX_ETHERNET), -}; - -static u64 ep93xx_eth_dma_mask =3D DMA_BIT_MASK(32); - -static struct platform_device ep93xx_eth_device =3D { - .name =3D "ep93xx-eth", - .id =3D -1, - .dev =3D { - .platform_data =3D &ep93xx_eth_data, - .coherent_dma_mask =3D DMA_BIT_MASK(32), - .dma_mask =3D &ep93xx_eth_dma_mask, - }, - .num_resources =3D ARRAY_SIZE(ep93xx_eth_resource), - .resource =3D ep93xx_eth_resource, -}; - -/** - * ep93xx_register_eth - Register the built-in ethernet platform device. - * @data: platform specific ethernet configuration (__initdata) - * @copy_addr: flag indicating that the MAC address should be copied - * from the IndAd registers (as programmed by the bootloader) - */ -void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_add= r) -{ - if (copy_addr) - memcpy_fromio(data->dev_addr, EP93XX_ETHERNET_BASE + 0x50, 6); - - ep93xx_eth_data =3D *data; - platform_device_register(&ep93xx_eth_device); -} - - -/************************************************************************* - * EP93xx i2c peripheral handling - *************************************************************************/ - -/* All EP93xx devices use the same two GPIO pins for I2C bit-banging */ -static struct gpiod_lookup_table ep93xx_i2c_gpiod_table =3D { - .dev_id =3D "i2c-gpio.0", - .table =3D { - /* Use local offsets on gpiochip/port "G" */ - GPIO_LOOKUP_IDX("gpio-ep93xx.6", 1, NULL, 0, - GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - GPIO_LOOKUP_IDX("gpio-ep93xx.6", 0, NULL, 1, - GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - }, -}; - -static struct platform_device ep93xx_i2c_device =3D { - .name =3D "i2c-gpio", - .id =3D 0, - .dev =3D { - .platform_data =3D NULL, - }, -}; - -/** - * ep93xx_register_i2c - Register the i2c platform device. - * @devices: platform specific i2c bus device information (__initdata) - * @num: the number of devices on the i2c bus - */ -void __init ep93xx_register_i2c(struct i2c_board_info *devices, int num) -{ - /* - * FIXME: this just sets the two pins as non-opendrain, as no - * platforms tries to do that anyway. Flag the applicable lines - * as open drain in the GPIO_LOOKUP above and the driver or - * gpiolib will handle open drain/open drain emulation as need - * be. Right now i2c-gpio emulates open drain which is not - * optimal. - */ - __raw_writel((0 << 1) | (0 << 0), - EP93XX_GPIO_EEDRIVE); - - i2c_register_board_info(0, devices, num); - gpiod_add_lookup_table(&ep93xx_i2c_gpiod_table); - platform_device_register(&ep93xx_i2c_device); -} - -/************************************************************************* - * EP93xx SPI peripheral handling - *************************************************************************/ -static struct ep93xx_spi_info ep93xx_spi_master_data; - -static struct resource ep93xx_spi_resources[] =3D { - DEFINE_RES_MEM(EP93XX_SPI_PHYS_BASE, 0x18), - DEFINE_RES_IRQ(IRQ_EP93XX_SSP), -}; - -static u64 ep93xx_spi_dma_mask =3D DMA_BIT_MASK(32); - -static struct platform_device ep93xx_spi_device =3D { - .name =3D "ep93xx-spi", - .id =3D 0, - .dev =3D { - .platform_data =3D &ep93xx_spi_master_data, - .coherent_dma_mask =3D DMA_BIT_MASK(32), - .dma_mask =3D &ep93xx_spi_dma_mask, - }, - .num_resources =3D ARRAY_SIZE(ep93xx_spi_resources), - .resource =3D ep93xx_spi_resources, -}; - -/** - * ep93xx_register_spi() - registers spi platform device - * @info: ep93xx board specific spi master info (__initdata) - * @devices: SPI devices to register (__initdata) - * @num: number of SPI devices to register - * - * This function registers platform device for the EP93xx SPI controller a= nd - * also makes sure that SPI pins are muxed so that I2S is not using those = pins. - */ -void __init ep93xx_register_spi(struct ep93xx_spi_info *info, - struct spi_board_info *devices, int num) -{ - /* - * When SPI is used, we need to make sure that I2S is muxed off from - * SPI pins. - */ - ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONSSP); - - ep93xx_spi_master_data =3D *info; - spi_register_board_info(devices, num); - platform_device_register(&ep93xx_spi_device); -} - -/************************************************************************* - * EP93xx LEDs - *************************************************************************/ -static const struct gpio_led ep93xx_led_pins[] __initconst =3D { - { - .name =3D "platform:grled", - }, { - .name =3D "platform:rdled", - }, -}; - -static const struct gpio_led_platform_data ep93xx_led_data __initconst =3D= { - .num_leds =3D ARRAY_SIZE(ep93xx_led_pins), - .leds =3D ep93xx_led_pins, -}; - -static struct gpiod_lookup_table ep93xx_leds_gpio_table =3D { - .dev_id =3D "leds-gpio", - .table =3D { - /* Use local offsets on gpiochip/port "E" */ - GPIO_LOOKUP_IDX("gpio-ep93xx.4", 0, NULL, 0, GPIO_ACTIVE_HIGH), - GPIO_LOOKUP_IDX("gpio-ep93xx.4", 1, NULL, 1, GPIO_ACTIVE_HIGH), - { } - }, -}; - -/************************************************************************* - * EP93xx pwm peripheral handling - *************************************************************************/ -static struct resource ep93xx_pwm0_resource[] =3D { - DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE, 0x10), -}; - -static struct platform_device ep93xx_pwm0_device =3D { - .name =3D "ep93xx-pwm", - .id =3D 0, - .num_resources =3D ARRAY_SIZE(ep93xx_pwm0_resource), - .resource =3D ep93xx_pwm0_resource, -}; - -static struct resource ep93xx_pwm1_resource[] =3D { - DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE + 0x20, 0x10), -}; - -static struct platform_device ep93xx_pwm1_device =3D { - .name =3D "ep93xx-pwm", - .id =3D 1, - .num_resources =3D ARRAY_SIZE(ep93xx_pwm1_resource), - .resource =3D ep93xx_pwm1_resource, -}; - -void __init ep93xx_register_pwm(int pwm0, int pwm1) -{ - if (pwm0) - platform_device_register(&ep93xx_pwm0_device); - - /* NOTE: EP9307 does not have PWMOUT1 (pin EGPIO14) */ - if (pwm1) - platform_device_register(&ep93xx_pwm1_device); -} - -int ep93xx_pwm_acquire_gpio(struct platform_device *pdev) -{ - int err; - - if (pdev->id =3D=3D 0) { - err =3D 0; - } else if (pdev->id =3D=3D 1) { - err =3D gpio_request(EP93XX_GPIO_LINE_EGPIO14, - dev_name(&pdev->dev)); - if (err) - return err; - err =3D gpio_direction_output(EP93XX_GPIO_LINE_EGPIO14, 0); - if (err) - goto fail; - - /* PWM 1 output on EGPIO[14] */ - ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_PONG); - } else { - err =3D -ENODEV; - } - - return err; - -fail: - gpio_free(EP93XX_GPIO_LINE_EGPIO14); - return err; -} -EXPORT_SYMBOL(ep93xx_pwm_acquire_gpio); - -void ep93xx_pwm_release_gpio(struct platform_device *pdev) -{ - if (pdev->id =3D=3D 1) { - gpio_direction_input(EP93XX_GPIO_LINE_EGPIO14); - gpio_free(EP93XX_GPIO_LINE_EGPIO14); - - /* EGPIO[14] used for GPIO */ - ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_PONG); - } -} -EXPORT_SYMBOL(ep93xx_pwm_release_gpio); - - -/************************************************************************* - * EP93xx video peripheral handling - *************************************************************************/ -static struct ep93xxfb_mach_info ep93xxfb_data; - -static struct resource ep93xx_fb_resource[] =3D { - DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE, 0x800), -}; - -static struct platform_device ep93xx_fb_device =3D { - .name =3D "ep93xx-fb", - .id =3D -1, - .dev =3D { - .platform_data =3D &ep93xxfb_data, - .coherent_dma_mask =3D DMA_BIT_MASK(32), - .dma_mask =3D &ep93xx_fb_device.dev.coherent_dma_mask, - }, - .num_resources =3D ARRAY_SIZE(ep93xx_fb_resource), - .resource =3D ep93xx_fb_resource, -}; - -/* The backlight use a single register in the framebuffer's register space= */ -#define EP93XX_RASTER_REG_BRIGHTNESS 0x20 - -static struct resource ep93xx_bl_resources[] =3D { - DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE + - EP93XX_RASTER_REG_BRIGHTNESS, 0x04), -}; - -static struct platform_device ep93xx_bl_device =3D { - .name =3D "ep93xx-bl", - .id =3D -1, - .num_resources =3D ARRAY_SIZE(ep93xx_bl_resources), - .resource =3D ep93xx_bl_resources, -}; - -/** - * ep93xx_register_fb - Register the framebuffer platform device. - * @data: platform specific framebuffer configuration (__initdata) - */ -void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data) -{ - ep93xxfb_data =3D *data; - platform_device_register(&ep93xx_fb_device); - platform_device_register(&ep93xx_bl_device); -} - - -/************************************************************************* - * EP93xx matrix keypad peripheral handling - *************************************************************************/ -static struct ep93xx_keypad_platform_data ep93xx_keypad_data; - -static struct resource ep93xx_keypad_resource[] =3D { - DEFINE_RES_MEM(EP93XX_KEY_MATRIX_PHYS_BASE, 0x0c), - DEFINE_RES_IRQ(IRQ_EP93XX_KEY), -}; - -static struct platform_device ep93xx_keypad_device =3D { - .name =3D "ep93xx-keypad", - .id =3D -1, - .dev =3D { - .platform_data =3D &ep93xx_keypad_data, - }, - .num_resources =3D ARRAY_SIZE(ep93xx_keypad_resource), - .resource =3D ep93xx_keypad_resource, -}; - -/** - * ep93xx_register_keypad - Register the keypad platform device. - * @data: platform specific keypad configuration (__initdata) - */ -void __init ep93xx_register_keypad(struct ep93xx_keypad_platform_data *dat= a) -{ - ep93xx_keypad_data =3D *data; - platform_device_register(&ep93xx_keypad_device); -} - -int ep93xx_keypad_acquire_gpio(struct platform_device *pdev) -{ - int err; - int i; - - for (i =3D 0; i < 8; i++) { - err =3D gpio_request(EP93XX_GPIO_LINE_C(i), dev_name(&pdev->dev)); - if (err) - goto fail_gpio_c; - err =3D gpio_request(EP93XX_GPIO_LINE_D(i), dev_name(&pdev->dev)); - if (err) - goto fail_gpio_d; - } - - /* Enable the keypad controller; GPIO ports C and D used for keypad */ - ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_KEYS | - EP93XX_SYSCON_DEVCFG_GONK); - - return 0; - -fail_gpio_d: - gpio_free(EP93XX_GPIO_LINE_C(i)); -fail_gpio_c: - for (--i; i >=3D 0; --i) { - gpio_free(EP93XX_GPIO_LINE_C(i)); - gpio_free(EP93XX_GPIO_LINE_D(i)); - } - return err; -} -EXPORT_SYMBOL(ep93xx_keypad_acquire_gpio); - -void ep93xx_keypad_release_gpio(struct platform_device *pdev) -{ - int i; - - for (i =3D 0; i < 8; i++) { - gpio_free(EP93XX_GPIO_LINE_C(i)); - gpio_free(EP93XX_GPIO_LINE_D(i)); - } - - /* Disable the keypad controller; GPIO ports C and D used for GPIO */ - ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS | - EP93XX_SYSCON_DEVCFG_GONK); -} -EXPORT_SYMBOL(ep93xx_keypad_release_gpio); - -/************************************************************************* - * EP93xx I2S audio peripheral handling - *************************************************************************/ -static struct resource ep93xx_i2s_resource[] =3D { - DEFINE_RES_MEM(EP93XX_I2S_PHYS_BASE, 0x100), - DEFINE_RES_IRQ(IRQ_EP93XX_SAI), -}; - -static struct platform_device ep93xx_i2s_device =3D { - .name =3D "ep93xx-i2s", - .id =3D -1, - .num_resources =3D ARRAY_SIZE(ep93xx_i2s_resource), - .resource =3D ep93xx_i2s_resource, -}; - -static struct platform_device ep93xx_pcm_device =3D { - .name =3D "ep93xx-pcm-audio", - .id =3D -1, -}; - -void __init ep93xx_register_i2s(void) -{ - platform_device_register(&ep93xx_i2s_device); - platform_device_register(&ep93xx_pcm_device); -} - -#define EP93XX_SYSCON_DEVCFG_I2S_MASK (EP93XX_SYSCON_DEVCFG_I2SONSSP | \ - EP93XX_SYSCON_DEVCFG_I2SONAC97) - -#define EP93XX_I2SCLKDIV_MASK (EP93XX_SYSCON_I2SCLKDIV_ORIDE | \ - EP93XX_SYSCON_I2SCLKDIV_SPOL) - -int ep93xx_i2s_acquire(void) -{ - unsigned val; - - ep93xx_devcfg_set_clear(EP93XX_SYSCON_DEVCFG_I2SONAC97, - EP93XX_SYSCON_DEVCFG_I2S_MASK); - - /* - * This is potentially racy with the clock api for i2s_mclk, sclk and=20 - * lrclk. Since the i2s driver is the only user of those clocks we - * rely on it to prevent parallel use of this function and the=20 - * clock api for the i2s clocks. - */ - val =3D __raw_readl(EP93XX_SYSCON_I2SCLKDIV); - val &=3D ~EP93XX_I2SCLKDIV_MASK; - val |=3D EP93XX_SYSCON_I2SCLKDIV_ORIDE | EP93XX_SYSCON_I2SCLKDIV_SPOL; - ep93xx_syscon_swlocked_write(val, EP93XX_SYSCON_I2SCLKDIV); - - return 0; -} -EXPORT_SYMBOL(ep93xx_i2s_acquire); - -void ep93xx_i2s_release(void) -{ - ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2S_MASK); -} -EXPORT_SYMBOL(ep93xx_i2s_release); - -/************************************************************************* - * EP93xx AC97 audio peripheral handling - *************************************************************************/ -static struct resource ep93xx_ac97_resources[] =3D { - DEFINE_RES_MEM(EP93XX_AAC_PHYS_BASE, 0xac), - DEFINE_RES_IRQ(IRQ_EP93XX_AACINTR), -}; - -static struct platform_device ep93xx_ac97_device =3D { - .name =3D "ep93xx-ac97", - .id =3D -1, - .num_resources =3D ARRAY_SIZE(ep93xx_ac97_resources), - .resource =3D ep93xx_ac97_resources, -}; - -void __init ep93xx_register_ac97(void) -{ - /* - * Make sure that the AC97 pins are not used by I2S. - */ - ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONAC97); - - platform_device_register(&ep93xx_ac97_device); - platform_device_register(&ep93xx_pcm_device); -} - -/************************************************************************* - * EP93xx Watchdog - *************************************************************************/ -static struct resource ep93xx_wdt_resources[] =3D { - DEFINE_RES_MEM(EP93XX_WATCHDOG_PHYS_BASE, 0x08), -}; - -static struct platform_device ep93xx_wdt_device =3D { - .name =3D "ep93xx-wdt", - .id =3D -1, - .num_resources =3D ARRAY_SIZE(ep93xx_wdt_resources), - .resource =3D ep93xx_wdt_resources, -}; - -/************************************************************************* - * EP93xx IDE - *************************************************************************/ -static struct resource ep93xx_ide_resources[] =3D { - DEFINE_RES_MEM(EP93XX_IDE_PHYS_BASE, 0x38), - DEFINE_RES_IRQ(IRQ_EP93XX_EXT3), -}; - -static struct platform_device ep93xx_ide_device =3D { - .name =3D "ep93xx-ide", - .id =3D -1, - .dev =3D { - .dma_mask =3D &ep93xx_ide_device.dev.coherent_dma_mask, - .coherent_dma_mask =3D DMA_BIT_MASK(32), - }, - .num_resources =3D ARRAY_SIZE(ep93xx_ide_resources), - .resource =3D ep93xx_ide_resources, -}; - -void __init ep93xx_register_ide(void) -{ - platform_device_register(&ep93xx_ide_device); -} - -int ep93xx_ide_acquire_gpio(struct platform_device *pdev) -{ - int err; - int i; - - err =3D gpio_request(EP93XX_GPIO_LINE_EGPIO2, dev_name(&pdev->dev)); - if (err) - return err; - err =3D gpio_request(EP93XX_GPIO_LINE_EGPIO15, dev_name(&pdev->dev)); - if (err) - goto fail_egpio15; - for (i =3D 2; i < 8; i++) { - err =3D gpio_request(EP93XX_GPIO_LINE_E(i), dev_name(&pdev->dev)); - if (err) - goto fail_gpio_e; - } - for (i =3D 4; i < 8; i++) { - err =3D gpio_request(EP93XX_GPIO_LINE_G(i), dev_name(&pdev->dev)); - if (err) - goto fail_gpio_g; - } - for (i =3D 0; i < 8; i++) { - err =3D gpio_request(EP93XX_GPIO_LINE_H(i), dev_name(&pdev->dev)); - if (err) - goto fail_gpio_h; - } - - /* GPIO ports E[7:2], G[7:4] and H used by IDE */ - ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_EONIDE | - EP93XX_SYSCON_DEVCFG_GONIDE | - EP93XX_SYSCON_DEVCFG_HONIDE); - return 0; - -fail_gpio_h: - for (--i; i >=3D 0; --i) - gpio_free(EP93XX_GPIO_LINE_H(i)); - i =3D 8; -fail_gpio_g: - for (--i; i >=3D 4; --i) - gpio_free(EP93XX_GPIO_LINE_G(i)); - i =3D 8; -fail_gpio_e: - for (--i; i >=3D 2; --i) - gpio_free(EP93XX_GPIO_LINE_E(i)); - gpio_free(EP93XX_GPIO_LINE_EGPIO15); -fail_egpio15: - gpio_free(EP93XX_GPIO_LINE_EGPIO2); - return err; -} -EXPORT_SYMBOL(ep93xx_ide_acquire_gpio); - -void ep93xx_ide_release_gpio(struct platform_device *pdev) -{ - int i; - - for (i =3D 2; i < 8; i++) - gpio_free(EP93XX_GPIO_LINE_E(i)); - for (i =3D 4; i < 8; i++) - gpio_free(EP93XX_GPIO_LINE_G(i)); - for (i =3D 0; i < 8; i++) - gpio_free(EP93XX_GPIO_LINE_H(i)); - gpio_free(EP93XX_GPIO_LINE_EGPIO15); - gpio_free(EP93XX_GPIO_LINE_EGPIO2); - - - /* GPIO ports E[7:2], G[7:4] and H used by GPIO */ - ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_EONIDE | - EP93XX_SYSCON_DEVCFG_GONIDE | - EP93XX_SYSCON_DEVCFG_HONIDE); -} -EXPORT_SYMBOL(ep93xx_ide_release_gpio); - -/************************************************************************* - * EP93xx ADC - *************************************************************************/ -static struct resource ep93xx_adc_resources[] =3D { - DEFINE_RES_MEM(EP93XX_ADC_PHYS_BASE, 0x28), - DEFINE_RES_IRQ(IRQ_EP93XX_TOUCH), -}; - -static struct platform_device ep93xx_adc_device =3D { - .name =3D "ep93xx-adc", - .id =3D -1, - .num_resources =3D ARRAY_SIZE(ep93xx_adc_resources), - .resource =3D ep93xx_adc_resources, -}; - -void __init ep93xx_register_adc(void) -{ - /* Power up ADC, deactivate Touch Screen Controller */ - ep93xx_devcfg_set_clear(EP93XX_SYSCON_DEVCFG_TIN, - EP93XX_SYSCON_DEVCFG_ADCPD); - - platform_device_register(&ep93xx_adc_device); -} - -/************************************************************************* - * EP93xx Security peripheral - *************************************************************************/ - -/* - * The Maverick Key is 256 bits of micro fuses blown at the factory during - * manufacturing to uniquely identify a part. - * - * See: http://arm.cirrus.com/forum/viewtopic.php?t=3D486&highlight=3Dmave= rick+key - */ -#define EP93XX_SECURITY_REG(x) (EP93XX_SECURITY_BASE + (x)) -#define EP93XX_SECURITY_SECFLG EP93XX_SECURITY_REG(0x2400) -#define EP93XX_SECURITY_FUSEFLG EP93XX_SECURITY_REG(0x2410) -#define EP93XX_SECURITY_UNIQID EP93XX_SECURITY_REG(0x2440) -#define EP93XX_SECURITY_UNIQCHK EP93XX_SECURITY_REG(0x2450) -#define EP93XX_SECURITY_UNIQVAL EP93XX_SECURITY_REG(0x2460) -#define EP93XX_SECURITY_SECID1 EP93XX_SECURITY_REG(0x2500) -#define EP93XX_SECURITY_SECID2 EP93XX_SECURITY_REG(0x2504) -#define EP93XX_SECURITY_SECCHK1 EP93XX_SECURITY_REG(0x2520) -#define EP93XX_SECURITY_SECCHK2 EP93XX_SECURITY_REG(0x2524) -#define EP93XX_SECURITY_UNIQID2 EP93XX_SECURITY_REG(0x2700) -#define EP93XX_SECURITY_UNIQID3 EP93XX_SECURITY_REG(0x2704) -#define EP93XX_SECURITY_UNIQID4 EP93XX_SECURITY_REG(0x2708) -#define EP93XX_SECURITY_UNIQID5 EP93XX_SECURITY_REG(0x270c) - -static char ep93xx_soc_id[33]; - -static const char __init *ep93xx_get_soc_id(void) -{ - unsigned int id, id2, id3, id4, id5; - - if (__raw_readl(EP93XX_SECURITY_UNIQVAL) !=3D 1) - return "bad Hamming code"; - - id =3D __raw_readl(EP93XX_SECURITY_UNIQID); - id2 =3D __raw_readl(EP93XX_SECURITY_UNIQID2); - id3 =3D __raw_readl(EP93XX_SECURITY_UNIQID3); - id4 =3D __raw_readl(EP93XX_SECURITY_UNIQID4); - id5 =3D __raw_readl(EP93XX_SECURITY_UNIQID5); - - if (id !=3D id2) - return "invalid"; - - /* Toss the unique ID into the entropy pool */ - add_device_randomness(&id2, 4); - add_device_randomness(&id3, 4); - add_device_randomness(&id4, 4); - add_device_randomness(&id5, 4); - - snprintf(ep93xx_soc_id, sizeof(ep93xx_soc_id), - "%08x%08x%08x%08x", id2, id3, id4, id5); - - return ep93xx_soc_id; -} - -static const char __init *ep93xx_get_soc_rev(void) -{ - int rev =3D ep93xx_chip_revision(); - - switch (rev) { - case EP93XX_CHIP_REV_D0: - return "D0"; - case EP93XX_CHIP_REV_D1: - return "D1"; - case EP93XX_CHIP_REV_E0: - return "E0"; - case EP93XX_CHIP_REV_E1: - return "E1"; - case EP93XX_CHIP_REV_E2: - return "E2"; - default: - return "unknown"; - } -} - -static const char __init *ep93xx_get_machine_name(void) -{ - return kasprintf(GFP_KERNEL,"%s", machine_desc->name); -} - -static struct device __init *ep93xx_init_soc(void) -{ - struct soc_device_attribute *soc_dev_attr; - struct soc_device *soc_dev; - - soc_dev_attr =3D kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); - if (!soc_dev_attr) - return NULL; - - soc_dev_attr->machine =3D ep93xx_get_machine_name(); - soc_dev_attr->family =3D "Cirrus Logic EP93xx"; - soc_dev_attr->revision =3D ep93xx_get_soc_rev(); - soc_dev_attr->soc_id =3D ep93xx_get_soc_id(); - - soc_dev =3D soc_device_register(soc_dev_attr); - if (IS_ERR(soc_dev)) { - kfree(soc_dev_attr->machine); - kfree(soc_dev_attr); - return NULL; - } - - return soc_device_to_device(soc_dev); -} - -struct device __init *ep93xx_init_devices(void) -{ - struct device *parent; - int i; - - /* Disallow access to MaverickCrunch initially */ - ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA); - - /* Default all ports to GPIO */ - ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS | - EP93XX_SYSCON_DEVCFG_GONK | - EP93XX_SYSCON_DEVCFG_EONIDE | - EP93XX_SYSCON_DEVCFG_GONIDE | - EP93XX_SYSCON_DEVCFG_HONIDE); - - parent =3D ep93xx_init_soc(); - - /* Get the GPIO working early, other devices need it */ - for (i =3D 0; i < ARRAY_SIZE(ep93xx_gpio_device); i++) - platform_device_register(ep93xx_gpio_device[i]); - - amba_device_register(&uart1_device, &iomem_resource); - amba_device_register(&uart2_device, &iomem_resource); - amba_device_register(&uart3_device, &iomem_resource); - - platform_device_register(&ep93xx_rtc_device); - platform_device_register(&ep93xx_ohci_device); - platform_device_register(&ep93xx_wdt_device); - - gpiod_add_lookup_table(&ep93xx_leds_gpio_table); - gpio_led_register_device(-1, &ep93xx_led_data); - - return parent; -} - -void ep93xx_restart(enum reboot_mode mode, const char *cmd) -{ - /* - * Set then clear the SWRST bit to initiate a software reset - */ - ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_SWRST); - ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_SWRST); - - while (1) - ; -} diff --git a/arch/arm/mach-ep93xx/dma.c b/arch/arm/mach-ep93xx/dma.c deleted file mode 100644 index 273954cbfced..000000000000 --- a/arch/arm/mach-ep93xx/dma.c +++ /dev/null @@ -1,115 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-ep93xx/dma.c - * - * Platform support code for the EP93xx dmaengine driver. - * - * Copyright (C) 2011 Mika Westerberg - * - * This work is based on the original dma-m2p implementation with - * following copyrights: - * - * Copyright (C) 2006 Lennert Buytenhek - * Copyright (C) 2006 Applied Data Systems - * Copyright (C) 2009 Ryan Mallon - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include "hardware.h" - -#include "soc.h" - -#define DMA_CHANNEL(_name, _base, _irq) \ - { .name =3D (_name), .base =3D (_base), .irq =3D (_irq) } - -/* - * DMA M2P channels. - * - * On the EP93xx chip the following peripherals my be allocated to the 10 - * Memory to Internal Peripheral (M2P) channels (5 transmit + 5 receive). - * - * I2S contains 3 Tx and 3 Rx DMA Channels - * AAC contains 3 Tx and 3 Rx DMA Channels - * UART1 contains 1 Tx and 1 Rx DMA Channels - * UART2 contains 1 Tx and 1 Rx DMA Channels - * UART3 contains 1 Tx and 1 Rx DMA Channels - * IrDA contains 1 Tx and 1 Rx DMA Channels - * - * Registers are mapped statically in ep93xx_map_io(). - */ -static struct ep93xx_dma_chan_data ep93xx_dma_m2p_channels[] =3D { - DMA_CHANNEL("m2p0", EP93XX_DMA_BASE + 0x0000, IRQ_EP93XX_DMAM2P0), - DMA_CHANNEL("m2p1", EP93XX_DMA_BASE + 0x0040, IRQ_EP93XX_DMAM2P1), - DMA_CHANNEL("m2p2", EP93XX_DMA_BASE + 0x0080, IRQ_EP93XX_DMAM2P2), - DMA_CHANNEL("m2p3", EP93XX_DMA_BASE + 0x00c0, IRQ_EP93XX_DMAM2P3), - DMA_CHANNEL("m2p4", EP93XX_DMA_BASE + 0x0240, IRQ_EP93XX_DMAM2P4), - DMA_CHANNEL("m2p5", EP93XX_DMA_BASE + 0x0200, IRQ_EP93XX_DMAM2P5), - DMA_CHANNEL("m2p6", EP93XX_DMA_BASE + 0x02c0, IRQ_EP93XX_DMAM2P6), - DMA_CHANNEL("m2p7", EP93XX_DMA_BASE + 0x0280, IRQ_EP93XX_DMAM2P7), - DMA_CHANNEL("m2p8", EP93XX_DMA_BASE + 0x0340, IRQ_EP93XX_DMAM2P8), - DMA_CHANNEL("m2p9", EP93XX_DMA_BASE + 0x0300, IRQ_EP93XX_DMAM2P9), -}; - -static struct ep93xx_dma_platform_data ep93xx_dma_m2p_data =3D { - .channels =3D ep93xx_dma_m2p_channels, - .num_channels =3D ARRAY_SIZE(ep93xx_dma_m2p_channels), -}; - -static u64 ep93xx_dma_m2p_mask =3D DMA_BIT_MASK(32); - -static struct platform_device ep93xx_dma_m2p_device =3D { - .name =3D "ep93xx-dma-m2p", - .id =3D -1, - .dev =3D { - .platform_data =3D &ep93xx_dma_m2p_data, - .dma_mask =3D &ep93xx_dma_m2p_mask, - .coherent_dma_mask =3D DMA_BIT_MASK(32), - }, -}; - -/* - * DMA M2M channels. - * - * There are 2 M2M channels which support memcpy/memset and in addition si= mple - * hardware requests from/to SSP and IDE. We do not implement an external - * hardware requests. - * - * Registers are mapped statically in ep93xx_map_io(). - */ -static struct ep93xx_dma_chan_data ep93xx_dma_m2m_channels[] =3D { - DMA_CHANNEL("m2m0", EP93XX_DMA_BASE + 0x0100, IRQ_EP93XX_DMAM2M0), - DMA_CHANNEL("m2m1", EP93XX_DMA_BASE + 0x0140, IRQ_EP93XX_DMAM2M1), -}; - -static struct ep93xx_dma_platform_data ep93xx_dma_m2m_data =3D { - .channels =3D ep93xx_dma_m2m_channels, - .num_channels =3D ARRAY_SIZE(ep93xx_dma_m2m_channels), -}; - -static u64 ep93xx_dma_m2m_mask =3D DMA_BIT_MASK(32); - -static struct platform_device ep93xx_dma_m2m_device =3D { - .name =3D "ep93xx-dma-m2m", - .id =3D -1, - .dev =3D { - .platform_data =3D &ep93xx_dma_m2m_data, - .dma_mask =3D &ep93xx_dma_m2m_mask, - .coherent_dma_mask =3D DMA_BIT_MASK(32), - }, -}; - -static int __init ep93xx_dma_init(void) -{ - platform_device_register(&ep93xx_dma_m2p_device); - platform_device_register(&ep93xx_dma_m2m_device); - return 0; -} -arch_initcall(ep93xx_dma_init); diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c deleted file mode 100644 index c1e880946f72..000000000000 --- a/arch/arm/mach-ep93xx/edb93xx.c +++ /dev/null @@ -1,344 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-ep93xx/edb93xx.c - * Cirrus Logic EDB93xx Development Board support. - * - * EDB93XX, EDB9301, EDB9307A - * Copyright (C) 2008-2009 H Hartley Sweeten - * - * EDB9302 - * Copyright (C) 2006 George Kashperko - * - * EDB9302A, EDB9315, EDB9315A - * Copyright (C) 2006 Lennert Buytenhek - * - * EDB9307 - * Copyright (C) 2007 Herbert Valerio Riedel - * - * EDB9312 - * Copyright (C) 2006 Infosys Technologies Limited - * Toufeeq Hussain - */ - -#include -#include -#include -#include -#include -#include - -#include - -#include "hardware.h" -#include -#include -#include "gpio-ep93xx.h" - -#include -#include - -#include "soc.h" - -static void __init edb93xx_register_flash(void) -{ - if (machine_is_edb9307() || machine_is_edb9312() || - machine_is_edb9315()) { - ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M); - } else { - ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M); - } -} - -static struct ep93xx_eth_data __initdata edb93xx_eth_data =3D { - .phy_id =3D 1, -}; - - -/************************************************************************* - * EDB93xx i2c peripheral handling - *************************************************************************/ - -static struct i2c_board_info __initdata edb93xxa_i2c_board_info[] =3D { - { - I2C_BOARD_INFO("isl1208", 0x6f), - }, -}; - -static struct i2c_board_info __initdata edb93xx_i2c_board_info[] =3D { - { - I2C_BOARD_INFO("ds1337", 0x68), - }, -}; - -static void __init edb93xx_register_i2c(void) -{ - if (machine_is_edb9302a() || machine_is_edb9307a() || - machine_is_edb9315a()) { - ep93xx_register_i2c(edb93xxa_i2c_board_info, - ARRAY_SIZE(edb93xxa_i2c_board_info)); - } else if (machine_is_edb9302() || machine_is_edb9307() - || machine_is_edb9312() || machine_is_edb9315()) { - ep93xx_register_i2c(edb93xx_i2c_board_info, - ARRAY_SIZE(edb93xx_i2c_board_info)); - } -} - - -/************************************************************************* - * EDB93xx SPI peripheral handling - *************************************************************************/ -static struct cs4271_platform_data edb93xx_cs4271_data =3D { - .gpio_nreset =3D -EINVAL, /* filled in later */ -}; - -static struct spi_board_info edb93xx_spi_board_info[] __initdata =3D { - { - .modalias =3D "cs4271", - .platform_data =3D &edb93xx_cs4271_data, - .max_speed_hz =3D 6000000, - .bus_num =3D 0, - .chip_select =3D 0, - .mode =3D SPI_MODE_3, - }, -}; - -static struct gpiod_lookup_table edb93xx_spi_cs_gpio_table =3D { - .dev_id =3D "spi0", - .table =3D { - GPIO_LOOKUP("gpio-ep93xx.0", 6, "cs", GPIO_ACTIVE_LOW), - { }, - }, -}; - -static struct ep93xx_spi_info edb93xx_spi_info __initdata =3D { - /* Intentionally left blank */ -}; - -static void __init edb93xx_register_spi(void) -{ - if (machine_is_edb9301() || machine_is_edb9302()) - edb93xx_cs4271_data.gpio_nreset =3D EP93XX_GPIO_LINE_EGPIO1; - else if (machine_is_edb9302a() || machine_is_edb9307a()) - edb93xx_cs4271_data.gpio_nreset =3D EP93XX_GPIO_LINE_H(2); - else if (machine_is_edb9315a()) - edb93xx_cs4271_data.gpio_nreset =3D EP93XX_GPIO_LINE_EGPIO14; - - gpiod_add_lookup_table(&edb93xx_spi_cs_gpio_table); - ep93xx_register_spi(&edb93xx_spi_info, edb93xx_spi_board_info, - ARRAY_SIZE(edb93xx_spi_board_info)); -} - - -/************************************************************************* - * EDB93xx I2S - *************************************************************************/ -static struct platform_device edb93xx_audio_device =3D { - .name =3D "edb93xx-audio", - .id =3D -1, -}; - -static int __init edb93xx_has_audio(void) -{ - return (machine_is_edb9301() || machine_is_edb9302() || - machine_is_edb9302a() || machine_is_edb9307a() || - machine_is_edb9315a()); -} - -static void __init edb93xx_register_i2s(void) -{ - if (edb93xx_has_audio()) { - ep93xx_register_i2s(); - platform_device_register(&edb93xx_audio_device); - } -} - - -/************************************************************************* - * EDB93xx pwm - *************************************************************************/ -static void __init edb93xx_register_pwm(void) -{ - if (machine_is_edb9301() || - machine_is_edb9302() || machine_is_edb9302a()) { - /* EP9301 and EP9302 only have pwm.1 (EGPIO14) */ - ep93xx_register_pwm(0, 1); - } else if (machine_is_edb9307() || machine_is_edb9307a()) { - /* EP9307 only has pwm.0 (PWMOUT) */ - ep93xx_register_pwm(1, 0); - } else { - /* EP9312 and EP9315 have both */ - ep93xx_register_pwm(1, 1); - } -} - - -/************************************************************************* - * EDB93xx framebuffer - *************************************************************************/ -static struct ep93xxfb_mach_info __initdata edb93xxfb_info =3D { - .flags =3D 0, -}; - -static int __init edb93xx_has_fb(void) -{ - /* These platforms have an ep93xx with video capability */ - return machine_is_edb9307() || machine_is_edb9307a() || - machine_is_edb9312() || machine_is_edb9315() || - machine_is_edb9315a(); -} - -static void __init edb93xx_register_fb(void) -{ - if (!edb93xx_has_fb()) - return; - - if (machine_is_edb9307a() || machine_is_edb9315a()) - edb93xxfb_info.flags |=3D EP93XXFB_USE_SDCSN0; - else - edb93xxfb_info.flags |=3D EP93XXFB_USE_SDCSN3; - - ep93xx_register_fb(&edb93xxfb_info); -} - - -/************************************************************************* - * EDB93xx IDE - *************************************************************************/ -static int __init edb93xx_has_ide(void) -{ - /* - * Although EDB9312 and EDB9315 do have IDE capability, they have - * INTRQ line wired as pull-up, which makes using IDE interface - * problematic. - */ - return machine_is_edb9312() || machine_is_edb9315() || - machine_is_edb9315a(); -} - -static void __init edb93xx_register_ide(void) -{ - if (!edb93xx_has_ide()) - return; - - ep93xx_register_ide(); -} - - -static void __init edb93xx_init_machine(void) -{ - ep93xx_init_devices(); - edb93xx_register_flash(); - ep93xx_register_eth(&edb93xx_eth_data, 1); - edb93xx_register_i2c(); - edb93xx_register_spi(); - edb93xx_register_i2s(); - edb93xx_register_pwm(); - edb93xx_register_fb(); - edb93xx_register_ide(); - ep93xx_register_adc(); -} - - -#ifdef CONFIG_MACH_EDB9301 -MACHINE_START(EDB9301, "Cirrus Logic EDB9301 Evaluation Board") - /* Maintainer: H Hartley Sweeten */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS, - .map_io =3D ep93xx_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D edb93xx_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_EDB9302 -MACHINE_START(EDB9302, "Cirrus Logic EDB9302 Evaluation Board") - /* Maintainer: George Kashperko */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS, - .map_io =3D ep93xx_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D edb93xx_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_EDB9302A -MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board") - /* Maintainer: Lennert Buytenhek */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS, - .map_io =3D ep93xx_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D edb93xx_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_EDB9307 -MACHINE_START(EDB9307, "Cirrus Logic EDB9307 Evaluation Board") - /* Maintainer: Herbert Valerio Riedel */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS, - .map_io =3D ep93xx_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D edb93xx_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_EDB9307A -MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board") - /* Maintainer: H Hartley Sweeten */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS, - .map_io =3D ep93xx_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D edb93xx_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_EDB9312 -MACHINE_START(EDB9312, "Cirrus Logic EDB9312 Evaluation Board") - /* Maintainer: Toufeeq Hussain */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS, - .map_io =3D ep93xx_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D edb93xx_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_EDB9315 -MACHINE_START(EDB9315, "Cirrus Logic EDB9315 Evaluation Board") - /* Maintainer: Lennert Buytenhek */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS, - .map_io =3D ep93xx_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D edb93xx_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_EDB9315A -MACHINE_START(EDB9315A, "Cirrus Logic EDB9315A Evaluation Board") - /* Maintainer: Lennert Buytenhek */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS, - .map_io =3D ep93xx_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D edb93xx_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END -#endif diff --git a/arch/arm/mach-ep93xx/ep93xx-regs.h b/arch/arm/mach-ep93xx/ep93= xx-regs.h deleted file mode 100644 index 8fa3646de0a4..000000000000 --- a/arch/arm/mach-ep93xx/ep93xx-regs.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_ARCH_EP93XX_REGS_H -#define __ASM_ARCH_EP93XX_REGS_H - -/* - * EP93xx linux memory map: - * - * virt phys size - * fe800000 5M per-platform mappings - * fed00000 80800000 2M APB - * fef00000 80000000 1M AHB - */ - -#define EP93XX_AHB_PHYS_BASE 0x80000000 -#define EP93XX_AHB_VIRT_BASE 0xfef00000 -#define EP93XX_AHB_SIZE 0x00100000 - -#define EP93XX_AHB_PHYS(x) (EP93XX_AHB_PHYS_BASE + (x)) -#define EP93XX_AHB_IOMEM(x) IOMEM(EP93XX_AHB_VIRT_BASE + (x)) - -#define EP93XX_APB_PHYS_BASE 0x80800000 -#define EP93XX_APB_VIRT_BASE 0xfed00000 -#define EP93XX_APB_SIZE 0x00200000 - -#define EP93XX_APB_PHYS(x) (EP93XX_APB_PHYS_BASE + (x)) -#define EP93XX_APB_IOMEM(x) IOMEM(EP93XX_APB_VIRT_BASE + (x)) - -/* APB UARTs */ -#define EP93XX_UART1_PHYS_BASE EP93XX_APB_PHYS(0x000c0000) -#define EP93XX_UART1_BASE EP93XX_APB_IOMEM(0x000c0000) - -#define EP93XX_UART2_PHYS_BASE EP93XX_APB_PHYS(0x000d0000) -#define EP93XX_UART2_BASE EP93XX_APB_IOMEM(0x000d0000) - -#define EP93XX_UART3_PHYS_BASE EP93XX_APB_PHYS(0x000e0000) -#define EP93XX_UART3_BASE EP93XX_APB_IOMEM(0x000e0000) - -#endif diff --git a/arch/arm/mach-ep93xx/gpio-ep93xx.h b/arch/arm/mach-ep93xx/gpio= -ep93xx.h deleted file mode 100644 index 7b46eb7e5507..000000000000 --- a/arch/arm/mach-ep93xx/gpio-ep93xx.h +++ /dev/null @@ -1,111 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Include file for the EP93XX GPIO controller machine specifics */ - -#ifndef __GPIO_EP93XX_H -#define __GPIO_EP93XX_H - -#include "ep93xx-regs.h" - -#define EP93XX_GPIO_PHYS_BASE EP93XX_APB_PHYS(0x00040000) -#define EP93XX_GPIO_BASE EP93XX_APB_IOMEM(0x00040000) -#define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x)) -#define EP93XX_GPIO_F_INT_STATUS EP93XX_GPIO_REG(0x5c) -#define EP93XX_GPIO_A_INT_STATUS EP93XX_GPIO_REG(0xa0) -#define EP93XX_GPIO_B_INT_STATUS EP93XX_GPIO_REG(0xbc) -#define EP93XX_GPIO_EEDRIVE EP93XX_GPIO_REG(0xc8) - -/* GPIO port A. */ -#define EP93XX_GPIO_LINE_A(x) ((x) + 0) -#define EP93XX_GPIO_LINE_EGPIO0 EP93XX_GPIO_LINE_A(0) -#define EP93XX_GPIO_LINE_EGPIO1 EP93XX_GPIO_LINE_A(1) -#define EP93XX_GPIO_LINE_EGPIO2 EP93XX_GPIO_LINE_A(2) -#define EP93XX_GPIO_LINE_EGPIO3 EP93XX_GPIO_LINE_A(3) -#define EP93XX_GPIO_LINE_EGPIO4 EP93XX_GPIO_LINE_A(4) -#define EP93XX_GPIO_LINE_EGPIO5 EP93XX_GPIO_LINE_A(5) -#define EP93XX_GPIO_LINE_EGPIO6 EP93XX_GPIO_LINE_A(6) -#define EP93XX_GPIO_LINE_EGPIO7 EP93XX_GPIO_LINE_A(7) - -/* GPIO port B. */ -#define EP93XX_GPIO_LINE_B(x) ((x) + 8) -#define EP93XX_GPIO_LINE_EGPIO8 EP93XX_GPIO_LINE_B(0) -#define EP93XX_GPIO_LINE_EGPIO9 EP93XX_GPIO_LINE_B(1) -#define EP93XX_GPIO_LINE_EGPIO10 EP93XX_GPIO_LINE_B(2) -#define EP93XX_GPIO_LINE_EGPIO11 EP93XX_GPIO_LINE_B(3) -#define EP93XX_GPIO_LINE_EGPIO12 EP93XX_GPIO_LINE_B(4) -#define EP93XX_GPIO_LINE_EGPIO13 EP93XX_GPIO_LINE_B(5) -#define EP93XX_GPIO_LINE_EGPIO14 EP93XX_GPIO_LINE_B(6) -#define EP93XX_GPIO_LINE_EGPIO15 EP93XX_GPIO_LINE_B(7) - -/* GPIO port C. */ -#define EP93XX_GPIO_LINE_C(x) ((x) + 40) -#define EP93XX_GPIO_LINE_ROW0 EP93XX_GPIO_LINE_C(0) -#define EP93XX_GPIO_LINE_ROW1 EP93XX_GPIO_LINE_C(1) -#define EP93XX_GPIO_LINE_ROW2 EP93XX_GPIO_LINE_C(2) -#define EP93XX_GPIO_LINE_ROW3 EP93XX_GPIO_LINE_C(3) -#define EP93XX_GPIO_LINE_ROW4 EP93XX_GPIO_LINE_C(4) -#define EP93XX_GPIO_LINE_ROW5 EP93XX_GPIO_LINE_C(5) -#define EP93XX_GPIO_LINE_ROW6 EP93XX_GPIO_LINE_C(6) -#define EP93XX_GPIO_LINE_ROW7 EP93XX_GPIO_LINE_C(7) - -/* GPIO port D. */ -#define EP93XX_GPIO_LINE_D(x) ((x) + 24) -#define EP93XX_GPIO_LINE_COL0 EP93XX_GPIO_LINE_D(0) -#define EP93XX_GPIO_LINE_COL1 EP93XX_GPIO_LINE_D(1) -#define EP93XX_GPIO_LINE_COL2 EP93XX_GPIO_LINE_D(2) -#define EP93XX_GPIO_LINE_COL3 EP93XX_GPIO_LINE_D(3) -#define EP93XX_GPIO_LINE_COL4 EP93XX_GPIO_LINE_D(4) -#define EP93XX_GPIO_LINE_COL5 EP93XX_GPIO_LINE_D(5) -#define EP93XX_GPIO_LINE_COL6 EP93XX_GPIO_LINE_D(6) -#define EP93XX_GPIO_LINE_COL7 EP93XX_GPIO_LINE_D(7) - -/* GPIO port E. */ -#define EP93XX_GPIO_LINE_E(x) ((x) + 32) -#define EP93XX_GPIO_LINE_GRLED EP93XX_GPIO_LINE_E(0) -#define EP93XX_GPIO_LINE_RDLED EP93XX_GPIO_LINE_E(1) -#define EP93XX_GPIO_LINE_DIORn EP93XX_GPIO_LINE_E(2) -#define EP93XX_GPIO_LINE_IDECS1n EP93XX_GPIO_LINE_E(3) -#define EP93XX_GPIO_LINE_IDECS2n EP93XX_GPIO_LINE_E(4) -#define EP93XX_GPIO_LINE_IDEDA0 EP93XX_GPIO_LINE_E(5) -#define EP93XX_GPIO_LINE_IDEDA1 EP93XX_GPIO_LINE_E(6) -#define EP93XX_GPIO_LINE_IDEDA2 EP93XX_GPIO_LINE_E(7) - -/* GPIO port F. */ -#define EP93XX_GPIO_LINE_F(x) ((x) + 16) -#define EP93XX_GPIO_LINE_WP EP93XX_GPIO_LINE_F(0) -#define EP93XX_GPIO_LINE_MCCD1 EP93XX_GPIO_LINE_F(1) -#define EP93XX_GPIO_LINE_MCCD2 EP93XX_GPIO_LINE_F(2) -#define EP93XX_GPIO_LINE_MCBVD1 EP93XX_GPIO_LINE_F(3) -#define EP93XX_GPIO_LINE_MCBVD2 EP93XX_GPIO_LINE_F(4) -#define EP93XX_GPIO_LINE_VS1 EP93XX_GPIO_LINE_F(5) -#define EP93XX_GPIO_LINE_READY EP93XX_GPIO_LINE_F(6) -#define EP93XX_GPIO_LINE_VS2 EP93XX_GPIO_LINE_F(7) - -/* GPIO port G. */ -#define EP93XX_GPIO_LINE_G(x) ((x) + 48) -#define EP93XX_GPIO_LINE_EECLK EP93XX_GPIO_LINE_G(0) -#define EP93XX_GPIO_LINE_EEDAT EP93XX_GPIO_LINE_G(1) -#define EP93XX_GPIO_LINE_SLA0 EP93XX_GPIO_LINE_G(2) -#define EP93XX_GPIO_LINE_SLA1 EP93XX_GPIO_LINE_G(3) -#define EP93XX_GPIO_LINE_DD12 EP93XX_GPIO_LINE_G(4) -#define EP93XX_GPIO_LINE_DD13 EP93XX_GPIO_LINE_G(5) -#define EP93XX_GPIO_LINE_DD14 EP93XX_GPIO_LINE_G(6) -#define EP93XX_GPIO_LINE_DD15 EP93XX_GPIO_LINE_G(7) - -/* GPIO port H. */ -#define EP93XX_GPIO_LINE_H(x) ((x) + 56) -#define EP93XX_GPIO_LINE_DD0 EP93XX_GPIO_LINE_H(0) -#define EP93XX_GPIO_LINE_DD1 EP93XX_GPIO_LINE_H(1) -#define EP93XX_GPIO_LINE_DD2 EP93XX_GPIO_LINE_H(2) -#define EP93XX_GPIO_LINE_DD3 EP93XX_GPIO_LINE_H(3) -#define EP93XX_GPIO_LINE_DD4 EP93XX_GPIO_LINE_H(4) -#define EP93XX_GPIO_LINE_DD5 EP93XX_GPIO_LINE_H(5) -#define EP93XX_GPIO_LINE_DD6 EP93XX_GPIO_LINE_H(6) -#define EP93XX_GPIO_LINE_DD7 EP93XX_GPIO_LINE_H(7) - -/* maximum value for gpio line identifiers */ -#define EP93XX_GPIO_LINE_MAX EP93XX_GPIO_LINE_H(7) - -/* maximum value for irq capable line identifiers */ -#define EP93XX_GPIO_LINE_MAX_IRQ EP93XX_GPIO_LINE_F(7) - -#endif /* __GPIO_EP93XX_H */ diff --git a/arch/arm/mach-ep93xx/hardware.h b/arch/arm/mach-ep93xx/hardwar= e.h deleted file mode 100644 index e7d850e04782..000000000000 --- a/arch/arm/mach-ep93xx/hardware.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * arch/arm/mach-ep93xx/include/mach/hardware.h - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include "platform.h" - -/* - * The EP93xx has two external crystal oscillators. To generate the - * required high-frequency clocks, the processor uses two phase-locked- - * loops (PLLs) to multiply the incoming external clock signal to much - * higher frequencies that are then divided down by programmable dividers - * to produce the needed clocks. The PLLs operate independently of one - * another. - */ -#define EP93XX_EXT_CLK_RATE 14745600 -#define EP93XX_EXT_RTC_RATE 32768 - -#define EP93XX_KEYTCHCLK_DIV4 (EP93XX_EXT_CLK_RATE / 4) -#define EP93XX_KEYTCHCLK_DIV16 (EP93XX_EXT_CLK_RATE / 16) - -#endif diff --git a/arch/arm/mach-ep93xx/irqs.h b/arch/arm/mach-ep93xx/irqs.h deleted file mode 100644 index 353201b90c66..000000000000 --- a/arch/arm/mach-ep93xx/irqs.h +++ /dev/null @@ -1,76 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - -#define IRQ_EP93XX_VIC0 1 - -#define IRQ_EP93XX_COMMRX (IRQ_EP93XX_VIC0 + 2) -#define IRQ_EP93XX_COMMTX (IRQ_EP93XX_VIC0 + 3) -#define IRQ_EP93XX_TIMER1 (IRQ_EP93XX_VIC0 + 4) -#define IRQ_EP93XX_TIMER2 (IRQ_EP93XX_VIC0 + 5) -#define IRQ_EP93XX_AACINTR (IRQ_EP93XX_VIC0 + 6) -#define IRQ_EP93XX_DMAM2P0 (IRQ_EP93XX_VIC0 + 7) -#define IRQ_EP93XX_DMAM2P1 (IRQ_EP93XX_VIC0 + 8) -#define IRQ_EP93XX_DMAM2P2 (IRQ_EP93XX_VIC0 + 9) -#define IRQ_EP93XX_DMAM2P3 (IRQ_EP93XX_VIC0 + 10) -#define IRQ_EP93XX_DMAM2P4 (IRQ_EP93XX_VIC0 + 11) -#define IRQ_EP93XX_DMAM2P5 (IRQ_EP93XX_VIC0 + 12) -#define IRQ_EP93XX_DMAM2P6 (IRQ_EP93XX_VIC0 + 13) -#define IRQ_EP93XX_DMAM2P7 (IRQ_EP93XX_VIC0 + 14) -#define IRQ_EP93XX_DMAM2P8 (IRQ_EP93XX_VIC0 + 15) -#define IRQ_EP93XX_DMAM2P9 (IRQ_EP93XX_VIC0 + 16) -#define IRQ_EP93XX_DMAM2M0 (IRQ_EP93XX_VIC0 + 17) -#define IRQ_EP93XX_DMAM2M1 (IRQ_EP93XX_VIC0 + 18) -#define IRQ_EP93XX_GPIO0MUX (IRQ_EP93XX_VIC0 + 19) -#define IRQ_EP93XX_GPIO1MUX (IRQ_EP93XX_VIC0 + 20) -#define IRQ_EP93XX_GPIO2MUX (IRQ_EP93XX_VIC0 + 21) -#define IRQ_EP93XX_GPIO3MUX (IRQ_EP93XX_VIC0 + 22) -#define IRQ_EP93XX_UART1RX (IRQ_EP93XX_VIC0 + 23) -#define IRQ_EP93XX_UART1TX (IRQ_EP93XX_VIC0 + 24) -#define IRQ_EP93XX_UART2RX (IRQ_EP93XX_VIC0 + 25) -#define IRQ_EP93XX_UART2TX (IRQ_EP93XX_VIC0 + 26) -#define IRQ_EP93XX_UART3RX (IRQ_EP93XX_VIC0 + 27) -#define IRQ_EP93XX_UART3TX (IRQ_EP93XX_VIC0 + 28) -#define IRQ_EP93XX_KEY (IRQ_EP93XX_VIC0 + 29) -#define IRQ_EP93XX_TOUCH (IRQ_EP93XX_VIC0 + 30) -#define EP93XX_VIC1_VALID_IRQ_MASK 0x7ffffffc - -#define IRQ_EP93XX_VIC1 (IRQ_EP93XX_VIC0 + 32) - -#define IRQ_EP93XX_EXT0 (IRQ_EP93XX_VIC1 + 0) -#define IRQ_EP93XX_EXT1 (IRQ_EP93XX_VIC1 + 1) -#define IRQ_EP93XX_EXT2 (IRQ_EP93XX_VIC1 + 2) -#define IRQ_EP93XX_64HZ (IRQ_EP93XX_VIC1 + 3) -#define IRQ_EP93XX_WATCHDOG (IRQ_EP93XX_VIC1 + 4) -#define IRQ_EP93XX_RTC (IRQ_EP93XX_VIC1 + 5) -#define IRQ_EP93XX_IRDA (IRQ_EP93XX_VIC1 + 6) -#define IRQ_EP93XX_ETHERNET (IRQ_EP93XX_VIC1 + 7) -#define IRQ_EP93XX_EXT3 (IRQ_EP93XX_VIC1 + 8) -#define IRQ_EP93XX_PROG (IRQ_EP93XX_VIC1 + 9) -#define IRQ_EP93XX_1HZ (IRQ_EP93XX_VIC1 + 10) -#define IRQ_EP93XX_VSYNC (IRQ_EP93XX_VIC1 + 11) -#define IRQ_EP93XX_VIDEO_FIFO (IRQ_EP93XX_VIC1 + 12) -#define IRQ_EP93XX_SSP1RX (IRQ_EP93XX_VIC1 + 13) -#define IRQ_EP93XX_SSP1TX (IRQ_EP93XX_VIC1 + 14) -#define IRQ_EP93XX_GPIO4MUX (IRQ_EP93XX_VIC1 + 15) -#define IRQ_EP93XX_GPIO5MUX (IRQ_EP93XX_VIC1 + 16) -#define IRQ_EP93XX_GPIO6MUX (IRQ_EP93XX_VIC1 + 17) -#define IRQ_EP93XX_GPIO7MUX (IRQ_EP93XX_VIC1 + 18) -#define IRQ_EP93XX_TIMER3 (IRQ_EP93XX_VIC1 + 19) -#define IRQ_EP93XX_UART1 (IRQ_EP93XX_VIC1 + 20) -#define IRQ_EP93XX_SSP (IRQ_EP93XX_VIC1 + 21) -#define IRQ_EP93XX_UART2 (IRQ_EP93XX_VIC1 + 22) -#define IRQ_EP93XX_UART3 (IRQ_EP93XX_VIC1 + 23) -#define IRQ_EP93XX_USB (IRQ_EP93XX_VIC1 + 24) -#define IRQ_EP93XX_ETHERNET_PME (IRQ_EP93XX_VIC1 + 25) -#define IRQ_EP93XX_DSP (IRQ_EP93XX_VIC1 + 26) -#define IRQ_EP93XX_GPIO_AB (IRQ_EP93XX_VIC1 + 27) -#define IRQ_EP93XX_SAI (IRQ_EP93XX_VIC1 + 28) -#define EP93XX_VIC2_VALID_IRQ_MASK 0x1fffffff - -#define NR_EP93XX_IRQS (IRQ_EP93XX_VIC1 + 32 + 24) - -#define EP93XX_BOARD_IRQ(x) (NR_EP93XX_IRQS + (x)) -#define EP93XX_BOARD_IRQS 32 - -#endif diff --git a/arch/arm/mach-ep93xx/platform.h b/arch/arm/mach-ep93xx/platfor= m.h deleted file mode 100644 index 3cf2113491d8..000000000000 --- a/arch/arm/mach-ep93xx/platform.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * arch/arm/mach-ep93xx/include/mach/platform.h - */ - -#ifndef __ASSEMBLY__ - -#include -#include - -struct device; -struct i2c_board_info; -struct spi_board_info; -struct platform_device; -struct ep93xxfb_mach_info; -struct ep93xx_keypad_platform_data; -struct ep93xx_spi_info; - -void ep93xx_map_io(void); -void ep93xx_init_irq(void); - -void ep93xx_register_flash(unsigned int width, - resource_size_t start, resource_size_t size); - -void ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr); -void ep93xx_register_i2c(struct i2c_board_info *devices, int num); -void ep93xx_register_spi(struct ep93xx_spi_info *info, - struct spi_board_info *devices, int num); -void ep93xx_register_fb(struct ep93xxfb_mach_info *data); -void ep93xx_register_pwm(int pwm0, int pwm1); -void ep93xx_register_keypad(struct ep93xx_keypad_platform_data *data); -void ep93xx_register_i2s(void); -void ep93xx_register_ac97(void); -void ep93xx_register_ide(void); -void ep93xx_register_adc(void); - -struct device *ep93xx_init_devices(void); -extern void ep93xx_timer_init(void); - -void ep93xx_restart(enum reboot_mode, const char *); - -#endif diff --git a/arch/arm/mach-ep93xx/soc.h b/arch/arm/mach-ep93xx/soc.h deleted file mode 100644 index 3245ebbd5069..000000000000 --- a/arch/arm/mach-ep93xx/soc.h +++ /dev/null @@ -1,212 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * arch/arm/mach-ep93xx/soc.h - * - * Copyright (C) 2012 Open Kernel Labs - * Copyright (C) 2012 Ryan Mallon - */ - -#ifndef _EP93XX_SOC_H -#define _EP93XX_SOC_H - -#include "ep93xx-regs.h" -#include "irqs.h" - -/* - * EP93xx Physical Memory Map: - * - * The ASDO pin is sampled at system reset to select a synchronous or - * asynchronous boot configuration. When ASDO is "1" (i.e. pulled-up) - * the synchronous boot mode is selected. When ASDO is "0" (i.e - * pulled-down) the asynchronous boot mode is selected. - * - * In synchronous boot mode nSDCE3 is decoded starting at physical address - * 0x00000000 and nCS0 is decoded starting at 0xf0000000. For asynchronous - * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3 - * decoded at 0xf0000000. - * - * There is known errata for the EP93xx dealing with External Memory - * Configurations. Please refer to "AN273: EP93xx Silicon Rev E Design - * Guidelines" for more information. This document can be found at: - * - * http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf - */ - -#define EP93XX_CS0_PHYS_BASE_ASYNC 0x00000000 /* ASDO Pin =3D 0 */ -#define EP93XX_SDCE3_PHYS_BASE_SYNC 0x00000000 /* ASDO Pin =3D 1 */ -#define EP93XX_CS1_PHYS_BASE 0x10000000 -#define EP93XX_CS2_PHYS_BASE 0x20000000 -#define EP93XX_CS3_PHYS_BASE 0x30000000 -#define EP93XX_PCMCIA_PHYS_BASE 0x40000000 -#define EP93XX_CS6_PHYS_BASE 0x60000000 -#define EP93XX_CS7_PHYS_BASE 0x70000000 -#define EP93XX_SDCE0_PHYS_BASE 0xc0000000 -#define EP93XX_SDCE1_PHYS_BASE 0xd0000000 -#define EP93XX_SDCE2_PHYS_BASE 0xe0000000 -#define EP93XX_SDCE3_PHYS_BASE_ASYNC 0xf0000000 /* ASDO Pin =3D 0 */ -#define EP93XX_CS0_PHYS_BASE_SYNC 0xf0000000 /* ASDO Pin =3D 1 */ - -/* AHB peripherals */ -#define EP93XX_DMA_BASE EP93XX_AHB_IOMEM(0x00000000) - -#define EP93XX_ETHERNET_PHYS_BASE EP93XX_AHB_PHYS(0x00010000) -#define EP93XX_ETHERNET_BASE EP93XX_AHB_IOMEM(0x00010000) - -#define EP93XX_USB_PHYS_BASE EP93XX_AHB_PHYS(0x00020000) -#define EP93XX_USB_BASE EP93XX_AHB_IOMEM(0x00020000) - -#define EP93XX_RASTER_PHYS_BASE EP93XX_AHB_PHYS(0x00030000) -#define EP93XX_RASTER_BASE EP93XX_AHB_IOMEM(0x00030000) - -#define EP93XX_GRAPHICS_ACCEL_BASE EP93XX_AHB_IOMEM(0x00040000) - -#define EP93XX_SDRAM_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00060000) - -#define EP93XX_PCMCIA_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00080000) - -#define EP93XX_BOOT_ROM_BASE EP93XX_AHB_IOMEM(0x00090000) - -#define EP93XX_IDE_PHYS_BASE EP93XX_AHB_PHYS(0x000a0000) -#define EP93XX_IDE_BASE EP93XX_AHB_IOMEM(0x000a0000) - -#define EP93XX_VIC1_BASE EP93XX_AHB_IOMEM(0x000b0000) - -#define EP93XX_VIC2_BASE EP93XX_AHB_IOMEM(0x000c0000) - -/* APB peripherals */ -#define EP93XX_TIMER_BASE EP93XX_APB_IOMEM(0x00010000) - -#define EP93XX_I2S_PHYS_BASE EP93XX_APB_PHYS(0x00020000) -#define EP93XX_I2S_BASE EP93XX_APB_IOMEM(0x00020000) - -#define EP93XX_SECURITY_BASE EP93XX_APB_IOMEM(0x00030000) - -#define EP93XX_AAC_PHYS_BASE EP93XX_APB_PHYS(0x00080000) -#define EP93XX_AAC_BASE EP93XX_APB_IOMEM(0x00080000) - -#define EP93XX_SPI_PHYS_BASE EP93XX_APB_PHYS(0x000a0000) -#define EP93XX_SPI_BASE EP93XX_APB_IOMEM(0x000a0000) - -#define EP93XX_IRDA_BASE EP93XX_APB_IOMEM(0x000b0000) - -#define EP93XX_KEY_MATRIX_PHYS_BASE EP93XX_APB_PHYS(0x000f0000) -#define EP93XX_KEY_MATRIX_BASE EP93XX_APB_IOMEM(0x000f0000) - -#define EP93XX_ADC_PHYS_BASE EP93XX_APB_PHYS(0x00100000) -#define EP93XX_ADC_BASE EP93XX_APB_IOMEM(0x00100000) -#define EP93XX_TOUCHSCREEN_BASE EP93XX_APB_IOMEM(0x00100000) - -#define EP93XX_PWM_PHYS_BASE EP93XX_APB_PHYS(0x00110000) -#define EP93XX_PWM_BASE EP93XX_APB_IOMEM(0x00110000) - -#define EP93XX_RTC_PHYS_BASE EP93XX_APB_PHYS(0x00120000) -#define EP93XX_RTC_BASE EP93XX_APB_IOMEM(0x00120000) - -#define EP93XX_WATCHDOG_PHYS_BASE EP93XX_APB_PHYS(0x00140000) -#define EP93XX_WATCHDOG_BASE EP93XX_APB_IOMEM(0x00140000) - -/* System controller */ -#define EP93XX_SYSCON_BASE EP93XX_APB_IOMEM(0x00130000) -#define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x)) -#define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00) -#define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04) -#define EP93XX_SYSCON_PWRCNT_FIR_EN (1<<31) -#define EP93XX_SYSCON_PWRCNT_UARTBAUD (1<<29) -#define EP93XX_SYSCON_PWRCNT_USH_EN 28 -#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 27 -#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 26 -#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 25 -#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 24 -#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 23 -#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 22 -#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 21 -#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 20 -#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 19 -#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 18 -#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 17 -#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 16 -#define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08) -#define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c) -#define EP93XX_SYSCON_CLKSET1 EP93XX_SYSCON_REG(0x20) -#define EP93XX_SYSCON_CLKSET1_NBYP1 (1<<23) -#define EP93XX_SYSCON_CLKSET2 EP93XX_SYSCON_REG(0x24) -#define EP93XX_SYSCON_CLKSET2_NBYP2 (1<<19) -#define EP93XX_SYSCON_CLKSET2_PLL2_EN (1<<18) -#define EP93XX_SYSCON_DEVCFG EP93XX_SYSCON_REG(0x80) -#define EP93XX_SYSCON_DEVCFG_SWRST (1<<31) -#define EP93XX_SYSCON_DEVCFG_D1ONG (1<<30) -#define EP93XX_SYSCON_DEVCFG_D0ONG (1<<29) -#define EP93XX_SYSCON_DEVCFG_IONU2 (1<<28) -#define EP93XX_SYSCON_DEVCFG_GONK (1<<27) -#define EP93XX_SYSCON_DEVCFG_TONG (1<<26) -#define EP93XX_SYSCON_DEVCFG_MONG (1<<25) -#define EP93XX_SYSCON_DEVCFG_U3EN 24 -#define EP93XX_SYSCON_DEVCFG_CPENA (1<<23) -#define EP93XX_SYSCON_DEVCFG_A2ONG (1<<22) -#define EP93XX_SYSCON_DEVCFG_A1ONG (1<<21) -#define EP93XX_SYSCON_DEVCFG_U2EN 20 -#define EP93XX_SYSCON_DEVCFG_EXVC (1<<19) -#define EP93XX_SYSCON_DEVCFG_U1EN 18 -#define EP93XX_SYSCON_DEVCFG_TIN (1<<17) -#define EP93XX_SYSCON_DEVCFG_HC3IN (1<<15) -#define EP93XX_SYSCON_DEVCFG_HC3EN (1<<14) -#define EP93XX_SYSCON_DEVCFG_HC1IN (1<<13) -#define EP93XX_SYSCON_DEVCFG_HC1EN (1<<12) -#define EP93XX_SYSCON_DEVCFG_HONIDE (1<<11) -#define EP93XX_SYSCON_DEVCFG_GONIDE (1<<10) -#define EP93XX_SYSCON_DEVCFG_PONG (1<<9) -#define EP93XX_SYSCON_DEVCFG_EONIDE (1<<8) -#define EP93XX_SYSCON_DEVCFG_I2SONSSP (1<<7) -#define EP93XX_SYSCON_DEVCFG_I2SONAC97 (1<<6) -#define EP93XX_SYSCON_DEVCFG_RASONP3 (1<<4) -#define EP93XX_SYSCON_DEVCFG_RAS (1<<3) -#define EP93XX_SYSCON_DEVCFG_ADCPD (1<<2) -#define EP93XX_SYSCON_DEVCFG_KEYS (1<<1) -#define EP93XX_SYSCON_DEVCFG_SHENA (1<<0) -#define EP93XX_SYSCON_VIDCLKDIV EP93XX_SYSCON_REG(0x84) -#define EP93XX_SYSCON_CLKDIV_ENABLE 15 -#define EP93XX_SYSCON_CLKDIV_ESEL (1<<14) -#define EP93XX_SYSCON_CLKDIV_PSEL (1<<13) -#define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8 -#define EP93XX_SYSCON_I2SCLKDIV EP93XX_SYSCON_REG(0x8c) -#define EP93XX_SYSCON_I2SCLKDIV_SENA 31 -#define EP93XX_SYSCON_I2SCLKDIV_ORIDE (1<<29) -#define EP93XX_SYSCON_I2SCLKDIV_SPOL (1<<19) -#define EP93XX_I2SCLKDIV_SDIV (1 << 16) -#define EP93XX_I2SCLKDIV_LRDIV32 (0 << 17) -#define EP93XX_I2SCLKDIV_LRDIV64 (1 << 17) -#define EP93XX_I2SCLKDIV_LRDIV128 (2 << 17) -#define EP93XX_I2SCLKDIV_LRDIV_MASK (3 << 17) -#define EP93XX_SYSCON_KEYTCHCLKDIV EP93XX_SYSCON_REG(0x90) -#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN 31 -#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV 16 -#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN 15 -#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0) -#define EP93XX_SYSCON_SYSCFG EP93XX_SYSCON_REG(0x9c) -#define EP93XX_SYSCON_SYSCFG_REV_MASK (0xf0000000) -#define EP93XX_SYSCON_SYSCFG_REV_SHIFT (28) -#define EP93XX_SYSCON_SYSCFG_SBOOT (1<<8) -#define EP93XX_SYSCON_SYSCFG_LCSN7 (1<<7) -#define EP93XX_SYSCON_SYSCFG_LCSN6 (1<<6) -#define EP93XX_SYSCON_SYSCFG_LASDO (1<<5) -#define EP93XX_SYSCON_SYSCFG_LEEDA (1<<4) -#define EP93XX_SYSCON_SYSCFG_LEECLK (1<<3) -#define EP93XX_SYSCON_SYSCFG_LCSN2 (1<<1) -#define EP93XX_SYSCON_SYSCFG_LCSN1 (1<<0) -#define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0) - -/* EP93xx System Controller software locked register write */ -void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg); -void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bit= s); - -static inline void ep93xx_devcfg_set_bits(unsigned int bits) -{ - ep93xx_devcfg_set_clear(bits, 0x00); -} - -static inline void ep93xx_devcfg_clear_bits(unsigned int bits) -{ - ep93xx_devcfg_set_clear(0x00, bits); -} - -#endif /* _EP93XX_SOC_H */ diff --git a/arch/arm/mach-ep93xx/timer-ep93xx.c b/arch/arm/mach-ep93xx/tim= er-ep93xx.c deleted file mode 100644 index dd4b164d1831..000000000000 --- a/arch/arm/mach-ep93xx/timer-ep93xx.c +++ /dev/null @@ -1,142 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "soc.h" - -/************************************************************************* - * Timer handling for EP93xx - ************************************************************************* - * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and - * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate - * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz, - * is free-running, and can't generate interrupts. - * - * The 508 kHz timers are ideal for use for the timer interrupt, as the - * most common values of HZ divide 508 kHz nicely. We pick the 32 bit - * timer (timer 3) to get as long sleep intervals as possible when using - * CONFIG_NO_HZ. - * - * The higher clock rate of timer 4 makes it a better choice than the - * other timers for use as clock source and for sched_clock(), providing - * a stable 40 bit time base. - ************************************************************************* - */ -#define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x)) -#define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00) -#define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04) -#define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08) -#define EP93XX_TIMER123_CONTROL_ENABLE (1 << 7) -#define EP93XX_TIMER123_CONTROL_MODE (1 << 6) -#define EP93XX_TIMER123_CONTROL_CLKSEL (1 << 3) -#define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c) -#define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20) -#define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24) -#define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28) -#define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c) -#define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60) -#define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64) -#define EP93XX_TIMER4_VALUE_HIGH_ENABLE (1 << 8) -#define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80) -#define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84) -#define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88) -#define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c) - -#define EP93XX_TIMER123_RATE 508469 -#define EP93XX_TIMER4_RATE 983040 - -static u64 notrace ep93xx_read_sched_clock(void) -{ - u64 ret; - - ret =3D readl(EP93XX_TIMER4_VALUE_LOW); - ret |=3D ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32); - return ret; -} - -u64 ep93xx_clocksource_read(struct clocksource *c) -{ - u64 ret; - - ret =3D readl(EP93XX_TIMER4_VALUE_LOW); - ret |=3D ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32); - return (u64) ret; -} - -static int ep93xx_clkevt_set_next_event(unsigned long next, - struct clock_event_device *evt) -{ - /* Default mode: periodic, off, 508 kHz */ - u32 tmode =3D EP93XX_TIMER123_CONTROL_MODE | - EP93XX_TIMER123_CONTROL_CLKSEL; - - /* Clear timer */ - writel(tmode, EP93XX_TIMER3_CONTROL); - - /* Set next event */ - writel(next, EP93XX_TIMER3_LOAD); - writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE, - EP93XX_TIMER3_CONTROL); - return 0; -} - - -static int ep93xx_clkevt_shutdown(struct clock_event_device *evt) -{ - /* Disable timer */ - writel(0, EP93XX_TIMER3_CONTROL); - - return 0; -} - -static struct clock_event_device ep93xx_clockevent =3D { - .name =3D "timer1", - .features =3D CLOCK_EVT_FEAT_ONESHOT, - .set_state_shutdown =3D ep93xx_clkevt_shutdown, - .set_state_oneshot =3D ep93xx_clkevt_shutdown, - .tick_resume =3D ep93xx_clkevt_shutdown, - .set_next_event =3D ep93xx_clkevt_set_next_event, - .rating =3D 300, -}; - -static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt =3D dev_id; - - /* Writing any value clears the timer interrupt */ - writel(1, EP93XX_TIMER3_CLEAR); - - evt->event_handler(evt); - - return IRQ_HANDLED; -} - -void __init ep93xx_timer_init(void) -{ - int irq =3D IRQ_EP93XX_TIMER3; - unsigned long flags =3D IRQF_TIMER | IRQF_IRQPOLL; - - /* Enable and register clocksource and sched_clock on timer 4 */ - writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE, - EP93XX_TIMER4_VALUE_HIGH); - clocksource_mmio_init(NULL, "timer4", - EP93XX_TIMER4_RATE, 200, 40, - ep93xx_clocksource_read); - sched_clock_register(ep93xx_read_sched_clock, 40, - EP93XX_TIMER4_RATE); - - /* Set up clockevent on timer 3 */ - if (request_irq(irq, ep93xx_timer_interrupt, flags, "ep93xx timer", - &ep93xx_clockevent)) - pr_err("Failed to request irq %d (ep93xx timer)\n", irq); - clockevents_config_and_register(&ep93xx_clockevent, - EP93XX_TIMER123_RATE, - 1, - 0xffffffffU); -} diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c deleted file mode 100644 index 0bbdf587c685..000000000000 --- a/arch/arm/mach-ep93xx/ts72xx.c +++ /dev/null @@ -1,422 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-ep93xx/ts72xx.c - * Technologic Systems TS72xx SBC support. - * - * Copyright (C) 2006 Lennert Buytenhek - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "gpio-ep93xx.h" -#include "hardware.h" - -#include -#include -#include - -#include "soc.h" -#include "ts72xx.h" - -/************************************************************************* - * IO map - *************************************************************************/ -static struct map_desc ts72xx_io_desc[] __initdata =3D { - { - .virtual =3D (unsigned long)TS72XX_MODEL_VIRT_BASE, - .pfn =3D __phys_to_pfn(TS72XX_MODEL_PHYS_BASE), - .length =3D TS72XX_MODEL_SIZE, - .type =3D MT_DEVICE, - }, { - .virtual =3D (unsigned long)TS72XX_OPTIONS_VIRT_BASE, - .pfn =3D __phys_to_pfn(TS72XX_OPTIONS_PHYS_BASE), - .length =3D TS72XX_OPTIONS_SIZE, - .type =3D MT_DEVICE, - }, { - .virtual =3D (unsigned long)TS72XX_OPTIONS2_VIRT_BASE, - .pfn =3D __phys_to_pfn(TS72XX_OPTIONS2_PHYS_BASE), - .length =3D TS72XX_OPTIONS2_SIZE, - .type =3D MT_DEVICE, - }, { - .virtual =3D (unsigned long)TS72XX_CPLDVER_VIRT_BASE, - .pfn =3D __phys_to_pfn(TS72XX_CPLDVER_PHYS_BASE), - .length =3D TS72XX_CPLDVER_SIZE, - .type =3D MT_DEVICE, - } -}; - -static void __init ts72xx_map_io(void) -{ - ep93xx_map_io(); - iotable_init(ts72xx_io_desc, ARRAY_SIZE(ts72xx_io_desc)); -} - - -/************************************************************************* - * NAND flash - *************************************************************************/ -#define TS72XX_NAND_CONTROL_ADDR_LINE 22 /* 0xN0400000 */ -#define TS72XX_NAND_BUSY_ADDR_LINE 23 /* 0xN0800000 */ - -static void ts72xx_nand_hwcontrol(struct nand_chip *chip, - int cmd, unsigned int ctrl) -{ - if (ctrl & NAND_CTRL_CHANGE) { - void __iomem *addr =3D chip->legacy.IO_ADDR_R; - unsigned char bits; - - addr +=3D (1 << TS72XX_NAND_CONTROL_ADDR_LINE); - - bits =3D __raw_readb(addr) & ~0x07; - bits |=3D (ctrl & NAND_NCE) << 2; /* bit 0 -> bit 2 */ - bits |=3D (ctrl & NAND_CLE); /* bit 1 -> bit 1 */ - bits |=3D (ctrl & NAND_ALE) >> 2; /* bit 2 -> bit 0 */ - - __raw_writeb(bits, addr); - } - - if (cmd !=3D NAND_CMD_NONE) - __raw_writeb(cmd, chip->legacy.IO_ADDR_W); -} - -static int ts72xx_nand_device_ready(struct nand_chip *chip) -{ - void __iomem *addr =3D chip->legacy.IO_ADDR_R; - - addr +=3D (1 << TS72XX_NAND_BUSY_ADDR_LINE); - - return !!(__raw_readb(addr) & 0x20); -} - -#define TS72XX_BOOTROM_PART_SIZE (SZ_16K) -#define TS72XX_REDBOOT_PART_SIZE (SZ_2M + SZ_1M) - -static struct mtd_partition ts72xx_nand_parts[] =3D { - { - .name =3D "TS-BOOTROM", - .offset =3D 0, - .size =3D TS72XX_BOOTROM_PART_SIZE, - .mask_flags =3D MTD_WRITEABLE, /* force read-only */ - }, { - .name =3D "Linux", - .offset =3D MTDPART_OFS_RETAIN, - .size =3D TS72XX_REDBOOT_PART_SIZE, - /* leave so much for last partition */ - }, { - .name =3D "RedBoot", - .offset =3D MTDPART_OFS_APPEND, - .size =3D MTDPART_SIZ_FULL, - .mask_flags =3D MTD_WRITEABLE, /* force read-only */ - }, -}; - -static struct platform_nand_data ts72xx_nand_data =3D { - .chip =3D { - .nr_chips =3D 1, - .chip_offset =3D 0, - .chip_delay =3D 15, - }, - .ctrl =3D { - .cmd_ctrl =3D ts72xx_nand_hwcontrol, - .dev_ready =3D ts72xx_nand_device_ready, - }, -}; - -static struct resource ts72xx_nand_resource[] =3D { - { - .start =3D 0, /* filled in later */ - .end =3D 0, /* filled in later */ - .flags =3D IORESOURCE_MEM, - }, -}; - -static struct platform_device ts72xx_nand_flash =3D { - .name =3D "gen_nand", - .id =3D -1, - .dev.platform_data =3D &ts72xx_nand_data, - .resource =3D ts72xx_nand_resource, - .num_resources =3D ARRAY_SIZE(ts72xx_nand_resource), -}; - -static void __init ts72xx_register_flash(struct mtd_partition *parts, int = n, - resource_size_t start) -{ - /* - * TS7200 has NOR flash all other TS72xx board have NAND flash. - */ - if (board_is_ts7200()) { - ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M); - } else { - ts72xx_nand_resource[0].start =3D start; - ts72xx_nand_resource[0].end =3D start + SZ_16M - 1; - - ts72xx_nand_data.chip.partitions =3D parts; - ts72xx_nand_data.chip.nr_partitions =3D n; - - platform_device_register(&ts72xx_nand_flash); - } -} - -/************************************************************************* - * RTC M48T86 - *************************************************************************/ -#define TS72XX_RTC_INDEX_PHYS_BASE (EP93XX_CS1_PHYS_BASE + 0x00800000) -#define TS72XX_RTC_DATA_PHYS_BASE (EP93XX_CS1_PHYS_BASE + 0x01700000) - -static struct resource ts72xx_rtc_resources[] =3D { - DEFINE_RES_MEM(TS72XX_RTC_INDEX_PHYS_BASE, 0x01), - DEFINE_RES_MEM(TS72XX_RTC_DATA_PHYS_BASE, 0x01), -}; - -static struct platform_device ts72xx_rtc_device =3D { - .name =3D "rtc-m48t86", - .id =3D -1, - .resource =3D ts72xx_rtc_resources, - .num_resources =3D ARRAY_SIZE(ts72xx_rtc_resources), -}; - -/************************************************************************* - * Watchdog (in CPLD) - *************************************************************************/ -#define TS72XX_WDT_CONTROL_PHYS_BASE (EP93XX_CS2_PHYS_BASE + 0x03800000) -#define TS72XX_WDT_FEED_PHYS_BASE (EP93XX_CS2_PHYS_BASE + 0x03c00000) - -static struct resource ts72xx_wdt_resources[] =3D { - DEFINE_RES_MEM(TS72XX_WDT_CONTROL_PHYS_BASE, 0x01), - DEFINE_RES_MEM(TS72XX_WDT_FEED_PHYS_BASE, 0x01), -}; - -static struct platform_device ts72xx_wdt_device =3D { - .name =3D "ts72xx-wdt", - .id =3D -1, - .resource =3D ts72xx_wdt_resources, - .num_resources =3D ARRAY_SIZE(ts72xx_wdt_resources), -}; - -/************************************************************************* - * ETH - *************************************************************************/ -static struct ep93xx_eth_data __initdata ts72xx_eth_data =3D { - .phy_id =3D 1, -}; - -/************************************************************************* - * SPI SD/MMC host - *************************************************************************/ -#define BK3_EN_SDCARD_PHYS_BASE 0x12400000 -#define BK3_EN_SDCARD_PWR 0x0 -#define BK3_DIS_SDCARD_PWR 0x0C -static void bk3_mmc_spi_setpower(struct device *dev, unsigned int vdd) -{ - void __iomem *pwr_sd =3D ioremap(BK3_EN_SDCARD_PHYS_BASE, SZ_4K); - - if (!pwr_sd) { - pr_err("Failed to enable SD card power!"); - return; - } - - pr_debug("%s: SD card pwr %s VDD:0x%x\n", __func__, - !!vdd ? "ON" : "OFF", vdd); - - if (!!vdd) - __raw_writeb(BK3_EN_SDCARD_PWR, pwr_sd); - else - __raw_writeb(BK3_DIS_SDCARD_PWR, pwr_sd); - - iounmap(pwr_sd); -} - -static struct mmc_spi_platform_data bk3_spi_mmc_data =3D { - .detect_delay =3D 500, - .powerup_msecs =3D 100, - .ocr_mask =3D MMC_VDD_32_33 | MMC_VDD_33_34, - .caps =3D MMC_CAP_NONREMOVABLE, - .setpower =3D bk3_mmc_spi_setpower, -}; - -/************************************************************************* - * SPI Bus - SD card access - *************************************************************************/ -static struct spi_board_info bk3_spi_board_info[] __initdata =3D { - { - .modalias =3D "mmc_spi", - .platform_data =3D &bk3_spi_mmc_data, - .max_speed_hz =3D 7.4E6, - .bus_num =3D 0, - .chip_select =3D 0, - .mode =3D SPI_MODE_0, - }, -}; - -/* - * This is a stub -> the FGPIO[3] pin is not connected on the schematic - * The all work is performed automatically by !SPI_FRAME (SFRM1) and - * goes through CPLD - */ -static struct gpiod_lookup_table bk3_spi_cs_gpio_table =3D { - .dev_id =3D "spi0", - .table =3D { - GPIO_LOOKUP("gpio-ep93xx.5", 3, "cs", GPIO_ACTIVE_LOW), - { }, - }, -}; - -static struct ep93xx_spi_info bk3_spi_master __initdata =3D { - .use_dma =3D 1, -}; - -/************************************************************************* - * TS72XX support code - *************************************************************************/ -#if IS_ENABLED(CONFIG_FPGA_MGR_TS73XX) - -/* Relative to EP93XX_CS1_PHYS_BASE */ -#define TS73XX_FPGA_LOADER_BASE 0x03c00000 - -static struct resource ts73xx_fpga_resources[] =3D { - { - .start =3D EP93XX_CS1_PHYS_BASE + TS73XX_FPGA_LOADER_BASE, - .end =3D EP93XX_CS1_PHYS_BASE + TS73XX_FPGA_LOADER_BASE + 1, - .flags =3D IORESOURCE_MEM, - }, -}; - -static struct platform_device ts73xx_fpga_device =3D { - .name =3D "ts73xx-fpga-mgr", - .id =3D -1, - .resource =3D ts73xx_fpga_resources, - .num_resources =3D ARRAY_SIZE(ts73xx_fpga_resources), -}; - -#endif - -/************************************************************************* - * SPI Bus - *************************************************************************/ -static struct spi_board_info ts72xx_spi_devices[] __initdata =3D { - { - .modalias =3D "tmp122", - .max_speed_hz =3D 2 * 1000 * 1000, - .bus_num =3D 0, - .chip_select =3D 0, - }, -}; - -static struct gpiod_lookup_table ts72xx_spi_cs_gpio_table =3D { - .dev_id =3D "spi0", - .table =3D { - /* DIO_17 */ - GPIO_LOOKUP("gpio-ep93xx.5", 2, "cs", GPIO_ACTIVE_LOW), - { }, - }, -}; - -static struct ep93xx_spi_info ts72xx_spi_info __initdata =3D { - /* Intentionally left blank */ -}; - -static void __init ts72xx_init_machine(void) -{ - ep93xx_init_devices(); - ts72xx_register_flash(ts72xx_nand_parts, ARRAY_SIZE(ts72xx_nand_parts), - is_ts9420_installed() ? - EP93XX_CS7_PHYS_BASE : EP93XX_CS6_PHYS_BASE); - platform_device_register(&ts72xx_rtc_device); - platform_device_register(&ts72xx_wdt_device); - - ep93xx_register_eth(&ts72xx_eth_data, 1); -#if IS_ENABLED(CONFIG_FPGA_MGR_TS73XX) - if (board_is_ts7300()) - platform_device_register(&ts73xx_fpga_device); -#endif - gpiod_add_lookup_table(&ts72xx_spi_cs_gpio_table); - ep93xx_register_spi(&ts72xx_spi_info, ts72xx_spi_devices, - ARRAY_SIZE(ts72xx_spi_devices)); -} - -MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC") - /* Maintainer: Lennert Buytenhek */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS, - .map_io =3D ts72xx_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D ts72xx_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END - -/************************************************************************* - * EP93xx I2S audio peripheral handling - *************************************************************************/ -static struct resource ep93xx_i2s_resource[] =3D { - DEFINE_RES_MEM(EP93XX_I2S_PHYS_BASE, 0x100), - DEFINE_RES_IRQ_NAMED(IRQ_EP93XX_SAI, "spilink i2s slave"), -}; - -static struct platform_device ep93xx_i2s_device =3D { - .name =3D "ep93xx-spilink-i2s", - .id =3D -1, - .num_resources =3D ARRAY_SIZE(ep93xx_i2s_resource), - .resource =3D ep93xx_i2s_resource, -}; - -/************************************************************************* - * BK3 support code - *************************************************************************/ -static struct mtd_partition bk3_nand_parts[] =3D { - { - .name =3D "System", - .offset =3D 0x00000000, - .size =3D 0x01e00000, - }, { - .name =3D "Data", - .offset =3D 0x01e00000, - .size =3D 0x05f20000 - }, { - .name =3D "RedBoot", - .offset =3D 0x07d20000, - .size =3D 0x002e0000, - .mask_flags =3D MTD_WRITEABLE, /* force RO */ - }, -}; - -static void __init bk3_init_machine(void) -{ - ep93xx_init_devices(); - - ts72xx_register_flash(bk3_nand_parts, ARRAY_SIZE(bk3_nand_parts), - EP93XX_CS6_PHYS_BASE); - - ep93xx_register_eth(&ts72xx_eth_data, 1); - - gpiod_add_lookup_table(&bk3_spi_cs_gpio_table); - ep93xx_register_spi(&bk3_spi_master, bk3_spi_board_info, - ARRAY_SIZE(bk3_spi_board_info)); - - /* Configure ep93xx's I2S to use AC97 pins */ - ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_I2SONAC97); - platform_device_register(&ep93xx_i2s_device); -} - -MACHINE_START(BK3, "Liebherr controller BK3.1") - /* Maintainer: Lukasz Majewski */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS, - .map_io =3D ts72xx_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D bk3_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END diff --git a/arch/arm/mach-ep93xx/ts72xx.h b/arch/arm/mach-ep93xx/ts72xx.h deleted file mode 100644 index 00b4941d29c9..000000000000 --- a/arch/arm/mach-ep93xx/ts72xx.h +++ /dev/null @@ -1,94 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * arch/arm/mach-ep93xx/include/mach/ts72xx.h - */ - -/* - * TS72xx memory map: - * - * virt phys size - * febff000 22000000 4K model number register (bits 0-2) - * febfe000 22400000 4K options register - * febfd000 22800000 4K options register #2 - * febfc000 23400000 4K CPLD version register - */ - -#ifndef __TS72XX_H_ -#define __TS72XX_H_ - -#define TS72XX_MODEL_PHYS_BASE 0x22000000 -#define TS72XX_MODEL_VIRT_BASE IOMEM(0xfebff000) -#define TS72XX_MODEL_SIZE 0x00001000 - -#define TS72XX_MODEL_TS7200 0x00 -#define TS72XX_MODEL_TS7250 0x01 -#define TS72XX_MODEL_TS7260 0x02 -#define TS72XX_MODEL_TS7300 0x03 -#define TS72XX_MODEL_TS7400 0x04 -#define TS72XX_MODEL_MASK 0x07 - - -#define TS72XX_OPTIONS_PHYS_BASE 0x22400000 -#define TS72XX_OPTIONS_VIRT_BASE IOMEM(0xfebfe000) -#define TS72XX_OPTIONS_SIZE 0x00001000 - -#define TS72XX_OPTIONS_COM2_RS485 0x02 -#define TS72XX_OPTIONS_MAX197 0x01 - - -#define TS72XX_OPTIONS2_PHYS_BASE 0x22800000 -#define TS72XX_OPTIONS2_VIRT_BASE IOMEM(0xfebfd000) -#define TS72XX_OPTIONS2_SIZE 0x00001000 - -#define TS72XX_OPTIONS2_TS9420 0x04 -#define TS72XX_OPTIONS2_TS9420_BOOT 0x02 - -#define TS72XX_CPLDVER_PHYS_BASE 0x23400000 -#define TS72XX_CPLDVER_VIRT_BASE IOMEM(0xfebfc000) -#define TS72XX_CPLDVER_SIZE 0x00001000 - -#ifndef __ASSEMBLY__ - -static inline int ts72xx_model(void) -{ - return __raw_readb(TS72XX_MODEL_VIRT_BASE) & TS72XX_MODEL_MASK; -} - -static inline int board_is_ts7200(void) -{ - return ts72xx_model() =3D=3D TS72XX_MODEL_TS7200; -} - -static inline int board_is_ts7250(void) -{ - return ts72xx_model() =3D=3D TS72XX_MODEL_TS7250; -} - -static inline int board_is_ts7260(void) -{ - return ts72xx_model() =3D=3D TS72XX_MODEL_TS7260; -} - -static inline int board_is_ts7300(void) -{ - return ts72xx_model() =3D=3D TS72XX_MODEL_TS7300; -} - -static inline int board_is_ts7400(void) -{ - return ts72xx_model() =3D=3D TS72XX_MODEL_TS7400; -} - -static inline int is_max197_installed(void) -{ - return !!(__raw_readb(TS72XX_OPTIONS_VIRT_BASE) & - TS72XX_OPTIONS_MAX197); -} - -static inline int is_ts9420_installed(void) -{ - return !!(__raw_readb(TS72XX_OPTIONS2_VIRT_BASE) & - TS72XX_OPTIONS2_TS9420); -} -#endif -#endif /* __TS72XX_H_ */ diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vi= sion_ep9307.c deleted file mode 100644 index 020223b0be2b..000000000000 --- a/arch/arm/mach-ep93xx/vision_ep9307.c +++ /dev/null @@ -1,311 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-ep93xx/vision_ep9307.c - * Vision Engraving Systems EP9307 SoM support. - * - * Copyright (C) 2008-2011 Vision Engraving Systems - * H Hartley Sweeten - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "hardware.h" -#include -#include -#include "gpio-ep93xx.h" - -#include -#include -#include - -#include "soc.h" - -/************************************************************************* - * Static I/O mappings for the FPGA - *************************************************************************/ -#define VISION_PHYS_BASE EP93XX_CS7_PHYS_BASE -#define VISION_VIRT_BASE 0xfebff000 - -static struct map_desc vision_io_desc[] __initdata =3D { - { - .virtual =3D VISION_VIRT_BASE, - .pfn =3D __phys_to_pfn(VISION_PHYS_BASE), - .length =3D SZ_4K, - .type =3D MT_DEVICE, - }, -}; - -static void __init vision_map_io(void) -{ - ep93xx_map_io(); - - iotable_init(vision_io_desc, ARRAY_SIZE(vision_io_desc)); -} - -/************************************************************************* - * Ethernet - *************************************************************************/ -static struct ep93xx_eth_data vision_eth_data __initdata =3D { - .phy_id =3D 1, -}; - -/************************************************************************* - * Framebuffer - *************************************************************************/ -#define VISION_LCD_ENABLE EP93XX_GPIO_LINE_EGPIO1 - -static int vision_lcd_setup(struct platform_device *pdev) -{ - int err; - - err =3D gpio_request_one(VISION_LCD_ENABLE, GPIOF_INIT_HIGH, - dev_name(&pdev->dev)); - if (err) - return err; - - ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_RAS | - EP93XX_SYSCON_DEVCFG_RASONP3 | - EP93XX_SYSCON_DEVCFG_EXVC); - - return 0; -} - -static void vision_lcd_teardown(struct platform_device *pdev) -{ - gpio_free(VISION_LCD_ENABLE); -} - -static void vision_lcd_blank(int blank_mode, struct fb_info *info) -{ - if (blank_mode) - gpio_set_value(VISION_LCD_ENABLE, 0); - else - gpio_set_value(VISION_LCD_ENABLE, 1); -} - -static struct ep93xxfb_mach_info ep93xxfb_info __initdata =3D { - .flags =3D EP93XXFB_USE_SDCSN0 | EP93XXFB_PCLK_FALLING, - .setup =3D vision_lcd_setup, - .teardown =3D vision_lcd_teardown, - .blank =3D vision_lcd_blank, -}; - - -/************************************************************************* - * GPIO Expanders - *************************************************************************/ -#define PCA9539_74_GPIO_BASE (EP93XX_GPIO_LINE_MAX + 1) -#define PCA9539_75_GPIO_BASE (PCA9539_74_GPIO_BASE + 16) -#define PCA9539_76_GPIO_BASE (PCA9539_75_GPIO_BASE + 16) -#define PCA9539_77_GPIO_BASE (PCA9539_76_GPIO_BASE + 16) - -static struct pca953x_platform_data pca953x_74_gpio_data =3D { - .gpio_base =3D PCA9539_74_GPIO_BASE, - .irq_base =3D EP93XX_BOARD_IRQ(0), -}; - -static struct pca953x_platform_data pca953x_75_gpio_data =3D { - .gpio_base =3D PCA9539_75_GPIO_BASE, - .irq_base =3D -1, -}; - -static struct pca953x_platform_data pca953x_76_gpio_data =3D { - .gpio_base =3D PCA9539_76_GPIO_BASE, - .irq_base =3D -1, -}; - -static struct pca953x_platform_data pca953x_77_gpio_data =3D { - .gpio_base =3D PCA9539_77_GPIO_BASE, - .irq_base =3D -1, -}; - -/************************************************************************* - * I2C Bus - *************************************************************************/ - -static struct i2c_board_info vision_i2c_info[] __initdata =3D { - { - I2C_BOARD_INFO("isl1208", 0x6f), - .irq =3D IRQ_EP93XX_EXT1, - }, { - I2C_BOARD_INFO("pca9539", 0x74), - .platform_data =3D &pca953x_74_gpio_data, - }, { - I2C_BOARD_INFO("pca9539", 0x75), - .platform_data =3D &pca953x_75_gpio_data, - }, { - I2C_BOARD_INFO("pca9539", 0x76), - .platform_data =3D &pca953x_76_gpio_data, - }, { - I2C_BOARD_INFO("pca9539", 0x77), - .platform_data =3D &pca953x_77_gpio_data, - }, -}; - -/************************************************************************* - * SPI CS4271 Audio Codec - *************************************************************************/ -static struct cs4271_platform_data vision_cs4271_data =3D { - .gpio_nreset =3D EP93XX_GPIO_LINE_H(2), -}; - -/************************************************************************* - * SPI Flash - *************************************************************************/ -static struct mtd_partition vision_spi_flash_partitions[] =3D { - { - .name =3D "SPI bootstrap", - .offset =3D 0, - .size =3D SZ_4K, - }, { - .name =3D "Bootstrap config", - .offset =3D MTDPART_OFS_APPEND, - .size =3D SZ_4K, - }, { - .name =3D "System config", - .offset =3D MTDPART_OFS_APPEND, - .size =3D MTDPART_SIZ_FULL, - }, -}; - -static struct flash_platform_data vision_spi_flash_data =3D { - .name =3D "SPI Flash", - .parts =3D vision_spi_flash_partitions, - .nr_parts =3D ARRAY_SIZE(vision_spi_flash_partitions), -}; - -/************************************************************************* - * SPI SD/MMC host - *************************************************************************/ -static struct mmc_spi_platform_data vision_spi_mmc_data =3D { - .detect_delay =3D 100, - .powerup_msecs =3D 100, - .ocr_mask =3D MMC_VDD_32_33 | MMC_VDD_33_34, - .caps2 =3D MMC_CAP2_RO_ACTIVE_HIGH, -}; - -static struct gpiod_lookup_table vision_spi_mmc_gpio_table =3D { - .dev_id =3D "mmc_spi.2", /* "mmc_spi @ CS2 */ - .table =3D { - /* Card detect */ - GPIO_LOOKUP_IDX("gpio-ep93xx.1", 7, NULL, 0, GPIO_ACTIVE_LOW), - /* Write protect */ - GPIO_LOOKUP_IDX("gpio-ep93xx.5", 0, NULL, 1, GPIO_ACTIVE_HIGH), - { }, - }, -}; - -/************************************************************************* - * SPI Bus - *************************************************************************/ -static struct spi_board_info vision_spi_board_info[] __initdata =3D { - { - .modalias =3D "cs4271", - .platform_data =3D &vision_cs4271_data, - .max_speed_hz =3D 6000000, - .bus_num =3D 0, - .chip_select =3D 0, - .mode =3D SPI_MODE_3, - }, { - .modalias =3D "sst25l", - .platform_data =3D &vision_spi_flash_data, - .max_speed_hz =3D 20000000, - .bus_num =3D 0, - .chip_select =3D 1, - .mode =3D SPI_MODE_3, - }, { - .modalias =3D "mmc_spi", - .platform_data =3D &vision_spi_mmc_data, - .max_speed_hz =3D 20000000, - .bus_num =3D 0, - .chip_select =3D 2, - .mode =3D SPI_MODE_3, - }, -}; - -static struct gpiod_lookup_table vision_spi_cs_gpio_table =3D { - .dev_id =3D "spi0", - .table =3D { - GPIO_LOOKUP_IDX("gpio-ep93xx.0", 6, "cs", 0, GPIO_ACTIVE_LOW), - GPIO_LOOKUP_IDX("gpio-ep93xx.0", 7, "cs", 1, GPIO_ACTIVE_LOW), - GPIO_LOOKUP_IDX("gpio-ep93xx.6", 2, "cs", 2, GPIO_ACTIVE_LOW), - { }, - }, -}; - -static struct ep93xx_spi_info vision_spi_master __initdata =3D { - .use_dma =3D 1, -}; - -/************************************************************************* - * I2S Audio - *************************************************************************/ -static struct platform_device vision_audio_device =3D { - .name =3D "edb93xx-audio", - .id =3D -1, -}; - -static void __init vision_register_i2s(void) -{ - ep93xx_register_i2s(); - platform_device_register(&vision_audio_device); -} - -/************************************************************************* - * Machine Initialization - *************************************************************************/ -static void __init vision_init_machine(void) -{ - ep93xx_init_devices(); - ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_64M); - ep93xx_register_eth(&vision_eth_data, 1); - ep93xx_register_fb(&ep93xxfb_info); - ep93xx_register_pwm(1, 0); - - /* - * Request the gpio expander's interrupt gpio line now to prevent - * the kernel from doing a WARN in gpiolib:gpio_ensure_requested(). - */ - if (gpio_request_one(EP93XX_GPIO_LINE_F(7), GPIOF_DIR_IN, - "pca9539:74")) - pr_warn("cannot request interrupt gpio for pca9539:74\n"); - - vision_i2c_info[1].irq =3D gpio_to_irq(EP93XX_GPIO_LINE_F(7)); - - ep93xx_register_i2c(vision_i2c_info, - ARRAY_SIZE(vision_i2c_info)); - gpiod_add_lookup_table(&vision_spi_mmc_gpio_table); - gpiod_add_lookup_table(&vision_spi_cs_gpio_table); - ep93xx_register_spi(&vision_spi_master, vision_spi_board_info, - ARRAY_SIZE(vision_spi_board_info)); - vision_register_i2s(); -} - -MACHINE_START(VISION_EP9307, "Vision Engraving Systems EP9307") - /* Maintainer: H Hartley Sweeten */ - .atag_offset =3D 0x100, - .nr_irqs =3D NR_EP93XX_IRQS + EP93XX_BOARD_IRQS, - .map_io =3D vision_map_io, - .init_irq =3D ep93xx_init_irq, - .init_time =3D ep93xx_timer_init, - .init_machine =3D vision_init_machine, - .restart =3D ep93xx_restart, -MACHINE_END --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45220C77B7E for ; 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a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1685598401; bh=xWUpGUw0TWo8/gQXUxgOP54SbLDyy19Iv6LZ2KMAncY=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=nAZy3XT7AKxpO19wr9RBXBPrbwqp/UXBJF8S47LspHqwPOQn+Sfe9NkxWN683We6e YjNctgvU8gFUXLZs6IAFRwS1ipxIkaWDeP8CIrxD9w+8e4fSwpZp1TTrJyFtjcWsqB Jg6ngcYB5lDwFTQ4b0BiKu3BVwllOyzpgoOWeHrU= Authentication-Results: mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij , Nikita Shubin Cc: Michael Peters , Kris Bahnsen , linux-kernel@vger.kernel.org Subject: [PATCH v1 40/43] ARM: ep93xx: soc: drop defines Date: Thu, 1 Jun 2023 08:45:45 +0300 Message-Id: <20230601054549.10843-22-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Remove unnecessary defines, as we dropped board files. Signed-off-by: Nikita Shubin --- include/linux/platform_data/eth-ep93xx.h | 10 ------ include/linux/platform_data/keypad-ep93xx.h | 32 ----------------- include/linux/soc/cirrus/ep93xx.h | 38 ++++++++------------- 3 files changed, 14 insertions(+), 66 deletions(-) delete mode 100644 include/linux/platform_data/eth-ep93xx.h delete mode 100644 include/linux/platform_data/keypad-ep93xx.h diff --git a/include/linux/platform_data/eth-ep93xx.h b/include/linux/platf= orm_data/eth-ep93xx.h deleted file mode 100644 index 8eef637a804d..000000000000 --- a/include/linux/platform_data/eth-ep93xx.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _LINUX_PLATFORM_DATA_ETH_EP93XX -#define _LINUX_PLATFORM_DATA_ETH_EP93XX - -struct ep93xx_eth_data { - unsigned char dev_addr[6]; - unsigned char phy_id; -}; - -#endif diff --git a/include/linux/platform_data/keypad-ep93xx.h b/include/linux/pl= atform_data/keypad-ep93xx.h deleted file mode 100644 index 3054fced8509..000000000000 --- a/include/linux/platform_data/keypad-ep93xx.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __KEYPAD_EP93XX_H -#define __KEYPAD_EP93XX_H - -struct matrix_keymap_data; - -/* flags for the ep93xx_keypad driver */ -#define EP93XX_KEYPAD_DISABLE_3_KEY (1<<0) /* disable 3-key reset */ -#define EP93XX_KEYPAD_DIAG_MODE (1<<1) /* diagnostic mode */ -#define EP93XX_KEYPAD_BACK_DRIVE (1<<2) /* back driving mode */ -#define EP93XX_KEYPAD_TEST_MODE (1<<3) /* scan only column 0 */ -#define EP93XX_KEYPAD_AUTOREPEAT (1<<4) /* enable key autorepeat */ - -/** - * struct ep93xx_keypad_platform_data - platform specific device structure - * @keymap_data: pointer to &matrix_keymap_data - * @debounce: debounce start count; terminal count is 0xff - * @prescale: row/column counter pre-scaler load value - * @flags: see above - */ -struct ep93xx_keypad_platform_data { - struct matrix_keymap_data *keymap_data; - unsigned int debounce; - unsigned int prescale; - unsigned int flags; - unsigned int clk_rate; -}; - -#define EP93XX_MATRIX_ROWS (8) -#define EP93XX_MATRIX_COLS (8) - -#endif /* __KEYPAD_EP93XX_H */ diff --git a/include/linux/soc/cirrus/ep93xx.h b/include/linux/soc/cirrus/e= p93xx.h index 37c0e17a45c0..2acce55692a4 100644 --- a/include/linux/soc/cirrus/ep93xx.h +++ b/include/linux/soc/cirrus/ep93xx.h @@ -2,44 +2,34 @@ #ifndef _SOC_EP93XX_H #define _SOC_EP93XX_H =20 -struct platform_device; - #define EP93XX_CHIP_REV_D0 3 #define EP93XX_CHIP_REV_D1 4 #define EP93XX_CHIP_REV_E0 5 #define EP93XX_CHIP_REV_E1 6 #define EP93XX_CHIP_REV_E2 7 =20 -#if defined(CONFIG_EP93XX_SOC_COMMON) -int ep93xx_pwm_acquire_gpio(struct platform_device *pdev); -void ep93xx_pwm_release_gpio(struct platform_device *pdev); -int ep93xx_ide_acquire_gpio(struct platform_device *pdev); -void ep93xx_ide_release_gpio(struct platform_device *pdev); -int ep93xx_keypad_acquire_gpio(struct platform_device *pdev); -void ep93xx_keypad_release_gpio(struct platform_device *pdev); -int ep93xx_i2s_acquire(void); -void ep93xx_i2s_release(void); -#else -static inline int ep93xx_pwm_acquire_gpio(struct platform_device *pdev) { = return 0; } -static inline void ep93xx_pwm_release_gpio(struct platform_device *pdev) {} -static inline int ep93xx_ide_acquire_gpio(struct platform_device *pdev) { = return 0; } -static inline void ep93xx_ide_release_gpio(struct platform_device *pdev) {} -static inline int ep93xx_keypad_acquire_gpio(struct platform_device *pdev)= { return 0; } -static inline void ep93xx_keypad_release_gpio(struct platform_device *pdev= ) {} -static inline int ep93xx_i2s_acquire(void) { return 0; } -static inline void ep93xx_i2s_release(void) {} -#endif - #if defined(CONFIG_ARCH_EP93XX) unsigned int ep93xx_chip_revision(void); -#if defined(CONFIG_EP93XX_SOC) void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bit= s); void ep93xx_syscon_swlocked_write(unsigned int val, unsigned int reg); void ep93xx_swlocked_update_bits(unsigned int reg, unsigned int mask, unsigned int val); -#endif #else static inline unsigned int ep93xx_chip_revision(void) { return 0; } +static inline void ep93xx_devcfg_set_clear(unsigned int set_bits, + unsigned int clear_bits) +{ + return 0; +} +void ep93xx_syscon_swlocked_write(unsigned int val, unsigned int reg) +{ + return 0; +} +void ep93xx_swlocked_update_bits(unsigned int reg, + unsigned int mask, unsigned int val) +{ + return 0; +} #endif =20 #endif --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BBD8EC77B61 for ; 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(no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Alexander Sverdlin Add ADC node describing AD Converter present on EP9301 and EP9302 SoCs. Signed-off-by: Alexander Sverdlin Signed-off-by: Nikita Shubin --- arch/arm/boot/dts/ep93xx.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/ep93xx.dtsi b/arch/arm/boot/dts/ep93xx.dtsi index 67ecfde539af..d896bdcc6b10 100644 --- a/arch/arm/boot/dts/ep93xx.dtsi +++ b/arch/arm/boot/dts/ep93xx.dtsi @@ -354,6 +354,15 @@ spi0: spi@808a0000 { status =3D "disabled"; }; =20 + adc: adc@80900000 { + compatible =3D "cirrus,ep9301-adc"; + reg =3D <0x80900000 0x28>; + clocks =3D <&syscon EP93XX_CLK_ADC>; + interrupt-parent =3D <&vic0>; + interrupts =3D <30>; + status =3D "disabled"; + }; + watchdog0: watchdog@80940000 { compatible =3D "cirrus,ep9301-wdt"; reg =3D <0x80940000 0x08>; --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E254DC77B7E for ; Thu, 1 Jun 2023 05:49:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231693AbjFAFta (ORCPT ); Thu, 1 Jun 2023 01:49:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54004 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231623AbjFAFs3 (ORCPT ); Thu, 1 Jun 2023 01:48:29 -0400 Received: from forward101a.mail.yandex.net (forward101a.mail.yandex.net [178.154.239.84]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CFE151707; Wed, 31 May 2023 22:47:18 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net [IPv6:2a02:6b8:c1f:5e51:0:640:23ee:0]) by forward101a.mail.yandex.net (Yandex) with ESMTP id E0DF446CCD; Thu, 1 Jun 2023 08:46:41 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id pjGDMhnDduQ0-vdzO11An; Thu, 01 Jun 2023 08:46:41 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1685598401; bh=x9FOqoVdtIK6AvjUk/vZreQ0aPbCN0QKaGLmIFcDMG0=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=ceW5BAfp7bZQZhhD9v8TtpXf4C1bHNhnLN6IffLMR5AkhohSctwWssM2PckFcT+xG IYeEz1+zxkhgRu8fLK2cgtfsxJWoAINS4gyrA061ItvE2IlFlEf7uu3iy05TdcRAEg 0Im3hBI7uAamqtcdJQuIyQMv2lN5wV0V0i6Qh0hc= Authentication-Results: mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: Nikita Shubin , Michael Peters , Kris Bahnsen , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 41/43] ARM: dts: ep93xx: Add I2S and AC97 nodes Date: Thu, 1 Jun 2023 08:45:46 +0300 Message-Id: <20230601054549.10843-23-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Alexander Sverdlin Add the audio interfaces present in EP93xx SoCs. Signed-off-by: Alexander Sverdlin Signed-off-by: Nikita Shubin --- arch/arm/boot/dts/ep93xx.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/ep93xx.dtsi b/arch/arm/boot/dts/ep93xx.dtsi index 6da556ceaf04..c8028534dda7 100644 --- a/arch/arm/boot/dts/ep93xx.dtsi +++ b/arch/arm/boot/dts/ep93xx.dtsi @@ -301,6 +301,17 @@ ide: ide@800a0000 { pinctrl-0 =3D <&ide_default_pins>; }; =20 + ac97: ac97@80880000 { + compatible =3D "cirrus,ep9301-ac97"; + #sound-dai-cells =3D <0>; + reg =3D <0x80880000 0xac>; + interrupt-parent =3D <&vic0>; + interrupts =3D <6>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ac97_default_pins>; + status =3D "disabled"; + }; + uart0: uart@808c0000 { compatible =3D "arm,primecell"; reg =3D <0x808c0000 0x1000>; --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE139C7618E for ; Mon, 24 Apr 2023 10:21:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231731AbjDXKVS (ORCPT ); Mon, 24 Apr 2023 06:21:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231626AbjDXKUo (ORCPT ); Mon, 24 Apr 2023 06:20:44 -0400 Received: from forward501c.mail.yandex.net (forward501c.mail.yandex.net [IPv6:2a02:6b8:c03:500:1:45:d181:d501]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 269D410DF; Mon, 24 Apr 2023 03:20:43 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net [IPv6:2a02:6b8:c12:261e:0:640:2e3d:0]) by forward501c.mail.yandex.net (Yandex) with ESMTP id 641195EE19; Mon, 24 Apr 2023 12:36:15 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id JZBb1pbWwKo0-0lLAHDCF; Mon, 24 Apr 2023 12:36:15 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1682328975; bh=y7dJz8FU5tfDpAY0eGkdfYiaw3POjVAiEmGtpiD+K7I=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=Ae86ylug5zIP3hrqEdZs5fOAVjGiBypkdvvpF4FHzEtH9iXURaoDa3LdB24TVjF7E +3deRQCYHVhJToNXFf0ggLVnnC/6MlF+r0MIwzC6gBvEsZzxznAtSSVKpqqIO/Xe63 K4jCreeWzt7KixBS7FSWpitBsQRv0urcUgaqbGjY= Authentication-Results: mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 41/43] ARM: dts: ep93xx: Add I2S and AC97 nodes Date: Mon, 24 Apr 2023 15:34:57 +0300 Message-Id: <20230424123522.18302-42-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Alexander Sverdlin Add the audio interfaces present in EP93xx SoCs. Signed-off-by: Alexander Sverdlin Signed-off-by: Nikita Shubin --- arch/arm/boot/dts/ep93xx.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/ep93xx.dtsi b/arch/arm/boot/dts/ep93xx.dtsi index d896bdcc6b10..bba5fa753176 100644 --- a/arch/arm/boot/dts/ep93xx.dtsi +++ b/arch/arm/boot/dts/ep93xx.dtsi @@ -174,6 +174,19 @@ dma1: dma-controller@80000100 { interrupts =3D <17>, <18>; }; =20 + i2s: i2s@80820000 { + compatible =3D "cirrus,ep9301-i2s"; + #sound-dai-cells =3D <0>; + reg =3D <0x80820000 0x100>; + interrupt-parent =3D <&vic1>; + interrupts =3D <28>; + clocks =3D <&syscon EP93XX_CLK_I2S_MCLK + &syscon EP93XX_CLK_I2S_SCLK + &syscon EP93XX_CLK_I2S_LRCLK>; + clock-names =3D "mclk", "sclk", "lrclk"; + status =3D "disabled"; + }; + gpio0: gpio@80840000 { compatible =3D "cirrus,ep9301-gpio"; chip-label =3D "A"; @@ -293,6 +306,17 @@ ide: ide@800a0000 { pinctrl-0 =3D <&ide_default_pins>; }; =20 + ac97: ac97@80880000 { + compatible =3D "cirrus,ep9301-ac97"; + #sound-dai-cells =3D <0>; + reg =3D <0x80880000 0xac>; + interrupt-parent =3D <&vic0>; + interrupts =3D <6>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ac97_default_pins>; + status =3D "disabled"; + }; + uart0: uart@808c0000 { compatible =3D "arm,primecell"; reg =3D <0x808c0000 0x1000>; --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92C4CC77B61 for ; Mon, 24 Apr 2023 10:21:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231149AbjDXKVl (ORCPT ); Mon, 24 Apr 2023 06:21:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231694AbjDXKU4 (ORCPT ); Mon, 24 Apr 2023 06:20:56 -0400 Received: from forward502b.mail.yandex.net (forward502b.mail.yandex.net [IPv6:2a02:6b8:c02:900:1:45:d181:d502]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8223740C8; 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(no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Alexander Sverdlin Missing parts: - USB Signed-off-by: Alexander Sverdlin Signed-off-by: Nikita Shubin --- arch/arm/boot/dts/ep93xx-edb9302.dts | 150 +++++++++++++++++++++++++++ 1 file changed, 150 insertions(+) create mode 100644 arch/arm/boot/dts/ep93xx-edb9302.dts diff --git a/arch/arm/boot/dts/ep93xx-edb9302.dts b/arch/arm/boot/dts/ep93x= x-edb9302.dts new file mode 100644 index 000000000000..4ca915384ba9 --- /dev/null +++ b/arch/arm/boot/dts/ep93xx-edb9302.dts @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +/* + * Device Tree file for Cirrus Logic EDB9302 board based on EP9302 SoC + */ +/dts-v1/; +#include "ep93xx.dtsi" + +/ { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "cirrus,edb9302", "cirrus,ep9301"; + model =3D "cirrus,edb9302"; + + chosen { + }; + + memory { + device_type =3D "memory"; + }; + + soc { + flash@60000000 { + compatible =3D "cfi-flash"; + reg =3D <0x60000000 0x1000000>; + bank-width =3D <2>; + }; + }; + + sound { + compatible =3D "simple-audio-card"; + simple-audio-card,name =3D "EDB93XX"; + simple-audio-card,format =3D "i2s"; + simple-audio-card,mclk-fs =3D <256>; + simple-audio-card,convert-channels =3D <2>; + simple-audio-card,convert-sample-format =3D "s32_le"; + + simple-audio-card,cpu { + sound-dai =3D <&i2s>; + system-clock-direction-out; + frame-master; + bitclock-master; + dai-sample-format =3D "s32_le"; + dai-channels =3D <2>; + }; + + simple-audio-card,codec { + sound-dai =3D <&codec>; + }; + }; +}; + +&pinctrl { + compatible =3D "cirrus,ep9301-pinctrl"; +}; + +&gpio0 { + gpio-ranges =3D <&pinctrl 0 153 1>, + <&pinctrl 1 152 1>, + <&pinctrl 2 151 1>, + <&pinctrl 3 148 1>, + <&pinctrl 4 147 1>, + <&pinctrl 5 146 1>, + <&pinctrl 6 145 1>, + <&pinctrl 7 144 1>; +}; + +&gpio1 { + gpio-ranges =3D <&pinctrl 0 143 1>, + <&pinctrl 1 142 1>, + <&pinctrl 2 141 1>, + <&pinctrl 3 140 1>, + <&pinctrl 4 165 1>, + <&pinctrl 5 164 1>, + <&pinctrl 6 163 1>, + <&pinctrl 7 160 1>; +}; + +&gpio2 { + gpio-ranges =3D <&pinctrl 0 115 1>; + /delete-property/ status; + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; +}; + +&gpio4 { + gpio-ranges =3D <&pinctrl 0 97 2>; + /delete-property/ status; +}; + +&gpio5 { + gpio-ranges =3D <&pinctrl 1 170 1>, + <&pinctrl 2 169 1>, + <&pinctrl 3 168 1>; +}; + +&gpio6 { + gpio-ranges =3D <&pinctrl 0 87 2>; + /delete-property/ status; +}; + +&gpio7 { + gpio-ranges =3D <&pinctrl 2 199 4>; + /delete-property/ status; +}; + +&spi0 { + cs-gpios =3D <&gpio0 6 GPIO_ACTIVE_LOW + &gpio0 7 GPIO_ACTIVE_LOW>; + use_dma; + /delete-property/ status; + + codec: cs4271@0 { + compatible =3D "cirrus,cs4271"; + #sound-dai-cells =3D <0>; + reg =3D <0>; + spi-max-frequency =3D <6000000>; + spi-cpol; + spi-cpha; + reset-gpio =3D <&gpio0 1 GPIO_ACTIVE_HIGH>; + }; + + eeprom: at25f1024@1 { + compatible =3D "atmel,at25"; + reg =3D <1>; + spi-max-frequency =3D <20000000>; + }; +}; + +&adc { + /delete-property/ status; +}; + +ð0 { + copy_addr; + phy_id =3D <1>; +}; + +&uart0 { + /delete-property/ status; +}; + +&uart1 { + /delete-property/ status; +}; + +&i2s { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2s_on_ac97_pins>; + /delete-property/ status; +}; --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91FC6C77B7A for ; Thu, 1 Jun 2023 05:49:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231786AbjFAFtk (ORCPT ); Thu, 1 Jun 2023 01:49:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229724AbjFAFse (ORCPT ); Thu, 1 Jun 2023 01:48:34 -0400 Received: from forward100a.mail.yandex.net (forward100a.mail.yandex.net [178.154.239.83]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5D54F1710; Wed, 31 May 2023 22:47:21 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net [IPv6:2a02:6b8:c1f:5e51:0:640:23ee:0]) by forward100a.mail.yandex.net (Yandex) with ESMTP id 4616346CED; Thu, 1 Jun 2023 08:46:43 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id pjGDMhnDduQ0-yXfE0LdX; Thu, 01 Jun 2023 08:46:43 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1685598403; bh=xD3SVSf4acaNP04jn6OY2mZkIosr4Bwx2X5BXPKtEow=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=SYg3dKVVEhH5oHPt1clRNOmzuX6chECD0wwJ3oKue13AgsoOvc/smfc2WBvMIiv8z 5THy0kuGaHc/WtHXtcHCCmOeptKKj67zf2SnFTtHfAh5QBiwK9cSnElE6WF8zFb5M6 U2wwipAs6Fkl1xJU0MDxSl2c3HzG8zkI5yYeYO48= Authentication-Results: mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: Nikita Shubin , Michael Peters , Kris Bahnsen , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 42/43] ARM: dts: ep93xx: Add EDB9302 DT Date: Thu, 1 Jun 2023 08:45:47 +0300 Message-Id: <20230601054549.10843-24-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Alexander Sverdlin Add device tree for Cirrus EDB9302. Signed-off-by: Alexander Sverdlin Signed-off-by: Nikita Shubin --- Notes: v0 -> v1: =20 - added USB - dropped 'Missing USB' in commit message - add mdio + eth phy arch/arm/boot/dts/ep93xx-edb9302.dts | 160 +++++++++++++++++++++++++++ 1 file changed, 160 insertions(+) create mode 100644 arch/arm/boot/dts/ep93xx-edb9302.dts diff --git a/arch/arm/boot/dts/ep93xx-edb9302.dts b/arch/arm/boot/dts/ep93x= x-edb9302.dts new file mode 100644 index 000000000000..3ec89f7587db --- /dev/null +++ b/arch/arm/boot/dts/ep93xx-edb9302.dts @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +/* + * Device Tree file for Cirrus Logic EDB9302 board based on EP9302 SoC + */ +/dts-v1/; +#include "ep93xx.dtsi" + +/ { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "cirrus,edb9302", "cirrus,ep9301"; + model =3D "cirrus,edb9302"; + + chosen { + }; + + memory { + device_type =3D "memory"; + }; + + soc { + flash@60000000 { + compatible =3D "cfi-flash"; + reg =3D <0x60000000 0x1000000>; + bank-width =3D <2>; + }; + }; + + sound { + compatible =3D "simple-audio-card"; + simple-audio-card,name =3D "EDB93XX"; + simple-audio-card,format =3D "i2s"; + simple-audio-card,mclk-fs =3D <256>; + simple-audio-card,convert-channels =3D <2>; + simple-audio-card,convert-sample-format =3D "s32_le"; + + simple-audio-card,cpu { + sound-dai =3D <&i2s>; + system-clock-direction-out; + frame-master; + bitclock-master; + dai-sample-format =3D "s32_le"; + dai-channels =3D <2>; + }; + + simple-audio-card,codec { + sound-dai =3D <&codec>; + }; + }; +}; + +&pinctrl { + compatible =3D "cirrus,ep9301-pinctrl"; +}; + +&gpio0 { + gpio-ranges =3D <&pinctrl 0 153 1>, + <&pinctrl 1 152 1>, + <&pinctrl 2 151 1>, + <&pinctrl 3 148 1>, + <&pinctrl 4 147 1>, + <&pinctrl 5 146 1>, + <&pinctrl 6 145 1>, + <&pinctrl 7 144 1>; +}; + +&gpio1 { + gpio-ranges =3D <&pinctrl 0 143 1>, + <&pinctrl 1 142 1>, + <&pinctrl 2 141 1>, + <&pinctrl 3 140 1>, + <&pinctrl 4 165 1>, + <&pinctrl 5 164 1>, + <&pinctrl 6 163 1>, + <&pinctrl 7 160 1>; +}; + +&gpio2 { + gpio-ranges =3D <&pinctrl 0 115 1>; + /delete-property/ status; + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; +}; + +&gpio4 { + gpio-ranges =3D <&pinctrl 0 97 2>; + /delete-property/ status; +}; + +&gpio5 { + gpio-ranges =3D <&pinctrl 1 170 1>, + <&pinctrl 2 169 1>, + <&pinctrl 3 168 1>; +}; + +&gpio6 { + gpio-ranges =3D <&pinctrl 0 87 2>; + /delete-property/ status; +}; + +&gpio7 { + gpio-ranges =3D <&pinctrl 2 199 4>; + /delete-property/ status; +}; + +&spi0 { + cs-gpios =3D <&gpio0 6 GPIO_ACTIVE_LOW + &gpio0 7 GPIO_ACTIVE_LOW>; + use_dma; + /delete-property/ status; + + codec: cs4271@0 { + compatible =3D "cirrus,cs4271"; + #sound-dai-cells =3D <0>; + reg =3D <0>; + spi-max-frequency =3D <6000000>; + spi-cpol; + spi-cpha; + reset-gpio =3D <&gpio0 1 GPIO_ACTIVE_HIGH>; + }; + + eeprom: at25f1024@1 { + compatible =3D "atmel,at25"; + reg =3D <1>; + spi-max-frequency =3D <20000000>; + }; +}; + +&adc { + /delete-property/ status; +}; + +ð0 { + phy-handle =3D <&phy0>; +}; + +&mdio0 { + phy0: ethernet-phy@1 { + reg =3D <1>; + device_type =3D "ethernet-phy"; + }; +}; + +&uart0 { + /delete-property/ status; +}; + +&uart1 { + /delete-property/ status; +}; + +&usb0 { + /delete-property/ status; +}; + +&i2s { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2s_on_ac97_pins>; + /delete-property/ status; +}; --=20 2.37.4 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89D2BC77B61 for ; Mon, 24 Apr 2023 10:20:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231648AbjDXKUo (ORCPT ); Mon, 24 Apr 2023 06:20:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44254 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231131AbjDXKUj (ORCPT ); Mon, 24 Apr 2023 06:20:39 -0400 Received: from forward501c.mail.yandex.net (forward501c.mail.yandex.net [IPv6:2a02:6b8:c03:500:1:45:d181:d501]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 55FCBD8 for ; Mon, 24 Apr 2023 03:20:36 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net [IPv6:2a02:6b8:c12:261e:0:640:2e3d:0]) by forward501c.mail.yandex.net (Yandex) with ESMTP id 148A25EE62; Mon, 24 Apr 2023 12:36:18 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id JZBb1pbWwKo0-6emUVMRt; Mon, 24 Apr 2023 12:36:17 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1682328977; bh=s+pdsEhaXejJ3ZUi+ppZ8/CkunFsOa248KpIzEwqhCw=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=ajtf7pN1m7MbOx9L4P8H4r+Y82+evxwyLL7hp32bCAq4FIa+lb2I00PYCqXEWCGtx /uSrgSixLVbaOfevJiEDmrJ+vOA6s37wtIZwZ7WR6QsjwjXMoLjNk0rQgoinseBM0a X/bB9mW44MULXkAZlPUdOE1q93Pmqbt3HNy9qDQA= Authentication-Results: mail-nwsmtp-smtp-production-main-39.myt.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin Cc: Arnd Bergmann , Linus Walleij , Alexander Sverdlin , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Arnd Bergmann , linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org Subject: [PATCH 43/43] ASoC: cirrus: edb93xx: Delete driver Date: Mon, 24 Apr 2023 15:34:59 +0300 Message-Id: <20230424123522.18302-44-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Alexander Sverdlin Can be replaced with "simple-audio-card" for the rates up to 50kHz, refer to commit "ARM: dts: ep93xx: Add EDB9302 DT". Signed-off-by: Alexander Sverdlin Signed-off-by: Nikita Shubin --- sound/soc/cirrus/Kconfig | 9 --- sound/soc/cirrus/Makefile | 4 -- sound/soc/cirrus/edb93xx.c | 119 ------------------------------------- 3 files changed, 132 deletions(-) delete mode 100644 sound/soc/cirrus/edb93xx.c diff --git a/sound/soc/cirrus/Kconfig b/sound/soc/cirrus/Kconfig index 34870c2d0cba..a88b7d61b4c1 100644 --- a/sound/soc/cirrus/Kconfig +++ b/sound/soc/cirrus/Kconfig @@ -27,12 +27,3 @@ config SND_EP93XX_SOC_I2S_WATCHDOG =20 endif # if SND_EP93XX_SOC_I2S =20 -config SND_EP93XX_SOC_EDB93XX - tristate "SoC Audio support for Cirrus Logic EDB93xx boards" - depends on SND_EP93XX_SOC && (MACH_EDB9301 || MACH_EDB9302 || MACH_EDB930= 2A || MACH_EDB9307A || MACH_EDB9315A) - select SND_EP93XX_SOC_I2S - select SND_SOC_CS4271_I2C if I2C - select SND_SOC_CS4271_SPI if SPI_MASTER - help - Say Y or M here if you want to add support for I2S audio on the - Cirrus Logic EDB93xx boards. diff --git a/sound/soc/cirrus/Makefile b/sound/soc/cirrus/Makefile index 19a86daad660..5916c03888cb 100644 --- a/sound/soc/cirrus/Makefile +++ b/sound/soc/cirrus/Makefile @@ -6,7 +6,3 @@ snd-soc-ep93xx-i2s-objs :=3D ep93xx-i2s.o obj-$(CONFIG_SND_EP93XX_SOC) +=3D snd-soc-ep93xx.o obj-$(CONFIG_SND_EP93XX_SOC_I2S) +=3D snd-soc-ep93xx-i2s.o =20 -# EP93XX Machine Support -snd-soc-edb93xx-objs :=3D edb93xx.o - -obj-$(CONFIG_SND_EP93XX_SOC_EDB93XX) +=3D snd-soc-edb93xx.o diff --git a/sound/soc/cirrus/edb93xx.c b/sound/soc/cirrus/edb93xx.c deleted file mode 100644 index 385290202912..000000000000 --- a/sound/soc/cirrus/edb93xx.c +++ /dev/null @@ -1,119 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * SoC audio for EDB93xx - * - * Copyright (c) 2010 Alexander Sverdlin - * - * This driver support CS4271 codec being master or slave, working - * in control port mode, connected either via SPI or I2C. - * The data format accepted is I2S or left-justified. - * DAPM support not implemented. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -static int edb93xx_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params) -{ - struct snd_soc_pcm_runtime *rtd =3D asoc_substream_to_rtd(substream); - struct snd_soc_dai *codec_dai =3D asoc_rtd_to_codec(rtd, 0); - struct snd_soc_dai *cpu_dai =3D asoc_rtd_to_cpu(rtd, 0); - int err; - unsigned int mclk_rate; - unsigned int rate =3D params_rate(params); - - /* - * According to CS4271 datasheet we use MCLK/LRCK=3D256 for - * rates below 50kHz and 128 for higher sample rates - */ - if (rate < 50000) - mclk_rate =3D rate * 64 * 4; - else - mclk_rate =3D rate * 64 * 2; - - err =3D snd_soc_dai_set_sysclk(codec_dai, 0, mclk_rate, - SND_SOC_CLOCK_IN); - if (err) - return err; - - return snd_soc_dai_set_sysclk(cpu_dai, 0, mclk_rate, - SND_SOC_CLOCK_OUT); -} - -static const struct snd_soc_ops edb93xx_ops =3D { - .hw_params =3D edb93xx_hw_params, -}; - -SND_SOC_DAILINK_DEFS(hifi, - DAILINK_COMP_ARRAY(COMP_CPU("ep93xx-i2s")), - DAILINK_COMP_ARRAY(COMP_CODEC("spi0.0", "cs4271-hifi")), - DAILINK_COMP_ARRAY(COMP_PLATFORM("ep93xx-i2s"))); - -static struct snd_soc_dai_link edb93xx_dai =3D { - .name =3D "CS4271", - .stream_name =3D "CS4271 HiFi", - .dai_fmt =3D SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | - SND_SOC_DAIFMT_CBC_CFC, - .ops =3D &edb93xx_ops, - SND_SOC_DAILINK_REG(hifi), -}; - -static struct snd_soc_card snd_soc_edb93xx =3D { - .name =3D "EDB93XX", - .owner =3D THIS_MODULE, - .dai_link =3D &edb93xx_dai, - .num_links =3D 1, -}; - -static int edb93xx_probe(struct platform_device *pdev) -{ - struct snd_soc_card *card =3D &snd_soc_edb93xx; - int ret; - - ret =3D ep93xx_i2s_acquire(); - if (ret) - return ret; - - card->dev =3D &pdev->dev; - - ret =3D snd_soc_register_card(card); - if (ret) { - dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", - ret); - ep93xx_i2s_release(); - } - - return ret; -} - -static int edb93xx_remove(struct platform_device *pdev) -{ - struct snd_soc_card *card =3D platform_get_drvdata(pdev); - - snd_soc_unregister_card(card); - ep93xx_i2s_release(); - - return 0; -} - -static struct platform_driver edb93xx_driver =3D { - .driver =3D { - .name =3D "edb93xx-audio", - }, - .probe =3D edb93xx_probe, - .remove =3D edb93xx_remove, -}; - -module_platform_driver(edb93xx_driver); - -MODULE_AUTHOR("Alexander Sverdlin "); -MODULE_DESCRIPTION("ALSA SoC EDB93xx"); -MODULE_LICENSE("GPL"); -MODULE_ALIAS("platform:edb93xx-audio"); --=20 2.39.2 From nobody Thu Feb 12 10:36:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A894C77B7A for ; Thu, 1 Jun 2023 05:49:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231548AbjFAFs6 (ORCPT ); Thu, 1 Jun 2023 01:48:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54152 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231741AbjFAFrz (ORCPT ); Thu, 1 Jun 2023 01:47:55 -0400 Received: from forward102a.mail.yandex.net (forward102a.mail.yandex.net [178.154.239.85]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD15DE66 for ; Wed, 31 May 2023 22:47:00 -0700 (PDT) Received: from mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net [IPv6:2a02:6b8:c1f:5e51:0:640:23ee:0]) by forward102a.mail.yandex.net (Yandex) with ESMTP id 4484946C8B; Thu, 1 Jun 2023 08:46:48 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id pjGDMhnDduQ0-xZDGLeYg; Thu, 01 Jun 2023 08:46:47 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maquefel.me; s=mail; t=1685598407; bh=zzn32xd7cKMN+KlXGuogowDTuSb0Y+02JH0jZARTi/s=; h=Message-Id:Date:In-Reply-To:Cc:Subject:References:To:From; b=GjqqQSIV9i90L3YcZxswj74Sa2lVJxvDcb5mRg55QLhkOVwgY320ZcN21RCP4qrRg OSu6Ndze8T8erqwOQ1s/SzbIZ9gRq4uLSgnivk5/uMlNBnYvNCkwf17qDItEl8Ho6+ 8FyC+ozCEy5jrq8x2en2C9d+vTEfxv93qMNpa6Lg= Authentication-Results: mail-nwsmtp-smtp-production-main-51.vla.yp-c.yandex.net; dkim=pass header.i=@maquefel.me From: Nikita Shubin To: Alexander Sverdlin , Arnd Bergmann , Linus Walleij , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Nikita Shubin , Nicolas Ferre , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Michael Peters , Kris Bahnsen , linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org Subject: [PATCH v1 43/43] ASoC: cirrus: edb93xx: Delete driver Date: Thu, 1 Jun 2023 08:45:48 +0300 Message-Id: <20230601054549.10843-25-nikita.shubin@maquefel.me> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230424123522.18302-1-nikita.shubin@maquefel.me> References: <20230424123522.18302-1-nikita.shubin@maquefel.me> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Alexander Sverdlin Can be replaced with "simple-audio-card" for the rates up to 50kHz, refer to commit "ARM: dts: ep93xx: Add EDB9302 DT". Signed-off-by: Alexander Sverdlin Signed-off-by: Nikita Shubin --- sound/soc/cirrus/Kconfig | 9 --- sound/soc/cirrus/Makefile | 4 -- sound/soc/cirrus/edb93xx.c | 117 ------------------------------------- 3 files changed, 130 deletions(-) delete mode 100644 sound/soc/cirrus/edb93xx.c diff --git a/sound/soc/cirrus/Kconfig b/sound/soc/cirrus/Kconfig index 38a83c4dcc2d..97def4e53fbc 100644 --- a/sound/soc/cirrus/Kconfig +++ b/sound/soc/cirrus/Kconfig @@ -31,12 +31,3 @@ config SND_EP93XX_SOC_I2S_WATCHDOG =20 endif # if SND_EP93XX_SOC_I2S =20 -config SND_EP93XX_SOC_EDB93XX - tristate "SoC Audio support for Cirrus Logic EDB93xx boards" - depends on SND_EP93XX_SOC && (MACH_EDB9301 || MACH_EDB9302 || MACH_EDB930= 2A || MACH_EDB9307A || MACH_EDB9315A) - select SND_EP93XX_SOC_I2S - select SND_SOC_CS4271_I2C if I2C - select SND_SOC_CS4271_SPI if SPI_MASTER - help - Say Y or M here if you want to add support for I2S audio on the - Cirrus Logic EDB93xx boards. diff --git a/sound/soc/cirrus/Makefile b/sound/soc/cirrus/Makefile index 19a86daad660..5916c03888cb 100644 --- a/sound/soc/cirrus/Makefile +++ b/sound/soc/cirrus/Makefile @@ -6,7 +6,3 @@ snd-soc-ep93xx-i2s-objs :=3D ep93xx-i2s.o obj-$(CONFIG_SND_EP93XX_SOC) +=3D snd-soc-ep93xx.o obj-$(CONFIG_SND_EP93XX_SOC_I2S) +=3D snd-soc-ep93xx-i2s.o =20 -# EP93XX Machine Support -snd-soc-edb93xx-objs :=3D edb93xx.o - -obj-$(CONFIG_SND_EP93XX_SOC_EDB93XX) +=3D snd-soc-edb93xx.o diff --git a/sound/soc/cirrus/edb93xx.c b/sound/soc/cirrus/edb93xx.c deleted file mode 100644 index f49caab21a25..000000000000 --- a/sound/soc/cirrus/edb93xx.c +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * SoC audio for EDB93xx - * - * Copyright (c) 2010 Alexander Sverdlin - * - * This driver support CS4271 codec being master or slave, working - * in control port mode, connected either via SPI or I2C. - * The data format accepted is I2S or left-justified. - * DAPM support not implemented. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -static int edb93xx_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params) -{ - struct snd_soc_pcm_runtime *rtd =3D asoc_substream_to_rtd(substream); - struct snd_soc_dai *codec_dai =3D asoc_rtd_to_codec(rtd, 0); - struct snd_soc_dai *cpu_dai =3D asoc_rtd_to_cpu(rtd, 0); - int err; - unsigned int mclk_rate; - unsigned int rate =3D params_rate(params); - - /* - * According to CS4271 datasheet we use MCLK/LRCK=3D256 for - * rates below 50kHz and 128 for higher sample rates - */ - if (rate < 50000) - mclk_rate =3D rate * 64 * 4; - else - mclk_rate =3D rate * 64 * 2; - - err =3D snd_soc_dai_set_sysclk(codec_dai, 0, mclk_rate, - SND_SOC_CLOCK_IN); - if (err) - return err; - - return snd_soc_dai_set_sysclk(cpu_dai, 0, mclk_rate, - SND_SOC_CLOCK_OUT); -} - -static const struct snd_soc_ops edb93xx_ops =3D { - .hw_params =3D edb93xx_hw_params, -}; - -SND_SOC_DAILINK_DEFS(hifi, - DAILINK_COMP_ARRAY(COMP_CPU("ep93xx-i2s")), - DAILINK_COMP_ARRAY(COMP_CODEC("spi0.0", "cs4271-hifi")), - DAILINK_COMP_ARRAY(COMP_PLATFORM("ep93xx-i2s"))); - -static struct snd_soc_dai_link edb93xx_dai =3D { - .name =3D "CS4271", - .stream_name =3D "CS4271 HiFi", - .dai_fmt =3D SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | - SND_SOC_DAIFMT_CBC_CFC, - .ops =3D &edb93xx_ops, - SND_SOC_DAILINK_REG(hifi), -}; - -static struct snd_soc_card snd_soc_edb93xx =3D { - .name =3D "EDB93XX", - .owner =3D THIS_MODULE, - .dai_link =3D &edb93xx_dai, - .num_links =3D 1, -}; - -static int edb93xx_probe(struct platform_device *pdev) -{ - struct snd_soc_card *card =3D &snd_soc_edb93xx; - int ret; - - ret =3D ep93xx_i2s_acquire(); - if (ret) - return ret; - - card->dev =3D &pdev->dev; - - ret =3D snd_soc_register_card(card); - if (ret) { - dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", - ret); - ep93xx_i2s_release(); - } - - return ret; -} - -static void edb93xx_remove(struct platform_device *pdev) -{ - struct snd_soc_card *card =3D platform_get_drvdata(pdev); - - snd_soc_unregister_card(card); - ep93xx_i2s_release(); -} - -static struct platform_driver edb93xx_driver =3D { - .driver =3D { - .name =3D "edb93xx-audio", - }, - .probe =3D edb93xx_probe, - .remove_new =3D edb93xx_remove, -}; - -module_platform_driver(edb93xx_driver); - -MODULE_AUTHOR("Alexander Sverdlin "); -MODULE_DESCRIPTION("ALSA SoC EDB93xx"); -MODULE_LICENSE("GPL"); -MODULE_ALIAS("platform:edb93xx-audio"); --=20 2.37.4