From nobody Tue Dec 16 12:21:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BABBC77B73 for ; Sun, 23 Apr 2023 17:25:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230136AbjDWRZs (ORCPT ); Sun, 23 Apr 2023 13:25:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34454 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230046AbjDWRZn (ORCPT ); Sun, 23 Apr 2023 13:25:43 -0400 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F30B310DC for ; Sun, 23 Apr 2023 10:25:41 -0700 (PDT) Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-2fa0ce30ac2so3293506f8f.3 for ; Sun, 23 Apr 2023 10:25:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1682270740; x=1684862740; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6edtHrRUhMOVgTrX/B7WTyKMw10ZM0V+1t1+5ZMKBJE=; b=JADuU+heM2MwZW61nEJP7BxXxJ+uBDr7C7gBiY+1WKF53GSrll27l31QhAAv//vNCR MyIIGRdjzcwFduWH0m5lY+8JVthfsqqXnx2kdG91PzmYiJzR0ew21vv1f8YkRcg+udXY 2gynCLOKAD0aiNiUmStVQHwLXFIDDuKHPct+E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682270740; x=1684862740; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6edtHrRUhMOVgTrX/B7WTyKMw10ZM0V+1t1+5ZMKBJE=; b=XrYVdh8w4nb3Pcb2sPLLXm3ZeGtHBaEJR4M/3eC70NHP/B2wa4CkIDz83aeydKJghr tnLj10VXePw/aWkIM3X1V574FjJLB7c2q9xqQ5++S2IVSyY8YD1hpeNLePg8xHLR97Lh IhTdBc4vZoBXUfFCxiPZVW8hLMFPmQpQZwlSs1s0aQ7ZORUicDb5jqhRzXGlBgZxDHMo roP6L82o28CqUskq/ZF/PfyNoX+mJwrRKHqD8x4qZGPtTLUrwvsagICL4dER87EpZN2z k0wpWkvlrc1DcMaAi5cgrqc8PAgZxVap4s2EIzxr+Emn6tqKSY7FZHSlJjAyW7e3GUGS ju+g== X-Gm-Message-State: AAQBX9dRSdafZlDdrmT6KSY3l3Uf2wLfqswp/4cagH8Yf8WWTTjq90Ez sTuGPk+GOUuhfzAnujNZ5C4XAD9/H44xeUbDy+eMVg== X-Google-Smtp-Source: AKy350aVRAXW4ATQqNQqvDdR+BpDs/g0j3TnW8XRhPkWLSn+glwqdMA7cgWlU85pvQIpoYnPzL9ovQ== X-Received: by 2002:adf:e28b:0:b0:2f8:24f7:cc4a with SMTP id v11-20020adfe28b000000b002f824f7cc4amr7634427wri.57.1682270740105; Sun, 23 Apr 2023 10:25:40 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.. ([37.159.119.249]) by smtp.gmail.com with ESMTPSA id j32-20020a05600c1c2000b003f173987ec2sm13511653wms.22.2023.04.23.10.25.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 10:25:39 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Amarula patchwork , michael@amarulasolutions.com, Dario Binacchi , Alexandre Torgue , Krzysztof Kozlowski , Lee Jones , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 1/4] dt-bindings: mfd: stm32f7: add binding definition for CAN3 Date: Sun, 23 Apr 2023 19:25:25 +0200 Message-Id: <20230423172528.1398158-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20230423172528.1398158-1-dario.binacchi@amarulasolutions.com> References: <20230423172528.1398158-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add binding definition for CAN3 peripheral. Signed-off-by: Dario Binacchi --- include/dt-bindings/mfd/stm32f7-rcc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/mfd/stm32f7-rcc.h b/include/dt-bindings/mf= d/stm32f7-rcc.h index a90f3613c584..8d73a9c51e2b 100644 --- a/include/dt-bindings/mfd/stm32f7-rcc.h +++ b/include/dt-bindings/mfd/stm32f7-rcc.h @@ -64,6 +64,7 @@ #define STM32F7_RCC_APB1_TIM14 8 #define STM32F7_RCC_APB1_LPTIM1 9 #define STM32F7_RCC_APB1_WWDG 11 +#define STM32F7_RCC_APB1_CAN3 13 #define STM32F7_RCC_APB1_SPI2 14 #define STM32F7_RCC_APB1_SPI3 15 #define STM32F7_RCC_APB1_SPDIFRX 16 --=20 2.32.0 From nobody Tue Dec 16 12:21:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C6BDC77B60 for ; Sun, 23 Apr 2023 17:25:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230149AbjDWRZv (ORCPT ); Sun, 23 Apr 2023 13:25:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34466 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230081AbjDWRZp (ORCPT ); Sun, 23 Apr 2023 13:25:45 -0400 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D0E4DE6C for ; Sun, 23 Apr 2023 10:25:43 -0700 (PDT) Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-2f7c281a015so2085118f8f.1 for ; Sun, 23 Apr 2023 10:25:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1682270742; x=1684862742; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Nj3vUN1sCuMDZhLchBZ5ljBaRgoXn81VamEs7vmRecg=; b=Ji3b5vRxqg5iClJvgPJMHub8Kjxgs8UZLI+g7Y8LUP1McxE80sz3nw4pl6WcPIXB4d K15cbt3FrTPMthAs0ChTixHRWAVs2PvDUtlbu6K3e5cL2WWRnyCIVFkfQLeKDAO2P/lG VWRMx7Pwt7ZZIILG7jWKH2JvDiYmzRQrFKYvc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682270742; x=1684862742; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Nj3vUN1sCuMDZhLchBZ5ljBaRgoXn81VamEs7vmRecg=; b=O1t6u5k+RIK1ByPvyfhTRvyAbRWDwtR2XHmbSVlYAyZITghMFmjPpBD8VaXwJptgpE 6LWDrihBYKdlqogZDNoLXePbA9e9FyPAZ9rj0kFK7Opu+nkUB9dx21MK58ikB6PaqqC3 ggd2U+7+JXXYdPqudqow3FxnSaCGt8EnI0YccVxlM9DzQJKo3ssxcUDTcLb0c0iHLcKO SPd2sQOf5WQhHUjo0/i2DK0SIemC7DVcedN+NlYVxdGIE8LxeScOt6iDTs4NxwZgVYFL yJWHW2clAFMbKn/lKdv+e8jjLquFlKJ/LfYNX9BbXaLyz3LXOkwbDR0eQO7KhglQFHCI I0PQ== X-Gm-Message-State: AAQBX9eoZMNUan/abmnCKXz6HDbAk8CuCJhbLBkizlAEJ2WfafAOHP8Z 4bOUqosJkj8YtFm/WIPlw3w7n+2FUTg/ndqCdrFdQg== X-Google-Smtp-Source: AKy350Yp9TPkUsEVOI68JeJjGIhVsrjKqa3F+lk9FvLIdPG1XydenC8cuqq/shshNTosvWiYP9Defw== X-Received: by 2002:adf:e803:0:b0:2f7:a333:8cab with SMTP id o3-20020adfe803000000b002f7a3338cabmr8356900wrm.71.1682270742024; Sun, 23 Apr 2023 10:25:42 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.. ([37.159.119.249]) by smtp.gmail.com with ESMTPSA id j32-20020a05600c1c2000b003f173987ec2sm13511653wms.22.2023.04.23.10.25.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 10:25:41 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Amarula patchwork , michael@amarulasolutions.com, Dario Binacchi , Alexandre Torgue , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 2/4] ARM: dts: stm32: add CAN support on stm32f746 Date: Sun, 23 Apr 2023 19:25:26 +0200 Message-Id: <20230423172528.1398158-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20230423172528.1398158-1-dario.binacchi@amarulasolutions.com> References: <20230423172528.1398158-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for bxcan (Basic eXtended CAN controller) to STM32F746. The chip contains three CAN peripherals, CAN1 and CAN2 in dual peripheral configuration and CAN3 in single peripheral configuration: - Dual CAN peripheral configuration: * CAN1: Primary bxCAN for managing the communication between a secondary bxCAN and the 512-byte SRAM memory. * CAN2: Secondary bxCAN with no direct access to the SRAM memory. This means that the two bxCAN cells share the 512-byte SRAM memory and CAN2 can't be used without enabling CAN1. - Single CAN peripheral configuration: * CAN3: Primary bxCAN with dedicated Memory Access Controller unit and 512-byte SRAM memory. ------------------------------------------------------------------------- | features | CAN1 | CAN2 | CAN 3 | ------------------------------------------------------------------------- | SRAM | 512-byte shared between CAN1 & CAN2 | 512-byte | ------------------------------------------------------------------------- | Filters | 26 filters shared between CAN1 & CAN2 | 14 filters | ------------------------------------------------------------------------- Signed-off-by: Dario Binacchi --- arch/arm/boot/dts/stm32f746.dtsi | 39 ++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746= .dtsi index dc868e6da40e..70371d9dbb7a 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -257,6 +257,16 @@ rtc: rtc@40002800 { status =3D "disabled"; }; =20 + can3: can@40003400 { + compatible =3D "st,stm32f4-bxcan"; + reg =3D <0x40003400 0x400>; + interrupts =3D <104>, <105>, <106>, <107>; + interrupt-names =3D "tx", "rx0", "rx1", "sce"; + resets =3D <&rcc STM32F7_APB1_RESET(CAN3)>; + clocks =3D <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>; + status =3D "disabled"; + }; + usart2: serial@40004400 { compatible =3D "st,stm32f7-uart"; reg =3D <0x40004400 0x400>; @@ -337,6 +347,35 @@ i2c4: i2c@40006000 { status =3D "disabled"; }; =20 + can1: can@40006400 { + compatible =3D "st,stm32f4-bxcan"; + reg =3D <0x40006400 0x200>; + interrupts =3D <19>, <20>, <21>, <22>; + interrupt-names =3D "tx", "rx0", "rx1", "sce"; + resets =3D <&rcc STM32F7_APB1_RESET(CAN1)>; + clocks =3D <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>; + st,can-primary; + st,gcan =3D <&gcan>; + status =3D "disabled"; + }; + + gcan: gcan@40006600 { + compatible =3D "st,stm32f4-gcan", "syscon"; + reg =3D <0x40006600 0x200>; + clocks =3D <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>; + }; + + can2: can@40006800 { + compatible =3D "st,stm32f4-bxcan"; + reg =3D <0x40006800 0x200>; + interrupts =3D <63>, <64>, <65>, <66>; + interrupt-names =3D "tx", "rx0", "rx1", "sce"; + resets =3D <&rcc STM32F7_APB1_RESET(CAN2)>; + clocks =3D <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>; + st,gcan =3D <&gcan>; + status =3D "disabled"; + }; + cec: cec@40006c00 { compatible =3D "st,stm32-cec"; reg =3D <0x40006C00 0x400>; --=20 2.32.0 From nobody Tue Dec 16 12:21:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25695C77B60 for ; Sun, 23 Apr 2023 17:26:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230178AbjDWRZz (ORCPT ); Sun, 23 Apr 2023 13:25:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34484 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229696AbjDWRZr (ORCPT ); Sun, 23 Apr 2023 13:25:47 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8304F10D4 for ; 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([37.159.119.249]) by smtp.gmail.com with ESMTPSA id j32-20020a05600c1c2000b003f173987ec2sm13511653wms.22.2023.04.23.10.25.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 10:25:43 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Amarula patchwork , michael@amarulasolutions.com, Dario Binacchi , Alexandre Torgue , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 3/4] ARM: dts: stm32: add pin map for CAN controller on stm32f7 Date: Sun, 23 Apr 2023 19:25:27 +0200 Message-Id: <20230423172528.1398158-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20230423172528.1398158-1-dario.binacchi@amarulasolutions.com> References: <20230423172528.1398158-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add pin configurations for using CAN controller on stm32f7. Signed-off-by: Dario Binacchi --- arch/arm/boot/dts/stm32f7-pinctrl.dtsi | 82 ++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/stm= 32f7-pinctrl.dtsi index c8e6c52fb248..9f65403295ca 100644 --- a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi @@ -283,6 +283,88 @@ pins2 { slew-rate =3D <2>; }; }; + + can1_pins_a: can1-0 { + pins1 { + pinmux =3D ; /* CAN1_TX */ + }; + pins2 { + pinmux =3D ; /* CAN1_RX */ + bias-pull-up; + }; + }; + + can1_pins_b: can1-1 { + pins1 { + pinmux =3D ; /* CAN1_TX */ + }; + pins2 { + pinmux =3D ; /* CAN1_RX */ + bias-pull-up; + }; + }; + + can1_pins_c: can1-2 { + pins1 { + pinmux =3D ; /* CAN1_TX */ + }; + pins2 { + pinmux =3D ; /* CAN1_RX */ + bias-pull-up; + + }; + }; + + can1_pins_d: can1-3 { + pins1 { + pinmux =3D ; /* CAN1_TX */ + }; + pins2 { + pinmux =3D ; /* CAN1_RX */ + bias-pull-up; + + }; + }; + + can2_pins_a: can2-0 { + pins1 { + pinmux =3D ; /* CAN2_TX */ + }; + pins2 { + pinmux =3D ; /* CAN2_RX */ + bias-pull-up; + }; + }; + + can2_pins_b: can2-1 { + pins1 { + pinmux =3D ; /* CAN2_TX */ + }; + pins2 { + pinmux =3D ; /* CAN2_RX */ + bias-pull-up; + }; + }; + + can3_pins_a: can3-0 { + pins1 { + pinmux =3D ; /* CAN3_TX */ + }; + pins2 { + pinmux =3D ; /* CAN3_RX */ + bias-pull-up; + }; + }; + + can3_pins_b: can3-1 { + pins1 { + pinmux =3D ; /* CAN3_TX */ + }; + pins2 { + pinmux =3D ; /* CAN3_RX */ + bias-pull-up; + }; + }; }; }; }; --=20 2.32.0 From nobody Tue Dec 16 12:21:34 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06E6DC77B73 for ; Sun, 23 Apr 2023 17:26:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229609AbjDWR0B (ORCPT ); Sun, 23 Apr 2023 13:26:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34512 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230139AbjDWRZs (ORCPT ); Sun, 23 Apr 2023 13:25:48 -0400 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 261AB10DF for ; Sun, 23 Apr 2023 10:25:47 -0700 (PDT) Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-3f1957e80a2so53999705e9.1 for ; Sun, 23 Apr 2023 10:25:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1682270745; x=1684862745; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MbxDPqhzMCS7xX3Keeglii9B+3fU/m4LAIoQKCOvlGw=; b=kFx5aT3ZHShtKXQkjX5bjO1mltO6ghMp7YmjXd5ZNvN76bvrP2gL4pOSBoqLeReB8G zeWLvoIy3pGRjaBg8ippvtE2ncmlfWQ4TADwU81Z+/hoRM/Bogq1AjHFchGRzH+I/e4P WZ8/UXVNRta+9EMAFm/75ZgVx4u7w4Zq4Gm40= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682270745; x=1684862745; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MbxDPqhzMCS7xX3Keeglii9B+3fU/m4LAIoQKCOvlGw=; b=NlffK9E0bFFMSG01zHH9JEysSO2Osyz7lBqzICQa6UdfazqcPoTXOQ03z8K+/W+bo7 eMvo5IgTu0Lbj8x0Kdx+t7X2+Mwd1kQ5jiP+IEOjFUbmWnTCoeBeojubesLIqkmcpxR1 KHjC6M4+SM+5VxBHIxu/NzEErNjG81lhFVq/FMfPx1Jh4lNIJX7slo7Y+jn9QPK8V7ET vlDXFDt5fyrm/ZGFzuhstlY9u6luFqY3SiTaMCTz9PI0SRYXx6uUt3xfS+Xjbtp1K72B OjH/lyFOq+5CEEOV34zLHxi9AehxcsvyIyy7gvEWTjgQgGIomwyZrquod5ZthGrHza7q fZag== X-Gm-Message-State: AAQBX9ebu4ozBn7w4sIEQjhWXEfiADm5lRvNe++hXUSDsDOLYC/ajlj8 kjn9sMxj2WqsFDbLxRY++qFiAemo9In7zq0EI+LecQ== X-Google-Smtp-Source: AKy350ZHuZgYLS/Hh8NQ9a899+cfyiN9BaStXdrvXMXXQ5mfLaLgd3HI+XE8ZsuF4x4OP0KwGf8x8A== X-Received: by 2002:a1c:e904:0:b0:3ed:3268:5f35 with SMTP id q4-20020a1ce904000000b003ed32685f35mr6156037wmc.18.1682270745255; Sun, 23 Apr 2023 10:25:45 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.. ([37.159.119.249]) by smtp.gmail.com with ESMTPSA id j32-20020a05600c1c2000b003f173987ec2sm13511653wms.22.2023.04.23.10.25.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 10:25:44 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Amarula patchwork , michael@amarulasolutions.com, Dario Binacchi , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Marc Kleine-Budde , Paolo Abeni , Wolfgang Grandegger , linux-can@vger.kernel.org, netdev@vger.kernel.org Subject: [PATCH 4/4] can: bxcan: add support for single peripheral configuration Date: Sun, 23 Apr 2023 19:25:28 +0200 Message-Id: <20230423172528.1398158-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20230423172528.1398158-1-dario.binacchi@amarulasolutions.com> References: <20230423172528.1398158-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for bxCAN controller in single peripheral configuration: - primary bxCAN - dedicated Memory Access Controller unit - 512-byte SRAM memory - 14 fiter banks Signed-off-by: Dario Binacchi --- drivers/net/can/bxcan.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/net/can/bxcan.c b/drivers/net/can/bxcan.c index e26ccd41e3cb..9bcbbb85da6e 100644 --- a/drivers/net/can/bxcan.c +++ b/drivers/net/can/bxcan.c @@ -155,6 +155,7 @@ struct bxcan_regs { u32 reserved0[88]; /* 0x20 */ struct bxcan_mb tx_mb[BXCAN_TX_MB_NUM]; /* 0x180 - tx mailbox */ struct bxcan_mb rx_mb[BXCAN_RX_MB_NUM]; /* 0x1b0 - rx mailbox */ + u32 reserved1[12]; /* 0x1d0 */ }; =20 struct bxcan_priv { @@ -922,6 +923,12 @@ static int bxcan_get_berr_counter(const struct net_dev= ice *ndev, return 0; } =20 +static const struct regmap_config bxcan_gcan_regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, +}; + static int bxcan_probe(struct platform_device *pdev) { struct device_node *np =3D pdev->dev.of_node; @@ -942,11 +949,18 @@ static int bxcan_probe(struct platform_device *pdev) =20 gcan =3D syscon_regmap_lookup_by_phandle(np, "st,gcan"); if (IS_ERR(gcan)) { - dev_err(dev, "failed to get shared memory base address\n"); - return PTR_ERR(gcan); + primary =3D true; + gcan =3D devm_regmap_init_mmio(dev, + regs + sizeof(struct bxcan_regs), + &bxcan_gcan_regmap_config); + if (IS_ERR(gcan)) { + dev_err(dev, "failed to get filter base address\n"); + return PTR_ERR(gcan); + } + } else { + primary =3D of_property_read_bool(np, "st,can-primary"); } =20 - primary =3D of_property_read_bool(np, "st,can-primary"); clk =3D devm_clk_get(dev, NULL); if (IS_ERR(clk)) { dev_err(dev, "failed to get clock\n"); --=20 2.32.0