From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 522B1C77B73 for ; Sun, 23 Apr 2023 14:12:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230120AbjDWOMG (ORCPT ); Sun, 23 Apr 2023 10:12:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59016 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229458AbjDWOME (ORCPT ); Sun, 23 Apr 2023 10:12:04 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B053B9 for ; Sun, 23 Apr 2023 07:12:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=V1oDkmbueRnnz+rHHKvWOOs8MJ4RbGDKdmsY3zOpu8c=; b=C8X0JyttvzfIZRkmdMIeTVc7jr uWzk7FyLU4tVJF6tWDU9ilaTYNyLbwiDmBI9EeXPAmdEV8uAFJVK7/F9zWtAh0UnRw5JRv1xbTYox qgbnp4/71R6hU95uy41F/0g+RaSktaXSjA1a8d9ns7pdr3WHgfypygBfP1cAsJAqIo93Ef/OxE2HE hcXZBOFO4sz7WlbRfmOM/+zeMAZ0dqs/TlNt5y7jhxvWOqDtYp0G8UZfjXtwg2wZZuZnp7SHqVHVy zITmGbRUxLyu9jhIv7+Eqmer4N2pJCz0GYbtQ+gVp3RIF/KiTw+kOwYrUh1XmLpo9aQgUwRZMSRI+ 58vqZ59A==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaRX-00ANVs-0Y; Sun, 23 Apr 2023 16:11:55 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , linux-kernel@vger.kernel.org Subject: [RFC PATCH 01/40] drm/amd/display: fix segment distribution for linear LUTs Date: Sun, 23 Apr 2023 13:10:13 -0100 Message-Id: <20230423141051.702990-2-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Harry Wentland The region and segment calculation was incapable of dealing with regions of more than 16 segments. We first fix this. Now that we can support regions up to 256 elements we can define a better segment distribution for near-linear LUTs for our maximum of 256 HW-supported points. With these changes an "identity" LUT looks visually indistinguishable from bypass and allows us to use our 3DLUT. Signed-off-by: Harry Wentland --- .../amd/display/dc/dcn10/dcn10_cm_common.c | 95 +++++++++++++++---- 1 file changed, 76 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c b/drive= rs/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c index 7a00fe525dfb..f27413e94280 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c @@ -346,20 +346,37 @@ bool cm_helper_translate_curve_to_hw_format( * segment is from 2^-10 to 2^1 * There are less than 256 points, for optimization */ - seg_distr[0] =3D 3; - seg_distr[1] =3D 4; - seg_distr[2] =3D 4; - seg_distr[3] =3D 4; - seg_distr[4] =3D 4; - seg_distr[5] =3D 4; - seg_distr[6] =3D 4; - seg_distr[7] =3D 4; - seg_distr[8] =3D 4; - seg_distr[9] =3D 4; - seg_distr[10] =3D 1; - - region_start =3D -10; - region_end =3D 1; + if (output_tf->tf =3D=3D TRANSFER_FUNCTION_LINEAR) { + seg_distr[0] =3D 0; /* 2 */ + seg_distr[1] =3D 1; /* 4 */ + seg_distr[2] =3D 2; /* 4 */ + seg_distr[3] =3D 3; /* 8 */ + seg_distr[4] =3D 4; /* 16 */ + seg_distr[5] =3D 5; /* 32 */ + seg_distr[6] =3D 6; /* 64 */ + seg_distr[7] =3D 7; /* 128 */ + + region_start =3D -8; + region_end =3D 1; + } else { + seg_distr[0] =3D 3; /* 8 */ + seg_distr[1] =3D 4; /* 16 */ + seg_distr[2] =3D 4; + seg_distr[3] =3D 4; + seg_distr[4] =3D 4; + seg_distr[5] =3D 4; + seg_distr[6] =3D 4; + seg_distr[7] =3D 4; + seg_distr[8] =3D 4; + seg_distr[9] =3D 4; + seg_distr[10] =3D 1; /* 2 */ + /* total =3D 8*16 + 8 + 64 + 2 =3D */ + + region_start =3D -10; + region_end =3D 1; + } + + } =20 for (i =3D region_end - region_start; i < MAX_REGIONS_NUMBER ; i++) @@ -372,16 +389,56 @@ bool cm_helper_translate_curve_to_hw_format( =20 j =3D 0; for (k =3D 0; k < (region_end - region_start); k++) { - increment =3D NUMBER_SW_SEGMENTS / (1 << seg_distr[k]); + /* + * We're using an ugly-ish hack here. Our HW allows for + * 256 segments per region but SW_SEGMENTS is 16. + * SW_SEGMENTS has some undocumented relationship to + * the number of points in the tf_pts struct, which + * is 512, unlike what's suggested TRANSFER_FUNC_POINTS. + * + * In order to work past this dilemma we'll scale our + * increment by (1 << 4) and then do the inverse (1 >> 4) + * when accessing the elements in tf_pts. + * + * TODO: find a better way using SW_SEGMENTS and + * TRANSFER_FUNC_POINTS definitions + */ + increment =3D (NUMBER_SW_SEGMENTS << 4) / (1 << seg_distr[k]); start_index =3D (region_start + k + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS; - for (i =3D start_index; i < start_index + NUMBER_SW_SEGMENTS; + for (i =3D (start_index << 4); i < (start_index << 4) + (NUMBER_SW_SEGME= NTS << 4); i +=3D increment) { + struct fixed31_32 in_plus_one, in; + struct fixed31_32 value, red_value, green_value, blue_value; + uint32_t t =3D i & 0xf; + if (j =3D=3D hw_points - 1) break; - rgb_resulted[j].red =3D output_tf->tf_pts.red[i]; - rgb_resulted[j].green =3D output_tf->tf_pts.green[i]; - rgb_resulted[j].blue =3D output_tf->tf_pts.blue[i]; + + in_plus_one =3D output_tf->tf_pts.red[(i >> 4) + 1]; + in =3D output_tf->tf_pts.red[i >> 4]; + value =3D dc_fixpt_sub(in_plus_one, in); + value =3D dc_fixpt_shr(dc_fixpt_mul_int(value, t), 4); + value =3D dc_fixpt_add(in, value); + red_value =3D value; + + in_plus_one =3D output_tf->tf_pts.green[(i >> 4) + 1]; + in =3D output_tf->tf_pts.green[i >> 4]; + value =3D dc_fixpt_sub(in_plus_one, in); + value =3D dc_fixpt_shr(dc_fixpt_mul_int(value, t), 4); + value =3D dc_fixpt_add(in, value); + green_value =3D value; + + in_plus_one =3D output_tf->tf_pts.blue[(i >> 4) + 1]; + in =3D output_tf->tf_pts.blue[i >> 4]; + value =3D dc_fixpt_sub(in_plus_one, in); + value =3D dc_fixpt_shr(dc_fixpt_mul_int(value, t), 4); + value =3D dc_fixpt_add(in, value); + blue_value =3D value; + + rgb_resulted[j].red =3D red_value; + rgb_resulted[j].green =3D green_value; + rgb_resulted[j].blue =3D blue_value; j++; } } --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9BF18C77B76 for ; Sun, 23 Apr 2023 14:12:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230163AbjDWOMI (ORCPT ); Sun, 23 Apr 2023 10:12:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59022 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229649AbjDWOMF (ORCPT ); Sun, 23 Apr 2023 10:12:05 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 89BCD10CC for ; Sun, 23 Apr 2023 07:12:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=VoRYWGMN5c9KG4TgMo/sMnf0C+k2cdqhrvLiKjpRO7A=; b=rpOzJFYoeReUqyZCbjrl9+lW6p znpkLJeZlULUEL9KwSv12WzUX8EKLpikCNGiQSyd7zQsBPbdNJVkusoz4CXXLRJzfmsMEsFx1Srr1 tXR9tru/pIjpEr2T/w3wSabpSyrIeJO3xTP+sM3eXr6oq0Ea2VK2yuWDnwfA3JJZ8maDBgLd/MrAO bhkSx05XBtQX1aXmE+4EIFftUvJarzG6BLSDlzUpTjFRZyZMLI6OEhOqMnyLA/UYBWoaptBByRz4V vDOCChvXQz9YXTMxC8YQt8OBEWL7CJXbnegEcmI1NlYJZY5m4Va8RKF2kjpNAa9gtQXNugQDsj88G 4j8B6Amg==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaRa-00ANVs-Ps; Sun, 23 Apr 2023 16:11:58 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , linux-kernel@vger.kernel.org Subject: [RFC PATCH 02/40] drm/amd/display: fix the delta clamping for shaper LUT Date: Sun, 23 Apr 2023 13:10:14 -0100 Message-Id: <20230423141051.702990-3-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Harry Wentland The shaper LUT requires a 10-bit value of the delta between segments. We were using dc_fixpt_clamp_u0d10() to do that but it doesn't do what we want it to do. It will preserve 10-bit precision after the decimal point, but that's not quite what we want. We want 14-bit precision and discard the 4 most-significant bytes. To do that we'll do dc_fixpt_clamp_u0d14() & 0x3ff instead. Signed-off-by: Harry Wentland --- .../gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c b/drive= rs/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c index f27413e94280..efa6cee649d0 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c @@ -539,10 +539,18 @@ bool cm_helper_translate_curve_to_hw_format( rgb->delta_green =3D dc_fixpt_sub(rgb_plus_1->green, rgb->green); rgb->delta_blue =3D dc_fixpt_sub(rgb_plus_1->blue, rgb->blue); =20 + if (fixpoint =3D=3D true) { - rgb->delta_red_reg =3D dc_fixpt_clamp_u0d10(rgb->delta_red); - rgb->delta_green_reg =3D dc_fixpt_clamp_u0d10(rgb->delta_green); - rgb->delta_blue_reg =3D dc_fixpt_clamp_u0d10(rgb->delta_blue); + uint32_t red_clamp =3D dc_fixpt_clamp_u0d14(rgb->delta_red); + uint32_t green_clamp =3D dc_fixpt_clamp_u0d14(rgb->delta_green); + uint32_t blue_clamp =3D dc_fixpt_clamp_u0d14(rgb->delta_blue); + + if (red_clamp >> 10 || green_clamp >> 10 || blue_clamp >> 10) + DC_LOG_WARNING("Losing delta precision while programming shaper LUT."); + + rgb->delta_red_reg =3D red_clamp & 0x3ff; + rgb->delta_green_reg =3D green_clamp & 0x3ff; + rgb->delta_blue_reg =3D blue_clamp & 0x3ff; rgb->red_reg =3D dc_fixpt_clamp_u0d14(rgb->red); rgb->green_reg =3D dc_fixpt_clamp_u0d14(rgb->green); rgb->blue_reg =3D dc_fixpt_clamp_u0d14(rgb->blue); --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE422C6FD18 for ; Sun, 23 Apr 2023 14:12:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230217AbjDWOMR (ORCPT ); Sun, 23 Apr 2023 10:12:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59128 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230173AbjDWOMM (ORCPT ); Sun, 23 Apr 2023 10:12:12 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F0FE127 for ; Sun, 23 Apr 2023 07:12:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=t2oXYPnyQYeafj80rDPPBk4DJ8Bih7Zw8inrjzwVK2k=; b=aP6aQ5wQasUVq+wLWIjGodQt00 LxejcRVm0NGApRky08NWdEeUpFtwqFGXZfG1nFO+TauDItvUKPJRf4yCfAHbqZI8qYIEhweQNuAZs e2PLcbfp7TVVKU3ZcyHGOl72JvMeTc5Qm5FPNTzGdGWbDtWZ8XSr2FqwIykOJrbQz2CaR9WsQma54 5DUODHpMMNwr+CNxJPFDVcIAq0sWsEWcq2cASJvjU51Dt697lL0odeA0v97oRsyGj3YvynKp/EeG8 3CGyaECE2hrwsRGd1wZtCOcoA67uI+hnGrVSX2jH5VuebhzdRABy7cjpsiXFDDSU//wlF63/I3guE WxIN7RFQ==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaRe-00ANVs-Kv; Sun, 23 Apr 2023 16:12:02 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 03/40] drm/amd/display: introduce Steam Deck color features to AMD display driver Date: Sun, 23 Apr 2023 13:10:15 -0100 Message-Id: <20230423141051.702990-4-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We are enabling a large set of color calibration features to enhance KMS color mgmt but these properties are specific of AMD display HW, and cannot be provided by other vendors. Therefore, set a config option to enable AMD driver-private properties used on Steam Deck color mgmt pipeline. Co-developed-by: Joshua Ashton Signed-off-by: Joshua Ashton Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/display/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/disp= lay/Kconfig index 06b438217c61..c45a8deb1098 100644 --- a/drivers/gpu/drm/amd/display/Kconfig +++ b/drivers/gpu/drm/amd/display/Kconfig @@ -53,5 +53,11 @@ config DRM_AMD_SECURE_DISPLAY of crc of specific region via debugfs. Cooperate with specific DMCU FW. =20 +config STEAM_DECK + bool "Enable color calibration features for Steam Deck" + depends on DRM_AMD_DC + help + Choose this option if you want to use AMDGPU features for broader + color management support on Steam Deck. =20 endmenu --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9879C6FD18 for ; Sun, 23 Apr 2023 14:12:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230246AbjDWOMm (ORCPT ); Sun, 23 Apr 2023 10:12:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59990 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230235AbjDWOMc (ORCPT ); Sun, 23 Apr 2023 10:12:32 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE04F1FD6 for ; Sun, 23 Apr 2023 07:12:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=61KSS5+ykrC2EpBhN11Qk1hbuXSnyOrLMv+gxM8XJiM=; b=EBlbem39+WObZkXT6cpRxHLypm sJSX69u+V+8TBPnkSJlNRH2ttHSacdtg9acvMnz/55ocsu8Koe3dKdyxugqLT+mOC+NnTEXXt1dKz RQs6n6CDGQW0lJ4r5DOh133lEtV+qPnPSEb2hr3uCJwGA7ijCsDz4soKbSIEA5RuAU4DiUkw5i0dT O/9CYFrOesSGjOPUk+BYFj7ICUN1USFkiHw3SF4VfEQd0TcILVY+Z/HCIPUWv9oiqI9adixNsMslC 98FsXi0h9xA9AnU7MEcxaBA7ThvHTt0mcpwcSl7oVDiU0IQdpNRCRkou3+Tb8FUuwPUOoU8eSQauZ HTuMR28Q==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaRh-00ANVs-QW; Sun, 23 Apr 2023 16:12:05 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 04/40] drm/drm_mode_object: increase max objects to accommodate new color props Date: Sun, 23 Apr 2023 13:10:16 -0100 Message-Id: <20230423141051.702990-5-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In the next patches we are adding 17 new properties for color correction: - CRTC: 3D LUT+size, shaper LUT+size, regamma TF (5) - Plane: Degamma LUT+size+TF, HDR multiplier, shaper LUT+size+TF, 3D LUT+si= ze, blend LUT+size+TF (12) We still need to detach driver-private counter from DRM/KMS-generic, by now, increase max objs to 41. Signed-off-by: Melissa Wen --- include/drm/drm_mode_object.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/drm/drm_mode_object.h b/include/drm/drm_mode_object.h index 912f1e415685..7e4fb7536c6a 100644 --- a/include/drm/drm_mode_object.h +++ b/include/drm/drm_mode_object.h @@ -60,7 +60,7 @@ struct drm_mode_object { void (*free_cb)(struct kref *kref); }; =20 -#define DRM_OBJECT_MAX_PROPERTY 24 +#define DRM_OBJECT_MAX_PROPERTY 47 /** * struct drm_object_properties - property tracking for &drm_mode_object */ --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F17D5C6FD18 for ; Sun, 23 Apr 2023 14:12:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230215AbjDWOM3 (ORCPT ); Sun, 23 Apr 2023 10:12:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59446 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230173AbjDWOMS (ORCPT ); Sun, 23 Apr 2023 10:12:18 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3DC7610D2 for ; Sun, 23 Apr 2023 07:12:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=MWZg+O3y0ybUoSZE+Ev3495R/hqyYOtAGPPhQThmk+k=; b=eKogjPhFWjQrXoV0+AGmU9qjw8 PUliAB3kyiGVgAeZD4mlaf5PKFpNtKs6eEDKgQdS8ZeedNSOpdQgBQ+QBgerpCOI8Ge8S3PZPwmIT SeyLbi1vMoTOW9YbNyrZETehq4zce1WQcAne90PaVEOdnQcdUSUSet7zWxt5hofFsLSbA4pnJ0unk 6EJL9EPWo7OEXsseSP/lRFG4H7RR9Un3WjFhQTaAkNE5if5/KqDIBgZU9kWi5/QuXFx9RLEvDCv5r JFWzDbiLfVyV01yucJsZRjsLFVeya8DHAx7QuB1KWd3zZcBj5GmgsyZyR+jQU65eE8MZ74IE9nvwq z+ZfQy9Q==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaRk-00ANVs-LA; Sun, 23 Apr 2023 16:12:08 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 05/40] drm/amd/display: add shaper LUT driver-private props Date: Sun, 23 Apr 2023 13:10:17 -0100 Message-Id: <20230423141051.702990-6-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" CRTC shaper LUT shapes the content after blending, i.e., de-linearizes or normalizes space before applying a 3D LUT color correction. In the next patch, we add CRTC 3D LUT property to DRM color management after this shaper LUT and before the current CRTC gamma LUT. Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 28 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 14 ++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 17 +++ .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 122 +++++++++++++++++- 4 files changed, 179 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/= amd/amdgpu/amdgpu_display.c index 8632ab695a6c..44c22cb87dde 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1247,6 +1247,30 @@ amdgpu_display_user_framebuffer_create(struct drm_de= vice *dev, return &amdgpu_fb->base; } =20 +#ifdef CONFIG_STEAM_DECK +static int +amdgpu_display_create_color_properties(struct amdgpu_device *adev) +{ + struct drm_property *prop; + + prop =3D drm_property_create(adev_to_drm(adev), + DRM_MODE_PROP_BLOB, + "AMD_SHAPER_LUT", 0); + if (!prop) + return -ENOMEM; + adev->mode_info.shaper_lut_property =3D prop; + + prop =3D drm_property_create_range(adev_to_drm(adev), + DRM_MODE_PROP_IMMUTABLE, + "AMD_SHAPER_LUT_SIZE", 0, UINT_MAX); + if (!prop) + return -ENOMEM; + adev->mode_info.shaper_lut_size_property =3D prop; + + return 0; +} +#endif + const struct drm_mode_config_funcs amdgpu_mode_funcs =3D { .fb_create =3D amdgpu_display_user_framebuffer_create, }; @@ -1323,6 +1347,10 @@ int amdgpu_display_modeset_create_props(struct amdgp= u_device *adev) return -ENOMEM; } =20 +#ifdef CONFIG_STEAM_DECK + if (amdgpu_display_create_color_properties(adev)) + return -ENOMEM; +#endif return 0; } =20 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd= /amdgpu/amdgpu_mode.h index b8633df418d4..1fd3497af3b5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -344,6 +344,20 @@ struct amdgpu_mode_info { int disp_priority; const struct amdgpu_display_funcs *funcs; const enum drm_plane_type *plane_type; + + /* Driver-private color mgmt props */ +#ifdef CONFIG_STEAM_DECK + /** + * @shaper_lut_property: CRTC property to set post-blending shaper LUT + * that converts content before 3D LUT gamma correction. + */ + struct drm_property *shaper_lut_property; + /** + * @shaper_lut_size_property: CRTC property for the size of + * post-blending shaper LUT as supported by the driver (read-only). + */ + struct drm_property *shaper_lut_size_property; +#endif }; =20 #define AMDGPU_MAX_BL_LEVEL 0xFF diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gp= u/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 2e2413fd73a4..de63455896cc 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -726,6 +726,23 @@ struct dm_crtc_state { struct dc_info_packet vrr_infopacket; =20 int abm_level; + +#ifdef CONFIG_STEAM_DECK + /* AMD driver-private color mgmt pipeline + * + * DRM provides CRTC degamma/ctm/gamma color mgmt features, but AMD HW + * has a larger set of post-blending color calibration features, as + * below: + */ + /** + * @shaper_lut: + * + * Lookup table used to de-linearize pixel data for gamma correction. + * See drm_crtc_enable_color_mgmt(). The blob (if not NULL) is an array + * of &struct drm_color_lut. + */ + struct drm_property_blob *shaper_lut; +#endif }; =20 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drive= rs/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index e3762e806617..503433e5cb38 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -229,7 +229,9 @@ static void dm_crtc_destroy_state(struct drm_crtc *crtc, if (cur->stream) dc_stream_release(cur->stream); =20 - +#ifdef CONFIG_STEAM_DECK + drm_property_blob_put(cur->shaper_lut); +#endif __drm_atomic_helper_crtc_destroy_state(state); =20 =20 @@ -266,7 +268,12 @@ static struct drm_crtc_state *dm_crtc_duplicate_state(= struct drm_crtc *crtc) state->crc_skip_count =3D cur->crc_skip_count; state->mpo_requested =3D cur->mpo_requested; /* TODO Duplicate dc_stream after objects are stream object is flattened = */ +#ifdef CONFIG_STEAM_DECK + state->shaper_lut =3D cur->shaper_lut; =20 + if (state->shaper_lut) + drm_property_blob_get(state->shaper_lut); +#endif return &state->base; } =20 @@ -299,6 +306,111 @@ static int amdgpu_dm_crtc_late_register(struct drm_cr= tc *crtc) } #endif =20 +#ifdef CONFIG_STEAM_DECK +/** + * drm_crtc_additional_color_mgmt - enable additional color properties + * @crtc: DRM CRTC + * + * This function lets the driver enable the 3D LUT color correction proper= ty + * on a CRTC. This includes shaper LUT, 3D LUT and regamma TF. The shaper + * LUT and 3D LUT property is only attached if its size is not 0. + */ +static void +dm_crtc_additional_color_mgmt(struct drm_crtc *crtc) +{ + struct amdgpu_device *adev =3D drm_to_adev(crtc->dev); + + if (adev->dm.dc->caps.color.mpc.num_3dluts) { + drm_object_attach_property(&crtc->base, + adev->mode_info.shaper_lut_property, 0); + drm_object_attach_property(&crtc->base, + adev->mode_info.shaper_lut_size_property, + MAX_COLOR_LUT_ENTRIES); + } +} + +static int +atomic_replace_property_blob_from_id(struct drm_device *dev, + struct drm_property_blob **blob, + uint64_t blob_id, + ssize_t expected_size, + ssize_t expected_elem_size, + bool *replaced) +{ + struct drm_property_blob *new_blob =3D NULL; + + if (blob_id !=3D 0) { + new_blob =3D drm_property_lookup_blob(dev, blob_id); + if (new_blob =3D=3D NULL) + return -EINVAL; + + if (expected_size > 0 && + new_blob->length !=3D expected_size) { + drm_property_blob_put(new_blob); + return -EINVAL; + } + if (expected_elem_size > 0 && + new_blob->length % expected_elem_size !=3D 0) { + drm_property_blob_put(new_blob); + return -EINVAL; + } + } + + *replaced |=3D drm_property_replace_blob(blob, new_blob); + drm_property_blob_put(new_blob); + + return 0; +} + +static int +amdgpu_dm_atomic_crtc_set_property(struct drm_crtc *crtc, + struct drm_crtc_state *state, + struct drm_property *property, + uint64_t val) +{ + struct amdgpu_device *adev =3D drm_to_adev(crtc->dev); + struct dm_crtc_state *acrtc_state =3D to_dm_crtc_state(state); + bool replaced =3D false; + int ret; + + if (property =3D=3D adev->mode_info.shaper_lut_property) { + ret =3D atomic_replace_property_blob_from_id(crtc->dev, + &acrtc_state->shaper_lut, + val, + -1, sizeof(struct drm_color_lut), + &replaced); + acrtc_state->base.color_mgmt_changed |=3D replaced; + return ret; + } else { + drm_dbg_atomic(crtc->dev, + "[CRTC:%d:%s] unknown property [PROP:%d:%s]]\n", + crtc->base.id, crtc->name, + property->base.id, property->name); + return -EINVAL; + } + + return 0; +} + +static int +amdgpu_dm_atomic_crtc_get_property(struct drm_crtc *crtc, + const struct drm_crtc_state *state, + struct drm_property *property, + uint64_t *val) +{ + struct amdgpu_device *adev =3D drm_to_adev(crtc->dev); + struct dm_crtc_state *acrtc_state =3D to_dm_crtc_state(state); + + if (property =3D=3D adev->mode_info.shaper_lut_property) + *val =3D (acrtc_state->shaper_lut) ? + acrtc_state->shaper_lut->base.id : 0; + else + return -EINVAL; + + return 0; +} +#endif + /* Implemented only the options currently available for the driver */ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs =3D { .reset =3D dm_crtc_reset_state, @@ -317,6 +429,10 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_func= s =3D { #if defined(CONFIG_DEBUG_FS) .late_register =3D amdgpu_dm_crtc_late_register, #endif +#ifdef CONFIG_STEAM_DECK + .atomic_set_property =3D amdgpu_dm_atomic_crtc_set_property, + .atomic_get_property =3D amdgpu_dm_atomic_crtc_get_property, +#endif }; =20 static void dm_crtc_helper_disable(struct drm_crtc *crtc) @@ -477,9 +593,11 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager = *dm, is_dcn =3D dm->adev->dm.dc->caps.color.dpp.dcn_arch; drm_crtc_enable_color_mgmt(&acrtc->base, is_dcn ? MAX_COLOR_LUT_ENTRIES := 0, true, MAX_COLOR_LUT_ENTRIES); - drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES); =20 +#ifdef CONFIG_STEAM_DECK + dm_crtc_additional_color_mgmt(&acrtc->base); +#endif return 0; =20 fail: --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84CBEC77B60 for ; Sun, 23 Apr 2023 14:12:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230189AbjDWOMg (ORCPT ); Sun, 23 Apr 2023 10:12:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59478 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230246AbjDWOM2 (ORCPT ); Sun, 23 Apr 2023 10:12:28 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DFF4430F4 for ; Sun, 23 Apr 2023 07:12:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=Bm3Geo0t068sVPmTEYcYCE9oJGTq0xUkld/+z+807H0=; b=B1NZFih/nsbd8wN6emS12XMH6n cwfjEmV3Y44Dz3/Jj7ajJQ/7sbm69ggsPB1k5wAAeN0ByvwkioyXOW6e+ROOXLqvS5Fspi704K85n z+HQDTm53njLaBKNoTVb/TByZQ5C8JeVPvNR1IMFkNNu1QCT8vxEMWEi27nofoUNZZqYP48++6puT PyoEa9gUMyzc6wPhuEj6wxGZDC0ffLsJ8oUwacWdtHxZifgKqubO+L94NfMh7hBY1xND4hh6w2lmA acVUfeUsfjyMas0hFFMbpfHUpU5ImuCoznCUlPt/Gam7swjP8337OZHbrF989Pxb1NEMNx3yivn9r Xz+mnWFQ==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaRn-00ANVs-ED; Sun, 23 Apr 2023 16:12:11 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 06/40] drm/amd/display: add 3D LUT driver-private props Date: Sun, 23 Apr 2023 13:10:18 -0100 Message-Id: <20230423141051.702990-7-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add CRTC 3D LUT for gamma correction using a 3D lookup table. A shaper lut must be set to shape the content for a non-linear space. That details should be handled by the driver according to HW color capabilities. Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 14 +++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 11 ++++++++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 13 ++++++++++++ .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 20 +++++++++++++++++++ 4 files changed, 58 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/= amd/amdgpu/amdgpu_display.c index 44c22cb87dde..2abe5fe87c10 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1267,6 +1267,20 @@ amdgpu_display_create_color_properties(struct amdgpu= _device *adev) return -ENOMEM; adev->mode_info.shaper_lut_size_property =3D prop; =20 + prop =3D drm_property_create(adev_to_drm(adev), + DRM_MODE_PROP_BLOB, + "AMD_LUT3D", 0); + if (!prop) + return -ENOMEM; + adev->mode_info.lut3d_property =3D prop; + + prop =3D drm_property_create_range(adev_to_drm(adev), + DRM_MODE_PROP_IMMUTABLE, + "AMD_LUT3D_SIZE", 0, UINT_MAX); + if (!prop) + return -ENOMEM; + adev->mode_info.lut3d_size_property =3D prop; + return 0; } #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd= /amdgpu/amdgpu_mode.h index 1fd3497af3b5..205fa4f5bea7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -357,6 +357,17 @@ struct amdgpu_mode_info { * post-blending shaper LUT as supported by the driver (read-only). */ struct drm_property *shaper_lut_size_property; + /** + * lut3d_property: CRTC property to set post-blending 3D LUT gamma + * correction; a shaper LUT can be used before applying 3D LUT to + * delinearize content. + */ + struct drm_property *lut3d_property; + /** + * @lut3d_size_property: CRTC property for the size of post-blending 3D + * LUT as supported by the driver (read-only). + */ + struct drm_property *lut3d_size_property; #endif }; =20 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gp= u/drm/amd/display/amdgpu_dm/amdgpu_dm.h index de63455896cc..09c3e1858b56 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -742,6 +742,15 @@ struct dm_crtc_state { * of &struct drm_color_lut. */ struct drm_property_blob *shaper_lut; + /** + * @lut3d: + * + * 3D Lookup table for converting pixel data. Position where it takes + * place depends on hw design, after @ctm or @gamma_lut. See + * drm_crtc_enable_color_mgmt(). The blob (if not NULL) is an array of + * &struct drm_color_lut. + */ + struct drm_property_blob *lut3d; #endif }; =20 @@ -804,6 +813,10 @@ void amdgpu_dm_update_freesync_caps(struct drm_connect= or *connector, =20 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); =20 +/* 3D LUT max size is 17x17x17 */ +#define MAX_COLOR_3DLUT_ENTRIES 4913 +#define MAX_COLOR_3DLUT_BITDEPTH 12 +/* 1D LUT degamma, regamma and shaper*/ #define MAX_COLOR_LUT_ENTRIES 4096 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drive= rs/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 503433e5cb38..0e1280228e6e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -231,6 +231,7 @@ static void dm_crtc_destroy_state(struct drm_crtc *crtc, =20 #ifdef CONFIG_STEAM_DECK drm_property_blob_put(cur->shaper_lut); + drm_property_blob_put(cur->lut3d); #endif __drm_atomic_helper_crtc_destroy_state(state); =20 @@ -270,9 +271,12 @@ static struct drm_crtc_state *dm_crtc_duplicate_state(= struct drm_crtc *crtc) /* TODO Duplicate dc_stream after objects are stream object is flattened = */ #ifdef CONFIG_STEAM_DECK state->shaper_lut =3D cur->shaper_lut; + state->lut3d =3D cur->lut3d; =20 if (state->shaper_lut) drm_property_blob_get(state->shaper_lut); + if (state->lut3d) + drm_property_blob_get(state->lut3d); #endif return &state->base; } @@ -326,6 +330,11 @@ dm_crtc_additional_color_mgmt(struct drm_crtc *crtc) drm_object_attach_property(&crtc->base, adev->mode_info.shaper_lut_size_property, MAX_COLOR_LUT_ENTRIES); + drm_object_attach_property(&crtc->base, + adev->mode_info.lut3d_property, 0); + drm_object_attach_property(&crtc->base, + adev->mode_info.lut3d_size_property, + MAX_COLOR_3DLUT_ENTRIES); } } =20 @@ -381,6 +390,14 @@ amdgpu_dm_atomic_crtc_set_property(struct drm_crtc *cr= tc, &replaced); acrtc_state->base.color_mgmt_changed |=3D replaced; return ret; + } else if (property =3D=3D adev->mode_info.lut3d_property) { + ret =3D atomic_replace_property_blob_from_id(crtc->dev, + &acrtc_state->lut3d, + val, + -1, sizeof(struct drm_color_lut), + &replaced); + acrtc_state->base.color_mgmt_changed |=3D replaced; + return ret; } else { drm_dbg_atomic(crtc->dev, "[CRTC:%d:%s] unknown property [PROP:%d:%s]]\n", @@ -404,6 +421,9 @@ amdgpu_dm_atomic_crtc_get_property(struct drm_crtc *crt= c, if (property =3D=3D adev->mode_info.shaper_lut_property) *val =3D (acrtc_state->shaper_lut) ? acrtc_state->shaper_lut->base.id : 0; + else if (property =3D=3D adev->mode_info.lut3d_property) + *val =3D (acrtc_state->lut3d) ? + acrtc_state->lut3d->base.id : 0; else return -EINVAL; =20 --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5712C77B73 for ; Sun, 23 Apr 2023 14:12:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230236AbjDWOMu (ORCPT ); Sun, 23 Apr 2023 10:12:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59970 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229659AbjDWOMh (ORCPT ); Sun, 23 Apr 2023 10:12:37 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9A2D510F0 for ; Sun, 23 Apr 2023 07:12:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=wQhPhw7uUonhHv6/pWaJwwFqQGY16VHjVM8DO5hkoxs=; b=qDuXtaWPVP/TKMVjyGy+mjnaLX LxYOPVWECl+YkJA4RcDIRr3nMqDwH2ZnP6/zouD+0EZfJ+tODlPAf6VUkVFj/wj0JO9Cwsg+A0TDk ChIum3eAfJKKKfE0+RWL41Wz7gIy0BPJH8sAatZzDeU20+2Agf6Z4PNBMNTEhg7H3itGe8e2D/gVF tjLHQ8IPFDgQW4rgXvK+AcW167XXtY+Qcfdn03BoHDtUGEQEDRZGxroN6D1TCkRV0vAGZPTsRJO8f P/8X0eEh7eH+PRsl//4vMrDl47QYkSDX8QDDsr3KBcf/J0GZRWnK+Q1/lzQ7yYHwkRt8wIL83Rd87 PWJjHKSQ==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaRq-00ANVs-Bb; Sun, 23 Apr 2023 16:12:14 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 07/40] drm/amd/display: add CRTC gamma TF to driver-private props Date: Sun, 23 Apr 2023 13:10:19 -0100 Message-Id: <20230423141051.702990-8-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Joshua Ashton Add predefined transfer function property to DRM CRTC gamma to convert to wire encoding with or without gamma LUT. Co-developed-by: Melissa Wen Signed-off-by: Melissa Wen Signed-off-by: Joshua Ashton --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 22 ++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 4 ++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 23 +++++++++++++++++++ .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 13 +++++++++++ 4 files changed, 62 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/= amd/amdgpu/amdgpu_display.c index 2abe5fe87c10..1913903cab88 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1248,6 +1248,19 @@ amdgpu_display_user_framebuffer_create(struct drm_de= vice *dev, } =20 #ifdef CONFIG_STEAM_DECK +static const struct drm_prop_enum_list drm_transfer_function_enum_list[] = =3D { + { DRM_TRANSFER_FUNCTION_DEFAULT, "Default" }, + { DRM_TRANSFER_FUNCTION_SRGB, "sRGB" }, + { DRM_TRANSFER_FUNCTION_BT709, "BT.709" }, + { DRM_TRANSFER_FUNCTION_PQ, "PQ (Perceptual Quantizer)" }, + { DRM_TRANSFER_FUNCTION_LINEAR, "Linear" }, + { DRM_TRANSFER_FUNCTION_UNITY, "Unity" }, + { DRM_TRANSFER_FUNCTION_HLG, "HLG (Hybrid Log Gamma)" }, + { DRM_TRANSFER_FUNCTION_GAMMA22, "Gamma 2.2" }, + { DRM_TRANSFER_FUNCTION_GAMMA24, "Gamma 2.4" }, + { DRM_TRANSFER_FUNCTION_GAMMA26, "Gamma 2.6" }, +}; + static int amdgpu_display_create_color_properties(struct amdgpu_device *adev) { @@ -1281,6 +1294,15 @@ amdgpu_display_create_color_properties(struct amdgpu= _device *adev) return -ENOMEM; adev->mode_info.lut3d_size_property =3D prop; =20 + prop =3D drm_property_create_enum(adev_to_drm(adev), + DRM_MODE_PROP_ENUM, + "GAMMA_TF", + drm_transfer_function_enum_list, + ARRAY_SIZE(drm_transfer_function_enum_list)); + if (!prop) + return -ENOMEM; + adev->mode_info.gamma_tf_property =3D prop; + return 0; } #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd= /amdgpu/amdgpu_mode.h index 205fa4f5bea7..76337e18c728 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -368,6 +368,10 @@ struct amdgpu_mode_info { * LUT as supported by the driver (read-only). */ struct drm_property *lut3d_size_property; + /** + * @gamma_tf_property: Transfer function for CRTC regamma. + */ + struct drm_property *gamma_tf_property; #endif }; =20 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gp= u/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 09c3e1858b56..1e90a2dd445e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -699,6 +699,23 @@ static inline void amdgpu_dm_set_mst_status(uint8_t *s= tatus, =20 extern const struct amdgpu_ip_block_version dm_ip_block; =20 +#ifdef CONFIG_STEAM_DECK +enum drm_transfer_function { + DRM_TRANSFER_FUNCTION_DEFAULT, + + DRM_TRANSFER_FUNCTION_SRGB, + DRM_TRANSFER_FUNCTION_BT709, + DRM_TRANSFER_FUNCTION_PQ, + DRM_TRANSFER_FUNCTION_LINEAR, + DRM_TRANSFER_FUNCTION_UNITY, + DRM_TRANSFER_FUNCTION_HLG, + DRM_TRANSFER_FUNCTION_GAMMA22, + DRM_TRANSFER_FUNCTION_GAMMA24, + DRM_TRANSFER_FUNCTION_GAMMA26, + DRM_TRANSFER_FUNCTION_MAX, +}; +#endif + struct dm_plane_state { struct drm_plane_state base; struct dc_plane_state *dc_state; @@ -751,6 +768,12 @@ struct dm_crtc_state { * &struct drm_color_lut. */ struct drm_property_blob *lut3d; + /** + * @gamma_tf: + * + * Pre-defined transfer function for converting internal FB -> wire encod= ing. + */ + enum drm_transfer_function gamma_tf; #endif }; =20 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drive= rs/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 0e1280228e6e..79324fbab1f1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -272,6 +272,7 @@ static struct drm_crtc_state *dm_crtc_duplicate_state(s= truct drm_crtc *crtc) #ifdef CONFIG_STEAM_DECK state->shaper_lut =3D cur->shaper_lut; state->lut3d =3D cur->lut3d; + state->gamma_tf =3D cur->gamma_tf; =20 if (state->shaper_lut) drm_property_blob_get(state->shaper_lut); @@ -336,6 +337,11 @@ dm_crtc_additional_color_mgmt(struct drm_crtc *crtc) adev->mode_info.lut3d_size_property, MAX_COLOR_3DLUT_ENTRIES); } + + if(adev->dm.dc->caps.color.mpc.ogam_ram) + drm_object_attach_property(&crtc->base, + adev->mode_info.gamma_tf_property, + DRM_TRANSFER_FUNCTION_DEFAULT); } =20 static int @@ -398,6 +404,11 @@ amdgpu_dm_atomic_crtc_set_property(struct drm_crtc *cr= tc, &replaced); acrtc_state->base.color_mgmt_changed |=3D replaced; return ret; + } else if (property =3D=3D adev->mode_info.gamma_tf_property) { + if (acrtc_state->gamma_tf !=3D val) { + acrtc_state->gamma_tf =3D val; + acrtc_state->base.color_mgmt_changed |=3D 1; + } } else { drm_dbg_atomic(crtc->dev, "[CRTC:%d:%s] unknown property [PROP:%d:%s]]\n", @@ -424,6 +435,8 @@ amdgpu_dm_atomic_crtc_get_property(struct drm_crtc *crt= c, else if (property =3D=3D adev->mode_info.lut3d_property) *val =3D (acrtc_state->lut3d) ? acrtc_state->lut3d->base.id : 0; + else if (property =3D=3D adev->mode_info.gamma_tf_property) + *val =3D acrtc_state->gamma_tf; else return -EINVAL; =20 --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F5B0C77B73 for ; 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b=NE7h2Ttlh5qeOufFgjOAuj/G/N Mp6FYLx78siblzVP66SdNvhoMEkWQ379KPdDVm0g22cVo3yC2oVgwcWaAOKs0kES8gdUaEdDAQkgg V6yplEEC6zaGkUnK/2AgU29axB7rlQcYjd01O06TNsIV4vq4TZT47+NuBevfCZJol5rhmHj1TWXDW GHguQtOBF2nekb6b5BIEwirgX4fRh0Zb32PiIy9cfpdenPEwYT+PTtOdHUgWzGk09qAv2wlaCq2Qh pokXGbQZnEL1lyjypEfC/ZJ/W283j3F7NOzsO/t32qIyViHQKcHjeTF1QBiZTCW/8LHsR+3Q1Vr3p sMXro7iA==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaRv-00ANVs-Ak; Sun, 23 Apr 2023 16:12:19 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 08/40] drm/drm_plane: track color mgmt changes per plane Date: Sun, 23 Apr 2023 13:10:20 -0100 Message-Id: <20230423141051.702990-9-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We will add color mgmt properties to DRM planes in the text patches and we want to track when one of this properties change to define atomic commit behaviors. Using a similar approach from CRTC color props, we set a color_mgmt_changed boolean whenever a plane color prop changes. Signed-off-by: Melissa Wen --- drivers/gpu/drm/drm_atomic.c | 1 + drivers/gpu/drm/drm_atomic_state_helper.c | 1 + include/drm/drm_plane.h | 7 +++++++ 3 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index c0dc5858a723..da2429470c4f 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -724,6 +724,7 @@ static void drm_atomic_plane_print_state(struct drm_pri= nter *p, drm_get_color_encoding_name(state->color_encoding)); drm_printf(p, "\tcolor-range=3D%s\n", drm_get_color_range_name(state->color_range)); + drm_printf(p, "\tcolor_mgmt_changed=3D%d\n", state->color_mgmt_changed); =20 if (plane->funcs->atomic_print_state) plane->funcs->atomic_print_state(p, state); diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/dr= m_atomic_state_helper.c index dfb57217253b..3df4c96a902e 100644 --- a/drivers/gpu/drm/drm_atomic_state_helper.c +++ b/drivers/gpu/drm/drm_atomic_state_helper.c @@ -338,6 +338,7 @@ void __drm_atomic_helper_plane_duplicate_state(struct d= rm_plane *plane, state->fence =3D NULL; state->commit =3D NULL; state->fb_damage_clips =3D NULL; + state->color_mgmt_changed =3D false; } EXPORT_SYMBOL(__drm_atomic_helper_plane_duplicate_state); =20 diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index 447e664e49d5..6c97380b8c76 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -237,6 +237,13 @@ struct drm_plane_state { =20 /** @state: backpointer to global drm_atomic_state */ struct drm_atomic_state *state; + + /** + * @color_mgmt_changed: Color management properties have changed. Used + * by the atomic helpers and drivers to steer the atomic commit control + * flow. + */ + bool color_mgmt_changed : 1; }; =20 static inline struct drm_rect --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31804C77B76 for ; Sun, 23 Apr 2023 14:13:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229479AbjDWONV (ORCPT ); Sun, 23 Apr 2023 10:13:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60738 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230231AbjDWONP (ORCPT ); Sun, 23 Apr 2023 10:13:15 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 01FAA2D77 for ; Sun, 23 Apr 2023 07:12:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=bS6ARIRzUtaQuNYcssnwhazUAE6VKWzVlbrPhB85lac=; b=LvGgwT2aOKaiVCropiT6vlCv5G t6mr873f067uJixAtakqOAr0rinkoh4+slU7QUIS4RwxRmgC5QgXf5xUOPza0V78koaCEyGleHuH1 j8D6vxWXxhZhAVCiMX51iACPk6n2eTWw6ANiZvbi1DDueil+9x/z/Goh7xnEwcRI7KtyyU5JAl3I1 5gz6BGH8GY/9Ug2PK0EVINTW2oB6emz+Nm5M4Mkw2RGwja6gG6BYryutmeZ3UdVCLLznAYxclZ1Ql CzY26Gi6ulrom1gDv1BwTeBWhRjqNZkTCd7hkRrFlPmey/Fkf/7p52nRfMNSFSvqA9NQEi8lX8m9W +5OwixHA==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaS0-00ANVs-Mu; Sun, 23 Apr 2023 16:12:24 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 09/40] drm/amd/display: move replace blob func to dm plane Date: Sun, 23 Apr 2023 13:10:21 -0100 Message-Id: <20230423141051.702990-10-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From amdgpu_dm_plane we can get it for both CRTC and plane color properties. We are adding new plane properties for AMD driver-private color mgmt. Signed-off-by: Melissa Wen --- .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 37 +------------------ .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 35 ++++++++++++++++++ .../amd/display/amdgpu_dm/amdgpu_dm_plane.h | 7 ++++ 3 files changed, 44 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drive= rs/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 79324fbab1f1..27d7a8b18013 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -344,39 +344,6 @@ dm_crtc_additional_color_mgmt(struct drm_crtc *crtc) DRM_TRANSFER_FUNCTION_DEFAULT); } =20 -static int -atomic_replace_property_blob_from_id(struct drm_device *dev, - struct drm_property_blob **blob, - uint64_t blob_id, - ssize_t expected_size, - ssize_t expected_elem_size, - bool *replaced) -{ - struct drm_property_blob *new_blob =3D NULL; - - if (blob_id !=3D 0) { - new_blob =3D drm_property_lookup_blob(dev, blob_id); - if (new_blob =3D=3D NULL) - return -EINVAL; - - if (expected_size > 0 && - new_blob->length !=3D expected_size) { - drm_property_blob_put(new_blob); - return -EINVAL; - } - if (expected_elem_size > 0 && - new_blob->length % expected_elem_size !=3D 0) { - drm_property_blob_put(new_blob); - return -EINVAL; - } - } - - *replaced |=3D drm_property_replace_blob(blob, new_blob); - drm_property_blob_put(new_blob); - - return 0; -} - static int amdgpu_dm_atomic_crtc_set_property(struct drm_crtc *crtc, struct drm_crtc_state *state, @@ -389,7 +356,7 @@ amdgpu_dm_atomic_crtc_set_property(struct drm_crtc *crt= c, int ret; =20 if (property =3D=3D adev->mode_info.shaper_lut_property) { - ret =3D atomic_replace_property_blob_from_id(crtc->dev, + ret =3D amdgpu_dm_replace_property_blob_from_id(crtc->dev, &acrtc_state->shaper_lut, val, -1, sizeof(struct drm_color_lut), @@ -397,7 +364,7 @@ amdgpu_dm_atomic_crtc_set_property(struct drm_crtc *crt= c, acrtc_state->base.color_mgmt_changed |=3D replaced; return ret; } else if (property =3D=3D adev->mode_info.lut3d_property) { - ret =3D atomic_replace_property_blob_from_id(crtc->dev, + ret =3D amdgpu_dm_replace_property_blob_from_id(crtc->dev, &acrtc_state->lut3d, val, -1, sizeof(struct drm_color_lut), diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/driv= ers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 322668973747..4e5498153be2 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1411,6 +1411,41 @@ static void dm_drm_plane_destroy_state(struct drm_pl= ane *plane, drm_atomic_helper_plane_destroy_state(plane, state); } =20 +#ifdef CONFIG_STEAM_DECK +int +amdgpu_dm_replace_property_blob_from_id(struct drm_device *dev, + struct drm_property_blob **blob, + uint64_t blob_id, + ssize_t expected_size, + ssize_t expected_elem_size, + bool *replaced) +{ + struct drm_property_blob *new_blob =3D NULL; + + if (blob_id !=3D 0) { + new_blob =3D drm_property_lookup_blob(dev, blob_id); + if (new_blob =3D=3D NULL) + return -EINVAL; + + if (expected_size > 0 && + new_blob->length !=3D expected_size) { + drm_property_blob_put(new_blob); + return -EINVAL; + } + if (expected_elem_size > 0 && + new_blob->length % expected_elem_size !=3D 0) { + drm_property_blob_put(new_blob); + return -EINVAL; + } + } + + *replaced |=3D drm_property_replace_blob(blob, new_blob); + drm_property_blob_put(new_blob); + + return 0; +} +#endif + static const struct drm_plane_funcs dm_plane_funcs =3D { .update_plane =3D drm_atomic_helper_update_plane, .disable_plane =3D drm_atomic_helper_disable_plane, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h b/driv= ers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h index 930f1572f898..1b05ac4c15f6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h @@ -51,6 +51,13 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct = amdgpu_device *adev, bool tmz_surface, bool force_disable_dcc); =20 +int amdgpu_dm_replace_property_blob_from_id(struct drm_device *dev, + struct drm_property_blob **blob, + uint64_t blob_id, + ssize_t expected_size, + ssize_t expected_elem_size, + bool *replaced); + int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, struct drm_plane *plane, unsigned long possible_crtcs, --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC16FC77B76 for ; Sun, 23 Apr 2023 14:13:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229623AbjDWONb (ORCPT ); Sun, 23 Apr 2023 10:13:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229749AbjDWONX (ORCPT ); Sun, 23 Apr 2023 10:13:23 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C90B91FDF for ; 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Sun, 23 Apr 2023 16:12:27 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 10/40] drm/amd/display: add plane degamma LUT driver-private props Date: Sun, 23 Apr 2023 13:10:22 -0100 Message-Id: <20230423141051.702990-11-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Joshua Ashton Create driver-private properties (not DRM KMS generic) for plane degamma LUT (user-blob and its size). Co-developed-by: Melissa Wen Signed-off-by: Melissa Wen Signed-off-by: Joshua Ashton --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 14 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 10 +++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 11 +++ .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 78 ++++++++++++++++++- 4 files changed, 111 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/= amd/amdgpu/amdgpu_display.c index 1913903cab88..996c9c3fd471 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1303,6 +1303,20 @@ amdgpu_display_create_color_properties(struct amdgpu= _device *adev) return -ENOMEM; adev->mode_info.gamma_tf_property =3D prop; =20 + prop =3D drm_property_create(adev_to_drm(adev), + DRM_MODE_PROP_BLOB, + "AMD_PLANE_DEGAMMA_LUT", 0); + if (!prop) + return -ENOMEM; + adev->mode_info.plane_degamma_lut_property =3D prop; + + prop =3D drm_property_create_range(adev_to_drm(adev), + DRM_MODE_PROP_IMMUTABLE, + "AMD_PLANE_DEGAMMA_LUT_SIZE", 0, UINT_MAX); + if (!prop) + return -ENOMEM; + adev->mode_info.plane_degamma_lut_size_property =3D prop; + return 0; } #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd= /amdgpu/amdgpu_mode.h index 76337e18c728..d4e609a8b67e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -372,6 +372,16 @@ struct amdgpu_mode_info { * @gamma_tf_property: Transfer function for CRTC regamma. */ struct drm_property *gamma_tf_property; + /** + * @plane_degamma_lut_property: Plane property to set a degamma LUT to + * convert color space before blending. + */ + struct drm_property *plane_degamma_lut_property; + /** + * @plane_degamma_lut_size_property: Plane property to define the max + * size of degamma LUT as supported by the driver (read-only). + */ + struct drm_property *plane_degamma_lut_size_property; #endif }; =20 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gp= u/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 1e90a2dd445e..b1d0c65d821d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -719,6 +719,17 @@ enum drm_transfer_function { struct dm_plane_state { struct drm_plane_state base; struct dc_plane_state *dc_state; + +#ifdef CONFIG_STEAM_DECK + /* Plane color mgmt */ + /** + * @degamma_lut: + * + * LUT for converting plane pixel data before going into plane merger. + * The blob (if not NULL) is an array of &struct drm_color_lut. + */ + struct drm_property_blob *degamma_lut; +#endif }; =20 struct dm_crtc_state { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/driv= ers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 4e5498153be2..7b9d62c70b30 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1337,7 +1337,10 @@ dm_drm_plane_duplicate_state(struct drm_plane *plane) dm_plane_state->dc_state =3D old_dm_plane_state->dc_state; dc_plane_state_retain(dm_plane_state->dc_state); } - +#ifdef CONFIG_STEAM_DECK + if (dm_plane_state->degamma_lut) + drm_property_blob_get(dm_plane_state->degamma_lut); +#endif return &dm_plane_state->base; } =20 @@ -1404,7 +1407,9 @@ static void dm_drm_plane_destroy_state(struct drm_pla= ne *plane, struct drm_plane_state *state) { struct dm_plane_state *dm_plane_state =3D to_dm_plane_state(state); - +#ifdef CONFIG_STEAM_DECK + drm_property_blob_put(dm_plane_state->degamma_lut); +#endif if (dm_plane_state->dc_state) dc_plane_state_release(dm_plane_state->dc_state); =20 @@ -1444,6 +1449,68 @@ amdgpu_dm_replace_property_blob_from_id(struct drm_d= evice *dev, =20 return 0; } + +static void +dm_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm, + struct drm_plane *plane) +{ + if (dm->dc->caps.color.dpp.dgam_ram || dm->dc->caps.color.dpp.gamma_corr = ) { + drm_object_attach_property(&plane->base, + dm->adev->mode_info.plane_degamma_lut_property, 0); + drm_object_attach_property(&plane->base, + dm->adev->mode_info.plane_degamma_lut_size_property, + MAX_COLOR_LUT_ENTRIES); + } +} + +static int +dm_atomic_plane_set_property(struct drm_plane *plane, + struct drm_plane_state *state, + struct drm_property *property, uint64_t val) +{ + struct dm_plane_state *dm_plane_state =3D to_dm_plane_state(state); + struct amdgpu_device *adev =3D drm_to_adev(plane->dev); + bool replaced =3D false; + int ret; + + if (property =3D=3D adev->mode_info.plane_degamma_lut_property) { + ret =3D amdgpu_dm_replace_property_blob_from_id(plane->dev, + &dm_plane_state->degamma_lut, + val, + -1, sizeof(struct drm_color_lut), + &replaced); + dm_plane_state->base.color_mgmt_changed |=3D replaced; + return ret; + } else { + drm_dbg_atomic(plane->dev, + "[PLANE:%d:%s] unknown property [PROP:%d:%s]]\n", + plane->base.id, plane->name, + property->base.id, property->name); + return -EINVAL; + } + + return 0; +} + +static int +dm_atomic_plane_get_property(struct drm_plane *plane, + const struct drm_plane_state *state, + struct drm_property *property, + uint64_t *val) + +{ + struct dm_plane_state *dm_plane_state =3D to_dm_plane_state(state); + struct amdgpu_device *adev =3D drm_to_adev(plane->dev); + + if (property =3D=3D adev->mode_info.plane_degamma_lut_property) { + *val =3D (dm_plane_state->degamma_lut) ? + dm_plane_state->degamma_lut->base.id : 0; + } else { + return -EINVAL; + } + + return 0; +} #endif =20 static const struct drm_plane_funcs dm_plane_funcs =3D { @@ -1454,6 +1521,10 @@ static const struct drm_plane_funcs dm_plane_funcs = =3D { .atomic_duplicate_state =3D dm_drm_plane_duplicate_state, .atomic_destroy_state =3D dm_drm_plane_destroy_state, .format_mod_supported =3D dm_plane_format_mod_supported, +#ifdef CONFIG_STEAM_DECK + .atomic_set_property =3D dm_atomic_plane_set_property, + .atomic_get_property =3D dm_atomic_plane_get_property, +#endif }; =20 int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, @@ -1524,6 +1595,9 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manage= r *dm, =20 drm_plane_helper_add(plane, &dm_plane_helper_funcs); =20 +#ifdef CONFIG_STEAM_DECK + dm_plane_attach_color_mgmt_properties(dm, plane); +#endif /* Create (reset) the plane state */ if (plane->funcs->reset) plane->funcs->reset(plane); --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9F53C77B78 for ; Sun, 23 Apr 2023 14:13:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230045AbjDWONd (ORCPT ); Sun, 23 Apr 2023 10:13:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32856 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230244AbjDWON3 (ORCPT ); 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Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaS7-00ANVs-22; Sun, 23 Apr 2023 16:12:31 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , linux-kernel@vger.kernel.org Subject: [RFC PATCH 11/40] drm/amd/display: add plane degamma TF driver-private property Date: Sun, 23 Apr 2023 13:10:23 -0100 Message-Id: <20230423141051.702990-12-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Joshua Ashton Allow userspace to tell the kernel driver the input space and, therefore, uses correct predefined transfer function (TF) to delinearize content with or without LUT (using hardcoded curve caps). Signed-off-by: Joshua Ashton --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 9 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 5 ++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 7 +++++ .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 28 +++++++++++++++++++ 4 files changed, 49 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/= amd/amdgpu/amdgpu_display.c index 996c9c3fd471..24595906dab1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1317,6 +1317,15 @@ amdgpu_display_create_color_properties(struct amdgpu= _device *adev) return -ENOMEM; adev->mode_info.plane_degamma_lut_size_property =3D prop; =20 + prop =3D drm_property_create_enum(adev_to_drm(adev), + DRM_MODE_PROP_ENUM, + "AMD_PLANE_DEGAMMA_TF", + drm_transfer_function_enum_list, + ARRAY_SIZE(drm_transfer_function_enum_list)); + if (!prop) + return -ENOMEM; + adev->mode_info.plane_degamma_tf_property =3D prop; + return 0; } #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd= /amdgpu/amdgpu_mode.h index d4e609a8b67e..ab9ce6f26c90 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -382,6 +382,11 @@ struct amdgpu_mode_info { * size of degamma LUT as supported by the driver (read-only). */ struct drm_property *plane_degamma_lut_size_property; + /** + * @plane_degamma_tf_property: Predefined transfer function to + * linearize content with or without LUT. + */ + struct drm_property *plane_degamma_tf_property; #endif }; =20 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gp= u/drm/amd/display/amdgpu_dm/amdgpu_dm.h index b1d0c65d821d..005632c1c9ec 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -729,6 +729,13 @@ struct dm_plane_state { * The blob (if not NULL) is an array of &struct drm_color_lut. */ struct drm_property_blob *degamma_lut; + /** + * @degamma_tf: + * + * Predefined transfer function to tell DC driver the input space to + * linearize. + */ + enum drm_transfer_function degamma_tf; #endif }; =20 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/driv= ers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 7b9d62c70b30..5b458cc0781c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1319,6 +1319,11 @@ static void dm_drm_plane_reset(struct drm_plane *pla= ne) =20 if (amdgpu_state) __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base); + +#ifdef CONFIG_STEAM_DECK + if (amdgpu_state) + amdgpu_state->degamma_tf =3D DRM_TRANSFER_FUNCTION_DEFAULT; +#endif } =20 static struct drm_plane_state * @@ -1450,6 +1455,19 @@ amdgpu_dm_replace_property_blob_from_id(struct drm_d= evice *dev, return 0; } =20 +static const struct drm_prop_enum_list drm_transfer_function_enum_list[] = =3D { + { DRM_TRANSFER_FUNCTION_DEFAULT, "Default" }, + { DRM_TRANSFER_FUNCTION_SRGB, "sRGB" }, + { DRM_TRANSFER_FUNCTION_BT709, "BT.709" }, + { DRM_TRANSFER_FUNCTION_PQ, "PQ (Perceptual Quantizer)" }, + { DRM_TRANSFER_FUNCTION_LINEAR, "Linear" }, + { DRM_TRANSFER_FUNCTION_UNITY, "Unity" }, + { DRM_TRANSFER_FUNCTION_HLG, "HLG (Hybrid Log Gamma)" }, + { DRM_TRANSFER_FUNCTION_GAMMA22, "Gamma 2.2" }, + { DRM_TRANSFER_FUNCTION_GAMMA24, "Gamma 2.4" }, + { DRM_TRANSFER_FUNCTION_GAMMA26, "Gamma 2.6" }, +}; + static void dm_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm, struct drm_plane *plane) @@ -1460,6 +1478,9 @@ dm_plane_attach_color_mgmt_properties(struct amdgpu_d= isplay_manager *dm, drm_object_attach_property(&plane->base, dm->adev->mode_info.plane_degamma_lut_size_property, MAX_COLOR_LUT_ENTRIES); + drm_object_attach_property(&plane->base, + dm->adev->mode_info.plane_degamma_tf_property, + DRM_TRANSFER_FUNCTION_DEFAULT); } } =20 @@ -1481,6 +1502,11 @@ dm_atomic_plane_set_property(struct drm_plane *plane, &replaced); dm_plane_state->base.color_mgmt_changed |=3D replaced; return ret; + } else if (property =3D=3D adev->mode_info.plane_degamma_tf_property) { + if (dm_plane_state->degamma_tf !=3D val) { + dm_plane_state->degamma_tf =3D val; + dm_plane_state->base.color_mgmt_changed =3D 1; + } } else { drm_dbg_atomic(plane->dev, "[PLANE:%d:%s] unknown property [PROP:%d:%s]]\n", @@ -1505,6 +1531,8 @@ dm_atomic_plane_get_property(struct drm_plane *plane, if (property =3D=3D adev->mode_info.plane_degamma_lut_property) { *val =3D (dm_plane_state->degamma_lut) ? dm_plane_state->degamma_lut->base.id : 0; + } else if (property =3D=3D adev->mode_info.plane_degamma_tf_property) { + *val =3D dm_plane_state->degamma_tf; } else { return -EINVAL; } --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 629BAC77B60 for ; Sun, 23 Apr 2023 14:14:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229782AbjDWOOG (ORCPT ); Sun, 23 Apr 2023 10:14:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33454 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229619AbjDWOOD (ORCPT ); Sun, 23 Apr 2023 10:14:03 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D355330FE for ; Sun, 23 Apr 2023 07:13:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=mNxdNED6L3HES4VBefAtsG63OTHIZrslESDcQiiim+M=; b=gmOQ3q2nfwj0Oz9By8BoODLpBY nlWFvAuX/nCjrsoRwqBnOvu2066ZTKBbV1SErilbIPPRLrxBtV/KWPbid0GMIyO0efOPS2r9whq0A zJStCM0vdyqfTIqe/n3FV9tKSV0Za4BhoTjefXnGciV3+7B4cIVtyUf4ZbL3mD5bi+9yctwQHIEfJ n9rskomfSRZN28dlPi6qFZPvlKXDWiYCorGwQblxgtaBjG22jhYjdJ3T/Y83k66Nf0wQ6tDd5VRv+ /WmFasbZZ6REAydvn3Edv4Yoeoc1HzxVBaY/iWeNkA2aCk9I39lVyGQ7bW1YmWLYStAvpVPKJJy65 k3LsJHwA==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaSA-00ANVs-GB; Sun, 23 Apr 2023 16:12:34 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 12/40] drm/amd/display: add plane HDR multiplier driver-private property Date: Sun, 23 Apr 2023 13:10:24 -0100 Message-Id: <20230423141051.702990-13-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Joshua Ashton Multiplier to 'gain' the plane. When PQ is decoded using the fixed func transfer function to the internal FP16 fb, 1.0 -> 80 nits (on AMD at least) When sRGB is decoded, 1.0 -> 1.0. Therefore, 1.0 multiplier =3D 80 nits for SDR content. So if you want, 203 nits for SDR content, pass in (203.0 / 80.0). Co-developed-by: Melissa Wen Signed-off-by: Melissa Wen Signed-off-by: Joshua Ashton --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 6 +++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 4 +++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 12 +++++++++ .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 25 ++++++++++++++----- 4 files changed, 41 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/= amd/amdgpu/amdgpu_display.c index 24595906dab1..dd658f162f6f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1326,6 +1326,12 @@ amdgpu_display_create_color_properties(struct amdgpu= _device *adev) return -ENOMEM; adev->mode_info.plane_degamma_tf_property =3D prop; =20 + prop =3D drm_property_create_range(adev_to_drm(adev), + 0, "AMD_PLANE_HDR_MULT", 0, UINT_MAX); + if (!prop) + return -ENOMEM; + adev->mode_info.plane_hdr_mult_property =3D prop; + return 0; } #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd= /amdgpu/amdgpu_mode.h index ab9ce6f26c90..65a9d62ffbe4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -387,6 +387,10 @@ struct amdgpu_mode_info { * linearize content with or without LUT. */ struct drm_property *plane_degamma_tf_property; + /** + * @plane_hdr_mult_property: + */ + struct drm_property *plane_hdr_mult_property; #endif }; =20 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gp= u/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 005632c1c9ec..bb7307b9cfd5 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -51,6 +51,7 @@ =20 #define AMDGPU_DMUB_NOTIFICATION_MAX 5 =20 +#define AMDGPU_HDR_MULT_DEFAULT (0x100000000LL) /* #include "include/amdgpu_dal_power_if.h" #include "amdgpu_dm_irq.h" @@ -736,6 +737,17 @@ struct dm_plane_state { * linearize. */ enum drm_transfer_function degamma_tf; + /** + * @hdr_mult: + * + * Multiplier to 'gain' the plane. When PQ is decoded using the fixed + * func transfer function to the internal FP16 fb, 1.0 -> 80 nits (on + * AMD at least). When sRGB is decoded, 1.0 -> 1.0, obviously. + * Therefore, 1.0 multiplier =3D 80 nits for SDR content. So if you + * want, 203 nits for SDR content, pass in (203.0 / 80.0). Format is + * S31.32 sign-magnitude. + */ + __u64 hdr_mult; #endif }; =20 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/driv= ers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 5b458cc0781c..57169dae8b3d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1321,8 +1321,10 @@ static void dm_drm_plane_reset(struct drm_plane *pla= ne) __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base); =20 #ifdef CONFIG_STEAM_DECK - if (amdgpu_state) + if (amdgpu_state) { amdgpu_state->degamma_tf =3D DRM_TRANSFER_FUNCTION_DEFAULT; + amdgpu_state->hdr_mult =3D AMDGPU_HDR_MULT_DEFAULT; + } #endif } =20 @@ -1424,11 +1426,11 @@ static void dm_drm_plane_destroy_state(struct drm_p= lane *plane, #ifdef CONFIG_STEAM_DECK int amdgpu_dm_replace_property_blob_from_id(struct drm_device *dev, - struct drm_property_blob **blob, - uint64_t blob_id, - ssize_t expected_size, - ssize_t expected_elem_size, - bool *replaced) + struct drm_property_blob **blob, + uint64_t blob_id, + ssize_t expected_size, + ssize_t expected_elem_size, + bool *replaced) { struct drm_property_blob *new_blob =3D NULL; =20 @@ -1482,6 +1484,10 @@ dm_plane_attach_color_mgmt_properties(struct amdgpu_= display_manager *dm, dm->adev->mode_info.plane_degamma_tf_property, DRM_TRANSFER_FUNCTION_DEFAULT); } + /* HDR MULT is always available */ + drm_object_attach_property(&plane->base, + dm->adev->mode_info.plane_hdr_mult_property, + AMDGPU_HDR_MULT_DEFAULT); } =20 static int @@ -1507,6 +1513,11 @@ dm_atomic_plane_set_property(struct drm_plane *plane, dm_plane_state->degamma_tf =3D val; dm_plane_state->base.color_mgmt_changed =3D 1; } + } else if (property =3D=3D adev->mode_info.plane_hdr_mult_property) { + if (dm_plane_state->hdr_mult !=3D val) { + dm_plane_state->hdr_mult =3D val; + dm_plane_state->base.color_mgmt_changed =3D 1; + } } else { drm_dbg_atomic(plane->dev, "[PLANE:%d:%s] unknown property [PROP:%d:%s]]\n", @@ -1533,6 +1544,8 @@ dm_atomic_plane_get_property(struct drm_plane *plane, dm_plane_state->degamma_lut->base.id : 0; } else if (property =3D=3D adev->mode_info.plane_degamma_tf_property) { *val =3D dm_plane_state->degamma_tf; + } else if (property =3D=3D adev->mode_info.plane_hdr_mult_property) { + *val =3D dm_plane_state->hdr_mult; } else { return -EINVAL; } --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02484C6FD18 for ; Sun, 23 Apr 2023 14:49:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230424AbjDWOtp (ORCPT ); Sun, 23 Apr 2023 10:49:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56032 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230239AbjDWOtn (ORCPT ); Sun, 23 Apr 2023 10:49:43 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 180221BE5 for ; Sun, 23 Apr 2023 07:49:26 -0700 (PDT) DKIM-Signature: v=1; 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Sun, 23 Apr 2023 16:12:39 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 13/40] drm/amd/display: add plane 3D LUT driver-private properties Date: Sun, 23 Apr 2023 13:10:25 -0100 Message-Id: <20230423141051.702990-14-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add 3D LUT property for plane gamma correction using a 3D lookup table. 3D LUT is more effective when applying in non-linear space, therefore, userpace may need one 1D LUT (shaper) before it to delinearize content and another 1D LUT after 3D LUT (blend) to linearize content again for blending. The next patches add these 1D LUTs to the plane color mgmt pipeline. Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 14 +++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 10 ++++++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 5 ++++ .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 24 +++++++++++++++++++ 4 files changed, 53 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/= amd/amdgpu/amdgpu_display.c index dd658f162f6f..8d4726978c6e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1332,6 +1332,20 @@ amdgpu_display_create_color_properties(struct amdgpu= _device *adev) return -ENOMEM; adev->mode_info.plane_hdr_mult_property =3D prop; =20 + prop =3D drm_property_create(adev_to_drm(adev), + DRM_MODE_PROP_BLOB, + "AMD_PLANE_LUT3D", 0); + if (!prop) + return -ENOMEM; + adev->mode_info.plane_lut3d_property =3D prop; + + prop =3D drm_property_create_range(adev_to_drm(adev), + DRM_MODE_PROP_IMMUTABLE, + "AMD_PLANE_LUT3D_SIZE", 0, UINT_MAX); + if (!prop) + return -ENOMEM; + adev->mode_info.plane_lut3d_size_property =3D prop; + return 0; } #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd= /amdgpu/amdgpu_mode.h index 65a9d62ffbe4..9d9dac26edfc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -391,6 +391,16 @@ struct amdgpu_mode_info { * @plane_hdr_mult_property: */ struct drm_property *plane_hdr_mult_property; + /** + * @plane_lut3d_property: Plane property for gamma correction using a + * 3D LUT (pre-blending). + */ + struct drm_property *plane_lut3d_property; + /** + * @plane_degamma_lut_size_property: Plane property to define the max + * size of 3D LUT as supported by the driver (read-only). + */ + struct drm_property *plane_lut3d_size_property; #endif }; =20 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gp= u/drm/amd/display/amdgpu_dm/amdgpu_dm.h index bb7307b9cfd5..b0ba0279dc25 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -748,6 +748,11 @@ struct dm_plane_state { * S31.32 sign-magnitude. */ __u64 hdr_mult; + /** + * @lut3d: 3D lookup table blob. The blob (if not NULL) is an array of + * &struct drm_color_lut. + */ + struct drm_property_blob *lut3d; #endif }; =20 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/driv= ers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 57169dae8b3d..0e418e161b0b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1347,7 +1347,10 @@ dm_drm_plane_duplicate_state(struct drm_plane *plane) #ifdef CONFIG_STEAM_DECK if (dm_plane_state->degamma_lut) drm_property_blob_get(dm_plane_state->degamma_lut); + if (dm_plane_state->lut3d) + drm_property_blob_get(dm_plane_state->lut3d); #endif + return &dm_plane_state->base; } =20 @@ -1416,7 +1419,9 @@ static void dm_drm_plane_destroy_state(struct drm_pla= ne *plane, struct dm_plane_state *dm_plane_state =3D to_dm_plane_state(state); #ifdef CONFIG_STEAM_DECK drm_property_blob_put(dm_plane_state->degamma_lut); + drm_property_blob_put(dm_plane_state->lut3d); #endif + if (dm_plane_state->dc_state) dc_plane_state_release(dm_plane_state->dc_state); =20 @@ -1488,6 +1493,14 @@ dm_plane_attach_color_mgmt_properties(struct amdgpu_= display_manager *dm, drm_object_attach_property(&plane->base, dm->adev->mode_info.plane_hdr_mult_property, AMDGPU_HDR_MULT_DEFAULT); + + if (dm->dc->caps.color.dpp.hw_3d_lut) { + drm_object_attach_property(&plane->base, + dm->adev->mode_info.plane_lut3d_property, 0); + drm_object_attach_property(&plane->base, + dm->adev->mode_info.plane_lut3d_size_property, + MAX_COLOR_3DLUT_ENTRIES); + } } =20 static int @@ -1518,6 +1531,14 @@ dm_atomic_plane_set_property(struct drm_plane *plane, dm_plane_state->hdr_mult =3D val; dm_plane_state->base.color_mgmt_changed =3D 1; } + } else if (property =3D=3D adev->mode_info.plane_lut3d_property) { + ret =3D amdgpu_dm_replace_property_blob_from_id(plane->dev, + &dm_plane_state->lut3d, + val, + -1, sizeof(struct drm_color_lut), + &replaced); + dm_plane_state->base.color_mgmt_changed |=3D replaced; + return ret; } else { drm_dbg_atomic(plane->dev, "[PLANE:%d:%s] unknown property [PROP:%d:%s]]\n", @@ -1546,6 +1567,9 @@ dm_atomic_plane_get_property(struct drm_plane *plane, *val =3D dm_plane_state->degamma_tf; } else if (property =3D=3D adev->mode_info.plane_hdr_mult_property) { *val =3D dm_plane_state->hdr_mult; + } else if (property =3D=3D adev->mode_info.plane_lut3d_property) { + *val =3D (dm_plane_state->lut3d) ? + dm_plane_state->lut3d->base.id : 0; } else { return -EINVAL; } --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25C5DC77B60 for ; Sun, 23 Apr 2023 14:50:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230478AbjDWOuD (ORCPT ); Sun, 23 Apr 2023 10:50:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230239AbjDWOt6 (ORCPT ); Sun, 23 Apr 2023 10:49:58 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F6F310E4 for ; Sun, 23 Apr 2023 07:49:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=6Ff9ArTJlhjOrz4Iyf2wgXUbGoNJsvmn8LGUWU50kvw=; b=kV82mWIjR+T/0TKTIHkNnso9y1 pj9TQUgP3KcKJTCLphT77F1zJ7XCv+tM2Ln5BULPV5hM/o+XqRkbY290rR5HQeg8QupGrJ5T9SOxp aNfGmJjQR/J3Pex79r/KaRVMGsMNh5jW2U+Kd5ui2gQ9VDDGyMqpKS0xmtlCpC6xaMAmdaggoZcLI mPZ4gVBBRNXQ7p72uO7m/mSBlsvcHHM4wDATqFzcQZc1Ax3Yi/fDQyNKfbFAQlcKPwvfLjhqNmneb yzAimWQG2DZaqeBAl0usp35JnkWNK2b7J1/wCocyiAlqss+4MLIuAvT9tLPKLZfICsRLbiC66PRjh GRpPLsLQ==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaSI-00ANVs-Vu; Sun, 23 Apr 2023 16:12:43 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 14/40] drm/amd/display: add plane shaper LUT driver-private properties Date: Sun, 23 Apr 2023 13:10:26 -0100 Message-Id: <20230423141051.702990-15-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Shaper 1D LUT delinearizes content before applying 3D LUT so that, it comes before 3D LUT. It's an optional property and drivers should attach it according to HW caps. Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 14 ++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 10 ++++++++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 5 +++++ .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 19 +++++++++++++++++++ 4 files changed, 48 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/= amd/amdgpu/amdgpu_display.c index 8d4726978c6e..f41406ee96ad 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1332,6 +1332,20 @@ amdgpu_display_create_color_properties(struct amdgpu= _device *adev) return -ENOMEM; adev->mode_info.plane_hdr_mult_property =3D prop; =20 + prop =3D drm_property_create(adev_to_drm(adev), + DRM_MODE_PROP_BLOB, + "AMD_PLANE_SHAPER_LUT", 0); + if (!prop) + return -ENOMEM; + adev->mode_info.plane_shaper_lut_property =3D prop; + + prop =3D drm_property_create_range(adev_to_drm(adev), + DRM_MODE_PROP_IMMUTABLE, + "AMD_PLANE_SHAPER_LUT_SIZE", 0, UINT_MAX); + if (!prop) + return -ENOMEM; + adev->mode_info.plane_shaper_lut_size_property =3D prop; + prop =3D drm_property_create(adev_to_drm(adev), DRM_MODE_PROP_BLOB, "AMD_PLANE_LUT3D", 0); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd= /amdgpu/amdgpu_mode.h index 9d9dac26edfc..756d5f70be0a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -391,6 +391,16 @@ struct amdgpu_mode_info { * @plane_hdr_mult_property: */ struct drm_property *plane_hdr_mult_property; + /** + * @shaper_lut_property: Plane property to set pre-blending shaper LUT + * that converts color content before 3D LUT. + */ + struct drm_property *plane_shaper_lut_property; + /** + * @shaper_lut_size_property: Plane property for the size of + * pre-blending shaper LUT as supported by the driver (read-only). + */ + struct drm_property *plane_shaper_lut_size_property; /** * @plane_lut3d_property: Plane property for gamma correction using a * 3D LUT (pre-blending). diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gp= u/drm/amd/display/amdgpu_dm/amdgpu_dm.h index b0ba0279dc25..d3ecc73129ff 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -748,6 +748,11 @@ struct dm_plane_state { * S31.32 sign-magnitude. */ __u64 hdr_mult; + /** + * @shaper_lut: shaper lookup table blob. The blob (if not NULL) is an + * array of &struct drm_color_lut. + */ + struct drm_property_blob *shaper_lut; /** * @lut3d: 3D lookup table blob. The blob (if not NULL) is an array of * &struct drm_color_lut. diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/driv= ers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 0e418e161b0b..69e2f1f86cce 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1347,6 +1347,8 @@ dm_drm_plane_duplicate_state(struct drm_plane *plane) #ifdef CONFIG_STEAM_DECK if (dm_plane_state->degamma_lut) drm_property_blob_get(dm_plane_state->degamma_lut); + if (dm_plane_state->shaper_lut) + drm_property_blob_get(dm_plane_state->shaper_lut); if (dm_plane_state->lut3d) drm_property_blob_get(dm_plane_state->lut3d); #endif @@ -1419,6 +1421,7 @@ static void dm_drm_plane_destroy_state(struct drm_pla= ne *plane, struct dm_plane_state *dm_plane_state =3D to_dm_plane_state(state); #ifdef CONFIG_STEAM_DECK drm_property_blob_put(dm_plane_state->degamma_lut); + drm_property_blob_put(dm_plane_state->shaper_lut); drm_property_blob_put(dm_plane_state->lut3d); #endif =20 @@ -1495,6 +1498,11 @@ dm_plane_attach_color_mgmt_properties(struct amdgpu_= display_manager *dm, AMDGPU_HDR_MULT_DEFAULT); =20 if (dm->dc->caps.color.dpp.hw_3d_lut) { + drm_object_attach_property(&plane->base, + dm->adev->mode_info.plane_shaper_lut_property, 0); + drm_object_attach_property(&plane->base, + dm->adev->mode_info.plane_shaper_lut_size_property, + MAX_COLOR_LUT_ENTRIES); drm_object_attach_property(&plane->base, dm->adev->mode_info.plane_lut3d_property, 0); drm_object_attach_property(&plane->base, @@ -1531,6 +1539,14 @@ dm_atomic_plane_set_property(struct drm_plane *plane, dm_plane_state->hdr_mult =3D val; dm_plane_state->base.color_mgmt_changed =3D 1; } + } else if (property =3D=3D adev->mode_info.plane_shaper_lut_property) { + ret =3D amdgpu_dm_replace_property_blob_from_id(plane->dev, + &dm_plane_state->shaper_lut, + val, + -1, sizeof(struct drm_color_lut), + &replaced); + dm_plane_state->base.color_mgmt_changed |=3D replaced; + return ret; } else if (property =3D=3D adev->mode_info.plane_lut3d_property) { ret =3D amdgpu_dm_replace_property_blob_from_id(plane->dev, &dm_plane_state->lut3d, @@ -1567,6 +1583,9 @@ dm_atomic_plane_get_property(struct drm_plane *plane, *val =3D dm_plane_state->degamma_tf; } else if (property =3D=3D adev->mode_info.plane_hdr_mult_property) { *val =3D dm_plane_state->hdr_mult; + } else if (property =3D=3D adev->mode_info.plane_shaper_lut_property) { + *val =3D (dm_plane_state->shaper_lut) ? + dm_plane_state->shaper_lut->base.id : 0; } else if (property =3D=3D adev->mode_info.plane_lut3d_property) { *val =3D (dm_plane_state->lut3d) ? dm_plane_state->lut3d->base.id : 0; --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BB23C77B60 for ; Sun, 23 Apr 2023 14:48:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230256AbjDWOsw (ORCPT ); Sun, 23 Apr 2023 10:48:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54806 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229836AbjDWOsr (ORCPT ); Sun, 23 Apr 2023 10:48:47 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C59F710F0 for ; Sun, 23 Apr 2023 07:48:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=KvhTbB+Kxd5FYe1aiUgkRyX7rJ0s9IuTtnkFeSJu+RY=; b=QToXh3jPx2EZMNZ2JLKAilJauf Jfd1Ns7DYII8MVMLpuyE4jT/HcukAegS+IN5ebTnSnEC6KiLu/URgl8YXFmo3W3dez9mqXM8Cr+Vv fkXwQ0nR1x3Gggw31jb+zqXIOgn8yCxFN4iiD7TMjOcwKSMU7fbgdpIRYOKiPFnbYKciAfo0EEpV9 Zhj5DMLLiqyFbX1Dmu1mbZZezZ4+DEI9we2JTYYxSwueqNdRZ4TNzVZXS46vTX+HgA+Pqe6vCKeSC SWKh4JDYBad2hzBBwLdRZzCYWs7EafdkPIDGRvfurG3gZsZ7ew4/dViGFMxHiyNFUpCkX8NlTBiKH I8Wa97Tw==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaSM-00ANVs-Kf; Sun, 23 Apr 2023 16:12:46 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 15/40] drm/amd/display: add plane shaper TF driver-private property Date: Sun, 23 Apr 2023 13:10:27 -0100 Message-Id: <20230423141051.702990-16-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add property to set predefined transfer function to enable delinearizing content with or without shaper LUT. Drivers should advertize this property acoording to HW caps. Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 9 +++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 6 ++++++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 6 ++++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 11 +++++++++++ 4 files changed, 32 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/= amd/amdgpu/amdgpu_display.c index f41406ee96ad..2bf8b19feae4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1346,6 +1346,15 @@ amdgpu_display_create_color_properties(struct amdgpu= _device *adev) return -ENOMEM; adev->mode_info.plane_shaper_lut_size_property =3D prop; =20 + prop =3D drm_property_create_enum(adev_to_drm(adev), + DRM_MODE_PROP_ENUM, + "AMD_PLANE_SHAPER_TF", + drm_transfer_function_enum_list, + ARRAY_SIZE(drm_transfer_function_enum_list)); + if (!prop) + return -ENOMEM; + adev->mode_info.plane_shaper_tf_property =3D prop; + prop =3D drm_property_create(adev_to_drm(adev), DRM_MODE_PROP_BLOB, "AMD_PLANE_LUT3D", 0); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd= /amdgpu/amdgpu_mode.h index 756d5f70be0a..17c7669ad9ab 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -401,6 +401,12 @@ struct amdgpu_mode_info { * pre-blending shaper LUT as supported by the driver (read-only). */ struct drm_property *plane_shaper_lut_size_property; + /** + * @plane_shaper_tf_property: Plane property to set a predefined + * transfer function for pre-blending shaper (before applying 3D LUT) + * with or without LUT. + */ + struct drm_property *plane_shaper_tf_property; /** * @plane_lut3d_property: Plane property for gamma correction using a * 3D LUT (pre-blending). diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gp= u/drm/amd/display/amdgpu_dm/amdgpu_dm.h index d3ecc73129ff..8a425e7a7e89 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -753,6 +753,12 @@ struct dm_plane_state { * array of &struct drm_color_lut. */ struct drm_property_blob *shaper_lut; + /** + * @shaper_tf: + * + * Predefined transfer function to delinearize color space. + */ + enum drm_transfer_function shaper_tf; /** * @lut3d: 3D lookup table blob. The blob (if not NULL) is an array of * &struct drm_color_lut. diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/driv= ers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 69e2f1f86cce..e4f28fbf6613 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1324,6 +1324,7 @@ static void dm_drm_plane_reset(struct drm_plane *plan= e) if (amdgpu_state) { amdgpu_state->degamma_tf =3D DRM_TRANSFER_FUNCTION_DEFAULT; amdgpu_state->hdr_mult =3D AMDGPU_HDR_MULT_DEFAULT; + amdgpu_state->shaper_tf =3D DRM_TRANSFER_FUNCTION_DEFAULT; } #endif } @@ -1503,6 +1504,9 @@ dm_plane_attach_color_mgmt_properties(struct amdgpu_d= isplay_manager *dm, drm_object_attach_property(&plane->base, dm->adev->mode_info.plane_shaper_lut_size_property, MAX_COLOR_LUT_ENTRIES); + drm_object_attach_property(&plane->base, + dm->adev->mode_info.plane_shaper_tf_property, + DRM_TRANSFER_FUNCTION_DEFAULT); drm_object_attach_property(&plane->base, dm->adev->mode_info.plane_lut3d_property, 0); drm_object_attach_property(&plane->base, @@ -1547,6 +1551,11 @@ dm_atomic_plane_set_property(struct drm_plane *plane, &replaced); dm_plane_state->base.color_mgmt_changed |=3D replaced; return ret; + } else if (property =3D=3D adev->mode_info.plane_shaper_tf_property) { + if (dm_plane_state->shaper_tf !=3D val) { + dm_plane_state->shaper_tf =3D val; + dm_plane_state->base.color_mgmt_changed =3D 1; + } } else if (property =3D=3D adev->mode_info.plane_lut3d_property) { ret =3D amdgpu_dm_replace_property_blob_from_id(plane->dev, &dm_plane_state->lut3d, @@ -1586,6 +1595,8 @@ dm_atomic_plane_get_property(struct drm_plane *plane, } else if (property =3D=3D adev->mode_info.plane_shaper_lut_property) { *val =3D (dm_plane_state->shaper_lut) ? dm_plane_state->shaper_lut->base.id : 0; + } else if (property =3D=3D adev->mode_info.plane_shaper_tf_property) { + *val =3D dm_plane_state->shaper_tf; } else if (property =3D=3D adev->mode_info.plane_lut3d_property) { *val =3D (dm_plane_state->lut3d) ? dm_plane_state->lut3d->base.id : 0; --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBDF6C77B60 for ; Sun, 23 Apr 2023 14:46:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230366AbjDWOqr (ORCPT ); Sun, 23 Apr 2023 10:46:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51784 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230388AbjDWOqj (ORCPT ); Sun, 23 Apr 2023 10:46:39 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 40C1E1701 for ; Sun, 23 Apr 2023 07:46:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=YuRvpsn5roC+eRUxTHLyKChKqQovXO5NGq7R4iJaNio=; b=FNUSIzcpPCB6FEpiH8zNLT8EVn FKHwSPuShGgq3xWnWZaDT3vF72WB3E+4l2s1M2C1c6QMBsRwUgFzuiVYUC/+/hBKWbDpCj4Sx3azm r5grGq3nR6ebdh67g1rIEj88WslocWkWQS0h0l4Su4LT5A7uziEHbR9+PLZwFZ2suBw4UlA+Kg7KZ ZNyVOWRBIJfGnuAmXCxcbrmXZz+aOdQbvrsGjJfUGx25Gcbs/93zjxsqDizmWncZzWYTYU/KUBmyk L8Rwi0hvAlQ97Rw8j1L1Xubxa9LNnpqJi4pPb+TL+Lz+iCHL8nUWUaWxMQXQ+8kmkvqeN8O4/8/p1 VOj7whEQ==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaSP-00ANVs-HQ; Sun, 23 Apr 2023 16:12:49 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , linux-kernel@vger.kernel.org Subject: [RFC PATCH 16/40] drm/amd/display: add plane blend LUT and TF driver-private properties Date: Sun, 23 Apr 2023 13:10:28 -0100 Message-Id: <20230423141051.702990-17-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Joshua Ashton Blend 1D LUT or a predefined transfer function can be set to linearize content before blending, so that it's positioned just before blending planes, and after 3D LUT (non-linear space). Shaper and Blend LUTs are 1D LUTs that sandwich 3D LUT. Drivers should advertize blend properties according to HW caps. Signed-off-by: Joshua Ashton --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 23 +++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 18 ++++++++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 12 +++++++ .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 34 +++++++++++++++++++ 4 files changed, 87 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/= amd/amdgpu/amdgpu_display.c index 2bf8b19feae4..0bcf0bc6baff 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1369,6 +1369,29 @@ amdgpu_display_create_color_properties(struct amdgpu= _device *adev) return -ENOMEM; adev->mode_info.plane_lut3d_size_property =3D prop; =20 + prop =3D drm_property_create(adev_to_drm(adev), + DRM_MODE_PROP_BLOB, + "AMD_PLANE_BLEND_LUT", 0); + if (!prop) + return -ENOMEM; + adev->mode_info.plane_blend_lut_property =3D prop; + + prop =3D drm_property_create_range(adev_to_drm(adev), + DRM_MODE_PROP_IMMUTABLE, + "AMD_PLANE_BLEND_LUT_SIZE", 0, UINT_MAX); + if (!prop) + return -ENOMEM; + adev->mode_info.plane_blend_lut_size_property =3D prop; + + prop =3D drm_property_create_enum(adev_to_drm(adev), + DRM_MODE_PROP_ENUM, + "AMD_PLANE_BLEND_TF", + drm_transfer_function_enum_list, + ARRAY_SIZE(drm_transfer_function_enum_list)); + if (!prop) + return -ENOMEM; + adev->mode_info.plane_blend_tf_property =3D prop; + return 0; } #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd= /amdgpu/amdgpu_mode.h index 17c7669ad9ab..f640dbd53b8c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -417,6 +417,24 @@ struct amdgpu_mode_info { * size of 3D LUT as supported by the driver (read-only). */ struct drm_property *plane_lut3d_size_property; + /** + * @plane_blend_lut_property: Plane property for output gamma before + * blending. Userspace set a blend LUT to convert colors after 3D LUT + * conversion. It works as a post-3D LUT 1D LUT, with shaper LUT, they + * are sandwiching 3D LUT with two 1D LUT. + */ + struct drm_property *plane_blend_lut_property; + /** + * @plane_blend_lut_size_property: Plane property to define the max + * size of blend LUT as supported by the driver (read-only). + */ + struct drm_property *plane_blend_lut_size_property; + /** + * @plane_blend_tf_property: Plane property to set a predefined + * transfer function for pre-blending blend (before applying 3D LUT) + * with or without LUT. + */ + struct drm_property *plane_blend_tf_property; #endif }; =20 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gp= u/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 8a425e7a7e89..54121c3fa040 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -764,6 +764,18 @@ struct dm_plane_state { * &struct drm_color_lut. */ struct drm_property_blob *lut3d; + /** + * @blend_lut: blend lut lookup table blob. The blob (if not NULL) is an + * array of &struct drm_color_lut. + */ + struct drm_property_blob *blend_lut; + /** + * @blend_tf: + * + * Pre-defined transfer function for converting plane pixel data before + * applying blend LUT. + */ + enum drm_transfer_function blend_tf; #endif }; =20 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/driv= ers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index e4f28fbf6613..cdbd11f3be20 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1325,6 +1325,7 @@ static void dm_drm_plane_reset(struct drm_plane *plan= e) amdgpu_state->degamma_tf =3D DRM_TRANSFER_FUNCTION_DEFAULT; amdgpu_state->hdr_mult =3D AMDGPU_HDR_MULT_DEFAULT; amdgpu_state->shaper_tf =3D DRM_TRANSFER_FUNCTION_DEFAULT; + amdgpu_state->blend_tf =3D DRM_TRANSFER_FUNCTION_DEFAULT; } #endif } @@ -1352,6 +1353,8 @@ dm_drm_plane_duplicate_state(struct drm_plane *plane) drm_property_blob_get(dm_plane_state->shaper_lut); if (dm_plane_state->lut3d) drm_property_blob_get(dm_plane_state->lut3d); + if (dm_plane_state->blend_lut) + drm_property_blob_get(dm_plane_state->blend_lut); #endif =20 return &dm_plane_state->base; @@ -1424,6 +1427,7 @@ static void dm_drm_plane_destroy_state(struct drm_pla= ne *plane, drm_property_blob_put(dm_plane_state->degamma_lut); drm_property_blob_put(dm_plane_state->shaper_lut); drm_property_blob_put(dm_plane_state->lut3d); + drm_property_blob_put(dm_plane_state->blend_lut); #endif =20 if (dm_plane_state->dc_state) @@ -1513,6 +1517,17 @@ dm_plane_attach_color_mgmt_properties(struct amdgpu_= display_manager *dm, dm->adev->mode_info.plane_lut3d_size_property, MAX_COLOR_3DLUT_ENTRIES); } + + if (dm->dc->caps.color.dpp.ogam_ram) { + drm_object_attach_property(&plane->base, + dm->adev->mode_info.plane_blend_lut_property, 0); + drm_object_attach_property(&plane->base, + dm->adev->mode_info.plane_blend_lut_size_property, + MAX_COLOR_LUT_ENTRIES); + drm_object_attach_property(&plane->base, + dm->adev->mode_info.plane_blend_tf_property, + DRM_TRANSFER_FUNCTION_DEFAULT); + } } =20 static int @@ -1564,6 +1579,19 @@ dm_atomic_plane_set_property(struct drm_plane *plane, &replaced); dm_plane_state->base.color_mgmt_changed |=3D replaced; return ret; + } else if (property =3D=3D adev->mode_info.plane_blend_lut_property) { + ret =3D amdgpu_dm_replace_property_blob_from_id(plane->dev, + &dm_plane_state->blend_lut, + val, + -1, sizeof(struct drm_color_lut), + &replaced); + dm_plane_state->base.color_mgmt_changed |=3D replaced; + return ret; + } else if (property =3D=3D adev->mode_info.plane_blend_tf_property) { + if (dm_plane_state->blend_tf !=3D val) { + dm_plane_state->blend_tf =3D val; + dm_plane_state->base.color_mgmt_changed =3D 1; + } } else { drm_dbg_atomic(plane->dev, "[PLANE:%d:%s] unknown property [PROP:%d:%s]]\n", @@ -1600,6 +1628,12 @@ dm_atomic_plane_get_property(struct drm_plane *plane, } else if (property =3D=3D adev->mode_info.plane_lut3d_property) { *val =3D (dm_plane_state->lut3d) ? dm_plane_state->lut3d->base.id : 0; + } else if (property =3D=3D adev->mode_info.plane_blend_lut_property) { + *val =3D (dm_plane_state->blend_lut) ? + dm_plane_state->blend_lut->base.id : 0; + } else if (property =3D=3D adev->mode_info.plane_blend_tf_property) { + *val =3D dm_plane_state->blend_tf; + } else { return -EINVAL; } --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0BEF8C77B60 for ; Sun, 23 Apr 2023 14:14:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230263AbjDWOOa (ORCPT ); Sun, 23 Apr 2023 10:14:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34000 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230231AbjDWOO1 (ORCPT ); Sun, 23 Apr 2023 10:14:27 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8BBDC30DB for ; Sun, 23 Apr 2023 07:13:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=K+6HAiokAFpNjOZfe6WgA9HAsgScvAWCci4ACm8KQN8=; b=hx19W7o99rbwOcYM34nXNbSSO2 wNL6y1AqnOcuv62B7tlO7cHm2Mamz7TFvnDOpoVdX4iSCqBDLy14RJJhCiu5e9fAAzMxhYCxxlaXl hySJDSRTL/Cv8+a33gH5aQIROjh5lQr06r9/8oQLXkcUXZ59HIWqAwXQnSLB9RRaKYYFb+Gs/qQyM PgNCnsEa34yModOd4L5BkD2Noo5QY4wFU+UvANqowu7JU7BehKBJnr4hxXkt4yPQWMWT4FZFDK1t6 UfbeEMnf8VkLNQVqDokT5RCPODHQYd5XKsjPOziSs/PvQev4t0yHiP0N/qayIdHHz940+zkg1PH0C JVIariXg==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaST-00ANVs-FW; Sun, 23 Apr 2023 16:12:53 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 17/40] drm/amd/display: add comments to describe DM crtc color mgmt behavior Date: Sun, 23 Apr 2023 13:10:29 -0100 Message-Id: <20230423141051.702990-18-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Describe some expected behavior of the AMD DM color mgmt programming. Signed-off-by: Melissa Wen --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/driv= ers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index a4cb23d059bd..fe779d10834e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -440,12 +440,23 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_s= tate *crtc) stream->out_transfer_func->type =3D TF_TYPE_DISTRIBUTED_POINTS; stream->out_transfer_func->tf =3D TRANSFER_FUNCTION_SRGB; =20 + /* Note: although we pass has_rom as parameter here, we never + * actually use ROM because the color module only takes the ROM + * path if transfer_func->type =3D=3D PREDEFINED. + * + * See more in mod_color_calculate_regamma_params() + */ r =3D __set_legacy_tf(stream->out_transfer_func, regamma_lut, regamma_size, has_rom); if (r) return r; } else if (has_regamma) { - /* If atomic regamma, CRTC RGM goes into RGM LUT. */ + /* CRTC RGM goes into RGM LUT. + * + * Note: there is no implicit sRGB regamma here. We are using + * degamma calculation from color module to calculate the curve + * from a linear base. + */ stream->out_transfer_func->type =3D TF_TYPE_DISTRIBUTED_POINTS; stream->out_transfer_func->tf =3D TRANSFER_FUNCTION_LINEAR; =20 --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BFFF6C6FD18 for ; Sun, 23 Apr 2023 14:14:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229982AbjDWOO2 (ORCPT ); Sun, 23 Apr 2023 10:14:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229726AbjDWOOZ (ORCPT ); Sun, 23 Apr 2023 10:14:25 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7452F30CA for ; Sun, 23 Apr 2023 07:13:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=fshOS/phNnywqSBclNdRCFpkoMQdWZs7fr2IAut5ZT0=; b=BtJ4pyaxdSoPnTZ+6hrLdkGn3J ThaZJtL9jgfH3W46t0EickvaTV1RcRBbRBtFLcIqmLXEO4cH/9wHo0uF/7TRv7xq02rBwYs38JVRI cRKqfACjAfjuzlRMHgFE6eJ4clTF0oU9e9wGD7U51lS6ePdh+ml8cARhCzFbMiu2pAFK8E1e2JTA0 6vH7lFIcUzwkeebvagpq38nIzFanGIUMwHbezSCvXbvcQ+djPBX+CR78NQ43bdGLb6P4kcV/tqcem fsJd568OQ7gjqkc+45X47JkDUimkGeK1dBnwBoOp/tXIuIIMhM8m9t7moV0apFxk95KjWNou7/qze qddg1PuQ==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaSW-00ANVs-Bb; Sun, 23 Apr 2023 16:12:56 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 18/40] drm/amd/display: encapsulate atomic regamma operation Date: Sun, 23 Apr 2023 13:10:30 -0100 Message-Id: <20230423141051.702990-19-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We are introducing DRM 3D LUT property to DM color pipeline in the next patch, but so far, only for atomic interface. By checking set_output_transfer_func in DC drivers with MPC 3D LUT support, we can verify that regamma is only programmed when 3D LUT programming fails. As a groundwork to introduce 3D LUT programming and better understand each step, detach atomic regamma programming from the crtc colocr updating code. Signed-off-by: Melissa Wen --- .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 52 ++++++++++++------- 1 file changed, 33 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/driv= ers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index fe779d10834e..f1885e9c614d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -303,6 +303,35 @@ static int __set_output_tf(struct dc_transfer_func *fu= nc, return res ? 0 : -ENOMEM; } =20 +static int amdgpu_dm_set_atomic_regamma(struct dc_stream_state *stream, + const struct drm_color_lut *regamma_lut, + uint32_t regamma_size, bool has_rom) +{ + int ret =3D 0; + if (regamma_size) { + /* CRTC RGM goes into RGM LUT. + * + * Note: there is no implicit sRGB regamma here. We are using + * degamma calculation from color module to calculate the curve + * from a linear base. + */ + stream->out_transfer_func->type =3D TF_TYPE_DISTRIBUTED_POINTS; + stream->out_transfer_func->tf =3D TRANSFER_FUNCTION_LINEAR; + + ret =3D __set_output_tf(stream->out_transfer_func, + regamma_lut, regamma_size, has_rom); + } else { + /* + * No CRTC RGM means we can just put the block into bypass + * since we don't have any plane level adjustments using it. + */ + stream->out_transfer_func->type =3D TF_TYPE_BYPASS; + stream->out_transfer_func->tf =3D TRANSFER_FUNCTION_LINEAR; + } + + return ret; +} + /** * __set_input_tf - calculates the input transfer function based on expect= ed * input space. @@ -450,27 +479,12 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_s= tate *crtc) regamma_size, has_rom); if (r) return r; - } else if (has_regamma) { - /* CRTC RGM goes into RGM LUT. - * - * Note: there is no implicit sRGB regamma here. We are using - * degamma calculation from color module to calculate the curve - * from a linear base. - */ - stream->out_transfer_func->type =3D TF_TYPE_DISTRIBUTED_POINTS; - stream->out_transfer_func->tf =3D TRANSFER_FUNCTION_LINEAR; - - r =3D __set_output_tf(stream->out_transfer_func, regamma_lut, - regamma_size, has_rom); + } else { + regamma_size =3D has_regamma ? regamma_size : 0; + r =3D amdgpu_dm_set_atomic_regamma(stream, regamma_lut, + regamma_size, has_rom); if (r) return r; - } else { - /* - * No CRTC RGM means we can just put the block into bypass - * since we don't have any plane level adjustments using it. - */ - stream->out_transfer_func->type =3D TF_TYPE_BYPASS; - stream->out_transfer_func->tf =3D TRANSFER_FUNCTION_LINEAR; } =20 /* --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE320C6FD18 for ; Sun, 23 Apr 2023 14:14:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230286AbjDWOOg (ORCPT ); Sun, 23 Apr 2023 10:14:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34086 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230257AbjDWOO3 (ORCPT ); Sun, 23 Apr 2023 10:14:29 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9FF772D74 for ; Sun, 23 Apr 2023 07:13:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=ZM4LRZ9R6oIPI6RNCnBj4XwAXqnDA6bTH1zIbaUH8Yk=; b=McvxyZbQR5ieSvLdcLtNnFAKYm xjAPptQxeLwrZVayHfVbBgABTGy+H8RtSJ7n+XENAMP64aHoNzX41hIYxJOEKV3BQWd/MM8qA+daH /vf4d91eWbUSclLJAwBIbNDLdhB1fyOAFOwPjTXFqZajrYc5w5GWocunQDs31V61gWE7hloR5jiJY rMbdDkVnSnRSE3R/rDHZ7FYPOXJRlK/MP9AAI2HcXcaaHyl1ngRC7J+K7wZu8UwynRsy+3IJMbxVy Bw3cRWS6hjkiC4wg2reOfwYHO1du36GeAmFMYOkUZ37R4QTIzOq8clCrmO2g9FKDvsPdbLZT3aTua o04joJww==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaSa-00ANVs-1Q; Sun, 23 Apr 2023 16:13:00 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 19/40] drm/amd/display: update lut3d and shaper lut to stream Date: Sun, 23 Apr 2023 13:10:31 -0100 Message-Id: <20230423141051.702990-20-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" It follows the same path of out_transfer_func for stream updates, since shaper LUT and 3D LUT is programmed in funcs.set_output_transfer_func() and this function is called in the atomic commit_tail when update_flags.bits.out_tf is set. Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/display/dc/core/dc.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd= /display/dc/core/dc.c index e65ba87ee2c5..9230c122d77e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2581,7 +2581,7 @@ static enum surface_update_type check_update_surfaces= _for_stream( stream_update->integer_scaling_update) su_flags->bits.scaling =3D 1; =20 - if (stream_update->out_transfer_func) + if (stream_update->out_transfer_func || stream_update->lut3d_func) su_flags->bits.out_tf =3D 1; =20 if (stream_update->abm_level) @@ -2936,6 +2936,14 @@ static void copy_stream_update_to_stream(struct dc *= dc, sizeof(struct dc_transfer_func_distributed_points)); } =20 + if (update->func_shaper && + stream->func_shaper !=3D update->func_shaper) + stream->func_shaper =3D update->func_shaper; + + if (update->lut3d_func && + stream->lut3d_func !=3D update->lut3d_func) + stream->lut3d_func =3D update->lut3d_func; + if (update->hdr_static_metadata) stream->hdr_static_metadata =3D *update->hdr_static_metadata; =20 --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70D77C77B60 for ; Sun, 23 Apr 2023 14:14:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230267AbjDWOOp (ORCPT ); Sun, 23 Apr 2023 10:14:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34248 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230292AbjDWOOh (ORCPT ); Sun, 23 Apr 2023 10:14:37 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D70C530F5 for ; Sun, 23 Apr 2023 07:14:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=3ClD7dV5VuRi0yBxsEkJ52hVcmkeVavwfEKm0GzWXV0=; b=Mscy7EO0gkStGjDQNcsCg5zVyN bq0TY2LHRPFrZ5GtBwNl/y2RthYAcEZ59rjOzdOUOUefA/FIqb5t2v7onqNismXpG1YPDQvFLxjiw T3Nc1vBouF+pTUlS2Fk5rHr0JVJRf0R0B5W0UVtbCv1Vj4qtKtDF9Q7F9AQbMxXM2EO4exvqtzK6M eDinz8eY/E9pc8Tu+09q4Vzb8yx2ZJ+JJR1ScWienqUfoAXo5r1u5XwQoQ6xF25b+W5oCt2UVP1b9 rJaHLeqPxbrkXXbdYvDUYNge1oyHQqOFnra1cnW5te9wf7+zQf0Xyo+5px76pAmT99ugIB37dbr6J /k+hqfYg==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaSd-00ANVs-8i; Sun, 23 Apr 2023 16:13:03 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 20/40] drm/amd/display: copy 3D LUT settings from crtc state to stream_update Date: Sun, 23 Apr 2023 13:10:32 -0100 Message-Id: <20230423141051.702990-21-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Joshua Ashton When commiting planes, we copy color mgmt resources to the stream state. Do the same for shaper and 3D LUTs. Co-developed-by: Melissa Wen Signed-off-by: Melissa Wen Signed-off-by: Joshua Ashton --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gp= u/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 76a776fd8437..729e37fa1873 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8190,6 +8190,10 @@ static void amdgpu_dm_commit_planes(struct drm_atomi= c_state *state, &acrtc_state->stream->csc_color_matrix; bundle->stream_update.out_transfer_func =3D acrtc_state->stream->out_transfer_func; + bundle->stream_update.lut3d_func =3D + (struct dc_3dlut *) acrtc_state->stream->lut3d_func; + bundle->stream_update.func_shaper =3D + (struct dc_transfer_func *) acrtc_state->stream->func_shaper; } =20 acrtc_state->stream->abm_level =3D acrtc_state->abm_level; --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3012EC6FD18 for ; Sun, 23 Apr 2023 14:15:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230371AbjDWOPh (ORCPT ); Sun, 23 Apr 2023 10:15:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230358AbjDWOPY (ORCPT ); Sun, 23 Apr 2023 10:15:24 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 78996273A for ; Sun, 23 Apr 2023 07:14:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=1pDv9ml0fMW1552wzaK0WkxguQ7efaI2g4W2c2iLaSQ=; b=Eox+XIAfqqBlMEmXETYlxVXbEh JHMNZPiMHotm9iHBFLCgTg0eMle01wIqFJm4RqTCF4aAo33wH93VNrc75eNg9GhToaQQ8MZR10sVS VVcU/Ad/u2MW3uASchmgY0rh/ZmfaZ2M0uPRWalgkOBjLFHWxJtajKLCq7TTFWO3KxZiHb/hsg7vB lm7esmn/xAWZc5vjeCb7V5QRcsbOCl8FLRoDuqvkvkMTTq9sRIXEff+iMavZKHEIa39gNBNpgOTDG 0V1X62DnqJA3REts/k7ijvTFdNinuGn+fMbGrnxYflTLiqHR+qSut+0U8lXTcgUikMRUGJoXot13l iqFJGnhw==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaSf-00ANVs-T7; Sun, 23 Apr 2023 16:13:06 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 21/40] drm/amd/display: allow BYPASS 3D LUT but keep shaper LUT settings Date: Sun, 23 Apr 2023 13:10:33 -0100 Message-Id: <20230423141051.702990-22-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" HW allows us to program shaper LUT without 3D LUT settings and it is also good for testing shaper LUT behavior, therefore, DC driver should allow acquiring both 3D and shaper LUT, but programing shaper LUT without 3D LUT (not initialized). Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/g= pu/drm/amd/display/dc/dcn30/dcn30_hwseq.c index 3303c9aae068..bacb0a001d68 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c @@ -113,7 +113,6 @@ static bool dcn30_set_mpc_shaper_3dlut(struct pipe_ctx = *pipe_ctx, } =20 if (stream->lut3d_func && - stream->lut3d_func->state.bits.initialized =3D=3D 1 && stream->lut3d_func->state.bits.rmu_idx_valid =3D=3D 1) { if (stream->lut3d_func->state.bits.rmu_mux_num =3D=3D 0) mpcc_id_projected =3D stream->lut3d_func->state.bits.mpc_rmu0_mux; @@ -131,8 +130,12 @@ static bool dcn30_set_mpc_shaper_3dlut(struct pipe_ctx= *pipe_ctx, if (acquired_rmu !=3D stream->lut3d_func->state.bits.rmu_mux_num) BREAK_TO_DEBUGGER(); =20 - result =3D mpc->funcs->program_3dlut(mpc, &stream->lut3d_func->lut_3d, - stream->lut3d_func->state.bits.rmu_mux_num); + if (stream->lut3d_func->state.bits.initialized =3D=3D 1) + result =3D mpc->funcs->program_3dlut(mpc, &stream->lut3d_func->lut_3d, + stream->lut3d_func->state.bits.rmu_mux_num); + else + result =3D mpc->funcs->program_3dlut(mpc, NULL, + stream->lut3d_func->state.bits.rmu_mux_num); result =3D mpc->funcs->program_shaper(mpc, shaper_lut, stream->lut3d_func->state.bits.rmu_mux_num); } else { --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1F05C77B73 for ; Sun, 23 Apr 2023 14:14:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230322AbjDWOOs (ORCPT ); Sun, 23 Apr 2023 10:14:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34256 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230297AbjDWOOh (ORCPT ); Sun, 23 Apr 2023 10:14:37 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BFEA230FC for ; Sun, 23 Apr 2023 07:14:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=S9VKUbO7MAPqhVMypvggSCZtQux9ThB4FE1T0I3nB9M=; b=K+L2mEiCcTRSWLNvjIWK7/xizd RT3sUnpGTVNFcJfIhaMk04c0H0X6XV3kedOP9m0QG+RJJZvUJ4B5qsVWXGAVRE3DKf6YcUXjbv/8n UoBhv1MQY3GsiHKiU0tBzvvhd/MQkovROYklwtrA17K9Tljdtqqzq7cDGxfoV37Sv9ZaYPXJU+6K+ KtuWR7QZPdEOX0gBz/VCMLdYh77DDOn1AcbOG471uRt/tNB8FXPG1MWViY5jtmtfoiUKpDBgd4Nxl CDhkArhDBuTHc7CXO6irwad2t7x3LGTsmaXyqplZ4pFcuxlVXty5gqR9Xdyj87a6llYK+pDvi0XnL ZkyHfi5w==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaSm-00ANVs-8B; Sun, 23 Apr 2023 16:13:12 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 22/40] drm/amd/display: handle MPC 3D LUT resources for a given context Date: Sun, 23 Apr 2023 13:10:34 -0100 Message-Id: <20230423141051.702990-23-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In the original dc_acquire_release_mpc_3dlut(), only current ctx is considered, which doesn't fit the steps for atomic checking new ctx. Therefore, create a function to handle 3D LUT resource for a given context, so that we can check resources availability in atomic_check time and handle failures properly. Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/display/dc/core/dc.c | 39 ++++++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dc.h | 8 +++++ 2 files changed, 47 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd= /display/dc/core/dc.c index 9230c122d77e..ee3fe4eae22e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2101,6 +2101,45 @@ bool dc_acquire_release_mpc_3dlut( return ret; } =20 +bool +dc_acquire_release_mpc_3dlut_for_ctx(struct dc *dc, + bool acquire, + struct dc_state *state, + struct dc_stream_state *stream, + struct dc_3dlut **lut, + struct dc_transfer_func **shaper) +{ + int pipe_idx; + bool ret =3D false; + bool found_pipe_idx =3D false; + const struct resource_pool *pool =3D dc->res_pool; + struct resource_context *res_ctx =3D &state->res_ctx; + int mpcc_id =3D 0; + + if (pool && res_ctx) { + if (acquire) { + /*find pipe idx for the given stream*/ + for (pipe_idx =3D 0; pipe_idx < pool->pipe_count; pipe_idx++) { + if (res_ctx->pipe_ctx[pipe_idx].stream =3D=3D stream) { + found_pipe_idx =3D true; + mpcc_id =3D res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst; + break; + } + } + } else + found_pipe_idx =3D true;/*for release pipe_idx is not required*/ + + if (found_pipe_idx) { + if (acquire && pool->funcs->acquire_post_bldn_3dlut) + ret =3D pool->funcs->acquire_post_bldn_3dlut(res_ctx, pool, mpcc_id, l= ut, shaper); + else if (!acquire && pool->funcs->release_post_bldn_3dlut) + ret =3D pool->funcs->release_post_bldn_3dlut(res_ctx, pool, lut, shape= r); + } + } + return ret; +} + + static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *conte= xt) { int i; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/disp= lay/dc/dc.h index b45974a2dec3..7fdb0bbb2df9 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1350,6 +1350,14 @@ bool dc_acquire_release_mpc_3dlut( struct dc_3dlut **lut, struct dc_transfer_func **shaper); =20 +bool +dc_acquire_release_mpc_3dlut_for_ctx(struct dc *dc, + bool acquire, + struct dc_state *state, + struct dc_stream_state *stream, + struct dc_3dlut **lut, + struct dc_transfer_func **shaper); + void dc_resource_state_copy_construct( const struct dc_state *src_ctx, struct dc_state *dst_ctx); --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A248DC6FD18 for ; Sun, 23 Apr 2023 14:15:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230313AbjDWOPE (ORCPT ); Sun, 23 Apr 2023 10:15:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230269AbjDWOOp (ORCPT ); Sun, 23 Apr 2023 10:14:45 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F2F9E3594 for ; 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Sun, 23 Apr 2023 16:13:15 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 23/40] drm/amd/display: dynamically acquire 3DLUT resources for color changes Date: Sun, 23 Apr 2023 13:10:35 -0100 Message-Id: <20230423141051.702990-24-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Joshua Ashton dc_acquire_release_mpc_3dlut_for_ctx initializes the bits required to program 3DLUT in DC MPC hw block, applied in set_output_transfer_func(). Since acquire/release can fail, we should check resources availability during atomic check considering the new context created. We dynamically acquire 3D LUT resources when we actually use them, so we don't limit ourselves with the stream count. Co-developed-by: Melissa Wen Signed-off-by: Melissa Wen Signed-off-by: Joshua Ashton --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ++- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 3 +- .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 55 ++++++++++++++++++- .../amd/display/dc/dcn301/dcn301_resource.c | 26 ++++++++- 4 files changed, 87 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gp= u/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 729e37fa1873..6b40e17892e5 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -9380,7 +9380,12 @@ static int dm_update_crtc_state(struct amdgpu_displa= y_manager *dm, */ if (dm_new_crtc_state->base.color_mgmt_changed || drm_atomic_crtc_needs_modeset(new_crtc_state)) { - ret =3D amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); + if (!dm_state) { + ret =3D dm_atomic_get_state(state, &dm_state); + if (ret) + goto fail; + } + ret =3D amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state, dm_state->co= ntext); if (ret) goto fail; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gp= u/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 54121c3fa040..5faf4fc87701 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -904,7 +904,8 @@ void amdgpu_dm_trigger_timing_sync(struct drm_device *d= ev); =20 void amdgpu_dm_init_color_mod(void); int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); -int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); +int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc, + struct dc_state *ctx); int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, struct dc_plane_state *dc_plane_state); =20 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/driv= ers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index f1885e9c614d..99b1738c98d3 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -332,6 +332,49 @@ static int amdgpu_dm_set_atomic_regamma(struct dc_stre= am_state *stream, return ret; } =20 +/* amdgpu_dm_atomic_shaper_lut3d - set DRM CRTC shaper LUT and 3D LUT to DC + * interface + * @dc: Display Core control structure + * @ctx: + * @stream: DC stream state to set shaper LUT and 3D LUT + * @drm_shaper_lut: DRM CRTC (user) shaper LUT + * @drm_shaper_size: size of shaper LUT + * @drm_lut3d: DRM CRTC (user) 3D LUT + * @drm_lut3d_size: size of 3D LUT + * + * Returns: + * 0 on success. + */ +static int amdgpu_dm_atomic_shaper_lut3d(struct dc *dc, + struct dc_state *ctx, + struct dc_stream_state *stream, + const struct drm_color_lut *drm_shaper_lut, + uint32_t drm_shaper_size, + const struct drm_color_lut *drm_lut3d, + uint32_t drm_lut3d_size) +{ + struct dc_3dlut *lut3d_func; + struct dc_transfer_func *func_shaper; + bool acquire =3D drm_shaper_size && drm_lut3d_size; + + lut3d_func =3D (struct dc_3dlut *)stream->lut3d_func; + func_shaper =3D (struct dc_transfer_func *)stream->func_shaper; + + ASSERT((lut3d_func && func_shaper) || (!lut3d_func && !func_shaper)); + if ((acquire && !lut3d_func && !func_shaper) || + (!acquire && lut3d_func && func_shaper)) + { + if (!dc_acquire_release_mpc_3dlut_for_ctx(dc, acquire, ctx, stream, + &lut3d_func, &func_shaper)) + return DC_ERROR_UNEXPECTED; + } + + stream->lut3d_func =3D lut3d_func; + stream->func_shaper =3D func_shaper; + + return 0; +} + /** * __set_input_tf - calculates the input transfer function based on expect= ed * input space. @@ -402,6 +445,7 @@ int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_st= ate *crtc_state) /** * amdgpu_dm_update_crtc_color_mgmt: Maps DRM color management to DC strea= m. * @crtc: amdgpu_dm crtc state + * @ctx: * * With no plane level color management properties we're free to use any * of the HW blocks as long as the CRTC CTM always comes before the @@ -421,7 +465,8 @@ int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_st= ate *crtc_state) * Returns: * 0 on success. Error code if setup fails. */ -int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) +int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc, + struct dc_state *ctx) { struct dc_stream_state *stream =3D crtc->stream; struct amdgpu_device *adev =3D drm_to_adev(crtc->base.state->dev); @@ -480,6 +525,14 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_st= ate *crtc) if (r) return r; } else { + r =3D amdgpu_dm_atomic_shaper_lut3d(adev->dm.dc, ctx, stream, + NULL, 0, NULL, 0); + if (r) + return r; + /* Note: OGAM is disabled if 3D LUT is successfully programmed. + * See params and set_output_gamma in + * dcn30_set_output_transfer_func() + */ regamma_size =3D has_regamma ? regamma_size : 0; r =3D amdgpu_dm_set_atomic_regamma(stream, regamma_lut, regamma_size, has_rom); diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c b/driv= ers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c index 5ac2a272c380..a6d6fcaaca1c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c @@ -1258,6 +1258,30 @@ static struct display_stream_compressor *dcn301_dsc_= create( return &dsc->base; } =20 +static enum dc_status +dcn301_remove_stream_from_ctx(struct dc *dc, + struct dc_state *new_ctx, + struct dc_stream_state *dc_stream) +{ + struct dc_3dlut *lut3d_func; + struct dc_transfer_func *func_shaper; + + lut3d_func =3D (struct dc_3dlut *)dc_stream->lut3d_func; + func_shaper =3D (struct dc_transfer_func *)dc_stream->func_shaper; + + ASSERT((lut3d_func && func_shaper) || (!lut3d_func && !func_shaper)); + if (lut3d_func && func_shaper) + { + if (!dc_acquire_release_mpc_3dlut_for_ctx(dc, false, new_ctx, dc_stream, + &lut3d_func, &func_shaper)) + return DC_ERROR_UNEXPECTED; + } + + dc_stream->lut3d_func =3D lut3d_func; + dc_stream->func_shaper =3D func_shaper; + + return dcn20_remove_stream_from_ctx(dc, new_ctx, dc_stream); +} =20 static void dcn301_destroy_resource_pool(struct resource_pool **pool) { @@ -1406,7 +1430,7 @@ static struct resource_funcs dcn301_res_pool_funcs = =3D { .acquire_idle_pipe_for_layer =3D dcn20_acquire_idle_pipe_for_layer, .add_stream_to_ctx =3D dcn30_add_stream_to_ctx, .add_dsc_to_stream_resource =3D dcn20_add_dsc_to_stream_resource, - .remove_stream_from_ctx =3D dcn20_remove_stream_from_ctx, + .remove_stream_from_ctx =3D dcn301_remove_stream_from_ctx, .populate_dml_writeback_from_context =3D dcn30_populate_dml_writeback_fro= m_context, .set_mcif_arb_params =3D dcn30_set_mcif_arb_params, .find_first_free_match_stream_enc_for_link =3D dcn10_find_first_free_matc= h_stream_enc_for_link, --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD41EC6FD18 for ; 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charset="utf-8" Map DRM CRTC 3D LUT in the atomic color mgmt pipeline to DC (post-blending). 3D LUT works better in a non-linear color space, therefore using a degamma to linearize the input space may produce unexpected results. The next patch introduces shaper LUT support that can be used to delinearize the color space before applying 3D LUT conversion. Signed-off-by: Melissa Wen --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 +- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 5 + .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 185 +++++++++++++++--- 3 files changed, 174 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gp= u/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 6b40e17892e5..760080e4a4da 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -9945,7 +9945,13 @@ static int amdgpu_dm_atomic_check(struct drm_device = *dev, DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n"); goto fail; } - +#ifdef CONFIG_STEAM_DECK + ret =3D amdgpu_dm_verify_lut3d_size(adev, new_crtc_state); + if (ret) { + DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n"); + goto fail; + } +#endif if (!new_crtc_state->enable) continue; =20 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gp= u/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 5faf4fc87701..b9840c1f3cdf 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -894,9 +894,14 @@ void amdgpu_dm_update_freesync_caps(struct drm_connect= or *connector, =20 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); =20 +#ifdef CONFIG_STEAM_DECK /* 3D LUT max size is 17x17x17 */ #define MAX_COLOR_3DLUT_ENTRIES 4913 #define MAX_COLOR_3DLUT_BITDEPTH 12 +int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev, + const struct drm_crtc_state *crtc_state); +#endif + /* 1D LUT degamma, regamma and shaper*/ #define MAX_COLOR_LUT_ENTRIES 4096 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/driv= ers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 99b1738c98d3..25010fa19bc8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -332,6 +332,117 @@ static int amdgpu_dm_set_atomic_regamma(struct dc_str= eam_state *stream, return ret; } =20 +/** + * __set_input_tf - calculates the input transfer function based on expect= ed + * input space. + * @func: transfer function + * @lut: lookup table that defines the color space + * @lut_size: size of respective lut. + * + * Returns: + * 0 in case of success. -ENOMEM if fails. + */ +static int __set_input_tf(struct dc_transfer_func *func, + const struct drm_color_lut *lut, uint32_t lut_size) +{ + struct dc_gamma *gamma =3D NULL; + bool res; + + gamma =3D dc_create_gamma(); + if (!gamma) + return -ENOMEM; + + gamma->type =3D GAMMA_CUSTOM; + gamma->num_entries =3D lut_size; + + __drm_lut_to_dc_gamma(lut, gamma, false); + + res =3D mod_color_calculate_degamma_params(NULL, func, gamma, true); + dc_gamma_release(&gamma); + + return res ? 0 : -ENOMEM; +} + +#ifdef CONFIG_STEAM_DECK +static void __to_dc_lut3d_color(struct dc_rgb *rgb, + const struct drm_color_lut lut, + int bit_precision) +{ + rgb->red =3D drm_color_lut_extract(lut.red, bit_precision); + rgb->green =3D drm_color_lut_extract(lut.green, bit_precision); + rgb->blue =3D drm_color_lut_extract(lut.blue, bit_precision); +} + +static void __drm_3dlut_to_dc_3dlut(const struct drm_color_lut *lut, + uint32_t lut3d_size, + struct tetrahedral_params *params, + bool use_tetrahedral_9, + int bit_depth) +{ + struct dc_rgb *lut0; + struct dc_rgb *lut1; + struct dc_rgb *lut2; + struct dc_rgb *lut3; + int lut_i, i; + + + if (use_tetrahedral_9) { + lut0 =3D params->tetrahedral_9.lut0; + lut1 =3D params->tetrahedral_9.lut1; + lut2 =3D params->tetrahedral_9.lut2; + lut3 =3D params->tetrahedral_9.lut3; + } else { + lut0 =3D params->tetrahedral_17.lut0; + lut1 =3D params->tetrahedral_17.lut1; + lut2 =3D params->tetrahedral_17.lut2; + lut3 =3D params->tetrahedral_17.lut3; + } + + for (lut_i =3D 0, i =3D 0; i < lut3d_size - 4; lut_i++, i +=3D 4) { + /* We should consider the 3dlut RGB values are distributed + * along four arrays lut0-3 where the first sizes 1229 and the + * other 1228. The bit depth supported for 3dlut channel is + * 12-bit, but DC also supports 10-bit. + * + * TODO: improve color pipeline API to enable the userspace set + * bit depth and 3D LUT size/stride, as specified by VA-API. + */ + __to_dc_lut3d_color(&lut0[lut_i], lut[i], bit_depth); + __to_dc_lut3d_color(&lut1[lut_i], lut[i + 1], bit_depth); + __to_dc_lut3d_color(&lut2[lut_i], lut[i + 2], bit_depth); + __to_dc_lut3d_color(&lut3[lut_i], lut[i + 3], bit_depth); + } + /* lut0 has 1229 points (lut_size/4 + 1) */ + __to_dc_lut3d_color(&lut0[lut_i], lut[i], bit_depth); +} + +/* amdgpu_dm_atomic_lut3d - set DRM 3D LUT to DC stream + * @drm_lut3d: DRM CRTC (user) 3D LUT + * @drm_lut3d_size: size of 3D LUT + * @lut3d: DC 3D LUT + * + * Map DRM CRTC 3D LUT to DC 3D LUT and all necessary bits to program it + * on DCN MPC accordingly. + */ +static void amdgpu_dm_atomic_lut3d(const struct drm_color_lut *drm_lut, + uint32_t drm_lut3d_size, + struct dc_3dlut *lut) +{ + if (!drm_lut3d_size) { + lut->state.bits.initialized =3D 0; + } else { + /* Stride and bit depth are not programmable by API yet. + * Therefore, only supports 17x17x17 3D LUT (12-bit). + */ + lut->lut_3d.use_tetrahedral_9 =3D false; + lut->lut_3d.use_12bits =3D true; + lut->state.bits.initialized =3D 1; + __drm_3dlut_to_dc_3dlut(drm_lut, drm_lut3d_size, &lut->lut_3d, + lut->lut_3d.use_tetrahedral_9, + MAX_COLOR_3DLUT_BITDEPTH); + } +} + /* amdgpu_dm_atomic_shaper_lut3d - set DRM CRTC shaper LUT and 3D LUT to DC * interface * @dc: Display Core control structure @@ -355,7 +466,7 @@ static int amdgpu_dm_atomic_shaper_lut3d(struct dc *dc, { struct dc_3dlut *lut3d_func; struct dc_transfer_func *func_shaper; - bool acquire =3D drm_shaper_size && drm_lut3d_size; + bool acquire =3D drm_shaper_size || drm_lut3d_size; =20 lut3d_func =3D (struct dc_3dlut *)stream->lut3d_func; func_shaper =3D (struct dc_transfer_func *)stream->func_shaper; @@ -369,42 +480,56 @@ static int amdgpu_dm_atomic_shaper_lut3d(struct dc *d= c, return DC_ERROR_UNEXPECTED; } =20 - stream->lut3d_func =3D lut3d_func; stream->func_shaper =3D func_shaper; + stream->lut3d_func =3D lut3d_func; + + if (!acquire) + return 0; + + /* We don't get DRM shaper LUT yet. We assume the input color + * space is already delinearized, so we don't need a shaper LUT + * and we can just BYPASS. + */ + func_shaper->type =3D TF_TYPE_BYPASS; + func_shaper->tf =3D TRANSFER_FUNCTION_LINEAR; + amdgpu_dm_atomic_lut3d(drm_lut3d, drm_lut3d_size, lut3d_func); =20 return 0; } =20 /** - * __set_input_tf - calculates the input transfer function based on expect= ed - * input space. - * @func: transfer function - * @lut: lookup table that defines the color space - * @lut_size: size of respective lut. + * amdgpu_dm_verify_lut3d_size - verifies if 3D LUT is supported and if DR= M 3D + * LUT matches the hw supported size + * @adev: amdgpu device + * @crtc_state: the DRM CRTC state + * + * Verifies if post-blending (MPC) 3D LUT is supported by the HW (DCN 3.0 = or + * newer) and if the DRM 3D LUT matches the supported size. * * Returns: - * 0 in case of success. -ENOMEM if fails. + * 0 on success. -EINVAL if lut size are invalid. */ -static int __set_input_tf(struct dc_transfer_func *func, - const struct drm_color_lut *lut, uint32_t lut_size) +int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev, + const struct drm_crtc_state *crtc_state) { - struct dc_gamma *gamma =3D NULL; - bool res; + const struct drm_color_lut *lut3d =3D NULL; + struct dm_crtc_state *acrtc_state =3D to_dm_crtc_state(crtc_state); + uint32_t exp_size, size; =20 - gamma =3D dc_create_gamma(); - if (!gamma) - return -ENOMEM; + exp_size =3D adev->dm.dc->caps.color.mpc.num_3dluts ? + MAX_COLOR_3DLUT_ENTRIES : 0; =20 - gamma->type =3D GAMMA_CUSTOM; - gamma->num_entries =3D lut_size; - - __drm_lut_to_dc_gamma(lut, gamma, false); + lut3d =3D __extract_blob_lut(acrtc_state->lut3d, &size); =20 - res =3D mod_color_calculate_degamma_params(NULL, func, gamma, true); - dc_gamma_release(&gamma); + if (lut3d && size !=3D exp_size) { + DRM_DEBUG_DRIVER("Invalid Gamma 3D LUT size. Should be %u but got %u.\n", + exp_size, size); + return -EINVAL; + } =20 - return res ? 0 : -ENOMEM; + return 0; } +#endif =20 /** * amdgpu_dm_verify_lut_sizes - verifies if DRM luts match the hw supporte= d sizes @@ -477,6 +602,16 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_st= ate *crtc, bool has_regamma, has_degamma; bool is_legacy; int r; +#ifdef CONFIG_STEAM_DECK + const struct drm_color_lut *lut3d; + uint32_t lut3d_size; + + r =3D amdgpu_dm_verify_lut3d_size(adev, &crtc->base); + if (r) + return r; + + lut3d =3D __extract_blob_lut(crtc->lut3d, &lut3d_size); +#endif =20 r =3D amdgpu_dm_verify_lut_sizes(&crtc->base); if (r) @@ -525,10 +660,14 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_s= tate *crtc, if (r) return r; } else { +#ifdef CONFIG_STEAM_DECK + lut3d_size =3D lut3d !=3D NULL ? lut3d_size : 0; r =3D amdgpu_dm_atomic_shaper_lut3d(adev->dm.dc, ctx, stream, - NULL, 0, NULL, 0); + NULL, 0, + lut3d, lut3d_size); if (r) return r; +#endif /* Note: OGAM is disabled if 3D LUT is successfully programmed. * See params and set_output_gamma in * dcn30_set_output_transfer_func() --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46F3BC77B60 for ; Sun, 23 Apr 2023 14:50:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230239AbjDWOuM (ORCPT ); Sun, 23 Apr 2023 10:50:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230403AbjDWOuG (ORCPT ); Sun, 23 Apr 2023 10:50:06 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C092110FD for ; Sun, 23 Apr 2023 07:49:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=T0QU+rn3vH/vhCGh2w+pB+FknzjEXDis7z0wQd69Ucg=; b=KsvdnIDgtkN+mFU1/LngtyfA5d lPyshycpBtzRBocFDJHhbU6OKz0Nx9xNY/ss/256mIatnlh/+QjyHXA9VflaBhksFTaB2+LLTNqim nY/ibVox19zMD8loxRtvUGRZJ9OmAHZB6PpRd14AlUdYZnCthOWrN0HzO/DI563ikaSL5km9038kP bTpMqgm8XDDlxswpF2w5R38RZmWCbU0z4qhDSPA5IA19gP2siJ375VQ+1wex5YCQejDPDOOSxHJgf 6Er7CXzS621K2NtHFnotO0C0hgoJ62h2XqZsQH1BPurnaIyuhT93Yc9EJq/YbCDGaCyB8S46zZYh/ oqFL8WPg==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaSv-00ANVs-J8; Sun, 23 Apr 2023 16:13:21 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 25/40] drm/amd/display: decouple steps to reuse in CRTC shaper LUT support Date: Sun, 23 Apr 2023 13:10:37 -0100 Message-Id: <20230423141051.702990-26-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Decouple steps of post-blending shaper LUT setup and LUT size validation according to HW caps as a preparation for DRM CRTC shaper LUT support. Signed-off-by: Melissa Wen --- .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 67 ++++++++++++++++--- 1 file changed, 58 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/driv= ers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 25010fa19bc8..672ca5e9e59c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -443,6 +443,48 @@ static void amdgpu_dm_atomic_lut3d(const struct drm_co= lor_lut *drm_lut, } } =20 +/** + * __set_input_tf - calculates the input transfer function based on expect= ed + * input space. + * @func: transfer function + * @lut: lookup table that defines the color space + * @lut_size: size of respective lut. + * + * Returns: + * 0 in case of success. -ENOMEM if fails. + */ +static int __set_input_tf(struct dc_transfer_func *func, + const struct drm_color_lut *lut, uint32_t lut_size) +{ + struct dc_gamma *gamma =3D NULL; + bool res; + + gamma =3D dc_create_gamma(); + if (!gamma) + return -ENOMEM; + + gamma->type =3D GAMMA_CUSTOM; + gamma->num_entries =3D lut_size; + + __drm_lut_to_dc_gamma(lut, gamma, false); + + res =3D mod_color_calculate_degamma_params(NULL, func, gamma, true); + dc_gamma_release(&gamma); + + return res ? 0 : -ENOMEM; +} + +static int amdgpu_dm_atomic_shaper_lut(struct dc_transfer_func *func_shape= r) +{ + /* We don't get DRM shaper LUT yet. We assume the input color space is al= ready + * delinearized, so we don't need a shaper LUT and we can just BYPASS + */ + func_shaper->type =3D TF_TYPE_BYPASS; + func_shaper->tf =3D TRANSFER_FUNCTION_LINEAR; + + return 0; +} + /* amdgpu_dm_atomic_shaper_lut3d - set DRM CRTC shaper LUT and 3D LUT to DC * interface * @dc: Display Core control structure @@ -486,15 +528,23 @@ static int amdgpu_dm_atomic_shaper_lut3d(struct dc *d= c, if (!acquire) return 0; =20 - /* We don't get DRM shaper LUT yet. We assume the input color - * space is already delinearized, so we don't need a shaper LUT - * and we can just BYPASS. - */ - func_shaper->type =3D TF_TYPE_BYPASS; - func_shaper->tf =3D TRANSFER_FUNCTION_LINEAR; amdgpu_dm_atomic_lut3d(drm_lut3d, drm_lut3d_size, lut3d_func); =20 - return 0; + return amdgpu_dm_atomic_shaper_lut(func_shaper); +} + +/** + * amdgpu_dm_lut3d_size - get expected size according to hw color caps + * @adev: amdgpu device + * @lut_size: default size + * + * Return: + * lut_size if DC 3D LUT is supported, zero otherwise. + */ +static uint32_t amdgpu_dm_get_lut3d_size(struct amdgpu_device *adev, + uint32_t lut_size) +{ + return adev->dm.dc->caps.color.mpc.num_3dluts ? lut_size : 0; } =20 /** @@ -516,8 +566,7 @@ int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *a= dev, struct dm_crtc_state *acrtc_state =3D to_dm_crtc_state(crtc_state); uint32_t exp_size, size; =20 - exp_size =3D adev->dm.dc->caps.color.mpc.num_3dluts ? - MAX_COLOR_3DLUT_ENTRIES : 0; + exp_size =3D amdgpu_dm_get_lut3d_size(adev, MAX_COLOR_3DLUT_ENTRIES); =20 lut3d =3D __extract_blob_lut(acrtc_state->lut3d, &size); =20 --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9CC89C6FD18 for ; Sun, 23 Apr 2023 14:49:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229796AbjDWOt3 (ORCPT ); Sun, 23 Apr 2023 10:49:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55326 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230325AbjDWOtX (ORCPT ); Sun, 23 Apr 2023 10:49:23 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 57FE82D50 for ; Sun, 23 Apr 2023 07:49:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=Muyaau4YvOlEED9C4uAM8ak2NdSxTNzeXN9VmH4gVg8=; b=RIi/I6X7R9U2EXTQ/46iYBOgt/ Q16kxpKaEe9OCsrh6q1xeW46Kdite61TIWCNgJO7BP2xVORvhdoAlVp/FPTGO1UEsL0YSP6HvsX6v 3DVGj2y8myl1uSjUAxLlH3PWtJPvmgwJQts9Jk9zsMX/3ZhuXm5nEupcNFflaIaSy/aL6UNK4x0/n PHuvrrunJQIMhtBoZovf0grLgxPWY1blvEKTahV9ca8F1GuZkloaqyjbURld8CZJ7A5l+AYaeFDzd nrjgbi5Uuf6UaEvPqJKVA/r8qHHpGLEnnXsh2aub327MWsVnlW/v5DIy0yOLKtwbrayNuePqlougm yQArAa1g==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaSy-00ANVs-8n; Sun, 23 Apr 2023 16:13:24 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 26/40] drm/amd/display: add CRTC shaper LUT support to amd color pipeline Date: Sun, 23 Apr 2023 13:10:38 -0100 Message-Id: <20230423141051.702990-27-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Now, we can use DRM CRTC shaper LUT to delinearize and/or normalize the color space for a more efficient 3D LUT support (so far, only for DRM atomic color mgmt). If a degamma 1D LUT is passed to linearize the color space, a custom shaper 1D LUT can be used before applying 3D LUT. NOTE: although DRM CRTC shaper and 3D LUTs are optional properties, from our tests, AMD HW doesn't allow 3D LUT when shaper LUT is set to BYPASS (without user shaper LUT) Signed-off-by: Melissa Wen --- .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 81 +++++++++---------- 1 file changed, 38 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/driv= ers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 672ca5e9e59c..ff29be3929af 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -443,46 +443,26 @@ static void amdgpu_dm_atomic_lut3d(const struct drm_c= olor_lut *drm_lut, } } =20 -/** - * __set_input_tf - calculates the input transfer function based on expect= ed - * input space. - * @func: transfer function - * @lut: lookup table that defines the color space - * @lut_size: size of respective lut. - * - * Returns: - * 0 in case of success. -ENOMEM if fails. - */ -static int __set_input_tf(struct dc_transfer_func *func, - const struct drm_color_lut *lut, uint32_t lut_size) +static int amdgpu_dm_atomic_shaper_lut(const struct drm_color_lut *shaper_= lut, + uint32_t shaper_size, + struct dc_transfer_func *func_shaper) { - struct dc_gamma *gamma =3D NULL; - bool res; - - gamma =3D dc_create_gamma(); - if (!gamma) - return -ENOMEM; - - gamma->type =3D GAMMA_CUSTOM; - gamma->num_entries =3D lut_size; - - __drm_lut_to_dc_gamma(lut, gamma, false); - - res =3D mod_color_calculate_degamma_params(NULL, func, gamma, true); - dc_gamma_release(&gamma); + int ret =3D 0; =20 - return res ? 0 : -ENOMEM; -} + if (shaper_size) { + /* If DRM shaper LUT is set, we assume a linear color space + * (linearized by DRM degamma 1D LUT or not) + */ + func_shaper->type =3D TF_TYPE_DISTRIBUTED_POINTS; + func_shaper->tf =3D TRANSFER_FUNCTION_LINEAR; =20 -static int amdgpu_dm_atomic_shaper_lut(struct dc_transfer_func *func_shape= r) -{ - /* We don't get DRM shaper LUT yet. We assume the input color space is al= ready - * delinearized, so we don't need a shaper LUT and we can just BYPASS - */ - func_shaper->type =3D TF_TYPE_BYPASS; - func_shaper->tf =3D TRANSFER_FUNCTION_LINEAR; + ret =3D __set_output_tf(func_shaper, shaper_lut, shaper_size, false); + } else { + func_shaper->type =3D TF_TYPE_BYPASS; + func_shaper->tf =3D TRANSFER_FUNCTION_LINEAR; + } =20 - return 0; + return ret; } =20 /* amdgpu_dm_atomic_shaper_lut3d - set DRM CRTC shaper LUT and 3D LUT to DC @@ -530,7 +510,8 @@ static int amdgpu_dm_atomic_shaper_lut3d(struct dc *dc, =20 amdgpu_dm_atomic_lut3d(drm_lut3d, drm_lut3d_size, lut3d_func); =20 - return amdgpu_dm_atomic_shaper_lut(func_shaper); + return amdgpu_dm_atomic_shaper_lut(drm_shaper_lut, + drm_shaper_size, func_shaper); } =20 /** @@ -562,12 +543,22 @@ static uint32_t amdgpu_dm_get_lut3d_size(struct amdgp= u_device *adev, int amdgpu_dm_verify_lut3d_size(struct amdgpu_device *adev, const struct drm_crtc_state *crtc_state) { - const struct drm_color_lut *lut3d =3D NULL; struct dm_crtc_state *acrtc_state =3D to_dm_crtc_state(crtc_state); + const struct drm_color_lut *shaper =3D NULL, *lut3d =3D NULL; uint32_t exp_size, size; =20 - exp_size =3D amdgpu_dm_get_lut3d_size(adev, MAX_COLOR_3DLUT_ENTRIES); + /* shaper LUT is only available if 3D LUT color caps*/ + exp_size =3D amdgpu_dm_get_lut3d_size(adev, MAX_COLOR_LUT_ENTRIES); + shaper =3D __extract_blob_lut(acrtc_state->shaper_lut, &size); =20 + if (shaper && size !=3D exp_size) { + DRM_DEBUG_DRIVER( + "Invalid Shaper LUT size. Should be %u but got %u.\n", + exp_size, size); + return -EINVAL; + } + + exp_size =3D amdgpu_dm_get_lut3d_size(adev, MAX_COLOR_3DLUT_ENTRIES); lut3d =3D __extract_blob_lut(acrtc_state->lut3d, &size); =20 if (lut3d && size !=3D exp_size) { @@ -652,14 +643,15 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_s= tate *crtc, bool is_legacy; int r; #ifdef CONFIG_STEAM_DECK - const struct drm_color_lut *lut3d; - uint32_t lut3d_size; + const struct drm_color_lut *shaper_lut, *lut3d; + uint32_t shaper_size, lut3d_size; =20 r =3D amdgpu_dm_verify_lut3d_size(adev, &crtc->base); if (r) return r; =20 lut3d =3D __extract_blob_lut(crtc->lut3d, &lut3d_size); + shaper_lut =3D __extract_blob_lut(crtc->shaper_lut, &shaper_size); #endif =20 r =3D amdgpu_dm_verify_lut_sizes(&crtc->base); @@ -711,11 +703,14 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_s= tate *crtc, } else { #ifdef CONFIG_STEAM_DECK lut3d_size =3D lut3d !=3D NULL ? lut3d_size : 0; + shaper_size =3D shaper_lut !=3D NULL ? shaper_size : 0; r =3D amdgpu_dm_atomic_shaper_lut3d(adev->dm.dc, ctx, stream, - NULL, 0, + shaper_lut, shaper_size, lut3d, lut3d_size); - if (r) + if (r) { + DRM_DEBUG_DRIVER("Failed on shaper/3D LUTs setup\n"); return r; + } #endif /* Note: OGAM is disabled if 3D LUT is successfully programmed. * See params and set_output_gamma in --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4239CC6FD18 for ; Sun, 23 Apr 2023 14:15:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230224AbjDWOPa (ORCPT ); Sun, 23 Apr 2023 10:15:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34360 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230342AbjDWOPV (ORCPT ); Sun, 23 Apr 2023 10:15:21 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6751330F5 for ; Sun, 23 Apr 2023 07:14:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=Hj+41OAGChCkaIi9YXRqlEYXZ5g/+UsZBvfDycRkUvs=; b=AQBnmpqHLmaGWXY8B+vvIMQ5fI FsT0iFt+CjslQ7cEGoxl5K2M+FTdDpUAE464kVGnbtKcrwodU4Fa3RwE1+wj2mUDdr0Ata/aqt1OG ie1fkBpZFsFebdeOabZum2K/5ateXqXV+un/E5r6SmgwKPbpYAbotaH4PPQfti7K5bbrrQmoIqK1+ bL+Uh06UrTyrUCWImEsm4bsY6cXMPU3w3cmksPrJB3QaDazsTdT7Qiq3X8IK1RtU0MNhFKuDlcWnF nbgWCSheuGPQaW2ADYc7XKBg2xwcq384WVArUiI0qhWKruD79KY/RKvcuPwLyhNvPR0rVyz8DA6Cz QXAsGmPg==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaT1-00ANVs-I6; Sun, 23 Apr 2023 16:13:27 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , linux-kernel@vger.kernel.org Subject: [RFC PATCH 27/40] drm/amd/display: add CRTC regamma TF support Date: Sun, 23 Apr 2023 13:10:39 -0100 Message-Id: <20230423141051.702990-28-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Joshua Ashton Add predefined transfer function programming. There is no out gamma ROM, but we can use AMD color modules to program LUT parameters from a predefined TF and an empty regamma LUT (or power LUT parameters with predefined TF setup). Signed-off-by: Joshua Ashton --- .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 60 ++++++++++++++----- 1 file changed, 44 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/driv= ers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index ff29be3929af..55aa876a5008 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -268,16 +268,18 @@ static int __set_output_tf(struct dc_transfer_func *f= unc, struct calculate_buffer cal_buffer =3D {0}; bool res; =20 - ASSERT(lut && lut_size =3D=3D MAX_COLOR_LUT_ENTRIES); - cal_buffer.buffer_index =3D -1; =20 - gamma =3D dc_create_gamma(); - if (!gamma) - return -ENOMEM; + if (lut_size) { + ASSERT(lut && lut_size =3D=3D MAX_COLOR_LUT_ENTRIES); =20 - gamma->num_entries =3D lut_size; - __drm_lut_to_dc_gamma(lut, gamma, false); + gamma =3D dc_create_gamma(); + if (!gamma) + return -ENOMEM; + + gamma->num_entries =3D lut_size; + __drm_lut_to_dc_gamma(lut, gamma, false); + } =20 if (func->tf =3D=3D TRANSFER_FUNCTION_LINEAR) { /* @@ -285,30 +287,34 @@ static int __set_output_tf(struct dc_transfer_func *f= unc, * on top of a linear input. But degamma params can be used * instead to simulate this. */ - gamma->type =3D GAMMA_CUSTOM; + if (gamma) + gamma->type =3D GAMMA_CUSTOM; res =3D mod_color_calculate_degamma_params(NULL, func, - gamma, true); + gamma, gamma !=3D NULL); } else { /* * Assume sRGB. The actual mapping will depend on whether the * input was legacy or not. */ - gamma->type =3D GAMMA_CS_TFM_1D; - res =3D mod_color_calculate_regamma_params(func, gamma, false, + if (gamma) + gamma->type =3D GAMMA_CS_TFM_1D; + res =3D mod_color_calculate_regamma_params(func, gamma, gamma !=3D NULL, has_rom, NULL, &cal_buffer); } =20 - dc_gamma_release(&gamma); + if (gamma) + dc_gamma_release(&gamma); =20 return res ? 0 : -ENOMEM; } =20 static int amdgpu_dm_set_atomic_regamma(struct dc_stream_state *stream, const struct drm_color_lut *regamma_lut, - uint32_t regamma_size, bool has_rom) + uint32_t regamma_size, bool has_rom, + enum dc_transfer_func_predefined tf) { int ret =3D 0; - if (regamma_size) { + if (regamma_size || tf !=3D TRANSFER_FUNCTION_LINEAR) { /* CRTC RGM goes into RGM LUT. * * Note: there is no implicit sRGB regamma here. We are using @@ -316,7 +322,7 @@ static int amdgpu_dm_set_atomic_regamma(struct dc_strea= m_state *stream, * from a linear base. */ stream->out_transfer_func->type =3D TF_TYPE_DISTRIBUTED_POINTS; - stream->out_transfer_func->tf =3D TRANSFER_FUNCTION_LINEAR; + stream->out_transfer_func->tf =3D tf; =20 ret =3D __set_output_tf(stream->out_transfer_func, regamma_lut, regamma_size, has_rom); @@ -364,6 +370,25 @@ static int __set_input_tf(struct dc_transfer_func *fun= c, } =20 #ifdef CONFIG_STEAM_DECK +static enum dc_transfer_func_predefined drm_tf_to_dc_tf(enum drm_transfer_= function drm_tf) +{ + switch (drm_tf) + { + default: + case DRM_TRANSFER_FUNCTION_DEFAULT: return TRANSFER_FUNCTION_LINEAR; + case DRM_TRANSFER_FUNCTION_SRGB: return TRANSFER_FUNCTION_SRGB; + + case DRM_TRANSFER_FUNCTION_BT709: return TRANSFER_FUNCTION_BT709; + case DRM_TRANSFER_FUNCTION_PQ: return TRANSFER_FUNCTION_PQ; + case DRM_TRANSFER_FUNCTION_LINEAR: return TRANSFER_FUNCTION_LINEAR; + case DRM_TRANSFER_FUNCTION_UNITY: return TRANSFER_FUNCTION_UNITY; + case DRM_TRANSFER_FUNCTION_HLG: return TRANSFER_FUNCTION_HLG; + case DRM_TRANSFER_FUNCTION_GAMMA22: return TRANSFER_FUNCTION_GAMMA22; + case DRM_TRANSFER_FUNCTION_GAMMA24: return TRANSFER_FUNCTION_GAMMA24; + case DRM_TRANSFER_FUNCTION_GAMMA26: return TRANSFER_FUNCTION_GAMMA26; + } +} + static void __to_dc_lut3d_color(struct dc_rgb *rgb, const struct drm_color_lut lut, int bit_precision) @@ -640,6 +665,7 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_sta= te *crtc, const struct drm_color_lut *degamma_lut, *regamma_lut; uint32_t degamma_size, regamma_size; bool has_regamma, has_degamma; + enum dc_transfer_func_predefined tf =3D TRANSFER_FUNCTION_LINEAR; bool is_legacy; int r; #ifdef CONFIG_STEAM_DECK @@ -652,6 +678,8 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_sta= te *crtc, =20 lut3d =3D __extract_blob_lut(crtc->lut3d, &lut3d_size); shaper_lut =3D __extract_blob_lut(crtc->shaper_lut, &shaper_size); + + tf =3D drm_tf_to_dc_tf(crtc->gamma_tf); #endif =20 r =3D amdgpu_dm_verify_lut_sizes(&crtc->base); @@ -718,7 +746,7 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_sta= te *crtc, */ regamma_size =3D has_regamma ? regamma_size : 0; r =3D amdgpu_dm_set_atomic_regamma(stream, regamma_lut, - regamma_size, has_rom); + regamma_size, has_rom, tf); if (r) return r; } --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21348C6FD18 for ; Sun, 23 Apr 2023 14:46:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230445AbjDWOqv (ORCPT ); Sun, 23 Apr 2023 10:46:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51972 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230418AbjDWOqo (ORCPT ); Sun, 23 Apr 2023 10:46:44 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90F7EE7C for ; Sun, 23 Apr 2023 07:46:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=8bT2ob0F8OaOVr4E4QYrwsso9uTEpOktmlUklSt8S/Q=; b=H0v1vztIlXOcj+FbNVovVSfxmS uLfgMVTH0Tki6M+t52HV7T8tsXMELFNbTc3nzcvA7RlIaoHnDJeegiil6v16jjibd/nQz/9L4qMJX wauTFprY5PTOrGaOSGSplXdDZUyQUHu/vGwbL5lwB5tGqmIzoNlOQ1NkmE70Gpmj03LNksO09AYX9 SFNmhLnRr9IPKs7Y1KiMqzrJ5wiKkpi3BPbmThmETI5lrb9MWUwiO+Kfg/WLQK6+/mnmQlqbRTsnJ ySloYFH2oXHJLsYK4stG70OUmDEi48Tw/b30wioMj19hLgbrzLZAJZenJGrDWEFhh9qdIze1upjSW HO2SnzWQ==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaT4-00ANVs-5O; Sun, 23 Apr 2023 16:13:30 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , linux-kernel@vger.kernel.org Subject: [RFC PATCH 28/40] drm/amd/display: set sdr_ref_white_level to 80 for out_transfer_func Date: Sun, 23 Apr 2023 13:10:40 -0100 Message-Id: <20230423141051.702990-29-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Joshua Ashton Otherwise this is just initialized to 0. This needs to actually have a value so that compute_curve can work for PQ EOTF. Signed-off-by: Joshua Ashton --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/driv= ers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 55aa876a5008..6e7271065a56 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -323,6 +323,7 @@ static int amdgpu_dm_set_atomic_regamma(struct dc_strea= m_state *stream, */ stream->out_transfer_func->type =3D TF_TYPE_DISTRIBUTED_POINTS; stream->out_transfer_func->tf =3D tf; + stream->out_transfer_func->sdr_ref_white_level =3D 80; =20 ret =3D __set_output_tf(stream->out_transfer_func, regamma_lut, regamma_size, has_rom); --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9474CC6FD18 for ; Sun, 23 Apr 2023 14:46:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230387AbjDWOqi (ORCPT ); Sun, 23 Apr 2023 10:46:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230326AbjDWOqg (ORCPT ); Sun, 23 Apr 2023 10:46:36 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24AF1E77 for ; Sun, 23 Apr 2023 07:46:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=lxN4o+4K+4Z4seUWpOvL7AAr75VVAUYJY+xnqLiCvUc=; b=ldnqTfdyEMGI4mbqShp9tr/liM YQTTbJw6WaTPud7IYSxZwA15m0J2bA8x23c73MjMq3kNtQd0Jt3KBobOZIBCzCb2XLvELGfbF/Qt7 eGDG9ZbCwoCkHFAKeP6qIoASRP+4hAHQqHkrEP+cEHDHNFSYvhmXDThVVCXcHMnApgb+tjAxqBGo6 6WAksnjMAdCXgRzIOxcu8T1hxp4gNNFaOl7PEijhMtUOop4Ao5ZSPsvN+N3pCUvbL17vhApJQ1xAn D+OXavQ94QlAL5RXXZVKQ6pgFQJoDRp+jeu2lzhWn/8vXDnUSLOqizYX5SuVqIKCsMhsokaJmtKSw DGzMjzdQ==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaT7-00ANVs-0P; Sun, 23 Apr 2023 16:13:33 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 29/40] drm/amd/display: add CRTC shaper TF support Date: Sun, 23 Apr 2023 13:10:41 -0100 Message-Id: <20230423141051.702990-30-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Inspired by regamma TF, follow similar steps to add TF + 1D LUT for shaper func. Reuse gamma_tf property, since the driver doesn't support shaper and out gamma at the same time. We could rename gamma_tf, if necessary to avoid misunderstandings, or add a specific property for shaper lut. Signed-off-by: Melissa Wen --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/driv= ers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 6e7271065a56..6a233380f284 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -470,19 +470,22 @@ static void amdgpu_dm_atomic_lut3d(const struct drm_c= olor_lut *drm_lut, } =20 static int amdgpu_dm_atomic_shaper_lut(const struct drm_color_lut *shaper_= lut, + bool has_rom, + enum dc_transfer_func_predefined tf, uint32_t shaper_size, struct dc_transfer_func *func_shaper) { int ret =3D 0; =20 - if (shaper_size) { + if (shaper_size || tf !=3D TRANSFER_FUNCTION_LINEAR) { /* If DRM shaper LUT is set, we assume a linear color space * (linearized by DRM degamma 1D LUT or not) */ func_shaper->type =3D TF_TYPE_DISTRIBUTED_POINTS; - func_shaper->tf =3D TRANSFER_FUNCTION_LINEAR; + func_shaper->tf =3D tf; + func_shaper->sdr_ref_white_level =3D 80; /* hardcoded for now */ =20 - ret =3D __set_output_tf(func_shaper, shaper_lut, shaper_size, false); + ret =3D __set_output_tf(func_shaper, shaper_lut, shaper_size, has_rom); } else { func_shaper->type =3D TF_TYPE_BYPASS; func_shaper->tf =3D TRANSFER_FUNCTION_LINEAR; @@ -509,12 +512,14 @@ static int amdgpu_dm_atomic_shaper_lut3d(struct dc *d= c, struct dc_stream_state *stream, const struct drm_color_lut *drm_shaper_lut, uint32_t drm_shaper_size, + bool has_rom, + enum dc_transfer_func_predefined tf, const struct drm_color_lut *drm_lut3d, uint32_t drm_lut3d_size) { struct dc_3dlut *lut3d_func; struct dc_transfer_func *func_shaper; - bool acquire =3D drm_shaper_size || drm_lut3d_size; + bool acquire =3D drm_shaper_size || drm_lut3d_size || tf !=3D TRANSFER_FU= NCTION_LINEAR; =20 lut3d_func =3D (struct dc_3dlut *)stream->lut3d_func; func_shaper =3D (struct dc_transfer_func *)stream->func_shaper; @@ -536,7 +541,7 @@ static int amdgpu_dm_atomic_shaper_lut3d(struct dc *dc, =20 amdgpu_dm_atomic_lut3d(drm_lut3d, drm_lut3d_size, lut3d_func); =20 - return amdgpu_dm_atomic_shaper_lut(drm_shaper_lut, + return amdgpu_dm_atomic_shaper_lut(drm_shaper_lut, has_rom, tf, drm_shaper_size, func_shaper); } =20 @@ -735,6 +740,7 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_sta= te *crtc, shaper_size =3D shaper_lut !=3D NULL ? shaper_size : 0; r =3D amdgpu_dm_atomic_shaper_lut3d(adev->dm.dc, ctx, stream, shaper_lut, shaper_size, + has_rom, tf, lut3d, lut3d_size); if (r) { DRM_DEBUG_DRIVER("Failed on shaper/3D LUTs setup\n"); --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D079C77B60 for ; Sun, 23 Apr 2023 14:50:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230481AbjDWOuW (ORCPT ); Sun, 23 Apr 2023 10:50:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230459AbjDWOuP (ORCPT ); Sun, 23 Apr 2023 10:50:15 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CA67010FB for ; Sun, 23 Apr 2023 07:50:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=uJMJ+NQtZ0XpbgcU5B6V/mq7bccUXUSsHINPFl3Guj4=; b=IhYMosca0wZ+B+VisCfWEo1sGl 2lQqN8jG09ZDejv+mI53UicwpH5fMnjrZ7Qb1/2dEKmd1yy8nzkvK5Smrs5Qs5WkHkJBoDmHf7AXh dlFAcJyDtpRMTgve+Hn1N7bZgZFmywRF/8ixSlzrFpgc403gIrKQBwen7HpIZWEDuAvrIEIUTJGgj /YmI1sY85xnZ+R1ppu+GGQV3wFqCyEREfiAwopG5AiSOs2UJIObEJ4Pf9H1xEaGDXDfC7X2yToqGc Lk4A819xB5lK1Pt7F++wJ6WUqOg6Z3Z+XzMdwPWZEv/pK6DyL5Fda3ja7GU4gse57Nis3N+nvF2yr QZA5shMQ==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaTA-00ANVs-Ad; Sun, 23 Apr 2023 16:13:36 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 30/40] drm/amd/display: mark plane as needing reset if plane color mgmt changes Date: Sun, 23 Apr 2023 13:10:42 -0100 Message-Id: <20230423141051.702990-31-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We took a similar path for CRTC color mgmt changes, since we remap CRTC degamma to plane/DPP block. Here we can use the status of `plane->color_mgmt_changed` to detect when a plane color property changed and recreate the plane accordingly. Co-developed-by: Joshua Ashton Signed-off-by: Joshua Ashton Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gp= u/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 760080e4a4da..1dac311cab67 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -9441,6 +9441,9 @@ static bool should_reset_plane(struct drm_atomic_stat= e *state, if (drm_atomic_crtc_needs_modeset(new_crtc_state)) return true; =20 + if (new_plane_state->color_mgmt_changed) + return true; + /* * If there are any new primary or overlay planes being added or * removed then the z-order can potentially change. To ensure --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97645C77B60 for ; Sun, 23 Apr 2023 14:49:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230421AbjDWOtL (ORCPT ); Sun, 23 Apr 2023 10:49:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55148 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230170AbjDWOtF (ORCPT ); Sun, 23 Apr 2023 10:49:05 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E541B1FD8 for ; Sun, 23 Apr 2023 07:48:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=QwuSO2LNJ+LJ1+yrvEcZOrqAYwcz+YFmvLiCu9u3lbQ=; b=mORa53lOjf6BQPulDyK5c+ctGp 7OS8D5hV+ZI9NRVY0Ypu6IY6WqiF0u0PogOM0YVPNCTSHAZv21TK2yltFeu/NOinJ5+GZDwCB8sIE XA2LN+prpg73D38iJoWmtLIxa5fZEQvsITh/jOLw7H43mP2xHOClrJnhXK8nwhrSnZlA7jJiRxwMo AcSCwp8ShKkdKEEZeFf0qUdetr2sbbhPccegDIUB1NCLhEWKf/hNebglaABOnRm6OA+ylqMCgVas3 VvKi5XzfLqcTNLiddrsRsJYHNLCQl/x982gL31yJZNkebLSzsCoJKFm5A1IFgEq6EuGdTydUlVViZ WfDpbpnQ==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaTD-00ANVs-Ax; Sun, 23 Apr 2023 16:13:39 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 31/40] drm/amd/display: decouple steps for mapping CRTC degamma to DC plane Date: Sun, 23 Apr 2023 13:10:43 -0100 Message-Id: <20230423141051.702990-32-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The next patch adds pre-blending degamma to AMD color mgmt pipeline, but pre-blending degamma caps (DPP) is currently in use to provide DRM CRTC atomic degamma or implict degamma on legacy gamma. Detach degamma usage regarging CRTC color properties to manage plane and CRTC color correction combinations. Signed-off-by: Melissa Wen --- .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 55 +++++++++++++------ 1 file changed, 38 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/driv= ers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 6a233380f284..518082222fff 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -791,20 +791,8 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_st= ate *crtc, return 0; } =20 -/** - * amdgpu_dm_update_plane_color_mgmt: Maps DRM color management to DC plan= e. - * @crtc: amdgpu_dm crtc state - * @dc_plane_state: target DC surface - * - * Update the underlying dc_stream_state's input transfer function (ITF) in - * preparation for hardware commit. The transfer function used depends on - * the preparation done on the stream for color management. - * - * Returns: - * 0 on success. -ENOMEM if mem allocation fails. - */ -int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, - struct dc_plane_state *dc_plane_state) +static int map_crtc_degamma_to_dc_plane(struct dm_crtc_state *crtc, + struct dc_plane_state *dc_plane_state) { const struct drm_color_lut *degamma_lut; enum dc_transfer_func_predefined tf =3D TRANSFER_FUNCTION_SRGB; @@ -827,8 +815,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_st= ate *crtc, °amma_size); ASSERT(degamma_size =3D=3D MAX_COLOR_LUT_ENTRIES); =20 - dc_plane_state->in_transfer_func->type =3D - TF_TYPE_DISTRIBUTED_POINTS; + dc_plane_state->in_transfer_func->type =3D TF_TYPE_DISTRIBUTED_POINTS; =20 /* * This case isn't fully correct, but also fairly @@ -864,7 +851,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_st= ate *crtc, degamma_lut, degamma_size); if (r) return r; - } else if (crtc->cm_is_degamma_srgb) { + } else { /* * For legacy gamma support we need the regamma input * in linear space. Assume that the input is sRGB. @@ -876,6 +863,40 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_s= tate *crtc, !mod_color_calculate_degamma_params(NULL, dc_plane_state->in_transfer_func, NULL, false)) return -ENOMEM; + } + + return 0; +} + +/** + * amdgpu_dm_update_plane_color_mgmt: Maps DRM color management to DC plan= e. + * @crtc: amdgpu_dm crtc state + * @dc_plane_state: target DC surface + * + * Update the underlying dc_stream_state's input transfer function (ITF) in + * preparation for hardware commit. The transfer function used depends on + * the preparation done on the stream for color management. + * + * Returns: + * 0 on success. -ENOMEM if mem allocation fails. + */ +int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, + struct dc_plane_state *dc_plane_state) +{ + bool has_crtc_cm_degamma; + int ret; + + has_crtc_cm_degamma =3D (crtc->cm_has_degamma || crtc->cm_is_degamma_srgb= ); + if (has_crtc_cm_degamma){ + /* AMD HW doesn't have post-blending degamma caps. When DRM + * CRTC atomic degamma is set, we maps it to DPP degamma block + * (pre-blending) or, on legacy gamma, we use DPP degamma to + * linearize (implicit degamma) from sRGB/BT709 according to + * the input space. + */ + ret =3D map_crtc_degamma_to_dc_plane(crtc, dc_plane_state); + if (ret) + return ret; } else { /* ...Otherwise we can just bypass the DGM block. */ dc_plane_state->in_transfer_func->type =3D TF_TYPE_BYPASS; --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7297C77B60 for ; Sun, 23 Apr 2023 14:48:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229526AbjDWOr7 (ORCPT ); Sun, 23 Apr 2023 10:47:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53788 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229948AbjDWOrz (ORCPT ); Sun, 23 Apr 2023 10:47:55 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 74CCF2D57 for ; Sun, 23 Apr 2023 07:47:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=/W4Otev8naKI+sTtsOTBF0+9f4KzatyGi8o5pO95DCc=; b=pccns+OHh+ISutnzDBzunpavg5 2jNNXAWTA3OhX/+/uK59iGeX89oRWnewx768uhx1o6BKUrJNxIjW+b1a+DtS5ZSKCUWFtEKnX21f1 SPVY/Hghr7FjxlcNuYexPZuiSIop9McU/7Z1LmdCQGfdY/ZK1ime3A/8vefdoZeTtQckJlJ4TuywT JVEScpNQqXPJDmxkUW9sHzVxVtasQzZTOkKZ0aBtfY7qAZtDXkb6Q0nYEOQ3GCNgJJMgdnpSd1KVU PNWQQ7FD7BxUqH8cbfKv73KTbY9ZIpVecTnoQqQzqcRxLjEqGTWe5rjpdmnnKjP9p7/bwo0+905e+ +cS9yeaw==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaTI-00ANVs-GJ; Sun, 23 Apr 2023 16:13:44 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , linux-kernel@vger.kernel.org Subject: [RFC PATCH 32/40] drm/amd/display: add support for plane degamma TF and LUT properties Date: Sun, 23 Apr 2023 13:10:44 -0100 Message-Id: <20230423141051.702990-33-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Joshua Ashton We only set CRTC degamma if we don't have plane degamma LUT or TF to configure. We return -EINVAL if we don't have plane degamma settings, so we can continue and check CRTC degamma. Signed-off-by: Joshua Ashton --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 + .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 71 +++++++++++++++++-- 3 files changed, 70 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gp= u/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 1dac311cab67..c0321272c129 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5043,7 +5043,9 @@ static int fill_dc_plane_attributes(struct amdgpu_dev= ice *adev, * Always set input transfer function, since plane state is refreshed * every time. */ - ret =3D amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state); + ret =3D amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, + plane_state, + dc_plane_state); if (ret) return ret; =20 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gp= u/drm/amd/display/amdgpu_dm/amdgpu_dm.h index b9840c1f3cdf..bcf74b7391c9 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -912,6 +912,7 @@ int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_st= ate *crtc_state); int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc, struct dc_state *ctx); int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, + struct drm_plane_state *plane_state, struct dc_plane_state *dc_plane_state); =20 void amdgpu_dm_update_connector_after_detect( diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/driv= ers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 518082222fff..693168cc1d9c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -868,9 +868,59 @@ static int map_crtc_degamma_to_dc_plane(struct dm_crtc= _state *crtc, return 0; } =20 +#ifdef CONFIG_STEAM_DECK +static int +__set_dm_plane_degamma(struct drm_plane_state *plane_state, + struct dc_plane_state *dc_plane_state) +{ + struct dm_plane_state *dm_plane_state =3D to_dm_plane_state(plane_state); + const struct drm_color_lut *degamma_lut; + enum drm_transfer_function drm_tf =3D DRM_TRANSFER_FUNCTION_DEFAULT; + uint32_t degamma_size; + bool has_degamma_lut; + int ret; + + degamma_lut =3D __extract_blob_lut(dm_plane_state->degamma_lut, °amma_= size); + + has_degamma_lut =3D degamma_lut && + !__is_lut_linear(degamma_lut, degamma_size); + + drm_tf =3D dm_plane_state->degamma_tf; + + /* If we don't have plane degamma LUT nor TF to set on DC, we have + * nothing to do here, return. + */ + if (!has_degamma_lut && drm_tf =3D=3D DRM_TRANSFER_FUNCTION_DEFAULT) + return -EINVAL; + + dc_plane_state->in_transfer_func->tf =3D drm_tf_to_dc_tf(drm_tf); + + if (has_degamma_lut) { + ASSERT(degamma_size =3D=3D MAX_COLOR_LUT_ENTRIES); + + dc_plane_state->in_transfer_func->type =3D + TF_TYPE_DISTRIBUTED_POINTS; + + ret =3D __set_input_tf(dc_plane_state->in_transfer_func, + degamma_lut, degamma_size); + if (ret) + return ret; + } else { + dc_plane_state->in_transfer_func->type =3D + TF_TYPE_PREDEFINED; + + if (!mod_color_calculate_degamma_params(NULL, + dc_plane_state->in_transfer_func, NULL, false)) + return -ENOMEM; + } + return 0; +} +#endif + /** * amdgpu_dm_update_plane_color_mgmt: Maps DRM color management to DC plan= e. * @crtc: amdgpu_dm crtc state + * @plane_state: DRM plane state * @dc_plane_state: target DC surface * * Update the underlying dc_stream_state's input transfer function (ITF) in @@ -881,13 +931,28 @@ static int map_crtc_degamma_to_dc_plane(struct dm_crt= c_state *crtc, * 0 on success. -ENOMEM if mem allocation fails. */ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, + struct drm_plane_state *plane_state, struct dc_plane_state *dc_plane_state) { bool has_crtc_cm_degamma; int ret; =20 + /* Initially, we can just bypass the DGM block. */ + dc_plane_state->in_transfer_func->type =3D TF_TYPE_BYPASS; + dc_plane_state->in_transfer_func->tf =3D TRANSFER_FUNCTION_LINEAR; + + /* After, we start to update values according to color props */ has_crtc_cm_degamma =3D (crtc->cm_has_degamma || crtc->cm_is_degamma_srgb= ); - if (has_crtc_cm_degamma){ + +#ifdef CONFIG_STEAM_DECK + ret =3D __set_dm_plane_degamma(plane_state, dc_plane_state); + if (ret !=3D -EINVAL) + return ret; + + /* As we don't have plane degamma, check if we have CRTC degamma + * waiting for mapping to pre-blending degamma block */ +#endif + if (has_crtc_cm_degamma) { /* AMD HW doesn't have post-blending degamma caps. When DRM * CRTC atomic degamma is set, we maps it to DPP degamma block * (pre-blending) or, on legacy gamma, we use DPP degamma to @@ -897,10 +962,6 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_s= tate *crtc, ret =3D map_crtc_degamma_to_dc_plane(crtc, dc_plane_state); if (ret) return ret; - } else { - /* ...Otherwise we can just bypass the DGM block. */ - dc_plane_state->in_transfer_func->type =3D TF_TYPE_BYPASS; - dc_plane_state->in_transfer_func->tf =3D TRANSFER_FUNCTION_LINEAR; } =20 return 0; --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A15FBC6FD18 for ; Sun, 23 Apr 2023 14:15:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230353AbjDWOPw (ORCPT ); Sun, 23 Apr 2023 10:15:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35044 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230348AbjDWOPe (ORCPT ); Sun, 23 Apr 2023 10:15:34 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BBFC73C0A for ; Sun, 23 Apr 2023 07:15:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=4GQm73N05wdyDPvLOueAQrdj1CPYaUCZeKkaAs7VjXY=; b=h2ixzavpfQLRZTKkPcsvUCerpa LoWyHwwWnSdmYYg+hC/Hnz4QMtMT7U68Rvz7ux818FUzfSWXCVmsN8eWeKnzaILchgmSYHg2gwph+ ke043JYgzHR+pr+v5CcOeYqNdOt7qZFyhmctCzqoPOV6hkqIHC7As5ZjpgZ+obUKlh1VhUKyKiRw1 cI1EU41E+TYX6+B2QSNH7eFjttLv/ar2/wHCjT/hoNPLcnheUAxZp7BcSmRvGuQc/jwdRgoUnrkni PdtbyQbeh6ROOvboSKntvevX6ke1BEKqEjBabV0BoivARn+hynJAbfVGHPYXXmlTiYLSqRthR6Dfi 2ghFpcpA==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaTL-00ANVs-Dv; Sun, 23 Apr 2023 16:13:47 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 33/40] drm/amd/display: reject atomic commit if setting both plane and CRTC degamma Date: Sun, 23 Apr 2023 13:10:45 -0100 Message-Id: <20230423141051.702990-34-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" DC only has pre-blending degamma caps (pre-blending/DPP) that is currently in use for CRTC/post-blending degamma, so that we don't have HW caps to perform plane and CRTC degamma at the same time. Reject atomic updates when serspace sets both plane and CRTC degamma properties. Signed-off-by: Melissa Wen --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/driv= ers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 693168cc1d9c..07303c9f3618 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -949,6 +949,17 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_s= tate *crtc, if (ret !=3D -EINVAL) return ret; =20 + /* We only have one degamma block available (pre-blending) for the + * whole color correction pipeline, so that we can't actually perform + * plane and CRTC degamma at the same time. Reject atomic updates when + * userspace sets both plane and CRTC degamma properties. + */ + if (has_crtc_cm_degamma && ret =3D=3D -EINVAL){ + drm_dbg_kms(crtc->base.crtc->dev, + "doesn't support plane and CRTC degamma at the same time\n"); + return -EINVAL; + } + /* As we don't have plane degamma, check if we have CRTC degamma * waiting for mapping to pre-blending degamma block */ #endif --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFF1AC6FD18 for ; Sun, 23 Apr 2023 14:47:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229585AbjDWOrK (ORCPT ); Sun, 23 Apr 2023 10:47:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51958 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230256AbjDWOrF (ORCPT ); Sun, 23 Apr 2023 10:47:05 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8EBC62700 for ; Sun, 23 Apr 2023 07:46:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=P4ZXpKFMtoIv2GHYDm0O+bIMEiRHVdDFlzSdVRRjl+4=; b=Xf5xbFUlVRcMeEfF92pKTWXigX R9y7r3VyMhFpJTzPExO/MEwG3xN9AyhwDWtZ+WGoZe8rbS3sdSGEV77TDsmVhg2icLCNnhOqq/nZq C94uECAkNCXMFTBXeOewYKAf3EFwNxYGTW+54d9UbLXWJkzvXXMvDYEDMY6JWdZI3UuFi1R/PW7yj Tj6FFfM6mOlk6Uz1yKXlU+iE+uuhNX59b6Q9G3mElUuCEDTy67bzM3TKt8//1H7bEjJsGJYcuqvdB rjmy50QlYBUT/bHPct4NQfoVfgJsbb5dW5VB8BZCE7LdtB78DNXJFGVC8sjgEQWkwzlmiQy7qFtJx UHH6t3+A==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaTO-00ANVs-Pv; Sun, 23 Apr 2023 16:13:50 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , linux-kernel@vger.kernel.org Subject: [RFC PATCH 34/40] drm/amd/display: add dc_fixpt_from_s3132 helper Date: Sun, 23 Apr 2023 13:10:46 -0100 Message-Id: <20230423141051.702990-35-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Joshua Ashton Detach value translation from CTM to reuse it for programming HDR multiplier property. Signed-off-by: Joshua Ashton --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 8 +------- drivers/gpu/drm/amd/display/include/fixed31_32.h | 12 ++++++++++++ 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/driv= ers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 07303c9f3618..d714728ca143 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -182,7 +182,6 @@ static void __drm_lut_to_dc_gamma(const struct drm_colo= r_lut *lut, static void __drm_ctm_to_dc_matrix(const struct drm_color_ctm *ctm, struct fixed31_32 *matrix) { - int64_t val; int i; =20 /* @@ -201,12 +200,7 @@ static void __drm_ctm_to_dc_matrix(const struct drm_co= lor_ctm *ctm, } =20 /* gamut_remap_matrix[i] =3D ctm[i - floor(i/4)] */ - val =3D ctm->matrix[i - (i / 4)]; - /* If negative, convert to 2's complement. */ - if (val & (1ULL << 63)) - val =3D -(val & ~(1ULL << 63)); - - matrix[i].value =3D val; + matrix[i] =3D dc_fixpt_from_s3132(ctm->matrix[i - (i / 4)]); } } =20 diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h b/drivers/gpu= /drm/amd/display/include/fixed31_32.h index ece97ae0e826..f4cc7f97329f 100644 --- a/drivers/gpu/drm/amd/display/include/fixed31_32.h +++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h @@ -69,6 +69,18 @@ static const struct fixed31_32 dc_fixpt_epsilon =3D { 1L= L }; static const struct fixed31_32 dc_fixpt_half =3D { 0x80000000LL }; static const struct fixed31_32 dc_fixpt_one =3D { 0x100000000LL }; =20 +static inline struct fixed31_32 dc_fixpt_from_s3132(__u64 x) +{ + struct fixed31_32 val; + + /* If negative, convert to 2's complement. */ + if (x & (1ULL << 63)) + x =3D -(x & ~(1ULL << 63)); + + val.value =3D x; + return val; +} + /* * @brief * Initialization routines --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA074C6FD18 for ; Sun, 23 Apr 2023 14:46:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230464AbjDWOq5 (ORCPT ); Sun, 23 Apr 2023 10:46:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51970 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230426AbjDWOqs (ORCPT ); Sun, 23 Apr 2023 10:46:48 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B5411712 for ; Sun, 23 Apr 2023 07:46:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=av8LLs8d/qgSpvCdtPWbCDxJo/b1Zt+to8SoXN3tsd4=; b=Wc6qM5pMHNGlmoH2r7Y20qQVBp NKC+XbkMbfhKMprtukVJt0Z3Hzi2/3R88FYmXDbi1XMux2VfCQ2+GUIwleAJ7MPYyXb8L6kAHGn1u 39U8bG5NZyU8GtHxABQ5ystAiLdgU5DLuKmtmMtB9nWSSYFZ4tqRTNbgyGm+V5Z6bn7QoafOVYS1Z zkAg8IXz0XjRFoqPMPRuyL/a8kdnN8ItCPt57F02eEsaF5PKDCbhtTxY5/pTESDnERfs3UYazgTHS g/4hBaT+VASklXTwWmidyr07D28OJzyX3UPkqnS0VIJZ6pSolPWDiUAqHAu+Nh2AzaW1a+yzabwQY gL4oFuoA==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaTW-00ANVs-29; Sun, 23 Apr 2023 16:13:58 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , linux-kernel@vger.kernel.org Subject: [RFC PATCH 35/40] drm/adm/display: add HDR multiplier support Date: Sun, 23 Apr 2023 13:10:47 -0100 Message-Id: <20230423141051.702990-36-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Joshua Ashton With `dc_fixpt_from_s3132()` translation, we can just use it to set hdr_mult. Signed-off-by: Joshua Ashton --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gp= u/drm/amd/display/amdgpu_dm/amdgpu_dm.c index c0321272c129..0e3b6d414ec4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7991,6 +7991,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic= _state *state, bundle->surface_updates[planes_count].gamma =3D dc_plane->gamma_correct= ion; bundle->surface_updates[planes_count].in_transfer_func =3D dc_plane->in= _transfer_func; bundle->surface_updates[planes_count].gamut_remap_matrix =3D &dc_plane-= >gamut_remap_matrix; + bundle->surface_updates[planes_count].hdr_mult =3D dc_plane->hdr_mult; } =20 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/driv= ers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index d714728ca143..854510b05194 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -939,6 +939,8 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_st= ate *crtc, has_crtc_cm_degamma =3D (crtc->cm_has_degamma || crtc->cm_is_degamma_srgb= ); =20 #ifdef CONFIG_STEAM_DECK + dc_plane_state->hdr_mult =3D dc_fixpt_from_s3132(dm_plane_state->hdr_mult= ); + ret =3D __set_dm_plane_degamma(plane_state, dc_plane_state); if (ret !=3D -EINVAL) return ret; @@ -969,5 +971,6 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_st= ate *crtc, return ret; } =20 + return 0; } --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2FE76C6FD18 for ; Sun, 23 Apr 2023 14:48:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229488AbjDWOsY (ORCPT ); Sun, 23 Apr 2023 10:48:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229587AbjDWOsV (ORCPT ); Sun, 23 Apr 2023 10:48:21 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 96D5610F0 for ; Sun, 23 Apr 2023 07:47:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=j3/12jxSdcW585zS5aTXAW8FYxDjDH8xTDC6oGODNZ4=; b=gGPYg1jP8KMZzxXdI1YyTRkYWD ZOSsJyEWVsUa4GnVoAhvsXfQe5MwF/3xExwFTIXBkBhDy26yZagqaIfPPwFlbEkrrNcPp3NBd7CBE cKO/cuBPRttDjjstSCMeNkP6/A7WLmMcJoClGtyLVXAtwsZga4YDQHji8U8a1HHhz6hienUN4W++V g3vS9eYtpHFvmFYUtrlL8GLh2d9et+g2dxLs6Bzn1Ewt/J7yqREVBcR/w9pFXOxaMg5xpSPow0Sfi 02XeYziyiJQbR9xryPVYgY113jjbSkCgryI/9m2MC3TEQVdXp7BXUzlfxY8tzz68AwJZFnQMRyu1g VY7vcTog==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaTZ-00ANVs-0W; Sun, 23 Apr 2023 16:14:01 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 36/40] drm/amd/display: add plane shaper/3D LUT and shaper TF support Date: Sun, 23 Apr 2023 13:10:48 -0100 Message-Id: <20230423141051.702990-37-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We already have the steps to program post-blending shaper/3D LUT on AMD display driver, so that we can reuse them and map plane properties to DC plane for pre-blending (plane) shaper/3D LUT setup. Signed-off-by: Melissa Wen --- .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 34 +++++++++++++++++-- .../drm/amd/display/dc/dcn20/dcn20_hwseq.c | 5 +-- 2 files changed, 35 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/driv= ers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 854510b05194..e17141fc8d12 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -909,6 +909,35 @@ __set_dm_plane_degamma(struct drm_plane_state *plane_s= tate, } return 0; } + +static int +amdgpu_dm_plane_set_color_properties(struct drm_plane_state *plane_state, + struct dc_plane_state *dc_plane_state) +{ + struct dm_plane_state *dm_plane_state =3D to_dm_plane_state(plane_state); + enum drm_transfer_function shaper_tf =3D DRM_TRANSFER_FUNCTION_DEFAULT; + const struct drm_color_lut *shaper_lut, *lut3d; + uint32_t lut3d_size, shaper_size; + + /* We have nothing to do here, return */ + if (!plane_state->color_mgmt_changed) + return 0; + + dc_plane_state->hdr_mult =3D dc_fixpt_from_s3132(dm_plane_state->hdr_mult= ); + + shaper_tf =3D dm_plane_state->shaper_tf; + shaper_lut =3D __extract_blob_lut(dm_plane_state->shaper_lut, &shaper_siz= e); + lut3d =3D __extract_blob_lut(dm_plane_state->lut3d, &lut3d_size); + lut3d_size =3D lut3d !=3D NULL ? lut3d_size : 0; + shaper_size =3D shaper_lut !=3D NULL ? shaper_size : 0; + + amdgpu_dm_atomic_lut3d(lut3d, lut3d_size, dc_plane_state->lut3d_func); + ret =3D amdgpu_dm_atomic_shaper_lut(shaper_lut, false, + drm_tf_to_dc_tf(shaper_tf), + shaper_size, dc_plane_state->in_shaper_func); + + return ret; +} #endif =20 /** @@ -939,7 +968,9 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_st= ate *crtc, has_crtc_cm_degamma =3D (crtc->cm_has_degamma || crtc->cm_is_degamma_srgb= ); =20 #ifdef CONFIG_STEAM_DECK - dc_plane_state->hdr_mult =3D dc_fixpt_from_s3132(dm_plane_state->hdr_mult= ); + ret =3D amdgpu_dm_plane_set_color_properties(plane_state, dc_plane_state); + if(ret) + return ret; =20 ret =3D __set_dm_plane_degamma(plane_state, dc_plane_state); if (ret !=3D -EINVAL) @@ -971,6 +1002,5 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_s= tate *crtc, return ret; } =20 - return 0; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/g= pu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index 5800acf6aae1..91fee60410f4 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -1759,8 +1759,9 @@ static void dcn20_program_pipe( hws->funcs.set_hdr_multiplier(pipe_ctx); =20 if (pipe_ctx->update_flags.bits.enable || - pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || - pipe_ctx->plane_state->update_flags.bits.gamma_change) + pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || + pipe_ctx->plane_state->update_flags.bits.gamma_change || + pipe_ctx->plane_state->update_flags.bits.lut_3d) hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); =20 /* dcn10_translate_regamma_to_hw_format takes 750us to finish --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A9C1C6FD18 for ; Sun, 23 Apr 2023 14:16:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230377AbjDWOQB (ORCPT ); Sun, 23 Apr 2023 10:16:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35770 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230363AbjDWOPg (ORCPT ); Sun, 23 Apr 2023 10:15:36 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4BE2F3C3A for ; Sun, 23 Apr 2023 07:15:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=cUSOYLuQjdiS9Ja6dEexWHo4C4Y5Ft7LRX3bN1lCnPA=; b=Hb2Dt82V6RFUBwoDi4OOl2AXD6 W25R+uc2mmPiqDDZdhT/qjdm9B2ExG7lHDc6ZSDHhEriZSu1Hsdenn/F1dLW+OC9hKfOa3L5l2pRD EzRoTJFneYRBuQu7Ltjmch4nxIhf7CK45/fBxGFI6GZTcrxJdVfAu9hiTth+25f4hinBoq+ezULAL 1LdBNRSzQtdELh+smst/0SliQMRLRYFhkmxtInCi8O0dj8vuhiI8VFXjszCZdBRxp7RolpA3g56UY 9t8/UqwevdkKIyOWXG1A4Z8kyizgGLVLeB8gvORC8dxiI3jCdDDrU02Zntxg7V2zZL9pK20gzt2gM BdVYLpOA==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaTb-00ANVs-JK; Sun, 23 Apr 2023 16:14:03 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , linux-kernel@vger.kernel.org Subject: [RFC PATCH 37/40] drm/amd/display: handle empty LUTs in __set_input_tf Date: Sun, 23 Apr 2023 13:10:49 -0100 Message-Id: <20230423141051.702990-38-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Joshua Ashton Unlike degamma, blend gamma doesn't support hardcoded curve (predefined/ROM), but we can use AMD color module to fill blend gamma parameters when we have non-linear plane gamma TF without plane gamma LUT. The regular degamma path doesn't hit this. Signed-off-by: Joshua Ashton --- .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 21 ++++++++++++------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/driv= ers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index e17141fc8d12..baa7fea9ebae 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -349,21 +349,26 @@ static int __set_input_tf(struct dc_transfer_func *fu= nc, struct dc_gamma *gamma =3D NULL; bool res; =20 - gamma =3D dc_create_gamma(); - if (!gamma) - return -ENOMEM; + if (lut_size) { + gamma =3D dc_create_gamma(); + if (!gamma) + return -ENOMEM; =20 - gamma->type =3D GAMMA_CUSTOM; - gamma->num_entries =3D lut_size; + gamma->type =3D GAMMA_CUSTOM; + gamma->num_entries =3D lut_size; =20 - __drm_lut_to_dc_gamma(lut, gamma, false); + __drm_lut_to_dc_gamma(lut, gamma, false); + } =20 - res =3D mod_color_calculate_degamma_params(NULL, func, gamma, true); - dc_gamma_release(&gamma); + res =3D mod_color_calculate_degamma_params(NULL, func, gamma, gamma !=3D = NULL); + + if (gamma) + dc_gamma_release(&gamma); =20 return res ? 0 : -ENOMEM; } =20 + #ifdef CONFIG_STEAM_DECK static enum dc_transfer_func_predefined drm_tf_to_dc_tf(enum drm_transfer_= function drm_tf) { --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0229C77B60 for ; Sun, 23 Apr 2023 14:46:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230333AbjDWOqg (ORCPT ); Sun, 23 Apr 2023 10:46:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51696 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229501AbjDWOqe (ORCPT ); Sun, 23 Apr 2023 10:46:34 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33EDBE79 for ; Sun, 23 Apr 2023 07:46:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=566kXB93gduhO2pKotI8dq2ueeNQbJHEXFmIOVEzq10=; b=FJPh6PhjvOZATxzA+xct5dbVc7 gvsyJq189sn9N+Sx8/b9V6/F8OeScwhlxwajOaTzJvKBQnCNtyZ+iM7bAPOTmI8wsDKons2orsKLg /LWoGEFqE+GwbFxo8YTX1W/W4nPqxZnaFQTQ7yN+8uFphqOhYLY6upDlZo1wFnu4ydap/J1htHOx1 ElZWZnaBcH19SMPD+XsHcuc+xXBL1MJlatgLUu1s4BcNufr4b8EfZk1FrYPnBxbRXMNmCFitoeLc0 3Sj1JESKDWFQTgypjuGrJMcSMfIko5ngJRmWOzro7uRcaVm0fvU318+tQz7TI3dbXMiWAAYJIj4Zl U/HVg21Q==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaTg-00ANVs-Do; Sun, 23 Apr 2023 16:14:08 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , linux-kernel@vger.kernel.org Subject: [RFC PATCH 38/40] drm/amd/display: add DRM plane blend LUT and TF support Date: Sun, 23 Apr 2023 13:10:50 -0100 Message-Id: <20230423141051.702990-39-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Joshua Ashton Map DRM plane blend properties to DPP blend gamma. Plane blend is a post-3D LUT curve that linearizes color space for blending. It may be defined by a user-blob LUT and/or predefined transfer function. As hardcoded curve (ROM) is not supported on blend gamma, we use AMD color module to fill parameters when setting non-linear TF with empty LUT. Signed-off-by: Joshua Ashton --- .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 60 +++++++++++++++++-- 1 file changed, 56 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/driv= ers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index baa7fea9ebae..a034c0c0d383 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -493,6 +493,34 @@ static int amdgpu_dm_atomic_shaper_lut(const struct dr= m_color_lut *shaper_lut, return ret; } =20 +static int amdgpu_dm_atomic_blend_lut(const struct drm_color_lut *blend_lu= t, + bool has_rom, + enum dc_transfer_func_predefined tf, + uint32_t blend_size, + struct dc_transfer_func *func_blend) +{ + int ret =3D 0; + + if (blend_size || tf !=3D TRANSFER_FUNCTION_LINEAR) { + /* DRM plane gamma LUT or TF means we are linearizing color + * space before blending (similar to degamma programming). As + * we don't have hardcoded curve support, or we use AMD color + * module to fill the parameters that will be translated to HW + * points. + */ + func_blend->type =3D TF_TYPE_DISTRIBUTED_POINTS; + func_blend->tf =3D tf; + func_blend->sdr_ref_white_level =3D 80; /* hardcoded for now */ + + ret =3D __set_input_tf(func_blend, blend_lut, blend_size); + } else { + func_blend->type =3D TF_TYPE_BYPASS; + func_blend->tf =3D TRANSFER_FUNCTION_LINEAR; + } + + return ret; +} + /* amdgpu_dm_atomic_shaper_lut3d - set DRM CRTC shaper LUT and 3D LUT to DC * interface * @dc: Display Core control structure @@ -921,9 +949,11 @@ amdgpu_dm_plane_set_color_properties(struct drm_plane_= state *plane_state, { struct dm_plane_state *dm_plane_state =3D to_dm_plane_state(plane_state); enum drm_transfer_function shaper_tf =3D DRM_TRANSFER_FUNCTION_DEFAULT; - const struct drm_color_lut *shaper_lut, *lut3d; - uint32_t lut3d_size, shaper_size; - + enum drm_transfer_function blend_tf =3D DRM_TRANSFER_FUNCTION_DEFAULT; + const struct drm_color_lut *shaper_lut, *lut3d, *blend_lut; + uint32_t lut3d_size, shaper_size, blend_size; + int ret; +=09 /* We have nothing to do here, return */ if (!plane_state->color_mgmt_changed) return 0; @@ -940,8 +970,30 @@ amdgpu_dm_plane_set_color_properties(struct drm_plane_= state *plane_state, ret =3D amdgpu_dm_atomic_shaper_lut(shaper_lut, false, drm_tf_to_dc_tf(shaper_tf), shaper_size, dc_plane_state->in_shaper_func); + if (ret) { + drm_dbg_kms(plane_state->plane->dev, + "setting plane %d shaper/3d lut failed.\n", + plane_state->plane->index); =20 - return ret; + return ret; + } + + blend_tf =3D dm_plane_state->blend_tf; + blend_lut =3D __extract_blob_lut(dm_plane_state->blend_lut, &blend_size); + blend_size =3D blend_lut !=3D NULL ? blend_size : 0; + + ret =3D amdgpu_dm_atomic_blend_lut(blend_lut, false, + drm_tf_to_dc_tf(blend_tf), + blend_size, dc_plane_state->blend_tf); + if (ret) { + drm_dbg_kms(plane_state->plane->dev, + "setting plane %d gamma lut failed.\n", + plane_state->plane->index); + + return ret; + } + + return 0; } #endif =20 --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD4E1C77B60 for ; Sun, 23 Apr 2023 14:16:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230344AbjDWOQ6 (ORCPT ); Sun, 23 Apr 2023 10:16:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230319AbjDWOQx (ORCPT ); Sun, 23 Apr 2023 10:16:53 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F013612B for ; Sun, 23 Apr 2023 07:16:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=ThKpXKa9g7weqsnCPtd4OEDTst1upZkxiTxtrVaNrZo=; b=l3NFJXyryB+V2jHF63KnKZh7N/ tqMOm8AWuWPKzrRUTZoIBRHuAMeYCCdGt3zyZhG8lML4Y4SbyiSeH4cgsnk+PuIHTh1QUAq9CvWs8 9z5T3W/S83PXwvDRmBsw5p/3CC7voRayxUW6LM3tY/7iQFnurh1IFNvRcJW89Jv2R14jgU8YusFOz 9r6QKI6UIOXsTGJFnns4kA2D8gMZ4Tu42j75bvDum/zMJmIYYFepEvGgw7YIgis1VI2M1RSmzDLN6 jxDKMmxcfaZ2ljNRocczsja39KWG2iEr8Ljvto2RTcqBnHTRuBw0EDa3ENcgkboVvVAlSIqvKZ2gO 4Xx/7DWw==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaTi-00ANVs-Ti; Sun, 23 Apr 2023 16:14:11 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Melissa Wen , linux-kernel@vger.kernel.org Subject: [RFC PATCH 39/40] drm/amd/display: copy dc_plane color settings to surface_updates Date: Sun, 23 Apr 2023 13:10:51 -0100 Message-Id: <20230423141051.702990-40-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" As per previous code, copy shaper, 3d and blend settings from dc_plane to surface_updates before commit. Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gp= u/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 0e3b6d414ec4..cdaaec1b2a3a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7987,11 +7987,13 @@ static void amdgpu_dm_commit_planes(struct drm_atom= ic_state *state, continue; =20 bundle->surface_updates[planes_count].surface =3D dc_plane; - if (new_pcrtc_state->color_mgmt_changed) { + if (new_pcrtc_state->color_mgmt_changed || new_plane_state->color_mgmt_c= hanged) { bundle->surface_updates[planes_count].gamma =3D dc_plane->gamma_correct= ion; bundle->surface_updates[planes_count].in_transfer_func =3D dc_plane->in= _transfer_func; bundle->surface_updates[planes_count].gamut_remap_matrix =3D &dc_plane-= >gamut_remap_matrix; bundle->surface_updates[planes_count].hdr_mult =3D dc_plane->hdr_mult; + bundle->surface_updates[planes_count].func_shaper =3D dc_plane->in_shap= er_func; + bundle->surface_updates[planes_count].lut3d_func =3D dc_plane->lut3d_fu= nc; } =20 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state, --=20 2.39.2 From nobody Fri Dec 19 06:39:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D378FC6FD18 for ; Sun, 23 Apr 2023 14:15:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230389AbjDWOPm (ORCPT ); Sun, 23 Apr 2023 10:15:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230331AbjDWOP3 (ORCPT ); Sun, 23 Apr 2023 10:15:29 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2D7412D46 for ; Sun, 23 Apr 2023 07:15:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=DSe48vE9nywjx4G3xnygTop+WxvlePBvLA+a/JHlHUc=; b=JIxgWWwNV5I9b+JeGqYfWNgjd/ 8rdv1Drcdv9QZIxwJVANyd5HLbtCLyJJIETXuvP3ivC1Y+Us68jrlyzzfufTze/73gCrizVxU9123 opcPsg0fkAlNGppOPlNtzSPq2SYKd2lWiMnd3ZnN9T2pEo7lItOuqSSAdCqwC2kHLj0F9uDSgdqSV td0yVqEI81iD3lVIlbco7S03v3nAe1rBELF/dPEimmtFKifIBVZt+URe014F5pQ8kWa0kCbQC6Kpr C5K9Ke68c/8CTe677l0PGaTwnXYZmlBm4JVOkhN8HCgMmbvHNUtn8LyQ9bWi9+he4fShwiR1rd6GQ 9jsCqjeQ==; Received: from nat-wifi.fi.muni.cz ([147.251.43.9] helo=killbill.fi.muni.cz) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1pqaTl-00ANVs-MW; Sun, 23 Apr 2023 16:14:13 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , linux-kernel@vger.kernel.org Subject: [RFC PATCH 40/40] drm/amd/display: allow newer DC hardware to use degamma ROM for PQ/HLG Date: Sun, 23 Apr 2023 13:10:52 -0100 Message-Id: <20230423141051.702990-41-mwen@igalia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230423141051.702990-1-mwen@igalia.com> References: <20230423141051.702990-1-mwen@igalia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Joshua Ashton Need to funnel the color caps through to these functions so it can check that the hardware is capable. Signed-off-by: Joshua Ashton --- .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 34 ++++++++++++------- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/driv= ers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index a034c0c0d383..f0b5f09b9146 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -336,6 +336,7 @@ static int amdgpu_dm_set_atomic_regamma(struct dc_strea= m_state *stream, /** * __set_input_tf - calculates the input transfer function based on expect= ed * input space. + * @caps: dc color capabilities * @func: transfer function * @lut: lookup table that defines the color space * @lut_size: size of respective lut. @@ -343,7 +344,7 @@ static int amdgpu_dm_set_atomic_regamma(struct dc_strea= m_state *stream, * Returns: * 0 in case of success. -ENOMEM if fails. */ -static int __set_input_tf(struct dc_transfer_func *func, +static int __set_input_tf(struct dc_color_caps *caps, struct dc_transfer_f= unc *func, const struct drm_color_lut *lut, uint32_t lut_size) { struct dc_gamma *gamma =3D NULL; @@ -360,7 +361,7 @@ static int __set_input_tf(struct dc_transfer_func *func, __drm_lut_to_dc_gamma(lut, gamma, false); } =20 - res =3D mod_color_calculate_degamma_params(NULL, func, gamma, gamma !=3D = NULL); + res =3D mod_color_calculate_degamma_params(caps, func, gamma, gamma !=3D = NULL); =20 if (gamma) dc_gamma_release(&gamma); @@ -512,7 +513,7 @@ static int amdgpu_dm_atomic_blend_lut(const struct drm_= color_lut *blend_lut, func_blend->tf =3D tf; func_blend->sdr_ref_white_level =3D 80; /* hardcoded for now */ =20 - ret =3D __set_input_tf(func_blend, blend_lut, blend_size); + ret =3D __set_input_tf(NULL, func_blend, blend_lut, blend_size); } else { func_blend->type =3D TF_TYPE_BYPASS; func_blend->tf =3D TRANSFER_FUNCTION_LINEAR; @@ -819,7 +820,8 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_sta= te *crtc, } =20 static int map_crtc_degamma_to_dc_plane(struct dm_crtc_state *crtc, - struct dc_plane_state *dc_plane_state) + struct dc_plane_state *dc_plane_state, + struct dc_color_caps *caps) { const struct drm_color_lut *degamma_lut; enum dc_transfer_func_predefined tf =3D TRANSFER_FUNCTION_SRGB; @@ -874,7 +876,7 @@ static int map_crtc_degamma_to_dc_plane(struct dm_crtc_= state *crtc, dc_plane_state->in_transfer_func->tf =3D TRANSFER_FUNCTION_LINEAR; =20 - r =3D __set_input_tf(dc_plane_state->in_transfer_func, + r =3D __set_input_tf(caps, dc_plane_state->in_transfer_func, degamma_lut, degamma_size); if (r) return r; @@ -887,7 +889,7 @@ static int map_crtc_degamma_to_dc_plane(struct dm_crtc_= state *crtc, dc_plane_state->in_transfer_func->tf =3D tf; =20 if (tf !=3D TRANSFER_FUNCTION_SRGB && - !mod_color_calculate_degamma_params(NULL, + !mod_color_calculate_degamma_params(caps, dc_plane_state->in_transfer_func, NULL, false)) return -ENOMEM; } @@ -898,7 +900,8 @@ static int map_crtc_degamma_to_dc_plane(struct dm_crtc_= state *crtc, #ifdef CONFIG_STEAM_DECK static int __set_dm_plane_degamma(struct drm_plane_state *plane_state, - struct dc_plane_state *dc_plane_state) + struct dc_plane_state *dc_plane_state, + struct dc_color_caps *color_caps) { struct dm_plane_state *dm_plane_state =3D to_dm_plane_state(plane_state); const struct drm_color_lut *degamma_lut; @@ -907,6 +910,9 @@ __set_dm_plane_degamma(struct drm_plane_state *plane_st= ate, bool has_degamma_lut; int ret; =20 + if (dc_plane_state->ctx && dc_plane_state->ctx->dc) + color_caps =3D &dc_plane_state->ctx->dc->caps.color; + degamma_lut =3D __extract_blob_lut(dm_plane_state->degamma_lut, °amma_= size); =20 has_degamma_lut =3D degamma_lut && @@ -928,8 +934,8 @@ __set_dm_plane_degamma(struct drm_plane_state *plane_st= ate, dc_plane_state->in_transfer_func->type =3D TF_TYPE_DISTRIBUTED_POINTS; =20 - ret =3D __set_input_tf(dc_plane_state->in_transfer_func, - degamma_lut, degamma_size); + ret =3D __set_input_tf(color_caps, dc_plane_state->in_transfer_func, + degamma_lut, degamma_size); if (ret) return ret; } else { @@ -945,7 +951,8 @@ __set_dm_plane_degamma(struct drm_plane_state *plane_st= ate, =20 static int amdgpu_dm_plane_set_color_properties(struct drm_plane_state *plane_state, - struct dc_plane_state *dc_plane_state) + struct dc_plane_state *dc_plane_state, + struct dc_color_caps *color_caps) { struct dm_plane_state *dm_plane_state =3D to_dm_plane_state(plane_state); enum drm_transfer_function shaper_tf =3D DRM_TRANSFER_FUNCTION_DEFAULT; @@ -1014,6 +1021,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_= state *crtc, struct drm_plane_state *plane_state, struct dc_plane_state *dc_plane_state) { + struct dc_color_caps *color_caps =3D NULL; bool has_crtc_cm_degamma; int ret; =20 @@ -1025,11 +1033,11 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crt= c_state *crtc, has_crtc_cm_degamma =3D (crtc->cm_has_degamma || crtc->cm_is_degamma_srgb= ); =20 #ifdef CONFIG_STEAM_DECK - ret =3D amdgpu_dm_plane_set_color_properties(plane_state, dc_plane_state); + ret =3D amdgpu_dm_plane_set_color_properties(plane_state, dc_plane_state,= color_caps); if(ret) return ret; =20 - ret =3D __set_dm_plane_degamma(plane_state, dc_plane_state); + ret =3D __set_dm_plane_degamma(plane_state, dc_plane_state, color_caps); if (ret !=3D -EINVAL) return ret; =20 @@ -1054,7 +1062,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_= state *crtc, * linearize (implicit degamma) from sRGB/BT709 according to * the input space. */ - ret =3D map_crtc_degamma_to_dc_plane(crtc, dc_plane_state); + ret =3D map_crtc_degamma_to_dc_plane(crtc, dc_plane_state, color_caps); if (ret) return ret; } --=20 2.39.2