From nobody Wed Dec 17 00:19:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9E3EC77B7F for ; Sun, 23 Apr 2023 09:55:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230145AbjDWJzU (ORCPT ); Sun, 23 Apr 2023 05:55:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60504 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229977AbjDWJzR (ORCPT ); Sun, 23 Apr 2023 05:55:17 -0400 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B7C8C10FD; Sun, 23 Apr 2023 02:55:15 -0700 (PDT) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 33N4UDCc016372; Sun, 23 Apr 2023 02:55:09 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=KzMK/K65loY1xIeXVTIjDHwBpYHIq8+pb5BAKV4qo/A=; b=fpovbT7GQI4OtwCNSxNP7HO5IbJrhVyWrK6g8LfJ1qHxGgtIPaaWAOJ6LQnelF1LvrcM GaQ65BRbPJmM0Ws1fsp7eVC3HnRuUqLfGmyRfPSNZfx+P9/z79aRl7bnGwrEk6SNNVEy YyhEqWB8byE0DcFVdo0vT5Id0sDSSECQXj91bSQJ993h43YEEF80wPE8dNiK4h+6icpk loNnMsJyNxMArNUIKnPZTSAaFUfu/fTORbiu+pk3RRwsqL3oDJSzfUJk21N/ZIhaexH/ ASibx58iz0f3GCrDAX4M/M9X2naTPNEkMO1iV1qaddfjWjsReg3Lb//2bGeVexNB1kiE lA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3q4f3p2pqk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 23 Apr 2023 02:55:08 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Sun, 23 Apr 2023 02:55:06 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Sun, 23 Apr 2023 02:55:06 -0700 Received: from hyd1soter3.marvell.com (unknown [10.29.37.12]) by maili.marvell.com (Postfix) with ESMTP id 49C083F70AD; Sun, 23 Apr 2023 02:55:03 -0700 (PDT) From: Geetha sowjanya To: , CC: , , , , , , , , Subject: [net PATCH 2/9] octeontx2-af: mcs: Write TCAM_DATA and TCAM_MASK registers at once Date: Sun, 23 Apr 2023 15:24:47 +0530 Message-ID: <20230423095454.21049-3-gakula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230423095454.21049-1-gakula@marvell.com> References: <20230423095454.21049-1-gakula@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: CaqQRHOJueD5JUClqU1epIUU-kjw-mYm X-Proofpoint-GUID: CaqQRHOJueD5JUClqU1epIUU-kjw-mYm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-23_06,2023-04-21_01,2023-02-09_01 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Subbaraya Sundeep As per hardware errata on CN10KB, all the four TCAM_DATA and TCAM_MASK registers has to be written at once otherwise write to individual registers will fail. Hence write to all TCAM_DATA registers and then to all TCAM_MASK registers. Fixes: cfc14181d497 ("octeontx2-af: cn10k: mcs: Manage the MCS block hardwa= re resources") Signed-off-by: Subbaraya Sundeep Signed-off-by: Sunil Kovvuri Goutham Signed-off-by: Geetha sowjanya Reviewed-by: Leon Romanovsky --- drivers/net/ethernet/marvell/octeontx2/af/mcs.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mcs.c b/drivers/net/= ethernet/marvell/octeontx2/af/mcs.c index 492baa0b594c..148417d633a5 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mcs.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/mcs.c @@ -473,6 +473,8 @@ void mcs_flowid_entry_write(struct mcs *mcs, u64 *data,= u64 *mask, int flow_id, for (reg_id =3D 0; reg_id < 4; reg_id++) { reg =3D MCSX_CPM_RX_SLAVE_FLOWID_TCAM_DATAX(reg_id, flow_id); mcs_reg_write(mcs, reg, data[reg_id]); + } + for (reg_id =3D 0; reg_id < 4; reg_id++) { reg =3D MCSX_CPM_RX_SLAVE_FLOWID_TCAM_MASKX(reg_id, flow_id); mcs_reg_write(mcs, reg, mask[reg_id]); } @@ -480,6 +482,8 @@ void mcs_flowid_entry_write(struct mcs *mcs, u64 *data,= u64 *mask, int flow_id, for (reg_id =3D 0; reg_id < 4; reg_id++) { reg =3D MCSX_CPM_TX_SLAVE_FLOWID_TCAM_DATAX(reg_id, flow_id); mcs_reg_write(mcs, reg, data[reg_id]); + } + for (reg_id =3D 0; reg_id < 4; reg_id++) { reg =3D MCSX_CPM_TX_SLAVE_FLOWID_TCAM_MASKX(reg_id, flow_id); mcs_reg_write(mcs, reg, mask[reg_id]); } --=20 2.25.1