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([2a02:810d:15c0:828:687d:8c5:41cb:9883]) by smtp.gmail.com with ESMTPSA id bj1-20020a170906b04100b0094f7acbafe0sm1528708ejb.177.2023.04.21.15.31.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Apr 2023 15:32:00 -0700 (PDT) From: Krzysztof Kozlowski To: Rob Herring , Krzysztof Kozlowski , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Krzysztof Kozlowski Subject: [PATCH] arm64: dts: marvell: add missing cache properties Date: Sat, 22 Apr 2023 00:31:59 +0200 Message-Id: <20230421223159.115412-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: ac5-98dx35xx-rd.dtb: l2-cache: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski --- Please take the patch via sub-arch SoC tree. --- arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 1 + arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi | 1 + arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi | 2 ++ arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi | 2 ++ 4 files changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boo= t/dts/marvell/ac5-98dx25xx.dtsi index 8bce64069138..c9ce1010c415 100644 --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi @@ -50,6 +50,7 @@ cpu1: cpu@1 { l2: l2-cache { compatible =3D "cache"; cache-level =3D <2>; + cache-unified; }; }; =20 diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm6= 4/boot/dts/marvell/armada-ap806-dual.dtsi index 990f70303fe6..3ed6fba1f438 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi @@ -52,6 +52,7 @@ l2: l2-cache { cache-line-size =3D <64>; cache-sets =3D <512>; cache-level =3D <2>; + cache-unified; }; }; =20 diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm6= 4/boot/dts/marvell/armada-ap806-quad.dtsi index a7b8e001cc9c..cf6a96ddcf40 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi @@ -82,6 +82,7 @@ l2_0: l2-cache0 { cache-line-size =3D <64>; cache-sets =3D <512>; cache-level =3D <2>; + cache-unified; }; =20 l2_1: l2-cache1 { @@ -90,6 +91,7 @@ l2_1: l2-cache1 { cache-line-size =3D <64>; cache-sets =3D <512>; cache-level =3D <2>; + cache-unified; }; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi b/arch/arm6= 4/boot/dts/marvell/armada-ap807-quad.dtsi index 7740098fd108..8848238f9565 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi @@ -82,6 +82,7 @@ l2_0: l2-cache0 { cache-line-size =3D <64>; cache-sets =3D <512>; cache-level =3D <2>; + cache-unified; }; =20 l2_1: l2-cache1 { @@ -90,6 +91,7 @@ l2_1: l2-cache1 { cache-line-size =3D <64>; cache-sets =3D <512>; cache-level =3D <2>; + cache-unified; }; }; }; --=20 2.34.1