From nobody Tue Dec 16 11:46:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CD64C7618E for ; Fri, 21 Apr 2023 22:32:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233763AbjDUWcn (ORCPT ); Fri, 21 Apr 2023 18:32:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33768 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233887AbjDUWcQ (ORCPT ); Fri, 21 Apr 2023 18:32:16 -0400 Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6205A2711 for ; Fri, 21 Apr 2023 15:31:59 -0700 (PDT) Received: by mail-ed1-x533.google.com with SMTP id 4fb4d7f45d1cf-5069097bac7so3807526a12.0 for ; Fri, 21 Apr 2023 15:31:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682116317; x=1684708317; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=pitbg/AnYT+7wXCt2mEuce2KB1B0+ui+WWGwpaQkC98=; b=obQptdKkaIozOZTGXFT1iVgi7FGrMW2Lj8aeh2p+N8wIZVxxTSYwSQFbVo0wieyBz5 dupy9VN1DyQ0aXwyZuqV5tQ+2BcMN0mwDRcy/Vaowqe+qnCSZo6sqQs+xsa1DuwIpwDx KkR9b4GhsHpkW32xOTQJjzFUPUmEtO5VPD723rkdbY8KSBYRjgIzrdOzW5S+VqQq/UG5 UjaSvL6HuXEudfIItlWBTQmFpkvVXXNWaRBt4Z0erOxFDDH+GLFnAT5ZFMasSBkx5iyl e42sd0Ax3liSxphHuDrnf4mqnLPQvyMWn5JIIVmb1WAkaMOAGF5JH4TKtSzvs3JiKrlr xKdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682116317; x=1684708317; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=pitbg/AnYT+7wXCt2mEuce2KB1B0+ui+WWGwpaQkC98=; b=QepGyB2v1st11DDwfqBD1rdASs8jwzN8K+ZjAX0X0WzkIXgRVIXqUm+pM1cTCzmsJG 5oatq/VPH76u/Jq3E+OsFaWi0G/xiSGfT6UMVh4gPOUv95zVKQLd1fmkUgLZxo0MkdPp 4t2+H/Qkmf8O2wB6hU2jfpMBKDU6g2m91P1KvxR5Rbo3p9pQRPSUEpQYBo/XDWU2xuXp P1OluDpN6ZeGwS1Usmuu3WP5PM+aojBo592sSRZQucFEpo58IirA5Uw0MLrtcjrh/9BB x9TlT6K8nxnYC92Ivk0GULmryRJpZ5pQeB4T+p0EcvkIYw4R4+KLqw6Lvi30VEF+NJmI YILg== X-Gm-Message-State: AAQBX9c4JQdntHx4crr4M2UGD/A2g+OOxYewI356quAg+9A+WIODCTlk PZE3mnFifS0c6aHRH6Wci/Y+vA== X-Google-Smtp-Source: AKy350a4cH/QIL/qloNHWJRinYsd8kmdQ+P6b2qfd9I7RLwogiFF9xZftwYXCGRC7bb0w960Uf+mMg== X-Received: by 2002:a50:fa89:0:b0:4fa:b302:84d4 with SMTP id w9-20020a50fa89000000b004fab30284d4mr6180279edr.13.1682116317328; Fri, 21 Apr 2023 15:31:57 -0700 (PDT) Received: from krzk-bin.. ([2a02:810d:15c0:828:687d:8c5:41cb:9883]) by smtp.gmail.com with ESMTPSA id p15-20020aa7cc8f000000b004aef147add6sm2223867edt.47.2023.04.21.15.31.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Apr 2023 15:31:56 -0700 (PDT) From: Krzysztof Kozlowski To: Rob Herring , Krzysztof Kozlowski , Lars Povlsen , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH] arm64: dts: microchip: add missing cache properties Date: Sat, 22 Apr 2023 00:31:55 +0200 Message-Id: <20230421223155.115339-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" As all level 2 and level 3 caches are unified, add required cache-unified and cache-level properties to fix warnings like: sparx5_pcb125.dtb: l2-cache0: 'cache-level' is a required property Signed-off-by: Krzysztof Kozlowski --- Please take the patch via sub-arch SoC tree. --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dt= s/microchip/sparx5.dtsi index 0367a00a269b..6f7651b06478 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -52,6 +52,8 @@ cpu1: cpu@1 { }; L2_0: l2-cache0 { compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; }; }; =20 --=20 2.34.1