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([2a02:810d:15c0:828:687d:8c5:41cb:9883]) by smtp.gmail.com with ESMTPSA id k1-20020a170906a38100b0094ece70481csm2537895ejz.197.2023.04.21.15.31.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Apr 2023 15:31:52 -0700 (PDT) From: Krzysztof Kozlowski To: =?UTF-8?q?Andreas=20F=C3=A4rber?= , Rob Herring , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-realtek-soc@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH] arm64: dts: realtek: add missing cache properties Date: Sat, 22 Apr 2023 00:31:50 +0200 Message-Id: <20230421223151.115243-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" As all level 2 and level 3 caches are unified, add required cache-unified and cache-level properties to fix warnings like: rtd1293-ds418j.dtb: l2-cache: 'cache-level' is a required property rtd1293-ds418j.dtb: l2-cache: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski --- Please take the patch via sub-arch SoC tree. --- arch/arm64/boot/dts/realtek/rtd1293.dtsi | 2 ++ arch/arm64/boot/dts/realtek/rtd1295.dtsi | 2 ++ arch/arm64/boot/dts/realtek/rtd1296.dtsi | 2 ++ arch/arm64/boot/dts/realtek/rtd1395.dtsi | 2 ++ arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 4 ++++ 5 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/realtek/rtd1293.dtsi b/arch/arm64/boot/dts= /realtek/rtd1293.dtsi index 2d92b56ac94d..d0c9387ac17a 100644 --- a/arch/arm64/boot/dts/realtek/rtd1293.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd1293.dtsi @@ -30,6 +30,8 @@ cpu1: cpu@1 { =20 l2: l2-cache { compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; }; }; =20 diff --git a/arch/arm64/boot/dts/realtek/rtd1295.dtsi b/arch/arm64/boot/dts= /realtek/rtd1295.dtsi index 1402abe80ea1..b7f63102f2dd 100644 --- a/arch/arm64/boot/dts/realtek/rtd1295.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd1295.dtsi @@ -44,6 +44,8 @@ cpu3: cpu@3 { =20 l2: l2-cache { compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; }; }; =20 diff --git a/arch/arm64/boot/dts/realtek/rtd1296.dtsi b/arch/arm64/boot/dts= /realtek/rtd1296.dtsi index fb864a139c97..4f805f576cef 100644 --- a/arch/arm64/boot/dts/realtek/rtd1296.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd1296.dtsi @@ -44,6 +44,8 @@ cpu3: cpu@3 { =20 l2: l2-cache { compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; }; }; =20 diff --git a/arch/arm64/boot/dts/realtek/rtd1395.dtsi b/arch/arm64/boot/dts= /realtek/rtd1395.dtsi index 05c9216a87ee..2efe5b25c83c 100644 --- a/arch/arm64/boot/dts/realtek/rtd1395.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd1395.dtsi @@ -44,6 +44,8 @@ cpu3: cpu@3 { =20 l2: l2-cache { compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; }; }; =20 diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi b/arch/arm64/boot/dts= /realtek/rtd16xx.dtsi index bf4d9e917925..34802cc62983 100644 --- a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi @@ -88,11 +88,15 @@ cpu5: cpu@500 { l2: l2-cache { compatible =3D "cache"; next-level-cache =3D <&l3>; + cache-level =3D <2>; + cache-unified; =20 }; =20 l3: l3-cache { compatible =3D "cache"; + cache-level =3D <3>; + cache-unified; }; }; =20 --=20 2.34.1