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([2a02:810d:15c0:828:687d:8c5:41cb:9883]) by smtp.gmail.com with ESMTPSA id aa21-20020a170907355500b00957dad777c1sm308173ejc.107.2023.04.21.15.31.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Apr 2023 15:31:50 -0700 (PDT) From: Krzysztof Kozlowski To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH] arm64: dts: rockchip: add missing cache properties Date: Sat, 22 Apr 2023 00:31:48 +0200 Message-Id: <20230421223149.115185-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: rk3588s-khadas-edge2.dtb: l3-cache: 'cache-unified' is a dependency of 'c= ache-size' Signed-off-by: Krzysztof Kozlowski --- Please take the patch via sub-arch SoC tree. --- arch/arm64/boot/dts/rockchip/rk3308.dtsi | 1 + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 1 + arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 9 +++++++++ 3 files changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts= /rockchip/rk3308.dtsi index dd228a256a32..2ae4bb7d5e62 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi @@ -97,6 +97,7 @@ CPU_SLEEP: cpu-sleep { l2: l2-cache { compatible =3D "cache"; cache-level =3D <2>; + cache-unified; }; }; =20 diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts= /rockchip/rk3328.dtsi index 6d7a7bf72ac7..e729e7a22b23 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -103,6 +103,7 @@ CPU_SLEEP: cpu-sleep { l2: l2-cache0 { compatible =3D "cache"; cache-level =3D <2>; + cache-unified; }; }; =20 diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dt= s/rockchip/rk3588s.dtsi index 657c019d27fa..5badc68fe9f0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -230,6 +230,7 @@ l2_cache_l0: l2-cache-l0 { cache-sets =3D <512>; cache-level =3D <2>; next-level-cache =3D <&l3_cache>; + cache-unified; }; =20 l2_cache_l1: l2-cache-l1 { @@ -239,6 +240,7 @@ l2_cache_l1: l2-cache-l1 { cache-sets =3D <512>; cache-level =3D <2>; next-level-cache =3D <&l3_cache>; + cache-unified; }; =20 l2_cache_l2: l2-cache-l2 { @@ -248,6 +250,7 @@ l2_cache_l2: l2-cache-l2 { cache-sets =3D <512>; cache-level =3D <2>; next-level-cache =3D <&l3_cache>; + cache-unified; }; =20 l2_cache_l3: l2-cache-l3 { @@ -257,6 +260,7 @@ l2_cache_l3: l2-cache-l3 { cache-sets =3D <512>; cache-level =3D <2>; next-level-cache =3D <&l3_cache>; + cache-unified; }; =20 l2_cache_b0: l2-cache-b0 { @@ -266,6 +270,7 @@ l2_cache_b0: l2-cache-b0 { cache-sets =3D <1024>; cache-level =3D <2>; next-level-cache =3D <&l3_cache>; + cache-unified; }; =20 l2_cache_b1: l2-cache-b1 { @@ -275,6 +280,7 @@ l2_cache_b1: l2-cache-b1 { cache-sets =3D <1024>; cache-level =3D <2>; next-level-cache =3D <&l3_cache>; + cache-unified; }; =20 l2_cache_b2: l2-cache-b2 { @@ -284,6 +290,7 @@ l2_cache_b2: l2-cache-b2 { cache-sets =3D <1024>; cache-level =3D <2>; next-level-cache =3D <&l3_cache>; + cache-unified; }; =20 l2_cache_b3: l2-cache-b3 { @@ -293,6 +300,7 @@ l2_cache_b3: l2-cache-b3 { cache-sets =3D <1024>; cache-level =3D <2>; next-level-cache =3D <&l3_cache>; + cache-unified; }; =20 l3_cache: l3-cache { @@ -301,6 +309,7 @@ l3_cache: l3-cache { cache-line-size =3D <64>; cache-sets =3D <4096>; cache-level =3D <3>; + cache-unified; }; }; =20 --=20 2.34.1