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([2a02:810d:15c0:828:687d:8c5:41cb:9883]) by smtp.gmail.com with ESMTPSA id l7-20020a1709060e0700b0094ee21fe943sm2557098eji.116.2023.04.21.15.31.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Apr 2023 15:31:48 -0700 (PDT) From: Krzysztof Kozlowski To: Rob Herring , Krzysztof Kozlowski , Kunihiko Hayashi , Masami Hiramatsu , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH] arm64: dts: socionext: add missing cache properties Date: Sat, 22 Apr 2023 00:31:47 +0200 Message-Id: <20230421223147.115156-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" As all level 2 and level 3 caches are unified, add required cache-unified and cache-level properties to fix warnings like: uniphier-ld11-ref.dtb: l2-cache: 'cache-level' is a required property uniphier-ld11-ref.dtb: l2-cache: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski --- Please take the patch via sub-arch SoC tree. --- arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 2 ++ arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 4 ++++ arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 2 ++ 3 files changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/= boot/dts/socionext/uniphier-ld11.dtsi index 7bb36b071475..4680571c264d 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi @@ -52,6 +52,8 @@ cpu1: cpu@1 { =20 l2: l2-cache { compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; }; }; =20 diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/= boot/dts/socionext/uniphier-ld20.dtsi index 4e2171630272..335093da6573 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -86,10 +86,14 @@ cpu3: cpu@101 { =20 a72_l2: l2-cache0 { compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; }; =20 a53_l2: l2-cache1 { compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; }; }; =20 diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/= boot/dts/socionext/uniphier-pxs3.dtsi index 38ccfb46ea42..d6e3cc6fdb25 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi @@ -83,6 +83,8 @@ cpu3: cpu@3 { =20 l2: l2-cache { compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; }; }; =20 --=20 2.34.1