From nobody Sat Sep 21 00:04:50 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29040C77B71 for ; Fri, 21 Apr 2023 14:37:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232777AbjDUOhp (ORCPT ); Fri, 21 Apr 2023 10:37:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45252 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232799AbjDUOhU (ORCPT ); Fri, 21 Apr 2023 10:37:20 -0400 Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4283030E6; Fri, 21 Apr 2023 07:37:14 -0700 (PDT) Received: by mail-ed1-x52b.google.com with SMTP id 4fb4d7f45d1cf-5055141a8fdso2485031a12.3; Fri, 21 Apr 2023 07:37:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682087832; x=1684679832; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rqdViajAeNRKoM+fdqJjjwXsteiyCgJeOZmgusmlzx4=; b=Dg80eefg4baD6Cj47D57vpBsiKF6d5o7WWzYvZ3aouHw/GUuVslih+JSx5ay1XFeIy M82YmVWKmCFIDuE/rilLhKwuaUaBOQPWzQstA7BDz6kGsLdQTQQMmVaDuCrfoAn27Bx3 DOParXeqagyhjSNTuWSKYBPbOLwbGS6MYx++RZHJvW8amQ1f1sCNc4dQhH7x3eE0MXDF B/rUMIXebo2VzzbV4AbASrA4l3ImcoTVY1flXg4qEY2tgO8WKFppGP0Sowouzqseuq16 Cn6Wb/UyXitsxZzfcQv4zqmzLRSrt5WH8Y7ypwkygMJtQVF3hYn38STGe/A6/We9KDqf X7ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682087832; x=1684679832; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rqdViajAeNRKoM+fdqJjjwXsteiyCgJeOZmgusmlzx4=; b=OlEAsxYyAt/0HpuFR0S717FH2syFs0UJ3gGQnULU+au0gg98+UUNsE9KABq+zdiZZ3 S1yiWYevJdyWCCMZPLGNb9MIHysQMVQo+WX5xt5Gwn+X3+pOzp8dH0iRko19q7H21hss aSeXwy/omUHaL/Dev3OzIcRcTtMxYxVnijKwWMaEtvdOGDr8msYHkm0yHeNGXV6tozNf ZCd7MN0YKR+e2qL5C0MdRwpCeReunaCjnjC7wXH6SmoEkWHeUH8SgIRsffwT+GW71cJ1 O8l6jK3ZiNu0t2cVVnejg7w0zhTBDhYgObv3TaFjEbrDzqDx1/g5p8DxHci2OKnuTIGs Wbzw== X-Gm-Message-State: AAQBX9dfXJ4VGaVe7qDetQmFMbtJo9YBh9APi1aLDAcV5briUqWGYX8D zRDVgTtxAAQEmROH0ksW2hI= X-Google-Smtp-Source: AKy350ahf3obWs94ix/YXjEXuZI1y8KeY5KkZOuNplbHTOqwHwb07LMntJ96k+NtedAjVDrnzuuMpw== X-Received: by 2002:a17:906:fcd4:b0:94f:50d:e16e with SMTP id qx20-20020a170906fcd400b0094f050de16emr2808682ejb.12.1682087832574; Fri, 21 Apr 2023 07:37:12 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id q27-20020a170906361b00b0094e1026bc66sm2168244ejb.140.2023.04.21.07.37.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Apr 2023 07:37:12 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [RFC PATCH net-next 08/22] net: dsa: mt7530: change p{5,6}_interface to p{5,6}_configured Date: Fri, 21 Apr 2023 17:36:34 +0300 Message-Id: <20230421143648.87889-9-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230421143648.87889-1-arinc.unal@arinc9.com> References: <20230421143648.87889-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL The idea of p5_interface and p6_interface pointers is to prevent mt753x_mac_config() from running twice for MT7531, as it's already run with mt753x_cpu_port_enable() from mt7531_setup_common(), if the port is used as a CPU port. Change p5_interface and p6_interface to p5_configured and p6_configured. Make them boolean. Do not set them for any other reason. The priv->p5_intf_sel check is useless as in this code path, it will always be P5_INTF_SEL_GMAC5. There was also no need to set priv->p5_interface and priv->p6_interface to PHY_INTERFACE_MODE_NA on mt7530_setup() and mt7531_setup() as they would already be set to that when "priv" is allocated. The pointers were of the phy_interface_t enumeration type, and the first element of the enum is PHY_INTERFACE_MODE_NA. There was nothing in between that would change this beforehand. Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Acked-by: Daniel Golle --- drivers/net/dsa/mt7530.c | 19 ++++--------------- drivers/net/dsa/mt7530.h | 10 ++++++---- 2 files changed, 10 insertions(+), 19 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index bac2388319a3..2f670e512415 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2237,8 +2237,6 @@ mt7530_setup(struct dsa_switch *ds) val |=3D MHWTRAP_MANUAL; mt7530_write(priv, MT7530_MHWTRAP, val); =20 - priv->p6_interface =3D PHY_INTERFACE_MODE_NA; - /* Enable and reset MIB counters */ mt7530_mib_reset(ds); =20 @@ -2460,10 +2458,6 @@ mt7531_setup(struct dsa_switch *ds) mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, MT7531_GPIO0_INTERRUPT); =20 - /* Let phylink decide the interface later. */ - priv->p5_interface =3D PHY_INTERFACE_MODE_NA; - priv->p6_interface =3D PHY_INTERFACE_MODE_NA; - /* Enable PHY core PLL, since phy_device has not yet been created * provided for phy_[read,write]_mmd_indirect is called, we provide * our own mt7531_ind_mmd_phy_[read,write] to complete this @@ -2733,25 +2727,20 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, in= t port, unsigned int mode, goto unsupported; break; case 5: /* Port 5, can be used as a CPU port. */ - if (priv->p5_interface =3D=3D state->interface) + if (priv->p5_configured) break; =20 if (mt753x_mac_config(ds, port, mode, state) < 0) goto unsupported; - - if (priv->p5_intf_sel !=3D P5_DISABLED) - priv->p5_interface =3D state->interface; break; case 6: /* Port 6, can be used as a CPU port. */ - if (priv->p6_interface =3D=3D state->interface) + if (priv->p6_configured) break; =20 mt753x_pad_setup(ds, state); =20 if (mt753x_mac_config(ds, port, mode, state) < 0) goto unsupported; - - priv->p6_interface =3D state->interface; break; default: unsupported: @@ -2859,12 +2848,12 @@ mt7531_cpu_port_config(struct dsa_switch *ds, int p= ort) else interface =3D PHY_INTERFACE_MODE_2500BASEX; =20 - priv->p5_interface =3D interface; + priv->p5_configured =3D true; break; case 6: interface =3D PHY_INTERFACE_MODE_2500BASEX; =20 - priv->p6_interface =3D interface; + priv->p6_configured =3D true; break; default: return -EINVAL; diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index f58828577520..c3a37a0f4843 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -745,8 +745,10 @@ struct mt753x_info { * @ports: Holding the state among ports * @reg_mutex: The lock for protecting among process accessing * registers - * @p6_interface: Holding the current port 6 interface - * @p5_interface: Holding the current port 5 interface + * @p6_configured: Flag for distinguishing if port 6 of the MT7531 switch + * is already configured + * @p5_configured: Flag for distinguishing if port 5 of the MT7531 switch + * is already configured * @p5_intf_sel: Holding the current port 5 interface select * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch * has got SGMII @@ -767,8 +769,8 @@ struct mt7530_priv { const struct mt753x_info *info; unsigned int id; bool mcm; - phy_interface_t p6_interface; - phy_interface_t p5_interface; + bool p6_configured; + bool p5_configured; p5_interface_select p5_intf_sel; bool p5_sgmii; u8 mirror_rx; --=20 2.37.2