From nobody Wed Dec 17 11:45:48 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BEFDAC77B72 for ; Thu, 20 Apr 2023 11:05:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234866AbjDTLFv (ORCPT ); Thu, 20 Apr 2023 07:05:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54770 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235277AbjDTLEe (ORCPT ); Thu, 20 Apr 2023 07:04:34 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E256D7695; Thu, 20 Apr 2023 04:03:15 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 969B324E116; Thu, 20 Apr 2023 19:00:55 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 20 Apr 2023 19:00:55 +0800 Received: from ubuntu.localdomain (113.72.144.253) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 20 Apr 2023 19:00:54 +0800 From: Minda Chen To: Emil Renner Berthing , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Pawel Laszczak , Greg Kroah-Hartman , Peter Chen , Roger Quadros , Philipp Zabel CC: , , , , , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Minda Chen" , Mason Huo Subject: [PATCH v5 1/7] dt-bindings: phy: Add StarFive JH7110 USB PHY Date: Thu, 20 Apr 2023 19:00:46 +0800 Message-ID: <20230420110052.3182-2-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230420110052.3182-1-minda.chen@starfivetech.com> References: <20230420110052.3182-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.144.253] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add StarFive JH7110 SoC USB 2.0 PHY dt-binding. Signed-off-by: Minda Chen Reviewed-by: Hal Feng Reviewed-by: Rob Herring --- .../bindings/phy/starfive,jh7110-usb-phy.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-u= sb-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.= yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml new file mode 100644 index 000000000000..269e9f9f12b6 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/starfive,jh7110-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 USB 2.0 PHY + +maintainers: + - Minda Chen + +properties: + compatible: + const: starfive,jh7110-usb-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + clocks: + items: + - description: PHY 125m + - description: app 125m + + clock-names: + items: + - const: 125m + - const: app_125m + +required: + - compatible + - reg + - clocks + - clock-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@10200000 { + compatible =3D "starfive,jh7110-usb-phy"; + reg =3D <0x10200000 0x10000>; + clocks =3D <&syscrg 95>, + <&stgcrg 6>; + clock-names =3D "125m", "app_125m"; + #phy-cells =3D <0>; + }; --=20 2.17.1 From nobody Wed Dec 17 11:45:48 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02EA8C77B72 for ; Thu, 20 Apr 2023 11:09:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235345AbjDTLJB (ORCPT ); Thu, 20 Apr 2023 07:09:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235451AbjDTLI2 (ORCPT ); Thu, 20 Apr 2023 07:08:28 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0265D55B8; Thu, 20 Apr 2023 04:04:37 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 62D5924E12B; Thu, 20 Apr 2023 19:00:56 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 20 Apr 2023 19:00:56 +0800 Received: from ubuntu.localdomain (113.72.144.253) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 20 Apr 2023 19:00:55 +0800 From: Minda Chen To: Emil Renner Berthing , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Pawel Laszczak , Greg Kroah-Hartman , Peter Chen , Roger Quadros , Philipp Zabel CC: , , , , , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Minda Chen" , Mason Huo Subject: [PATCH v5 2/7] dt-bindings: phy: Add StarFive JH7110 PCIe PHY Date: Thu, 20 Apr 2023 19:00:47 +0800 Message-ID: <20230420110052.3182-3-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230420110052.3182-1-minda.chen@starfivetech.com> References: <20230420110052.3182-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.144.253] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add StarFive JH7110 SoC PCIe 2.0 PHY dt-binding. PCIe PHY0 (phy@10210000) can be used as USB 3.0 PHY. Signed-off-by: Minda Chen Reviewed-by: Hal Feng Reviewed-by: Rob Herring --- .../phy/starfive,jh7110-pcie-phy.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-p= cie-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy= .yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml new file mode 100644 index 000000000000..2e83a6164cd1 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 PCIe 2.0 PHY + +maintainers: + - Minda Chen + +properties: + compatible: + const: starfive,jh7110-pcie-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + starfive,sys-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to System Register Controller sys_syscon = node. + - description: PHY connect offset of SYS_SYSCONSAIF__SYSCFG regi= ster for USB PHY. + description: + The phandle to System Register Controller syscon node and the PHY co= nnect offset + of SYS_SYSCONSAIF__SYSCFG register. Connect PHY to USB3 controller. + + starfive,stg-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to System Register Controller stg_syscon = node. + - description: PHY mode offset of STG_SYSCONSAIF__SYSCFG registe= r. + - description: PHY enable for USB offset of STG_SYSCONSAIF__SYSC= FG register. + description: + The phandle to System Register Controller syscon node and the offset + of STG_SYSCONSAIF__SYSCFG register for PCIe PHY. Total 2 regsisters = offset. + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@10210000 { + compatible =3D "starfive,jh7110-pcie-phy"; + reg =3D <0x10210000 0x10000>; + #phy-cells =3D <0>; + starfive,sys-syscon =3D <&sys_syscon 0x18>; + starfive,stg-syscon =3D <&stg_syscon 0x148 0x1f4>; + }; --=20 2.17.1 From nobody Wed Dec 17 11:45:48 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B03BC77B76 for ; Thu, 20 Apr 2023 11:06:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234095AbjDTLGK (ORCPT ); Thu, 20 Apr 2023 07:06:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235388AbjDTLE5 (ORCPT ); Thu, 20 Apr 2023 07:04:57 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 47E924C00; Thu, 20 Apr 2023 04:03:31 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 3752324E2A6; Thu, 20 Apr 2023 19:00:57 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 20 Apr 2023 19:00:57 +0800 Received: from ubuntu.localdomain (113.72.144.253) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 20 Apr 2023 19:00:56 +0800 From: Minda Chen To: Emil Renner Berthing , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Pawel Laszczak , Greg Kroah-Hartman , Peter Chen , Roger Quadros , Philipp Zabel CC: , , , , , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Minda Chen" , Mason Huo Subject: [PATCH v5 3/7] phy: starfive: Add JH7110 USB 2.0 PHY driver Date: Thu, 20 Apr 2023 19:00:48 +0800 Message-ID: <20230420110052.3182-4-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230420110052.3182-1-minda.chen@starfivetech.com> References: <20230420110052.3182-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.144.253] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add Starfive JH7110 SoC USB 2.0 PHY driver support. USB 2.0 PHY default connect to Cadence USB controller. Signed-off-by: Minda Chen --- MAINTAINERS | 6 + drivers/phy/starfive/Kconfig | 11 ++ drivers/phy/starfive/Makefile | 1 + drivers/phy/starfive/phy-jh7110-usb.c | 162 ++++++++++++++++++++++++++ 4 files changed, 180 insertions(+) create mode 100644 drivers/phy/starfive/phy-jh7110-usb.c diff --git a/MAINTAINERS b/MAINTAINERS index 1aef5ba46d71..c09ea66dcd5a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19968,6 +19968,12 @@ M: William Qiu S: Supported F: Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.y= aml =20 +STARFIVE JH71X0 USB PHY DRIVER +M: Minda Chen +S: Supported +F: Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml +F: drivers/phy/starfive/phy-jh7110-usb.c + STATIC BRANCH/CALL M: Peter Zijlstra M: Josh Poimboeuf diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig index f989b8ff8bcb..2c013c390dee 100644 --- a/drivers/phy/starfive/Kconfig +++ b/drivers/phy/starfive/Kconfig @@ -11,3 +11,14 @@ config PHY_STARFIVE_DPHY_RX Choose this option if you have a StarFive D-PHY in your system. If M is selected, the module will be called phy-starfive-dphy-rx. + +config PHY_STARFIVE_JH7110_USB + tristate "Starfive JH7110 USB 2.0 PHY support" + depends on USB_SUPPORT + select GENERIC_PHY + select USB_PHY + help + Enable this to support the StarFive USB 2.0 PHY, + used with the Cadence USB controller. + If M is selected, the module will be called + phy-jh7110-usb.ko. diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile index 7ec576cb30ae..176443852f4d 100644 --- a/drivers/phy/starfive/Makefile +++ b/drivers/phy/starfive/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PHY_STARFIVE_DPHY_RX) +=3D phy-starfive-dphy-rx.o +obj-$(CONFIG_PHY_STARFIVE_JH7110_USB) +=3D phy-jh7110-usb.o diff --git a/drivers/phy/starfive/phy-jh7110-usb.c b/drivers/phy/starfive/p= hy-jh7110-usb.c new file mode 100644 index 000000000000..4a12df0692cd --- /dev/null +++ b/drivers/phy/starfive/phy-jh7110-usb.c @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * StarFive JH7110 USB 2.0 PHY driver + * + * Copyright (C) 2023 StarFive Technology Co., Ltd. + * Author: Minda Chen + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define USB_125M_CLK_RATE 125000000 +#define USB_LS_KEEPALIVE_OFF 0x4 +#define USB_LS_KEEPALIVE_ENABLE BIT(4) + +struct jh7110_usb2_phy { + struct phy *phy; + void __iomem *regs; + struct clk *usb_125m_clk; + struct clk *app_125m; + enum phy_mode mode; +}; + +static void jh7110_usb2_mode_set(struct jh7110_usb2_phy *phy) +{ + unsigned int val; + + if (phy->mode !=3D PHY_MODE_USB_HOST) { + /* Enable the LS speed keep-alive signal */ + val =3D readl(phy->regs + USB_LS_KEEPALIVE_OFF); + val |=3D USB_LS_KEEPALIVE_ENABLE; + writel(val, phy->regs + USB_LS_KEEPALIVE_OFF); + } +} + +static int jh7110_usb2_phy_set_mode(struct phy *_phy, + enum phy_mode mode, int submode) +{ + struct jh7110_usb2_phy *phy =3D phy_get_drvdata(_phy); + + switch (mode) { + case PHY_MODE_USB_HOST: + case PHY_MODE_USB_DEVICE: + case PHY_MODE_USB_OTG: + break; + default: + return -EINVAL; + } + + if (mode !=3D phy->mode) { + dev_info(&_phy->dev, "Changing phy to %d\n", mode); + phy->mode =3D mode; + jh7110_usb2_mode_set(phy); + } + + return 0; +} + +static int jh7110_usb2_phy_init(struct phy *_phy) +{ + struct jh7110_usb2_phy *phy =3D phy_get_drvdata(_phy); + int ret; + + ret =3D clk_set_rate(phy->usb_125m_clk, USB_125M_CLK_RATE); + if (ret) + return ret; + + ret =3D clk_prepare_enable(phy->app_125m); + if (ret) + return ret; + + return 0; +} + +static int jh7110_usb2_phy_exit(struct phy *_phy) +{ + struct jh7110_usb2_phy *phy =3D phy_get_drvdata(_phy); + + clk_disable_unprepare(phy->app_125m); + + return 0; +} + +static const struct phy_ops jh7110_usb2_phy_ops =3D { + .init =3D jh7110_usb2_phy_init, + .exit =3D jh7110_usb2_phy_exit, + .set_mode =3D jh7110_usb2_phy_set_mode, + .owner =3D THIS_MODULE, +}; + +static int jh7110_usb_phy_probe(struct platform_device *pdev) +{ + struct jh7110_usb2_phy *phy; + struct device *dev =3D &pdev->dev; + struct phy_provider *phy_provider; + + phy =3D devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); + if (!phy) + return -ENOMEM; + + phy->usb_125m_clk =3D devm_clk_get(dev, "125m"); + if (IS_ERR(phy->usb_125m_clk)) + return dev_err_probe(dev, PTR_ERR(phy->usb_125m_clk), + "Failed to get 125m clock\n"); + + phy->app_125m =3D devm_clk_get(dev, "app_125m"); + if (IS_ERR(phy->app_125m)) + return dev_err_probe(dev, PTR_ERR(phy->app_125m), + "Failed to get app 125m clock\n"); + + phy->regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(phy->regs)) + return dev_err_probe(dev, PTR_ERR(phy->regs), + "Failed to map phy base\n"); + + phy->phy =3D devm_phy_create(dev, NULL, &jh7110_usb2_phy_ops); + if (IS_ERR(phy->phy)) + return dev_err_probe(dev, PTR_ERR(phy->phy), + "Failed to create phy\n"); + + platform_set_drvdata(pdev, phy); + phy_set_drvdata(phy->phy, phy); + phy_provider =3D devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static int jh7110_usb_phy_remove(struct platform_device *pdev) +{ + struct jh7110_usb2_phy *phy =3D platform_get_drvdata(pdev); + + clk_disable_unprepare(phy->app_125m); + platform_set_drvdata(pdev, NULL); + + return 0; +} + +static const struct of_device_id jh7110_usb_phy_of_match[] =3D { + { .compatible =3D "starfive,jh7110-usb-phy" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, jh7110_usb_phy_of_match); + +static struct platform_driver jh7110_usb_phy_driver =3D { + .probe =3D jh7110_usb_phy_probe, + .remove =3D jh7110_usb_phy_remove, + .driver =3D { + .of_match_table =3D jh7110_usb_phy_of_match, + .name =3D "jh7110-usb-phy", + } +}; +module_platform_driver(jh7110_usb_phy_driver); + +MODULE_DESCRIPTION("StarFive JH7110 USB 2.0 PHY driver"); +MODULE_AUTHOR("Minda Chen "); +MODULE_LICENSE("GPL"); --=20 2.17.1 From nobody Wed Dec 17 11:45:48 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F43EC77B7C for ; Thu, 20 Apr 2023 11:03:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235297AbjDTLDe (ORCPT ); Thu, 20 Apr 2023 07:03:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48308 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235261AbjDTLDS (ORCPT ); Thu, 20 Apr 2023 07:03:18 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24DB0AD26; Thu, 20 Apr 2023 04:01:45 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 04B3F24E2A7; Thu, 20 Apr 2023 19:00:58 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 20 Apr 2023 19:00:58 +0800 Received: from ubuntu.localdomain (113.72.144.253) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 20 Apr 2023 19:00:56 +0800 From: Minda Chen To: Emil Renner Berthing , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Pawel Laszczak , Greg Kroah-Hartman , Peter Chen , Roger Quadros , Philipp Zabel CC: , , , , , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Minda Chen" , Mason Huo Subject: [PATCH v5 4/7] phy: starfive: Add JH7110 PCIE 2.0 PHY driver Date: Thu, 20 Apr 2023 19:00:49 +0800 Message-ID: <20230420110052.3182-5-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230420110052.3182-1-minda.chen@starfivetech.com> References: <20230420110052.3182-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.144.253] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add Starfive JH7110 SoC PCIe 2.0 PHY driver support. PCIe 2.0 PHY default connect to PCIe controller. But pcie0 PHY can connect to USB 3.0 controlller. Signed-off-by: Minda Chen --- MAINTAINERS | 4 +- drivers/phy/starfive/Kconfig | 11 ++ drivers/phy/starfive/Makefile | 1 + drivers/phy/starfive/phy-jh7110-pcie.c | 202 +++++++++++++++++++++++++ 4 files changed, 217 insertions(+), 1 deletion(-) create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c diff --git a/MAINTAINERS b/MAINTAINERS index c09ea66dcd5a..8e0f755ba91b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19968,10 +19968,12 @@ M: William Qiu S: Supported F: Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.y= aml =20 -STARFIVE JH71X0 USB PHY DRIVER +STARFIVE JH71X0 PCIE AND USB PHY DRIVER M: Minda Chen S: Supported +F: Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml F: Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml +F: drivers/phy/starfive/phy-jh7110-pcie.c F: drivers/phy/starfive/phy-jh7110-usb.c =20 STATIC BRANCH/CALL diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig index 2c013c390dee..c21c21d284a6 100644 --- a/drivers/phy/starfive/Kconfig +++ b/drivers/phy/starfive/Kconfig @@ -12,6 +12,17 @@ config PHY_STARFIVE_DPHY_RX system. If M is selected, the module will be called phy-starfive-dphy-rx. =20 +config PHY_STARFIVE_JH7110_PCIE + tristate "Starfive JH7110 PCIE 2.0/USB 3.0 PHY support" + depends on USB_SUPPORT + select GENERIC_PHY + select USB_PHY + help + Enable this to support the StarFive PCIe 2.0 PHY, + or used as USB 3.0 PHY. + If M is selected, the module will be called + phy-jh7110-pcie.ko. + config PHY_STARFIVE_JH7110_USB tristate "Starfive JH7110 USB 2.0 PHY support" depends on USB_SUPPORT diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile index 176443852f4d..03a55aad53a2 100644 --- a/drivers/phy/starfive/Makefile +++ b/drivers/phy/starfive/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PHY_STARFIVE_DPHY_RX) +=3D phy-starfive-dphy-rx.o +obj-$(CONFIG_PHY_STARFIVE_JH7110_PCIE) +=3D phy-jh7110-pcie.o obj-$(CONFIG_PHY_STARFIVE_JH7110_USB) +=3D phy-jh7110-usb.o diff --git a/drivers/phy/starfive/phy-jh7110-pcie.c b/drivers/phy/starfive/= phy-jh7110-pcie.c new file mode 100644 index 000000000000..fe029daef62e --- /dev/null +++ b/drivers/phy/starfive/phy-jh7110-pcie.c @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * StarFive JH7110 PCIe 2.0 PHY driver + * + * Copyright (C) 2023 StarFive Technology Co., Ltd. + * Author: Minda Chen + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCIE_KVCO_LEVEL_OFF (0x28) +#define PCIE_USB3_PHY_PLL_CTL_OFF (0x7c) +#define PCIE_KVCO_TUNE_SIGNAL_OFF (0x80) +#define PCIE_USB3_PHY_ENABLE BIT(4) +#define PHY_KVCO_FINE_TUNE_LEVEL 0x91 +#define PHY_KVCO_FINE_TUNE_SIGNALS 0xc + +#define USB_PDRSTN_SPLIT BIT(17) + +#define PCIE_PHY_MODE BIT(20) +#define PCIE_PHY_MODE_MASK GENMASK(21, 20) +#define PCIE_USB3_BUS_WIDTH_MASK GENMASK(3, 2) +#define PCIE_USB3_RATE_MASK GENMASK(6, 5) +#define PCIE_USB3_RX_STANDBY_MASK BIT(7) +#define PCIE_USB3_PHY_ENABLE BIT(4) + +struct jh7110_pcie_phy { + struct phy *phy; + struct regmap *stg_syscon; + struct regmap *sys_syscon; + void __iomem *regs; + u32 sys_phy_connect; + u32 stg_pcie_mode; + u32 stg_pcie_usb; + enum phy_mode mode; +}; + +static int jh7110_usb3_mode_set(struct jh7110_pcie_phy *data) +{ + if (!data->stg_syscon || !data->sys_syscon) { + dev_info(&data->phy->dev, "don't support usb3 mode\n"); + return -EINVAL; + } + + regmap_update_bits(data->stg_syscon, data->stg_pcie_mode, + PCIE_PHY_MODE_MASK, PCIE_PHY_MODE); + regmap_update_bits(data->stg_syscon, data->stg_pcie_usb, + PCIE_USB3_BUS_WIDTH_MASK, 0); + regmap_update_bits(data->stg_syscon, data->stg_pcie_usb, + PCIE_USB3_RATE_MASK, 0); + regmap_update_bits(data->stg_syscon, data->stg_pcie_usb, + PCIE_USB3_RX_STANDBY_MASK, 0); + regmap_update_bits(data->stg_syscon, data->stg_pcie_usb, + PCIE_USB3_PHY_ENABLE, PCIE_USB3_PHY_ENABLE); + + /* Connect usb 3.0 phy mode */ + regmap_update_bits(data->sys_syscon, data->sys_phy_connect, + USB_PDRSTN_SPLIT, 0); + + /* Configuare spread-spectrum mode: down-spread-spectrum */ + writel(PCIE_USB3_PHY_ENABLE, data->regs + PCIE_USB3_PHY_PLL_CTL_OFF); + + return 0; +} + +static void jh7110_pcie_mode_set(struct jh7110_pcie_phy *phy) +{ + /* PCIe Multi-PHY PLL KVCO Gain fine tune settings: */ + writel(PHY_KVCO_FINE_TUNE_LEVEL, phy->regs + PCIE_KVCO_LEVEL_OFF); + writel(PHY_KVCO_FINE_TUNE_SIGNALS, phy->regs + PCIE_KVCO_TUNE_SIGNAL_OFF); +} + +static int jh7110_pcie_phy_set_mode(struct phy *_phy, + enum phy_mode mode, int submode) +{ + struct jh7110_pcie_phy *phy =3D phy_get_drvdata(_phy); + int ret; + + if (mode =3D=3D phy->mode) + return 0; + + switch (mode) { + case PHY_MODE_USB_HOST: + case PHY_MODE_USB_DEVICE: + case PHY_MODE_USB_OTG: + ret =3D jh7110_usb3_mode_set(phy); + if (ret) + return ret; + break; + case PHY_MODE_PCIE: + jh7110_pcie_mode_set(phy); + break; + default: + return -EINVAL; + } + + dev_info(&_phy->dev, "Changing phy mode to %d\n", mode); + phy->mode =3D mode; + + return 0; +} + +static int jh7110_pcie_phy_init(struct phy *_phy) +{ + return 0; +} + +static int jh7110_pcie_phy_exit(struct phy *_phy) +{ + return 0; +} + +static const struct phy_ops jh7110_pcie_phy_ops =3D { + .init =3D jh7110_pcie_phy_init, + .exit =3D jh7110_pcie_phy_exit, + .set_mode =3D jh7110_pcie_phy_set_mode, + .owner =3D THIS_MODULE, +}; + +static int jh7110_pcie_phy_probe(struct platform_device *pdev) +{ + struct jh7110_pcie_phy *phy; + struct device *dev =3D &pdev->dev; + struct phy_provider *phy_provider; + u32 args[2]; + + phy =3D devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); + if (!phy) + return -ENOMEM; + + phy->regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(phy->regs)) + return PTR_ERR(phy->regs); + + phy->phy =3D devm_phy_create(dev, NULL, &jh7110_pcie_phy_ops); + if (IS_ERR(phy->phy)) + return dev_err_probe(dev, PTR_ERR(phy->regs), + "Failed to map phy base\n"); + + phy->sys_syscon =3D + syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node, + "starfive,sys-syscon", + 1, args); + + if (!IS_ERR_OR_NULL(phy->sys_syscon)) + phy->sys_phy_connect =3D args[0]; + else + phy->sys_syscon =3D NULL; + + phy->stg_syscon =3D + syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node, + "starfive,stg-syscon", + 2, args); + + if (!IS_ERR_OR_NULL(phy->stg_syscon)) { + phy->stg_pcie_mode =3D args[0]; + phy->stg_pcie_usb =3D args[1]; + } else { + phy->stg_syscon =3D NULL; + } + + platform_set_drvdata(pdev, phy); + phy_set_drvdata(phy->phy, phy); + phy_provider =3D devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static int jh7110_pcie_phy_remove(struct platform_device *pdev) +{ + platform_set_drvdata(pdev, NULL); + + return 0; +} + +static const struct of_device_id jh7110_pcie_phy_of_match[] =3D { + { .compatible =3D "starfive,jh7110-pcie-phy" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, jh7110_pcie_phy_of_match); + +static struct platform_driver jh7110_pcie_phy_driver =3D { + .probe =3D jh7110_pcie_phy_probe, + .remove =3D jh7110_pcie_phy_remove, + .driver =3D { + .of_match_table =3D jh7110_pcie_phy_of_match, + .name =3D "jh7110-pcie-phy", + } +}; +module_platform_driver(jh7110_pcie_phy_driver); + +MODULE_DESCRIPTION("StarFive JH7110 PCIe 2.0 PHY driver"); +MODULE_AUTHOR("Minda Chen "); +MODULE_LICENSE("GPL"); --=20 2.17.1 From nobody Wed Dec 17 11:45:48 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F791C77B72 for ; Thu, 20 Apr 2023 11:03:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234953AbjDTLDj (ORCPT ); Thu, 20 Apr 2023 07:03:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48494 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234917AbjDTLDT (ORCPT ); Thu, 20 Apr 2023 07:03:19 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 809F6559D; Thu, 20 Apr 2023 04:01:53 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id D76EF24E1C6; Thu, 20 Apr 2023 19:00:58 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 20 Apr 2023 19:00:58 +0800 Received: from ubuntu.localdomain (113.72.144.253) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 20 Apr 2023 19:00:57 +0800 From: Minda Chen To: Emil Renner Berthing , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Pawel Laszczak , Greg Kroah-Hartman , Peter Chen , Roger Quadros , Philipp Zabel CC: , , , , , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Minda Chen" , Mason Huo Subject: [PATCH v5 5/7] dt-bindings: usb: Add StarFive JH7110 USB controller Date: Thu, 20 Apr 2023 19:00:50 +0800 Message-ID: <20230420110052.3182-6-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230420110052.3182-1-minda.chen@starfivetech.com> References: <20230420110052.3182-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.144.253] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" StarFive JH7110 platforms USB have a wrapper module around the Cadence USBSS-DRD controller. Add binding information doc for that. Signed-off-by: Minda Chen Reviewed-by: Peter Chen Reviewed-by: Hal Feng --- .../bindings/usb/starfive,jh7110-usb.yaml | 131 ++++++++++++++++++ 1 file changed, 131 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-u= sb.yaml diff --git a/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml= b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml new file mode 100644 index 000000000000..e6bd8a583da3 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/starfive,jh7110-usb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 Cadence USBSS-DRD SoC controller + +maintainers: + - Minda Chen + +properties: + compatible: + const: starfive,jh7110-usb + + reg: + items: + - description: OTG controller registers + - description: XHCI Host controller registers + - description: DEVICE controller registers + + reg-names: + items: + - const: otg + - const: xhci + - const: dev + + interrupts: + items: + - description: XHCI host controller interrupt + - description: Device controller interrupt + - description: OTG/DRD controller interrupt + + interrupt-names: + items: + - const: host + - const: peripheral + - const: otg + + clocks: + items: + - description: low power clock + - description: STB clock + - description: APB clock + - description: AXI clock + - description: UTMI APB clock + + clock-names: + items: + - const: lpm + - const: stb + - const: apb + - const: axi + - const: utmi_apb + + resets: + items: + - description: Power up reset + - description: APB clock reset + - description: AXI clock reset + - description: UTMI APB clock reset + + reset-names: + items: + - const: pwrup + - const: apb + - const: axi + - const: utmi_apb + + starfive,stg-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to System Register Controller stg_syscon= node. + - description: dr mode register offset of STG_SYSCONSAIF__SYSCF= G register for USB. + description: + The phandle to System Register Controller syscon node and the offset + of STG_SYSCONSAIF__SYSCFG register for USB. + + dr_mode: + enum: [host, otg, peripheral] + + phys: + minItems: 1 + maxItems: 2 + + phy-names: + minItems: 1 + maxItems: 2 + items: + anyOf: + - const: usb2 + - const: usb3 + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - clocks + - resets + - starfive,stg-syscon + - dr_mode + +additionalProperties: false + +examples: + - | + usb@10100000 { + compatible =3D "starfive,jh7110-usb"; + reg =3D <0x10100000 0x10000>, + <0x10110000 0x10000>, + <0x10120000 0x10000>; + reg-names =3D "otg", "xhci", "dev"; + interrupts =3D <100>, <108>, <110>; + interrupt-names =3D "host", "peripheral", "otg"; + clocks =3D <&syscrg 4>, + <&stgcrg 5>, + <&stgcrg 1>, + <&stgcrg 3>, + <&stgcrg 2>; + clock-names =3D "lpm", "stb", "apb", "axi", "utmi_apb"; + resets =3D <&stgcrg 10>, + <&stgcrg 8>, + <&stgcrg 7>, + <&stgcrg 9>; + reset-names =3D "pwrup", "apb", "axi", "utmi_apb"; + starfive,stg-syscon =3D <&stg_syscon 0x4>; + dr_mode =3D "host"; + }; --=20 2.17.1 From nobody Wed Dec 17 11:45:48 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3311DC77B73 for ; Thu, 20 Apr 2023 11:05:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235303AbjDTLFr (ORCPT ); Thu, 20 Apr 2023 07:05:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54778 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235283AbjDTLEf (ORCPT ); Thu, 20 Apr 2023 07:04:35 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 71D9A9F; Thu, 20 Apr 2023 04:03:15 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id C14C124E1D1; Thu, 20 Apr 2023 19:00:59 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 20 Apr 2023 19:00:59 +0800 Received: from ubuntu.localdomain (113.72.144.253) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 20 Apr 2023 19:00:58 +0800 From: Minda Chen To: Emil Renner Berthing , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Pawel Laszczak , Greg Kroah-Hartman , Peter Chen , Roger Quadros , Philipp Zabel CC: , , , , , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Minda Chen" , Mason Huo Subject: [PATCH v5 6/7] usb: cdns3: Add StarFive JH7110 USB driver Date: Thu, 20 Apr 2023 19:00:51 +0800 Message-ID: <20230420110052.3182-7-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230420110052.3182-1-minda.chen@starfivetech.com> References: <20230420110052.3182-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.144.253] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Adds Specific Glue layer to support USB peripherals on StarFive JH7110 SoC. There is a Cadence USB3 core for JH7110 SoCs, the cdns core is the child of this USB wrapper module device. Signed-off-by: Minda Chen Acked-by: Peter Chen --- MAINTAINERS | 6 + drivers/usb/cdns3/Kconfig | 11 + drivers/usb/cdns3/Makefile | 1 + drivers/usb/cdns3/cdns3-starfive.c | 390 +++++++++++++++++++++++++++++ drivers/usb/cdns3/core.h | 3 + 5 files changed, 411 insertions(+) create mode 100644 drivers/usb/cdns3/cdns3-starfive.c diff --git a/MAINTAINERS b/MAINTAINERS index 8e0f755ba91b..3164a5cef6ee 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19976,6 +19976,12 @@ F: Documentation/devicetree/bindings/phy/starfive,= jh7110-usb-phy.yaml F: drivers/phy/starfive/phy-jh7110-pcie.c F: drivers/phy/starfive/phy-jh7110-usb.c =20 +STARFIVE JH71X0 USB DRIVERS +M: Minda Chen +S: Maintained +F: Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml +F: drivers/usb/cdns3/cdns3-starfive.c + STATIC BRANCH/CALL M: Peter Zijlstra M: Josh Poimboeuf diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig index b98ca0a1352a..0a514b591527 100644 --- a/drivers/usb/cdns3/Kconfig +++ b/drivers/usb/cdns3/Kconfig @@ -78,6 +78,17 @@ config USB_CDNS3_IMX =20 For example, imx8qm and imx8qxp. =20 +config USB_CDNS3_STARFIVE + tristate "Cadence USB3 support on StarFive SoC platforms" + depends on ARCH_STARFIVE || COMPILE_TEST + help + Say 'Y' or 'M' here if you are building for StarFive SoCs + platforms that contain Cadence USB3 controller core. + + e.g. JH7110. + + If you choose to build this driver as module it will + be dynamically linked and module will be called cdns3-starfive.ko endif =20 if USB_CDNS_SUPPORT diff --git a/drivers/usb/cdns3/Makefile b/drivers/usb/cdns3/Makefile index 61edb2f89276..48dfae75b5aa 100644 --- a/drivers/usb/cdns3/Makefile +++ b/drivers/usb/cdns3/Makefile @@ -24,6 +24,7 @@ endif obj-$(CONFIG_USB_CDNS3_PCI_WRAP) +=3D cdns3-pci-wrap.o obj-$(CONFIG_USB_CDNS3_TI) +=3D cdns3-ti.o obj-$(CONFIG_USB_CDNS3_IMX) +=3D cdns3-imx.o +obj-$(CONFIG_USB_CDNS3_STARFIVE) +=3D cdns3-starfive.o =20 cdnsp-udc-pci-y :=3D cdnsp-pci.o =20 diff --git a/drivers/usb/cdns3/cdns3-starfive.c b/drivers/usb/cdns3/cdns3-s= tarfive.c new file mode 100644 index 000000000000..afe1c6652660 --- /dev/null +++ b/drivers/usb/cdns3/cdns3-starfive.c @@ -0,0 +1,390 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * cdns3-starfive.c - StarFive specific Glue layer for Cadence USB Control= ler + * + * Copyright (C) 2023 StarFive Technology Co., Ltd. + * + * Author: Yanhong Wang + * Author: Mason Huo + * Author: Minda Chen + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "core.h" + +#define USB_STRAP_HOST BIT(17) +#define USB_STRAP_DEVICE BIT(18) +#define USB_STRAP_MASK GENMASK(18, 16) + +#define USB_SUSPENDM_HOST BIT(19) +#define USB_SUSPENDM_MASK BIT(19) +#define CDNS_IRQ_WAKEUP_INDEX 3 + +struct cdns_starfive { + struct device *dev; + struct phy *usb2_phy; + struct phy *usb3_phy; + struct regmap *stg_syscon; + struct reset_control *resets; + struct clk_bulk_data *clks; + int num_clks; + enum phy_mode phy_mode; + u32 stg_usb_mode; +}; + +static int set_phy_power_on(struct cdns_starfive *data) +{ + int ret; + + ret =3D phy_power_on(data->usb2_phy); + if (ret) + return ret; + + ret =3D phy_power_on(data->usb3_phy); + if (ret) + phy_power_off(data->usb2_phy); + + return ret; +} + +static void cdns_mode_init(struct platform_device *pdev, + struct cdns_starfive *data) +{ + enum usb_dr_mode mode; + + mode =3D usb_get_dr_mode(&pdev->dev); + + switch (mode) { + case USB_DR_MODE_HOST: + regmap_update_bits(data->stg_syscon, + data->stg_usb_mode, + USB_STRAP_MASK, + USB_STRAP_HOST); + regmap_update_bits(data->stg_syscon, + data->stg_usb_mode, + USB_SUSPENDM_MASK, + USB_SUSPENDM_HOST); + data->phy_mode =3D PHY_MODE_USB_HOST; + break; + + case USB_DR_MODE_PERIPHERAL: + regmap_update_bits(data->stg_syscon, data->stg_usb_mode, + USB_STRAP_MASK, USB_STRAP_DEVICE); + regmap_update_bits(data->stg_syscon, data->stg_usb_mode, + USB_SUSPENDM_MASK, 0); + data->phy_mode =3D PHY_MODE_USB_DEVICE; + break; + + case USB_DR_MODE_OTG: + data->phy_mode =3D PHY_MODE_USB_OTG; + default: + break; + } +} + +static int cdns_clk_rst_init(struct cdns_starfive *data) +{ + int ret; + + ret =3D clk_bulk_prepare_enable(data->num_clks, data->clks); + if (ret) + return dev_err_probe(data->dev, ret, + "failed to enable clocks\n"); + + ret =3D reset_control_deassert(data->resets); + if (ret) { + dev_err(data->dev, "failed to reset clocks\n"); + goto err_clk_init; + } + + return ret; + +err_clk_init: + clk_bulk_disable_unprepare(data->num_clks, data->clks); + return ret; +} + +static void cdns_clk_rst_deinit(struct cdns_starfive *data) +{ + reset_control_assert(data->resets); + clk_bulk_disable_unprepare(data->num_clks, data->clks); +} + +static int cdns_starfive_phy_init(struct cdns_starfive *data) +{ + int ret; + + ret =3D phy_init(data->usb2_phy); + if (ret) + return ret; + + ret =3D phy_init(data->usb3_phy); + if (ret) + goto err_phy3_init; + + phy_set_mode(data->usb2_phy, data->phy_mode); + phy_set_mode(data->usb3_phy, data->phy_mode); + + ret =3D set_phy_power_on(data); + if (ret) + goto err_phy_power_on; + + return 0; + +err_phy_power_on: + phy_exit(data->usb3_phy); +err_phy3_init: + phy_exit(data->usb2_phy); + return ret; +} + +static void cdns_starfive_phy_deinit(struct cdns_starfive *data) +{ + phy_power_off(data->usb3_phy); + phy_power_off(data->usb2_phy); + phy_exit(data->usb3_phy); + phy_exit(data->usb2_phy); +} + +static int cdns_starfive_platform_device_add(struct platform_device *pdev, + struct cdns_starfive *data) +{ + struct platform_device *cdns3; + struct resource cdns_res[CDNS_RESOURCES_NUM], *res; + struct device *dev =3D &pdev->dev; + const char *reg_name[CDNS_IOMEM_RESOURCES_NUM] =3D {"otg", "xhci", "dev"}; + const char *irq_name[CDNS_IRQ_RESOURCES_NUM] =3D {"host", "peripheral", "= otg", "wakeup"}; + int i, ret, res_idx =3D 0; + + cdns3 =3D platform_device_alloc("cdns-usb3", PLATFORM_DEVID_AUTO); + if (!cdns3) + return dev_err_probe(dev, -ENOMEM, + "couldn't alloc cdns3 usb device\n"); + + cdns3->dev.parent =3D dev; + memset(cdns_res, 0, sizeof(cdns_res)); + + for (i =3D 0; i < CDNS_IOMEM_RESOURCES_NUM; i++) { + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, reg_name[i]); + if (!res) { + ret =3D dev_err_probe(dev, + -ENXIO, + "couldn't get %s reg resource\n", + reg_name[i]); + goto free_memory; + } + cdns_res[res_idx] =3D *res; + res_idx++; + } + + for (i =3D 0; i < CDNS_IRQ_RESOURCES_NUM; i++) { + if (i =3D=3D CDNS_IRQ_WAKEUP_INDEX) { + ret =3D platform_get_irq_byname_optional(pdev, irq_name[i]); + if (ret < 0) + continue; + } else { + ret =3D platform_get_irq_byname(pdev, irq_name[i]); + if (ret < 0) { + dev_err(dev, "couldn't get %s irq\n", irq_name[i]); + goto free_memory; + } + } + cdns_res[res_idx].start =3D ret; + cdns_res[res_idx].end =3D ret; + cdns_res[res_idx].flags =3D IORESOURCE_IRQ; + cdns_res[res_idx].name =3D irq_name[i]; + res_idx++; + } + + ret =3D platform_device_add_resources(cdns3, cdns_res, res_idx); + if (ret) { + dev_err(dev, "couldn't add res to cdns3 device\n"); + goto free_memory; + } + + ret =3D platform_device_add(cdns3); + if (ret) { + dev_err(dev, "failed to register cdns3 device\n"); + goto free_memory; + } + + return ret; +free_memory: + platform_device_put(cdns3); + return ret; +} + +static int cdns_starfive_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct cdns_starfive *data; + unsigned int args; + int ret; + + data =3D devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + platform_set_drvdata(pdev, data); + + data->dev =3D dev; + + data->stg_syscon =3D + syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node, + "starfive,stg-syscon", 1, &args); + + if (IS_ERR(data->stg_syscon)) + return dev_err_probe(dev, PTR_ERR(data->stg_syscon), + "Failed to parse starfive,stg-syscon\n"); + + data->stg_usb_mode =3D args; + + data->num_clks =3D devm_clk_bulk_get_all(data->dev, &data->clks); + if (data->num_clks < 0) + return dev_err_probe(data->dev, -ENODEV, + "Failed to get clocks\n"); + + data->resets =3D devm_reset_control_array_get_exclusive(data->dev); + if (IS_ERR(data->resets)) + return dev_err_probe(data->dev, PTR_ERR(data->resets), + "Failed to get resets"); + + data->usb2_phy =3D devm_phy_optional_get(dev, "usb2"); + if (IS_ERR(data->usb2_phy)) + return dev_err_probe(dev, PTR_ERR(data->usb2_phy), + "Failed to parse usb2 PHY\n"); + + data->usb3_phy =3D devm_phy_optional_get(dev, "usb3"); + if (IS_ERR(data->usb3_phy)) + return dev_err_probe(dev, PTR_ERR(data->usb3_phy), + "Failed to parse usb3 PHY\n"); + + cdns_mode_init(pdev, data); + + ret =3D cdns_clk_rst_init(data); + if (ret) + return ret; + + ret =3D cdns_starfive_phy_init(data); + if (ret) { + dev_err(dev, "Failed to init PHY\n"); + goto err_clk_init; + } + + ret =3D cdns_starfive_platform_device_add(pdev, data); + if (ret) { + dev_err(dev, "Failed to create children\n"); + goto err_phy_init; + } + + device_set_wakeup_capable(dev, true); + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + + dev_info(dev, "usb mode %d probe success\n", data->phy_mode); + + return 0; + +err_phy_init: + cdns_starfive_phy_deinit(data); +err_clk_init: + cdns_clk_rst_deinit(data); + return ret; +} + +static int cdns_starfive_remove_core(struct device *dev, void *c) +{ + struct platform_device *pdev =3D to_platform_device(dev); + + platform_device_unregister(pdev); + + return 0; +} + +static int cdns_starfive_remove(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct cdns_starfive *data =3D dev_get_drvdata(dev); + + pm_runtime_get_sync(dev); + device_for_each_child(dev, NULL, cdns_starfive_remove_core); + + cdns_starfive_phy_deinit(data); + cdns_clk_rst_deinit(data); + pm_runtime_disable(dev); + pm_runtime_put_noidle(dev); + platform_set_drvdata(pdev, NULL); + + return 0; +} + +#ifdef CONFIG_PM +static int cdns_starfive_resume(struct device *dev) +{ + struct cdns_starfive *data =3D dev_get_drvdata(dev); + int ret; + + ret =3D clk_bulk_prepare_enable(data->num_clks, data->clks); + if (ret) + return ret; + + ret =3D reset_control_deassert(data->resets); + if (ret) { + clk_bulk_disable_unprepare(data->num_clks, data->clks); + return ret; + } + + ret =3D cdns_starfive_phy_init(data); + if (ret) + cdns_clk_rst_deinit(data); + + return ret; +} + +static int cdns_starfive_suspend(struct device *dev) +{ + struct cdns_starfive *data =3D dev_get_drvdata(dev); + + cdns_starfive_phy_deinit(data); + cdns_clk_rst_deinit(data); + return 0; +} +#endif + +static const struct dev_pm_ops cdns_starfive_pm_ops =3D { + SET_RUNTIME_PM_OPS(cdns_starfive_suspend, cdns_starfive_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(cdns_starfive_suspend, cdns_starfive_resume) +}; + +static const struct of_device_id cdns_starfive_of_match[] =3D { + { .compatible =3D "starfive,jh7110-usb", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, cdns_starfive_of_match); + +static struct platform_driver cdns_starfive_driver =3D { + .probe =3D cdns_starfive_probe, + .remove =3D cdns_starfive_remove, + .driver =3D { + .name =3D "cdns3-starfive", + .of_match_table =3D cdns_starfive_of_match, + .pm =3D &cdns_starfive_pm_ops, + }, +}; +module_platform_driver(cdns_starfive_driver); + +MODULE_ALIAS("platform:cdns3-starfive"); +MODULE_AUTHOR("YanHong Wang "); +MODULE_AUTHOR("Mason Huo "); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Cadence USB3 StarFive Glue Layer"); diff --git a/drivers/usb/cdns3/core.h b/drivers/usb/cdns3/core.h index 2d332a788871..8d44ab504898 100644 --- a/drivers/usb/cdns3/core.h +++ b/drivers/usb/cdns3/core.h @@ -38,6 +38,9 @@ struct cdns_role_driver { }; =20 #define CDNS_XHCI_RESOURCES_NUM 2 +#define CDNS_IOMEM_RESOURCES_NUM 3 +#define CDNS_IRQ_RESOURCES_NUM 4 +#define CDNS_RESOURCES_NUM (CDNS_IOMEM_RESOURCES_NUM + CDNS_IRQ_RESOURCES_= NUM) =20 struct cdns3_platform_data { int (*platform_suspend)(struct device *dev, --=20 2.17.1 From nobody Wed Dec 17 11:45:48 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A642C77B72 for ; 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Thu, 20 Apr 2023 19:00:59 +0800 From: Minda Chen To: Emil Renner Berthing , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Pawel Laszczak , Greg Kroah-Hartman , Peter Chen , Roger Quadros , Philipp Zabel CC: , , , , , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Minda Chen" , Mason Huo Subject: [PATCH v5 7/7] riscv: dts: starfive: Add USB dts configuration for JH7110 Date: Thu, 20 Apr 2023 19:00:52 +0800 Message-ID: <20230420110052.3182-8-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230420110052.3182-1-minda.chen@starfivetech.com> References: <20230420110052.3182-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.144.253] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add USB wrapper layer and Cadence USB3 controller dts configuration for StarFive JH7110 SoC and VisionFive2 Board. USB controller connect to PHY, The PHY dts configuration are also added. Signed-off-by: Minda Chen --- .../jh7110-starfive-visionfive-2.dtsi | 7 +++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 44 +++++++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi= b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index 1155b97b593d..fa97ebfd93ad 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -221,3 +221,10 @@ pinctrl-0 =3D <&uart0_pins>; status =3D "okay"; }; + +&usb0 { + phys =3D <&usbphy0>; + phy-names =3D "usb2"; + dr_mode =3D "peripheral"; + status =3D "okay"; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts= /starfive/jh7110.dtsi index 29cd798b6732..eee395e19cdb 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -366,6 +366,50 @@ status =3D "disabled"; }; =20 + usb0: usb@10100000 { + compatible =3D "starfive,jh7110-usb"; + reg =3D <0x0 0x10100000 0x0 0x10000>, + <0x0 0x10110000 0x0 0x10000>, + <0x0 0x10120000 0x0 0x10000>; + reg-names =3D "otg", "xhci", "dev"; + interrupts =3D <100>, <108>, <110>; + interrupt-names =3D "host", "peripheral", "otg"; + clocks =3D <&stgcrg JH7110_STGCLK_USB0_LPM>, + <&stgcrg JH7110_STGCLK_USB0_STB>, + <&stgcrg JH7110_STGCLK_USB0_APB>, + <&stgcrg JH7110_STGCLK_USB0_AXI>, + <&stgcrg JH7110_STGCLK_USB0_UTMI_APB>; + clock-names =3D "lpm", "stb", "apb", "axi", "utmi_apb"; + resets =3D <&stgcrg JH7110_STGRST_USB0_PWRUP>, + <&stgcrg JH7110_STGRST_USB0_APB>, + <&stgcrg JH7110_STGRST_USB0_AXI>, + <&stgcrg JH7110_STGRST_USB0_UTMI_APB>; + reset-names =3D "pwrup", "apb", "axi", "utmi_apb"; + starfive,stg-syscon =3D <&stg_syscon 0x4>; + status =3D "disabled"; + }; + + usbphy0: phy@10200000 { + compatible =3D "starfive,jh7110-usb-phy"; + reg =3D <0x0 0x10200000 0x0 0x10000>; + clocks =3D <&syscrg JH7110_SYSCLK_USB_125M>, + <&stgcrg JH7110_STGCLK_USB0_APP_125>; + clock-names =3D "125m", "app_125m"; + #phy-cells =3D <0>; + }; + + pciephy0: phy@10210000 { + compatible =3D "starfive,jh7110-pcie-phy"; + reg =3D <0x0 0x10210000 0x0 0x10000>; + #phy-cells =3D <0>; + }; + + pciephy1: phy@10220000 { + compatible =3D "starfive,jh7110-pcie-phy"; + reg =3D <0x0 0x10220000 0x0 0x10000>; + #phy-cells =3D <0>; + }; + stgcrg: clock-controller@10230000 { compatible =3D "starfive,jh7110-stgcrg"; reg =3D <0x0 0x10230000 0x0 0x10000>; --=20 2.17.1