From nobody Wed Dec 17 13:44:39 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E2A3C6FD18 for ; Thu, 20 Apr 2023 02:42:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233694AbjDTCma (ORCPT ); Wed, 19 Apr 2023 22:42:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41738 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233685AbjDTCl7 (ORCPT ); Wed, 19 Apr 2023 22:41:59 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 565955B81; Wed, 19 Apr 2023 19:41:29 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id B3C4A24E250; Thu, 20 Apr 2023 10:41:21 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 20 Apr 2023 10:41:21 +0800 Received: from SD-Server.starfivetech.com (113.72.144.253) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 20 Apr 2023 10:41:20 +0800 From: Walker Chen To: Jaroslav Kysela , Takashi Iwai , "Rob Herring" , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Liam Girdwood , Mark Brown , Walker Chen CC: , , , Subject: [PATCH v2 3/4] ASoC: starfive: Add JH7110 TDM driver Date: Thu, 20 Apr 2023 10:41:17 +0800 Message-ID: <20230420024118.22677-4-walker.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230420024118.22677-1-walker.chen@starfivetech.com> References: <20230420024118.22677-1-walker.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.144.253] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add tdm driver support for the StarFive JH7110 SoC. Signed-off-by: Walker Chen --- MAINTAINERS | 6 + sound/soc/Kconfig | 1 + sound/soc/Makefile | 1 + sound/soc/starfive/Kconfig | 15 + sound/soc/starfive/Makefile | 2 + sound/soc/starfive/jh7110_tdm.c | 579 ++++++++++++++++++++++++++++++++ sound/soc/starfive/jh7110_tdm.h | 155 +++++++++ 7 files changed, 759 insertions(+) create mode 100644 sound/soc/starfive/Kconfig create mode 100644 sound/soc/starfive/Makefile create mode 100644 sound/soc/starfive/jh7110_tdm.c create mode 100644 sound/soc/starfive/jh7110_tdm.h diff --git a/MAINTAINERS b/MAINTAINERS index 5f9c544bc189..add89615d327 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19945,6 +19945,12 @@ F: Documentation/devicetree/bindings/power/starfiv= e* F: drivers/soc/starfive/jh71xx_pmu.c F: include/dt-bindings/power/starfive,jh7110-pmu.h =20 +STARFIVE JH7110 TDM DRIVERS +M: Walker Chen +S: Maintained +F: Documentation/devicetree/bindings/sound/starfive,jh7110-tdm.yaml +F: sound/soc/starfive/jh7110-tdm.* + STARFIVE SOC DRIVERS M: Conor Dooley S: Maintained diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig index 848fbae26c3b..8d1d9401ecf2 100644 --- a/sound/soc/Kconfig +++ b/sound/soc/Kconfig @@ -91,6 +91,7 @@ source "sound/soc/sh/Kconfig" source "sound/soc/sof/Kconfig" source "sound/soc/spear/Kconfig" source "sound/soc/sprd/Kconfig" +source "sound/soc/starfive/Kconfig" source "sound/soc/sti/Kconfig" source "sound/soc/stm/Kconfig" source "sound/soc/sunxi/Kconfig" diff --git a/sound/soc/Makefile b/sound/soc/Makefile index 507eaed1d6a1..65aeb4ef4068 100644 --- a/sound/soc/Makefile +++ b/sound/soc/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_SND_SOC) +=3D sh/ obj-$(CONFIG_SND_SOC) +=3D sof/ obj-$(CONFIG_SND_SOC) +=3D spear/ obj-$(CONFIG_SND_SOC) +=3D sprd/ +obj-$(CONFIG_SND_SOC) +=3D starfive/ obj-$(CONFIG_SND_SOC) +=3D sti/ obj-$(CONFIG_SND_SOC) +=3D stm/ obj-$(CONFIG_SND_SOC) +=3D sunxi/ diff --git a/sound/soc/starfive/Kconfig b/sound/soc/starfive/Kconfig new file mode 100644 index 000000000000..737c956f7b93 --- /dev/null +++ b/sound/soc/starfive/Kconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only +config SND_SOC_STARFIVE + tristate "Audio support for StarFive SoC" + depends on COMPILE_TEST || SOC_STARFIVE + help + Say Y or M if you want to add support for codecs attached to + the Starfive SoCs' Audio interfaces. You will also need to + select the audio interfaces to support below. + +config SND_SOC_JH7110_TDM + tristate "JH7110 TDM device driver" + depends on HAVE_CLK && SND_SOC_STARFIVE + select SND_SOC_GENERIC_DMAENGINE_PCM + help + Say Y or M if you want to add support for StarFive TDM driver. diff --git a/sound/soc/starfive/Makefile b/sound/soc/starfive/Makefile new file mode 100644 index 000000000000..f7d960211d72 --- /dev/null +++ b/sound/soc/starfive/Makefile @@ -0,0 +1,2 @@ +# StarFive Platform Support +obj-$(CONFIG_SND_SOC_JH7110_TDM) +=3D jh7110_tdm.o diff --git a/sound/soc/starfive/jh7110_tdm.c b/sound/soc/starfive/jh7110_td= m.c new file mode 100644 index 000000000000..ec374db2e133 --- /dev/null +++ b/sound/soc/starfive/jh7110_tdm.c @@ -0,0 +1,579 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * TDM driver for the StarFive JH7110 SoC + * + * Copyright (C) 2023 StarFive Technology Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "jh7110_tdm.h" + +static inline u32 jh7110_tdm_readl(struct jh7110_tdm_dev *tdm, u16 reg) +{ + return readl_relaxed(tdm->tdm_base + reg); +} + +static inline void jh7110_tdm_writel(struct jh7110_tdm_dev *tdm, u16 reg, = u32 val) +{ + writel_relaxed(val, tdm->tdm_base + reg); +} + +static void jh7110_tdm_save_context(struct jh7110_tdm_dev *tdm, + struct snd_pcm_substream *substream) +{ + tdm->saved_pcmgbcr =3D jh7110_tdm_readl(tdm, TDM_PCMGBCR); + tdm->saved_pcmdiv =3D jh7110_tdm_readl(tdm, TDM_PCMDIV); + + if (substream->stream =3D=3D SNDRV_PCM_STREAM_PLAYBACK) + tdm->saved_pcmtxcr =3D jh7110_tdm_readl(tdm, TDM_PCMTXCR); + else + tdm->saved_pcmrxcr =3D jh7110_tdm_readl(tdm, TDM_PCMRXCR); +} + +static void jh7110_tdm_start(struct jh7110_tdm_dev *tdm, struct snd_pcm_su= bstream *substream) +{ + u32 data; + unsigned int val; + + data =3D jh7110_tdm_readl(tdm, TDM_PCMGBCR); + jh7110_tdm_writel(tdm, TDM_PCMGBCR, data | PCMGBCR_ENABLE); + + if (substream->stream =3D=3D SNDRV_PCM_STREAM_PLAYBACK) { + val =3D jh7110_tdm_readl(tdm, TDM_PCMTXCR); + jh7110_tdm_writel(tdm, TDM_PCMTXCR, val | PCMTXCR_TXEN); + } else { + val =3D jh7110_tdm_readl(tdm, TDM_PCMRXCR); + jh7110_tdm_writel(tdm, TDM_PCMRXCR, val | PCMRXCR_RXEN); + } +} + +static void jh7110_tdm_stop(struct jh7110_tdm_dev *tdm, struct snd_pcm_sub= stream *substream) +{ + unsigned int val; + + if (substream->stream =3D=3D SNDRV_PCM_STREAM_PLAYBACK) { + val =3D jh7110_tdm_readl(tdm, TDM_PCMTXCR); + val &=3D ~PCMTXCR_TXEN; + jh7110_tdm_writel(tdm, TDM_PCMTXCR, val); + } else { + val =3D jh7110_tdm_readl(tdm, TDM_PCMRXCR); + val &=3D ~PCMRXCR_RXEN; + jh7110_tdm_writel(tdm, TDM_PCMRXCR, val); + } +} + +static int jh7110_tdm_syncdiv(struct jh7110_tdm_dev *tdm) +{ + u32 sl, sscale, syncdiv; + + sl =3D (tdm->rx.sl >=3D tdm->tx.sl) ? tdm->rx.sl : tdm->tx.sl; + sscale =3D (tdm->rx.sscale >=3D tdm->tx.sscale) ? tdm->rx.sscale : tdm->t= x.sscale; + syncdiv =3D tdm->pcmclk / tdm->samplerate - 1; + + if ((syncdiv + 1) < (sl * sscale)) { + dev_err(tdm->dev, "Failed to set syncdiv!\n"); + return -EINVAL; + } + + if (tdm->syncm =3D=3D TDM_SYNCM_LONG && + (tdm->rx.sscale <=3D 1 || tdm->tx.sscale <=3D 1)) { + if ((syncdiv + 1) <=3D sl) { + dev_err(tdm->dev, "Wrong syncdiv! It must be (syncdiv+1) > max[tx.sl, r= x.sl]\n"); + return -EINVAL; + } + } + + jh7110_tdm_writel(tdm, TDM_PCMDIV, syncdiv); + return 0; +} + +static void jh7110_tdm_control(struct jh7110_tdm_dev *tdm) +{ + u32 data; + + data =3D (tdm->clkpolity << CLKPOL_BIT) | + (tdm->elm << ELM_BIT) | + (tdm->syncm << SYNCM_BIT) | + (tdm->ms_mode << MS_BIT); + jh7110_tdm_writel(tdm, TDM_PCMGBCR, data); +} + +static void jh7110_tdm_config(struct jh7110_tdm_dev *tdm, + struct snd_pcm_substream *substream) +{ + u32 datarx, datatx; + + jh7110_tdm_control(tdm); + jh7110_tdm_syncdiv(tdm); + + datarx =3D (tdm->rx.ifl << IFL_BIT) | + (tdm->rx.wl << WL_BIT) | + (tdm->rx.sscale << SSCALE_BIT) | + (tdm->rx.sl << SL_BIT) | + (tdm->rx.lrj << LRJ_BIT); + + datatx =3D (tdm->tx.ifl << IFL_BIT) | + (tdm->tx.wl << WL_BIT) | + (tdm->tx.sscale << SSCALE_BIT) | + (tdm->tx.sl << SL_BIT) | + (tdm->tx.lrj << LRJ_BIT); + + if (substream->stream =3D=3D SNDRV_PCM_STREAM_PLAYBACK) + jh7110_tdm_writel(tdm, TDM_PCMTXCR, datatx); + else + jh7110_tdm_writel(tdm, TDM_PCMRXCR, datarx); +} + +static void jh7110_tdm_clk_disable(struct jh7110_tdm_dev *tdm) +{ + clk_disable_unprepare(tdm->clk_tdm); + clk_disable_unprepare(tdm->clk_tdm_ext); + clk_disable_unprepare(tdm->clk_tdm_internal); + clk_disable_unprepare(tdm->clk_tdm_apb); + clk_disable_unprepare(tdm->clk_tdm_ahb); + clk_disable_unprepare(tdm->clk_mclk_inner); +} + +static int jh7110_tdm_clk_enable(struct jh7110_tdm_dev *tdm) +{ + int ret; + + ret =3D clk_prepare_enable(tdm->clk_mclk_inner); + if (ret) { + dev_err(tdm->dev, "failed to prepare enable clk_mclk_inner\n"); + return ret; + } + + ret =3D clk_prepare_enable(tdm->clk_tdm_ahb); + if (ret) { + dev_err(tdm->dev, "Failed to prepare enable clk_tdm_ahb\n"); + goto dis_mclk_inner_clk; + } + + ret =3D clk_prepare_enable(tdm->clk_tdm_apb); + if (ret) { + dev_err(tdm->dev, "Failed to prepare enable clk_tdm_apb\n"); + goto dis_tdm_ahb_clk; + } + + ret =3D clk_prepare_enable(tdm->clk_tdm_internal); + if (ret) { + dev_err(tdm->dev, "Failed to prepare enable clk_tdm_intl\n"); + goto dis_tdm_apb_clk; + } + + ret =3D clk_prepare_enable(tdm->clk_tdm_ext); + if (ret) { + dev_err(tdm->dev, "Failed to prepare enable clk_tdm_ext\n"); + goto dis_tdm_internal_clk; + } + + ret =3D clk_prepare_enable(tdm->clk_tdm); + if (ret) { + dev_err(tdm->dev, "Failed to prepare enable clk_tdm\n"); + goto dis_tdm_ext_clk; + } + + ret =3D reset_control_deassert(tdm->resets); + if (ret) { + dev_err(tdm->dev, "%s: failed to deassert tdm resets\n", __func__); + goto dis_tdm_clk; + } + + ret =3D clk_set_parent(tdm->clk_tdm, tdm->clk_tdm_ext); + if (ret) { + dev_err(tdm->dev, "Can't set clock source for clk_tdm: %d\n", ret); + goto dis_tdm_clk; + } + return 0; + +dis_tdm_clk: + clk_disable_unprepare(tdm->clk_tdm); +dis_tdm_ext_clk: + clk_disable_unprepare(tdm->clk_tdm_ext); +dis_tdm_internal_clk: + clk_disable_unprepare(tdm->clk_tdm_internal); +dis_tdm_apb_clk: + clk_disable_unprepare(tdm->clk_tdm_apb); +dis_tdm_ahb_clk: + clk_disable_unprepare(tdm->clk_tdm_ahb); +dis_mclk_inner_clk: + clk_disable_unprepare(tdm->clk_mclk_inner); + + return ret; +} + +#ifdef CONFIG_PM +static int jh7110_tdm_runtime_suspend(struct device *dev) +{ + struct jh7110_tdm_dev *tdm =3D dev_get_drvdata(dev); + + jh7110_tdm_clk_disable(tdm); + + return 0; +} + +static int jh7110_tdm_runtime_resume(struct device *dev) +{ + struct jh7110_tdm_dev *tdm =3D dev_get_drvdata(dev); + + return jh7110_tdm_clk_enable(tdm); +} +#endif + +#ifdef CONFIG_PM_SLEEP +static int jh7110_tdm_suspend(struct snd_soc_component *component) +{ + return pm_runtime_force_suspend(component->dev); +} + +static int jh7110_tdm_resume(struct snd_soc_component *component) +{ + struct jh7110_tdm_dev *tdm =3D snd_soc_component_get_drvdata(component); + + /* restore context */ + jh7110_tdm_writel(tdm, TDM_PCMGBCR, tdm->saved_pcmgbcr); + jh7110_tdm_writel(tdm, TDM_PCMDIV, tdm->saved_pcmdiv); + + return pm_runtime_force_resume(component->dev); +} + +#else +#define jh7110_tdm_suspend NULL +#define jh7110_tdm_resume NULL +#endif + +static const struct snd_soc_component_driver jh7110_tdm_component =3D { + .name =3D "jh7110-tdm", + .suspend =3D jh7110_tdm_suspend, + .resume =3D jh7110_tdm_resume, +}; + +static int jh7110_tdm_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct jh7110_tdm_dev *tdm =3D snd_soc_dai_get_drvdata(dai); + int chan_wl, chan_sl, chan_nr; + unsigned int data_width; + unsigned int dma_bus_width; + struct snd_dmaengine_dai_dma_data *dma_data =3D NULL; + struct snd_soc_pcm_runtime *rtd =3D asoc_substream_to_rtd(substream); + struct snd_soc_dai_link *dai_link =3D rtd->dai_link; + + dai_link->stop_dma_first =3D 1; + + data_width =3D params_width(params); + + tdm->samplerate =3D params_rate(params); + tdm->pcmclk =3D params_channels(params) * tdm->samplerate * data_width; + + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + chan_wl =3D TDM_16BIT_WORD_LEN; + chan_sl =3D TDM_16BIT_SLOT_LEN; + dma_bus_width =3D DMA_SLAVE_BUSWIDTH_2_BYTES; + break; + + case SNDRV_PCM_FORMAT_S32_LE: + chan_wl =3D TDM_32BIT_WORD_LEN; + chan_sl =3D TDM_32BIT_SLOT_LEN; + dma_bus_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; + break; + + default: + dev_err(tdm->dev, "tdm: unsupported PCM fmt"); + return -EINVAL; + } + + chan_nr =3D params_channels(params); + switch (chan_nr) { + case ONE_CHANNEL_SUPPORT: + case TWO_CHANNEL_SUPPORT: + case FOUR_CHANNEL_SUPPORT: + case SIX_CHANNEL_SUPPORT: + case EIGHT_CHANNEL_SUPPORT: + break; + default: + dev_err(tdm->dev, "channel not supported\n"); + return -EINVAL; + } + + if (substream->stream =3D=3D SNDRV_PCM_STREAM_PLAYBACK) { + tdm->tx.wl =3D chan_wl; + tdm->tx.sl =3D chan_sl; + tdm->tx.sscale =3D chan_nr; + tdm->play_dma_data.addr_width =3D dma_bus_width; + dma_data =3D &tdm->play_dma_data; + } else { + tdm->rx.wl =3D chan_wl; + tdm->rx.sl =3D chan_sl; + tdm->rx.sscale =3D chan_nr; + tdm->capture_dma_data.addr_width =3D dma_bus_width; + dma_data =3D &tdm->capture_dma_data; + } + + snd_soc_dai_set_dma_data(dai, substream, dma_data); + + jh7110_tdm_config(tdm, substream); + jh7110_tdm_save_context(tdm, substream); + + return 0; +} + +static int jh7110_tdm_trigger(struct snd_pcm_substream *substream, + int cmd, struct snd_soc_dai *dai) +{ + struct jh7110_tdm_dev *tdm =3D snd_soc_dai_get_drvdata(dai); + int ret =3D 0; + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + /* restore context */ + if (substream->stream =3D=3D SNDRV_PCM_STREAM_PLAYBACK) + jh7110_tdm_writel(tdm, TDM_PCMTXCR, tdm->saved_pcmtxcr); + else + jh7110_tdm_writel(tdm, TDM_PCMRXCR, tdm->saved_pcmrxcr); + + jh7110_tdm_start(tdm, substream); + break; + + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_SUSPEND: + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + jh7110_tdm_stop(tdm, substream); + break; + default: + ret =3D -EINVAL; + break; + } + return ret; +} + +static const struct snd_soc_dai_ops jh7110_tdm_dai_ops =3D { + .hw_params =3D jh7110_tdm_hw_params, + .trigger =3D jh7110_tdm_trigger, +}; + +static int jh7110_tdm_dai_probe(struct snd_soc_dai *dai) +{ + struct jh7110_tdm_dev *tdm =3D snd_soc_dai_get_drvdata(dai); + + snd_soc_dai_init_dma_data(dai, &tdm->play_dma_data, &tdm->capture_dma_dat= a); + snd_soc_dai_set_drvdata(dai, tdm); + return 0; +} + +#define JH7110_TDM_RATES SNDRV_PCM_RATE_8000_48000 + +#define JH7110_TDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S32_LE) + +static struct snd_soc_dai_driver jh7110_tdm_dai =3D { + .name =3D "sf_tdm", + .id =3D 0, + .playback =3D { + .stream_name =3D "Playback", + .channels_min =3D 1, + .channels_max =3D 8, + .rates =3D JH7110_TDM_RATES, + .formats =3D JH7110_TDM_FORMATS, + }, + .capture =3D { + .stream_name =3D "Capture", + .channels_min =3D 1, + .channels_max =3D 8, + .rates =3D JH7110_TDM_RATES, + .formats =3D JH7110_TDM_FORMATS, + }, + .ops =3D &jh7110_tdm_dai_ops, + .probe =3D jh7110_tdm_dai_probe, + .symmetric_rate =3D 1, +}; + +static const struct snd_pcm_hardware jh7110_pcm_hardware =3D { + .info =3D (SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_MMAP_VALID | + SNDRV_PCM_INFO_PAUSE | + SNDRV_PCM_INFO_RESUME | + SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_BLOCK_TRANSFER), + .buffer_bytes_max =3D 192512, + .period_bytes_min =3D 4096, + .period_bytes_max =3D 32768, + .periods_min =3D 1, + .periods_max =3D 48, + .fifo_size =3D 16, +}; + +static const struct snd_dmaengine_pcm_config jh7110_dmaengine_pcm_config = =3D { + .pcm_hardware =3D &jh7110_pcm_hardware, + .prepare_slave_config =3D snd_dmaengine_pcm_prepare_slave_config, + .prealloc_buffer_size =3D 192512, +}; + +static void jh7110_tdm_init_params(struct jh7110_tdm_dev *tdm) +{ + tdm->clkpolity =3D TDM_TX_RASING_RX_FALLING; + if (tdm->frame_mode =3D=3D SHORT_LATER) { + tdm->elm =3D TDM_ELM_LATE; + tdm->syncm =3D TDM_SYNCM_SHORT; + } else if (tdm->frame_mode =3D=3D SHORT_EARLY) { + tdm->elm =3D TDM_ELM_EARLY; + tdm->syncm =3D TDM_SYNCM_SHORT; + } else { + tdm->elm =3D TDM_ELM_EARLY; + tdm->syncm =3D TDM_SYNCM_LONG; + } + + tdm->ms_mode =3D TDM_AS_SLAVE; + tdm->rx.ifl =3D TDM_FIFO_HALF; + tdm->tx.ifl =3D TDM_FIFO_HALF; + tdm->rx.wl =3D TDM_16BIT_WORD_LEN; + tdm->tx.wl =3D TDM_16BIT_WORD_LEN; + tdm->rx.sscale =3D 2; + tdm->tx.sscale =3D 2; + tdm->rx.lrj =3D TDM_LEFT_JUSTIFT; + tdm->tx.lrj =3D TDM_LEFT_JUSTIFT; + + tdm->play_dma_data.addr =3D TDM_FIFO; + tdm->play_dma_data.addr_width =3D DMA_SLAVE_BUSWIDTH_2_BYTES; + tdm->play_dma_data.fifo_size =3D TDM_FIFO_DEPTH / 2; + tdm->play_dma_data.maxburst =3D 16; + + tdm->capture_dma_data.addr =3D TDM_FIFO; + tdm->capture_dma_data.addr_width =3D DMA_SLAVE_BUSWIDTH_2_BYTES; + tdm->capture_dma_data.fifo_size =3D TDM_FIFO_DEPTH / 2; + tdm->capture_dma_data.maxburst =3D 8; +} + +static int jh7110_tdm_clk_reset_init(struct platform_device *pdev, + struct jh7110_tdm_dev *tdm) +{ + int ret; + + static struct clk_bulk_data clks[] =3D { + { .id =3D "tdm_ahb" }, + { .id =3D "tdm_apb" }, + { .id =3D "tdm_internal" }, + { .id =3D "tdm" }, + { .id =3D "mclk_inner" }, + { .id =3D "tdm_ext" }, + }; + + ret =3D devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(clks), clks); + if (ret) { + dev_err(&pdev->dev, "Failed to get tdm clocks\n"); + return ret; + } + + tdm->clk_tdm_ahb =3D clks[0].clk; + tdm->clk_tdm_apb =3D clks[1].clk; + tdm->clk_tdm_internal =3D clks[2].clk; + tdm->clk_tdm =3D clks[3].clk; + tdm->clk_mclk_inner =3D clks[4].clk; + tdm->clk_tdm_ext =3D clks[5].clk; + + tdm->resets =3D devm_reset_control_array_get_exclusive(&pdev->dev); + if (IS_ERR(tdm->resets)) { + ret =3D PTR_ERR(tdm->resets); + dev_err(&pdev->dev, "Failed to get tdm resets"); + return ret; + } + + return jh7110_tdm_clk_enable(tdm); +} + +static int jh7110_tdm_probe(struct platform_device *pdev) +{ + struct jh7110_tdm_dev *tdm; + int ret; + + tdm =3D devm_kzalloc(&pdev->dev, sizeof(*tdm), GFP_KERNEL); + if (!tdm) + return -ENOMEM; + + tdm->tdm_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(tdm->tdm_base)) + return PTR_ERR(tdm->tdm_base); + + tdm->dev =3D &pdev->dev; + + ret =3D jh7110_tdm_clk_reset_init(pdev, tdm); + if (ret) { + dev_err(&pdev->dev, "Failed to enable audio-tdm clock\n"); + return ret; + } + + tdm->frame_mode =3D SHORT_LATER; + jh7110_tdm_init_params(tdm); + + dev_set_drvdata(&pdev->dev, tdm); + ret =3D devm_snd_soc_register_component(&pdev->dev, &jh7110_tdm_component, + &jh7110_tdm_dai, 1); + if (ret !=3D 0) { + dev_err(&pdev->dev, "Failed to register dai\n"); + return ret; + } + + ret =3D devm_snd_dmaengine_pcm_register(&pdev->dev, + &jh7110_dmaengine_pcm_config, + SND_DMAENGINE_PCM_FLAG_COMPAT); + if (ret) { + dev_err(&pdev->dev, "Could not register pcm: %d\n", ret); + return ret; + } + + pm_runtime_enable(&pdev->dev); +#ifdef CONFIG_PM + jh7110_tdm_clk_disable(tdm); +#endif + + return 0; +} + +static int jh7110_tdm_dev_remove(struct platform_device *pdev) +{ + pm_runtime_disable(&pdev->dev); + return 0; +} + +static const struct of_device_id jh7110_tdm_of_match[] =3D { + {.compatible =3D "starfive,jh7110-tdm",}, + {} +}; + +MODULE_DEVICE_TABLE(of, jh7110_tdm_of_match); + +static const struct dev_pm_ops jh7110_tdm_pm_ops =3D { + SET_RUNTIME_PM_OPS(jh7110_tdm_runtime_suspend, + jh7110_tdm_runtime_resume, NULL) +}; + +static struct platform_driver jh7110_tdm_driver =3D { + .driver =3D { + .name =3D "jh7110-tdm", + .of_match_table =3D jh7110_tdm_of_match, + .pm =3D &jh7110_tdm_pm_ops, + }, + .probe =3D jh7110_tdm_probe, + .remove =3D jh7110_tdm_dev_remove, +}; +module_platform_driver(jh7110_tdm_driver); + +MODULE_AUTHOR("Walker Chen "); +MODULE_DESCRIPTION("StarFive JH7110 TDM ASoC Driver"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/starfive/jh7110_tdm.h b/sound/soc/starfive/jh7110_td= m.h new file mode 100644 index 000000000000..aa4ab3624319 --- /dev/null +++ b/sound/soc/starfive/jh7110_tdm.h @@ -0,0 +1,155 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * TDM driver for the StarFive JH7110 SoC + * + * Copyright (C) 2023 StarFive Technology Co., Ltd. + */ +#ifndef __SND_SOC_STARFIVE_TDM_H +#define __SND_SOC_STARFIVE_TDM_H + +#include +#include +#include +#include +#include +#include +#include + +#define TDM_PCMGBCR 0x00 + #define PCMGBCR_MASK 0x1e + #define PCMGBCR_ENABLE BIT(0) + #define PCMGBCR_TRITXEN BIT(4) + #define CLKPOL_BIT 5 + #define TRITXEN_BIT 4 + #define ELM_BIT 3 + #define SYNCM_BIT 2 + #define MS_BIT 1 +#define TDM_PCMTXCR 0x04 + #define PCMTXCR_TXEN BIT(0) + #define IFL_BIT 11 + #define WL_BIT 8 + #define SSCALE_BIT 4 + #define SL_BIT 2 + #define LRJ_BIT 1 +#define TDM_PCMRXCR 0x08 + #define PCMRXCR_RXEN BIT(0) + #define PCMRXCR_RXSL_MASK 0xc + #define PCMRXCR_RXSL_16BIT 0x4 + #define PCMRXCR_RXSL_32BIT 0x8 + #define PCMRXCR_SCALE_MASK 0xf0 + #define PCMRXCR_SCALE_1CH 0x10 +#define TDM_PCMDIV 0x0c + +/* DMA registers */ +#define TDM_FIFO 0x170c0000 +#define TDM_FIFO_DEPTH 32 + +#define ONE_CHANNEL_SUPPORT 1 +#define TWO_CHANNEL_SUPPORT 2 +#define FOUR_CHANNEL_SUPPORT 4 +#define SIX_CHANNEL_SUPPORT 6 +#define EIGHT_CHANNEL_SUPPORT 8 + +enum TDM_MASTER_SLAVE_MODE { + TDM_AS_MASTER =3D 0, + TDM_AS_SLAVE, +}; + +enum TDM_CLKPOL { + /* tx raising and rx falling */ + TDM_TX_RASING_RX_FALLING =3D 0, + /* tx falling and rx raising */ + TDM_TX_FALLING_RX_RASING, +}; + +enum TDM_FRAME_MODE { + SHORT_EARLY =3D 0, + SHORT_LATER, + LONG, +}; + +enum TDM_ELM { + /* only work while SYNCM=3D0 */ + TDM_ELM_LATE =3D 0, + TDM_ELM_EARLY, +}; + +enum TDM_SYNCM { + /* short frame sync */ + TDM_SYNCM_SHORT =3D 0, + /* long frame sync */ + TDM_SYNCM_LONG, +}; + +enum TDM_IFL { + /* FIFO to send or received : half-1/2, Quarter-1/4 */ + TDM_FIFO_HALF =3D 0, + TDM_FIFO_QUARTER, +}; + +enum TDM_WL { + /* send or received word length */ + TDM_8BIT_WORD_LEN =3D 0, + TDM_16BIT_WORD_LEN, + TDM_20BIT_WORD_LEN, + TDM_24BIT_WORD_LEN, + TDM_32BIT_WORD_LEN, +}; + +enum TDM_SL { + /* send or received slot length */ + TDM_8BIT_SLOT_LEN =3D 0, + TDM_16BIT_SLOT_LEN, + TDM_32BIT_SLOT_LEN, +}; + +enum TDM_LRJ { + /* left-justify or right-justify */ + TDM_RIGHT_JUSTIFY =3D 0, + TDM_LEFT_JUSTIFT, +}; + +struct tdm_chan_cfg { + enum TDM_IFL ifl; + enum TDM_WL wl; + unsigned char sscale; + enum TDM_SL sl; + enum TDM_LRJ lrj; + unsigned char enable; +}; + +struct jh7110_tdm_dev { + void __iomem *tdm_base; + struct device *dev; + struct clk *clk_tdm_ahb; + struct clk *clk_tdm_apb; + struct clk *clk_tdm_internal; + struct clk *clk_tdm; + struct clk *clk_mclk_inner; + struct clk *clk_tdm_ext; + struct reset_control *resets; + + enum TDM_CLKPOL clkpolity; + enum TDM_ELM elm; + enum TDM_SYNCM syncm; + enum TDM_MASTER_SLAVE_MODE ms_mode; + enum TDM_FRAME_MODE frame_mode; + + struct tdm_chan_cfg tx; + struct tdm_chan_cfg rx; + + u16 syncdiv; + u32 samplerate; + u32 pcmclk; + + /* data related to DMA transfers b/w tdm and DMAC */ + struct snd_dmaengine_dai_dma_data play_dma_data; + struct snd_dmaengine_dai_dma_data capture_dma_data; + u32 saved_pcmgbcr; + u32 saved_pcmtxcr; + u32 saved_pcmrxcr; + u32 saved_pcmdiv; + +}; + +#endif /* __SND_SOC_STARFIVE_TDM_H */ --=20 2.17.1