From nobody Thu Dec 18 15:29:06 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47978C77B73 for ; Wed, 19 Apr 2023 22:22:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232692AbjDSWWO (ORCPT ); Wed, 19 Apr 2023 18:22:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42208 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232456AbjDSWVc (ORCPT ); Wed, 19 Apr 2023 18:21:32 -0400 Received: from mail-pg1-x533.google.com (mail-pg1-x533.google.com [IPv6:2607:f8b0:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0DF2FA256 for ; Wed, 19 Apr 2023 15:20:06 -0700 (PDT) Received: by mail-pg1-x533.google.com with SMTP id 41be03b00d2f7-51b6d0b9430so211644a12.2 for ; Wed, 19 Apr 2023 15:20:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1681942729; x=1684534729; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XK5xUw/rzaPgA4jO4a/YwH8Byrp1ajuQRNW8VnU2lnI=; b=QfXuULt6GKdZ0yIYOBu58cROq1xtd+AwU5tA9tWSYcP8puXwvEN9RX3lXVuV60tyoW 4Q0CSfUoxv6NDjypNOuOT4ywNhU7IYB+qeWNkXwN91wiD9TQD3HOmit1hlHNqFbWVtNJ ziwh+QBq1N6MeIyCvSv5s6RR13cXyHzSqXBQKCnCZR2rrQanp3QhB3VbRYZ2jQSTPE6d Vpg87adIN6SFou4dfOJ3ZLRcLAQq2ZlEUcDyGi0vckdKvSSc1nPlKdGfKGwb9h5rUo3e rLKhVd1kgYj7FOEo7g+ojtFs7lAxzBaXut+YFsbxt/trii3p8w9AEE1pM3je3JF/e5ut 1yXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681942729; x=1684534729; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XK5xUw/rzaPgA4jO4a/YwH8Byrp1ajuQRNW8VnU2lnI=; b=JfQ5VwfbMv3XNb7Ij7YNl3IWOaj3uUeoMBuPb4rqkoKliGLVORo3BXzYm70aoG6oU2 OVDiqWeIDdldYzjoXT/+O4qP5CbFr79Li5zfWsSIjZO9hqs+1MK4sCCYwHrrUMpdWQGx UOJ4/oFLTQpDYK5/LF4BZcWdKto/RjqoEmpPA+E91DGtGsJn7VwWDiQZ63Zh/qsc2ttf pvghvzlOBEHzoP6A+IxmF/U7CC7d8IRp0rvRBfp+6vKFjWriSJ0X+iU9aCp/Ru44W9Q8 HoFrdJJbHRRU5ZmK3X8LxvrhFt3J9vLqd6E/VVjcTQIcKVKkdKGoPJ1n/Y3HqMV2ayR7 w3ng== X-Gm-Message-State: AAQBX9d2q+5++TRwwLDuoGG2nCekLuyiS4UTd42dzEslM0r43jwzWJaN TIpe5+RKAgG/XE6ugFpqaanHh09eupQpgCMRht4= X-Google-Smtp-Source: AKy350baQTNt4Vs4HHjBbXvyObvJ3IXFGZptf7h2H+OASSZVy5+7QV7+crZBWOtRSKw2ldJwBUdMWw== X-Received: by 2002:a17:903:784:b0:1a2:9183:a499 with SMTP id kn4-20020a170903078400b001a29183a499mr5853196plb.34.1681942729515; Wed, 19 Apr 2023 15:18:49 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id jn11-20020a170903050b00b00196807b5189sm11619190plb.292.2023.04.19.15.18.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 15:18:49 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Rajnesh Kanwal , Atish Patra , Alexandre Ghiti , Andrew Jones , Andrew Morton , Anup Patel , Atish Patra , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Suzuki K Poulose , Will Deacon , Marc Zyngier , Sean Christopherson , linux-coco@lists.linux.dev, Dylan Reid , abrestic@rivosinc.com, Samuel Ortiz , Christoph Hellwig , Conor Dooley , Greg Kroah-Hartman , Guo Ren , Heiko Stuebner , Jiri Slaby , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, Mayuresh Chitale , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Uladzislau Rezki Subject: [RFC 36/48] RISC-V: KVM: Read/write gprs from/to shmem in case of TVM VCPU. Date: Wed, 19 Apr 2023 15:17:04 -0700 Message-Id: <20230419221716.3603068-37-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230419221716.3603068-1-atishp@rivosinc.com> References: <20230419221716.3603068-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Rajnesh Kanwal For TVM vcpus, TSM uses shared memory to exposes gprs for the trusted VCPU. This change makes sure we use shmem when doing mmio emulation for trusted VMs. Signed-off-by: Rajnesh Kanwal Signed-off-by: Atish Patra --- arch/riscv/kvm/vcpu_insn.c | 98 +++++++++++++++++++++++++++++++++----- 1 file changed, 85 insertions(+), 13 deletions(-) diff --git a/arch/riscv/kvm/vcpu_insn.c b/arch/riscv/kvm/vcpu_insn.c index 331489f..56eeb86 100644 --- a/arch/riscv/kvm/vcpu_insn.c +++ b/arch/riscv/kvm/vcpu_insn.c @@ -7,6 +7,9 @@ #include #include #include +#include +#include +#include =20 #define INSN_OPCODE_MASK 0x007c #define INSN_OPCODE_SHIFT 2 @@ -116,6 +119,10 @@ #define REG_OFFSET(insn, pos) \ (SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK) =20 +#define REG_INDEX(insn, pos) \ + ((SHIFT_RIGHT((insn), (pos)-LOG_REGBYTES) & REG_MASK) / \ + (__riscv_xlen / 8)) + #define REG_PTR(insn, pos, regs) \ ((ulong *)((ulong)(regs) + REG_OFFSET(insn, pos))) =20 @@ -600,6 +607,7 @@ int kvm_riscv_vcpu_mmio_store(struct kvm_vcpu *vcpu, st= ruct kvm_run *run, int len =3D 0, insn_len =3D 0; struct kvm_cpu_trap utrap =3D { 0 }; struct kvm_cpu_context *ct =3D &vcpu->arch.guest_context; + void *nshmem; =20 /* Determine trapped instruction */ if (htinst & 0x1) { @@ -627,7 +635,15 @@ int kvm_riscv_vcpu_mmio_store(struct kvm_vcpu *vcpu, s= truct kvm_run *run, insn_len =3D INSN_LEN(insn); } =20 - data =3D GET_RS2(insn, &vcpu->arch.guest_context); + if (is_cove_vcpu(vcpu)) { + nshmem =3D nacl_shmem(); + data =3D nacl_shmem_gpr_read_cove(nshmem, + REG_INDEX(insn, SH_RS2) * 8 + + KVM_ARCH_GUEST_ZERO); + } else { + data =3D GET_RS2(insn, &vcpu->arch.guest_context); + } + data8 =3D data16 =3D data32 =3D data64 =3D data; =20 if ((insn & INSN_MASK_SW) =3D=3D INSN_MATCH_SW) { @@ -643,19 +659,43 @@ int kvm_riscv_vcpu_mmio_store(struct kvm_vcpu *vcpu, = struct kvm_run *run, #ifdef CONFIG_64BIT } else if ((insn & INSN_MASK_C_SD) =3D=3D INSN_MATCH_C_SD) { len =3D 8; - data64 =3D GET_RS2S(insn, &vcpu->arch.guest_context); + if (is_cove_vcpu(vcpu)) { + data64 =3D nacl_shmem_gpr_read_cove( + nshmem, + RVC_RS2S(insn) * 8 + KVM_ARCH_GUEST_ZERO); + } else { + data64 =3D GET_RS2S(insn, &vcpu->arch.guest_context); + } } else if ((insn & INSN_MASK_C_SDSP) =3D=3D INSN_MATCH_C_SDSP && ((insn >> SH_RD) & 0x1f)) { len =3D 8; - data64 =3D GET_RS2C(insn, &vcpu->arch.guest_context); + if (is_cove_vcpu(vcpu)) { + data64 =3D nacl_shmem_gpr_read_cove( + nshmem, REG_INDEX(insn, SH_RS2C) * 8 + + KVM_ARCH_GUEST_ZERO); + } else { + data64 =3D GET_RS2C(insn, &vcpu->arch.guest_context); + } #endif } else if ((insn & INSN_MASK_C_SW) =3D=3D INSN_MATCH_C_SW) { len =3D 4; - data32 =3D GET_RS2S(insn, &vcpu->arch.guest_context); + if (is_cove_vcpu(vcpu)) { + data32 =3D nacl_shmem_gpr_read_cove( + nshmem, + RVC_RS2S(insn) * 8 + KVM_ARCH_GUEST_ZERO); + } else { + data32 =3D GET_RS2S(insn, &vcpu->arch.guest_context); + } } else if ((insn & INSN_MASK_C_SWSP) =3D=3D INSN_MATCH_C_SWSP && ((insn >> SH_RD) & 0x1f)) { len =3D 4; - data32 =3D GET_RS2C(insn, &vcpu->arch.guest_context); + if (is_cove_vcpu(vcpu)) { + data32 =3D nacl_shmem_gpr_read_cove( + nshmem, REG_INDEX(insn, SH_RS2C) * 8 + + KVM_ARCH_GUEST_ZERO); + } else { + data32 =3D GET_RS2C(insn, &vcpu->arch.guest_context); + } } else { return -EOPNOTSUPP; } @@ -725,6 +765,7 @@ int kvm_riscv_vcpu_mmio_return(struct kvm_vcpu *vcpu, s= truct kvm_run *run) u64 data64; ulong insn; int len, shift; + void *nshmem; =20 if (vcpu->arch.mmio_decode.return_handled) return 0; @@ -738,26 +779,57 @@ int kvm_riscv_vcpu_mmio_return(struct kvm_vcpu *vcpu,= struct kvm_run *run) len =3D vcpu->arch.mmio_decode.len; shift =3D vcpu->arch.mmio_decode.shift; =20 + if (is_cove_vcpu(vcpu)) + nshmem =3D nacl_shmem(); + switch (len) { case 1: data8 =3D *((u8 *)run->mmio.data); - SET_RD(insn, &vcpu->arch.guest_context, - (ulong)data8 << shift >> shift); + if (is_cove_vcpu(vcpu)) { + nacl_shmem_gpr_write_cove(nshmem, + REG_INDEX(insn, SH_RD) * 8 + + KVM_ARCH_GUEST_ZERO, + (unsigned long)data8); + } else { + SET_RD(insn, &vcpu->arch.guest_context, + (ulong)data8 << shift >> shift); + } break; case 2: data16 =3D *((u16 *)run->mmio.data); - SET_RD(insn, &vcpu->arch.guest_context, - (ulong)data16 << shift >> shift); + if (is_cove_vcpu(vcpu)) { + nacl_shmem_gpr_write_cove(nshmem, + REG_INDEX(insn, SH_RD) * 8 + + KVM_ARCH_GUEST_ZERO, + (unsigned long)data16); + } else { + SET_RD(insn, &vcpu->arch.guest_context, + (ulong)data16 << shift >> shift); + } break; case 4: data32 =3D *((u32 *)run->mmio.data); - SET_RD(insn, &vcpu->arch.guest_context, - (ulong)data32 << shift >> shift); + if (is_cove_vcpu(vcpu)) { + nacl_shmem_gpr_write_cove(nshmem, + REG_INDEX(insn, SH_RD) * 8 + + KVM_ARCH_GUEST_ZERO, + (unsigned long)data32); + } else { + SET_RD(insn, &vcpu->arch.guest_context, + (ulong)data32 << shift >> shift); + } break; case 8: data64 =3D *((u64 *)run->mmio.data); - SET_RD(insn, &vcpu->arch.guest_context, - (ulong)data64 << shift >> shift); + if (is_cove_vcpu(vcpu)) { + nacl_shmem_gpr_write_cove(nshmem, + REG_INDEX(insn, SH_RD) * 8 + + KVM_ARCH_GUEST_ZERO, + (unsigned long)data64); + } else { + SET_RD(insn, &vcpu->arch.guest_context, + (ulong)data64 << shift >> shift); + } break; default: return -EOPNOTSUPP; --=20 2.25.1